LLVM 19.0.0git
SPIRVISelLowering.h
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1//===-- SPIRVISelLowering.h - SPIR-V DAG Lowering Interface -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that SPIR-V uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
15#define LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
16
17#include "SPIRVGlobalRegistry.h"
19#include <set>
20
21namespace llvm {
22class SPIRVSubtarget;
23
25 const SPIRVSubtarget &STI;
26
27 // Record of already processed machine functions
28 mutable std::set<const MachineFunction *> ProcessedMF;
29
30public:
32 const SPIRVSubtarget &ST)
33 : TargetLowering(TM), STI(ST) {}
34
35 // Stop IRTranslator breaking up FMA instrs to preserve types information.
37 EVT) const override {
38 return true;
39 }
40
41 // prevent creation of jump tables
42 bool areJTsAllowed(const Function *) const override { return false; }
43
44 // This is to prevent sexts of non-i64 vector indices which are generated
45 // within general IRTranslator hence type generation for it is omitted.
46 MVT getVectorIdxTy(const DataLayout &DL) const override {
47 return MVT::getIntegerVT(32);
48 }
51 EVT VT) const override;
53 EVT VT) const override;
54 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
56 unsigned Intrinsic) const override;
57
58 std::pair<unsigned, const TargetRegisterClass *>
60 StringRef Constraint, MVT VT) const override;
61 unsigned
63 std::optional<MVT> RegisterVT = std::nullopt) const override {
64 return 1;
65 }
66
67 // Call the default implementation and finalize target lowering by inserting
68 // extra instructions required to preserve validity of SPIR-V code imposed by
69 // the standard.
70 void finalizeLowering(MachineFunction &MF) const override;
71};
72} // namespace llvm
73
74#endif // LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
This class represents a function call, abstracting a target machine's calling convention.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Machine Value Type.
static MVT getIntegerVT(unsigned BitWidth)
bool areJTsAllowed(const Function *) const override
Return true if lowering to a jump table is allowed.
unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const override
Return the number of registers that this ValueType will eventually require.
MVT getVectorIdxTy(const DataLayout &DL) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
SPIRVTargetLowering(const TargetMachine &TM, const SPIRVSubtarget &ST)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Extended Value Type.
Definition: ValueTypes.h:34