21#define GET_INSTRINFO_CTOR_DTOR
22#include "SPIRVGenInstrInfo.inc"
29 switch (
MI.getOpcode()) {
30 case SPIRV::OpConstantTrue:
31 case SPIRV::OpConstantFalse:
32 case SPIRV::OpConstantI:
33 case SPIRV::OpConstantF:
34 case SPIRV::OpConstantComposite:
35 case SPIRV::OpConstantSampler:
36 case SPIRV::OpConstantNull:
37 case SPIRV::OpSpecConstantTrue:
38 case SPIRV::OpSpecConstantFalse:
39 case SPIRV::OpSpecConstant:
40 case SPIRV::OpSpecConstantComposite:
41 case SPIRV::OpSpecConstantOp:
43 case SPIRV::OpConstantFunctionPointerINTEL:
51 auto &
MRI =
MI.getMF()->getRegInfo();
52 if (
MI.getNumDefs() >= 1 &&
MI.getOperand(0).isReg()) {
53 auto DefRegClass =
MRI.getRegClassOrNull(
MI.getOperand(0).getReg());
54 return DefRegClass && DefRegClass->getID() == SPIRV::TYPERegClass.getID();
56 return MI.getOpcode() == SPIRV::OpTypeForwardPointer;
61 switch (
MI.getOpcode()) {
62 case SPIRV::OpDecorate:
63 case SPIRV::OpDecorateId:
64 case SPIRV::OpDecorateString:
65 case SPIRV::OpMemberDecorate:
66 case SPIRV::OpMemberDecorateString:
74 switch (
MI.getOpcode()) {
75 case SPIRV::OpCapability:
76 case SPIRV::OpExtension:
77 case SPIRV::OpExtInstImport:
78 case SPIRV::OpMemoryModel:
79 case SPIRV::OpEntryPoint:
80 case SPIRV::OpExecutionMode:
81 case SPIRV::OpExecutionModeId:
83 case SPIRV::OpSourceExtension:
85 case SPIRV::OpSourceContinued:
87 case SPIRV::OpMemberName:
88 case SPIRV::OpModuleProcessed:
96 switch (
MI.getOpcode()) {
115 switch (
MI.getOpcode()) {
122 case SPIRV::OpShiftLeftLogicalS:
123 case SPIRV::OpShiftLeftLogicalV:
124 case SPIRV::OpSNegate:
132 switch (
MI.getOpcode()) {
176 bool AllowModify)
const {
184 if (
MI->getOpcode() == SPIRV::OpBranch) {
185 TBB =
MI->getOperand(0).getMBB();
187 }
else if (
MI->getOpcode() == SPIRV::OpBranchConditional) {
188 Cond.push_back(
MI->getOperand(0));
189 TBB =
MI->getOperand(1).getMBB();
190 if (
MI->getNumOperands() == 3) {
191 FBB =
MI->getOperand(2).getMBB();
205 int *BytesRemoved)
const {
207 " to OpPhi instructions. Try using -O0 instead.");
227 "propagated to OpPhi instructions. Try using "
239 assert(
I->isCopy() &&
"Copy instruction is expected");
240 auto DstOp =
I->getOperand(0);
241 auto SrcOp =
I->getOperand(1);
243 "Register operands are expected in COPY");
244 auto &
MRI =
I->getMF()->getRegInfo();
249 if (
MI.getOpcode() == SPIRV::GET_ID ||
MI.getOpcode() == SPIRV::GET_fID ||
250 MI.getOpcode() == SPIRV::GET_pID ||
MI.getOpcode() == SPIRV::GET_vfID ||
251 MI.getOpcode() == SPIRV::GET_vID) {
252 auto &
MRI =
MI.getMF()->getRegInfo();
253 MRI.replaceRegWith(
MI.getOperand(0).getReg(),
MI.getOperand(1).getReg());
254 MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file declares the MachineIRBuilder class.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Wrapper class representing physical registers. Should be passed by value.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Representation of each machine instruction.
bool isConstantInstr(const MachineInstr &MI) const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool isTypeDeclInstr(const MachineInstr &MI) const
bool canUseFastMathFlags(const MachineInstr &MI) const
bool isDecorationInstr(const MachineInstr &MI) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isHeaderInstr(const MachineInstr &MI) const
bool canUseNUW(const MachineInstr &MI) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool canUseNSW(const MachineInstr &MI) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is an optimization pass for GlobalISel generic memory operations.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.