LLVM  13.0.0git
MachineBasicBlock.cpp
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1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Collect the sequence of machine instructions for a basic block.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/Config/llvm-config.h"
27 #include "llvm/IR/BasicBlock.h"
28 #include "llvm/IR/DataLayout.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCContext.h"
33 #include "llvm/Support/DataTypes.h"
34 #include "llvm/Support/Debug.h"
37 #include <algorithm>
38 using namespace llvm;
39 
40 #define DEBUG_TYPE "codegen"
41 
43  "print-slotindexes",
44  cl::desc("When printing machine IR, annotate instructions and blocks with "
45  "SlotIndexes when available"),
46  cl::init(true), cl::Hidden);
47 
48 MachineBasicBlock::MachineBasicBlock(MachineFunction &MF, const BasicBlock *B)
49  : BB(B), Number(-1), xParent(&MF) {
50  Insts.Parent = this;
51  if (B)
52  IrrLoopHeaderWeight = B->getIrrLoopHeaderWeight();
53 }
54 
55 MachineBasicBlock::~MachineBasicBlock() {
56 }
57 
58 /// Return the MCSymbol for this basic block.
60  if (!CachedMCSymbol) {
61  const MachineFunction *MF = getParent();
62  MCContext &Ctx = MF->getContext();
63 
64  // We emit a non-temporary symbol -- with a descriptive name -- if it begins
65  // a section (with basic block sections). Otherwise we fall back to use temp
66  // label.
67  if (MF->hasBBSections() && isBeginSection()) {
68  SmallString<5> Suffix;
69  if (SectionID == MBBSectionID::ColdSectionID) {
70  Suffix += ".cold";
71  } else if (SectionID == MBBSectionID::ExceptionSectionID) {
72  Suffix += ".eh";
73  } else {
74  // For symbols that represent basic block sections, we add ".__part." to
75  // allow tools like symbolizers to know that this represents a part of
76  // the original function.
77  Suffix = (Suffix + Twine(".__part.") + Twine(SectionID.Number)).str();
78  }
79  CachedMCSymbol = Ctx.getOrCreateSymbol(MF->getName() + Suffix);
80  } else {
82  CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
83  Twine(MF->getFunctionNumber()) +
84  "_" + Twine(getNumber()));
85  }
86  }
87  return CachedMCSymbol;
88 }
89 
91  if (!CachedEHCatchretMCSymbol) {
92  const MachineFunction *MF = getParent();
95  << "$ehgcr_" << MF->getFunctionNumber() << '_' << getNumber();
96  CachedEHCatchretMCSymbol = MF->getContext().getOrCreateSymbol(SymbolName);
97  }
98  return CachedEHCatchretMCSymbol;
99 }
100 
102  if (!CachedEndMCSymbol) {
103  const MachineFunction *MF = getParent();
104  MCContext &Ctx = MF->getContext();
105  auto Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
106  CachedEndMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB_END" +
107  Twine(MF->getFunctionNumber()) +
108  "_" + Twine(getNumber()));
109  }
110  return CachedEndMCSymbol;
111 }
112 
114  MBB.print(OS);
115  return OS;
116 }
117 
119  return Printable([&MBB](raw_ostream &OS) { return MBB.printAsOperand(OS); });
120 }
121 
122 /// When an MBB is added to an MF, we need to update the parent pointer of the
123 /// MBB, the MBB numbering, and any instructions in the MBB to be on the right
124 /// operand list for registers.
125 ///
126 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
127 /// gets the next available unique MBB number. If it is removed from a
128 /// MachineFunction, it goes back to being #-1.
130  MachineBasicBlock *N) {
131  MachineFunction &MF = *N->getParent();
132  N->Number = MF.addToMBBNumbering(N);
133 
134  // Make sure the instructions have their operands in the reginfo lists.
135  MachineRegisterInfo &RegInfo = MF.getRegInfo();
137  I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
138  I->AddRegOperandsToUseLists(RegInfo);
139 }
140 
142  MachineBasicBlock *N) {
143  N->getParent()->removeFromMBBNumbering(N->Number);
144  N->Number = -1;
145 }
146 
147 /// When we add an instruction to a basic block list, we update its parent
148 /// pointer and add its operands from reg use/def lists if appropriate.
150  assert(!N->getParent() && "machine instruction already in a basic block");
151  N->setParent(Parent);
152 
153  // Add the instruction's register operands to their corresponding
154  // use/def lists.
155  MachineFunction *MF = Parent->getParent();
156  N->AddRegOperandsToUseLists(MF->getRegInfo());
157  MF->handleInsertion(*N);
158 }
159 
160 /// When we remove an instruction from a basic block list, we update its parent
161 /// pointer and remove its operands from reg use/def lists if appropriate.
163  assert(N->getParent() && "machine instruction not in a basic block");
164 
165  // Remove from the use/def lists.
166  if (MachineFunction *MF = N->getMF()) {
167  MF->handleRemoval(*N);
168  N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
169  }
170 
171  N->setParent(nullptr);
172 }
173 
174 /// When moving a range of instructions from one MBB list to another, we need to
175 /// update the parent pointers and the use/def lists.
177  instr_iterator First,
178  instr_iterator Last) {
179  assert(Parent->getParent() == FromList.Parent->getParent() &&
180  "cannot transfer MachineInstrs between MachineFunctions");
181 
182  // If it's within the same BB, there's nothing to do.
183  if (this == &FromList)
184  return;
185 
186  assert(Parent != FromList.Parent && "Two lists have the same parent?");
187 
188  // If splicing between two blocks within the same function, just update the
189  // parent pointers.
190  for (; First != Last; ++First)
191  First->setParent(Parent);
192 }
193 
195  assert(!MI->getParent() && "MI is still in a block!");
196  Parent->getParent()->DeleteMachineInstr(MI);
197 }
198 
201  while (I != E && I->isPHI())
202  ++I;
203  assert((I == E || !I->isInsideBundle()) &&
204  "First non-phi MI cannot be inside a bundle!");
205  return I;
206 }
207 
211 
212  iterator E = end();
213  while (I != E && (I->isPHI() || I->isPosition() ||
214  TII->isBasicBlockPrologue(*I)))
215  ++I;
216  // FIXME: This needs to change if we wish to bundle labels
217  // inside the bundle.
218  assert((I == E || !I->isInsideBundle()) &&
219  "First non-phi / non-label instruction is inside a bundle!");
220  return I;
221 }
222 
226 
227  iterator E = end();
228  while (I != E && (I->isPHI() || I->isPosition() || I->isDebugInstr() ||
229  TII->isBasicBlockPrologue(*I)))
230  ++I;
231  // FIXME: This needs to change if we wish to bundle labels / dbg_values
232  // inside the bundle.
233  assert((I == E || !I->isInsideBundle()) &&
234  "First non-phi / non-label / non-debug "
235  "instruction is inside a bundle!");
236  return I;
237 }
238 
240  iterator B = begin(), E = end(), I = E;
241  while (I != B && ((--I)->isTerminator() || I->isDebugInstr()))
242  ; /*noop */
243  while (I != E && !I->isTerminator())
244  ++I;
245  return I;
246 }
247 
249  instr_iterator B = instr_begin(), E = instr_end(), I = E;
250  while (I != B && ((--I)->isTerminator() || I->isDebugInstr()))
251  ; /*noop */
252  while (I != E && !I->isTerminator())
253  ++I;
254  return I;
255 }
256 
259  // Skip over begin-of-block dbg_value instructions.
260  return skipDebugInstructionsForward(begin(), end(), SkipPseudoOp);
261 }
262 
265  // Skip over end-of-block dbg_value instructions.
267  while (I != B) {
268  --I;
269  // Return instruction that starts a bundle.
270  if (I->isDebugInstr() || I->isInsideBundle())
271  continue;
272  if (SkipPseudoOp && I->isPseudoProbe())
273  continue;
274  return I;
275  }
276  // The block is all debug values.
277  return end();
278 }
279 
281  for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
282  if ((*I)->isEHPad())
283  return true;
284  return false;
285 }
286 
288  return getParent()->begin() == getIterator();
289 }
290 
291 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
293  print(dbgs());
294 }
295 #endif
296 
298  for (const MachineBasicBlock *Succ : successors()) {
299  if (Succ->isInlineAsmBrIndirectTarget())
300  return true;
301  }
302  return false;
303 }
304 
307  return false;
308  return true;
309 }
310 
312  if (const BasicBlock *LBB = getBasicBlock())
313  return LBB->getName();
314  else
315  return StringRef("", 0);
316 }
317 
318 /// Return a hopefully unique identifier for this block.
319 std::string MachineBasicBlock::getFullName() const {
320  std::string Name;
321  if (getParent())
322  Name = (getParent()->getName() + ":").str();
323  if (getBasicBlock())
324  Name += getBasicBlock()->getName();
325  else
326  Name += ("BB" + Twine(getNumber())).str();
327  return Name;
328 }
329 
331  bool IsStandalone) const {
332  const MachineFunction *MF = getParent();
333  if (!MF) {
334  OS << "Can't print out MachineBasicBlock because parent MachineFunction"
335  << " is null\n";
336  return;
337  }
338  const Function &F = MF->getFunction();
339  const Module *M = F.getParent();
340  ModuleSlotTracker MST(M);
341  MST.incorporateFunction(F);
342  print(OS, MST, Indexes, IsStandalone);
343 }
344 
346  const SlotIndexes *Indexes,
347  bool IsStandalone) const {
348  const MachineFunction *MF = getParent();
349  if (!MF) {
350  OS << "Can't print out MachineBasicBlock because parent MachineFunction"
351  << " is null\n";
352  return;
353  }
354 
355  if (Indexes && PrintSlotIndexes)
356  OS << Indexes->getMBBStartIdx(this) << '\t';
357 
359  OS << ":\n";
360 
362  const MachineRegisterInfo &MRI = MF->getRegInfo();
364  bool HasLineAttributes = false;
365 
366  // Print the preds of this block according to the CFG.
367  if (!pred_empty() && IsStandalone) {
368  if (Indexes) OS << '\t';
369  // Don't indent(2), align with previous line attributes.
370  OS << "; predecessors: ";
371  ListSeparator LS;
372  for (auto *Pred : predecessors())
373  OS << LS << printMBBReference(*Pred);
374  OS << '\n';
375  HasLineAttributes = true;
376  }
377 
378  if (!succ_empty()) {
379  if (Indexes) OS << '\t';
380  // Print the successors
381  OS.indent(2) << "successors: ";
382  ListSeparator LS;
383  for (auto I = succ_begin(), E = succ_end(); I != E; ++I) {
384  OS << LS << printMBBReference(**I);
385  if (!Probs.empty())
386  OS << '('
387  << format("0x%08" PRIx32, getSuccProbability(I).getNumerator())
388  << ')';
389  }
390  if (!Probs.empty() && IsStandalone) {
391  // Print human readable probabilities as comments.
392  OS << "; ";
393  ListSeparator LS;
394  for (auto I = succ_begin(), E = succ_end(); I != E; ++I) {
395  const BranchProbability &BP = getSuccProbability(I);
396  OS << LS << printMBBReference(**I) << '('
397  << format("%.2f%%",
398  rint(((double)BP.getNumerator() / BP.getDenominator()) *
399  100.0 * 100.0) /
400  100.0)
401  << ')';
402  }
403  }
404 
405  OS << '\n';
406  HasLineAttributes = true;
407  }
408 
409  if (!livein_empty() && MRI.tracksLiveness()) {
410  if (Indexes) OS << '\t';
411  OS.indent(2) << "liveins: ";
412 
413  ListSeparator LS;
414  for (const auto &LI : liveins()) {
415  OS << LS << printReg(LI.PhysReg, TRI);
416  if (!LI.LaneMask.all())
417  OS << ":0x" << PrintLaneMask(LI.LaneMask);
418  }
419  HasLineAttributes = true;
420  }
421 
422  if (HasLineAttributes)
423  OS << '\n';
424 
425  bool IsInBundle = false;
426  for (const MachineInstr &MI : instrs()) {
427  if (Indexes && PrintSlotIndexes) {
428  if (Indexes->hasIndex(MI))
429  OS << Indexes->getInstructionIndex(MI);
430  OS << '\t';
431  }
432 
433  if (IsInBundle && !MI.isInsideBundle()) {
434  OS.indent(2) << "}\n";
435  IsInBundle = false;
436  }
437 
438  OS.indent(IsInBundle ? 4 : 2);
439  MI.print(OS, MST, IsStandalone, /*SkipOpers=*/false, /*SkipDebugLoc=*/false,
440  /*AddNewLine=*/false, &TII);
441 
442  if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
443  OS << " {";
444  IsInBundle = true;
445  }
446  OS << '\n';
447  }
448 
449  if (IsInBundle)
450  OS.indent(2) << "}\n";
451 
452  if (IrrLoopHeaderWeight && IsStandalone) {
453  if (Indexes) OS << '\t';
454  OS.indent(2) << "; Irreducible loop header weight: "
455  << IrrLoopHeaderWeight.getValue() << '\n';
456  }
457 }
458 
459 /// Print the basic block's name as:
460 ///
461 /// bb.{number}[.{ir-name}] [(attributes...)]
462 ///
463 /// The {ir-name} is only printed when the \ref PrintNameIr flag is passed
464 /// (which is the default). If the IR block has no name, it is identified
465 /// numerically using the attribute syntax as "(%ir-block.{ir-slot})".
466 ///
467 /// When the \ref PrintNameAttributes flag is passed, additional attributes
468 /// of the block are printed when set.
469 ///
470 /// \param printNameFlags Combination of \ref PrintNameFlag flags indicating
471 /// the parts to print.
472 /// \param moduleSlotTracker Optional ModuleSlotTracker. This method will
473 /// incorporate its own tracker when necessary to
474 /// determine the block's IR name.
475 void MachineBasicBlock::printName(raw_ostream &os, unsigned printNameFlags,
476  ModuleSlotTracker *moduleSlotTracker) const {
477  os << "bb." << getNumber();
478  bool hasAttributes = false;
479 
480  if (printNameFlags & PrintNameIr) {
481  if (const auto *bb = getBasicBlock()) {
482  if (bb->hasName()) {
483  os << '.' << bb->getName();
484  } else {
485  hasAttributes = true;
486  os << " (";
487 
488  int slot = -1;
489 
490  if (moduleSlotTracker) {
491  slot = moduleSlotTracker->getLocalSlot(bb);
492  } else if (bb->getParent()) {
493  ModuleSlotTracker tmpTracker(bb->getModule(), false);
494  tmpTracker.incorporateFunction(*bb->getParent());
495  slot = tmpTracker.getLocalSlot(bb);
496  }
497 
498  if (slot == -1)
499  os << "<ir-block badref>";
500  else
501  os << (Twine("%ir-block.") + Twine(slot)).str();
502  }
503  }
504  }
505 
506  if (printNameFlags & PrintNameAttributes) {
507  if (hasAddressTaken()) {
508  os << (hasAttributes ? ", " : " (");
509  os << "address-taken";
510  hasAttributes = true;
511  }
512  if (isEHPad()) {
513  os << (hasAttributes ? ", " : " (");
514  os << "landing-pad";
515  hasAttributes = true;
516  }
517  if (isEHFuncletEntry()) {
518  os << (hasAttributes ? ", " : " (");
519  os << "ehfunclet-entry";
520  hasAttributes = true;
521  }
522  if (getAlignment() != Align(1)) {
523  os << (hasAttributes ? ", " : " (");
524  os << "align " << getAlignment().value();
525  hasAttributes = true;
526  }
527  if (getSectionID() != MBBSectionID(0)) {
528  os << (hasAttributes ? ", " : " (");
529  os << "bbsections ";
530  switch (getSectionID().Type) {
531  case MBBSectionID::SectionType::Exception:
532  os << "Exception";
533  break;
535  os << "Cold";
536  break;
537  default:
538  os << getSectionID().Number;
539  }
540  hasAttributes = true;
541  }
542  }
543 
544  if (hasAttributes)
545  os << ')';
546 }
547 
549  bool /*PrintType*/) const {
550  OS << '%';
551  printName(OS, 0);
552 }
553 
555  LiveInVector::iterator I = find_if(
556  LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
557  if (I == LiveIns.end())
558  return;
559 
560  I->LaneMask &= ~LaneMask;
561  if (I->LaneMask.none())
562  LiveIns.erase(I);
563 }
564 
567  // Get non-const version of iterator.
568  LiveInVector::iterator LI = LiveIns.begin() + (I - LiveIns.begin());
569  return LiveIns.erase(LI);
570 }
571 
574  LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
575  return I != livein_end() && (I->LaneMask & LaneMask).any();
576 }
577 
579  llvm::sort(LiveIns,
580  [](const RegisterMaskPair &LI0, const RegisterMaskPair &LI1) {
581  return LI0.PhysReg < LI1.PhysReg;
582  });
583  // Liveins are sorted by physreg now we can merge their lanemasks.
584  LiveInVector::const_iterator I = LiveIns.begin();
585  LiveInVector::const_iterator J;
586  LiveInVector::iterator Out = LiveIns.begin();
587  for (; I != LiveIns.end(); ++Out, I = J) {
588  MCRegister PhysReg = I->PhysReg;
589  LaneBitmask LaneMask = I->LaneMask;
590  for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J)
591  LaneMask |= J->LaneMask;
592  Out->PhysReg = PhysReg;
593  Out->LaneMask = LaneMask;
594  }
595  LiveIns.erase(Out, LiveIns.end());
596 }
597 
598 Register
600  assert(getParent() && "MBB must be inserted in function");
601  assert(Register::isPhysicalRegister(PhysReg) && "Expected physreg");
602  assert(RC && "Register class is required");
603  assert((isEHPad() || this == &getParent()->front()) &&
604  "Only the entry block and landing pads can have physreg live ins");
605 
606  bool LiveIn = isLiveIn(PhysReg);
610 
611  // Look for an existing copy.
612  if (LiveIn)
613  for (;I != E && I->isCopy(); ++I)
614  if (I->getOperand(1).getReg() == PhysReg) {
615  Register VirtReg = I->getOperand(0).getReg();
616  if (!MRI.constrainRegClass(VirtReg, RC))
617  llvm_unreachable("Incompatible live-in register class.");
618  return VirtReg;
619  }
620 
621  // No luck, create a virtual register.
622  Register VirtReg = MRI.createVirtualRegister(RC);
623  BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
624  .addReg(PhysReg, RegState::Kill);
625  if (!LiveIn)
626  addLiveIn(PhysReg);
627  return VirtReg;
628 }
629 
631  getParent()->splice(NewAfter->getIterator(), getIterator());
632 }
633 
635  getParent()->splice(++NewBefore->getIterator(), getIterator());
636 }
637 
639  MachineBasicBlock *PreviousLayoutSuccessor) {
640  LLVM_DEBUG(dbgs() << "Updating terminators on " << printMBBReference(*this)
641  << "\n");
642 
644  // A block with no successors has no concerns with fall-through edges.
645  if (this->succ_empty())
646  return;
647 
648  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
651  bool B = TII->analyzeBranch(*this, TBB, FBB, Cond);
652  (void) B;
653  assert(!B && "UpdateTerminators requires analyzable predecessors!");
654  if (Cond.empty()) {
655  if (TBB) {
656  // The block has an unconditional branch. If its successor is now its
657  // layout successor, delete the branch.
658  if (isLayoutSuccessor(TBB))
659  TII->removeBranch(*this);
660  } else {
661  // The block has an unconditional fallthrough, or the end of the block is
662  // unreachable.
663 
664  // Unfortunately, whether the end of the block is unreachable is not
665  // immediately obvious; we must fall back to checking the successor list,
666  // and assuming that if the passed in block is in the succesor list and
667  // not an EHPad, it must be the intended target.
668  if (!PreviousLayoutSuccessor || !isSuccessor(PreviousLayoutSuccessor) ||
669  PreviousLayoutSuccessor->isEHPad())
670  return;
671 
672  // If the unconditional successor block is not the current layout
673  // successor, insert a branch to jump to it.
674  if (!isLayoutSuccessor(PreviousLayoutSuccessor))
675  TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL);
676  }
677  return;
678  }
679 
680  if (FBB) {
681  // The block has a non-fallthrough conditional branch. If one of its
682  // successors is its layout successor, rewrite it to a fallthrough
683  // conditional branch.
684  if (isLayoutSuccessor(TBB)) {
686  return;
687  TII->removeBranch(*this);
688  TII->insertBranch(*this, FBB, nullptr, Cond, DL);
689  } else if (isLayoutSuccessor(FBB)) {
690  TII->removeBranch(*this);
691  TII->insertBranch(*this, TBB, nullptr, Cond, DL);
692  }
693  return;
694  }
695 
696  // We now know we're going to fallthrough to PreviousLayoutSuccessor.
697  assert(PreviousLayoutSuccessor);
698  assert(!PreviousLayoutSuccessor->isEHPad());
699  assert(isSuccessor(PreviousLayoutSuccessor));
700 
701  if (PreviousLayoutSuccessor == TBB) {
702  // We had a fallthrough to the same basic block as the conditional jump
703  // targets. Remove the conditional jump, leaving an unconditional
704  // fallthrough or an unconditional jump.
705  TII->removeBranch(*this);
706  if (!isLayoutSuccessor(TBB)) {
707  Cond.clear();
708  TII->insertBranch(*this, TBB, nullptr, Cond, DL);
709  }
710  return;
711  }
712 
713  // The block has a fallthrough conditional branch.
714  if (isLayoutSuccessor(TBB)) {
716  // We can't reverse the condition, add an unconditional branch.
717  Cond.clear();
718  TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL);
719  return;
720  }
721  TII->removeBranch(*this);
722  TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL);
723  } else if (!isLayoutSuccessor(PreviousLayoutSuccessor)) {
724  TII->removeBranch(*this);
725  TII->insertBranch(*this, TBB, PreviousLayoutSuccessor, Cond, DL);
726  }
727 }
728 
730 #ifndef NDEBUG
731  int64_t Sum = 0;
732  for (auto Prob : Probs)
733  Sum += Prob.getNumerator();
734  // Due to precision issue, we assume that the sum of probabilities is one if
735  // the difference between the sum of their numerators and the denominator is
736  // no greater than the number of successors.
738  Probs.size() &&
739  "The sum of successors's probabilities exceeds one.");
740 #endif // NDEBUG
741 }
742 
744  BranchProbability Prob) {
745  // Probability list is either empty (if successor list isn't empty, this means
746  // disabled optimization) or has the same size as successor list.
747  if (!(Probs.empty() && !Successors.empty()))
748  Probs.push_back(Prob);
749  Successors.push_back(Succ);
750  Succ->addPredecessor(this);
751 }
752 
754  // We need to make sure probability list is either empty or has the same size
755  // of successor list. When this function is called, we can safely delete all
756  // probability in the list.
757  Probs.clear();
758  Successors.push_back(Succ);
759  Succ->addPredecessor(this);
760 }
761 
763  MachineBasicBlock *New,
764  bool NormalizeSuccProbs) {
765  succ_iterator OldI = llvm::find(successors(), Old);
766  assert(OldI != succ_end() && "Old is not a successor of this block!");
768  "New is already a successor of this block!");
769 
770  // Add a new successor with equal probability as the original one. Note
771  // that we directly copy the probability using the iterator rather than
772  // getting a potentially synthetic probability computed when unknown. This
773  // preserves the probabilities as-is and then we can renormalize them and
774  // query them effectively afterward.
775  addSuccessor(New, Probs.empty() ? BranchProbability::getUnknown()
776  : *getProbabilityIterator(OldI));
777  if (NormalizeSuccProbs)
779 }
780 
782  bool NormalizeSuccProbs) {
783  succ_iterator I = find(Successors, Succ);
784  removeSuccessor(I, NormalizeSuccProbs);
785 }
786 
789  assert(I != Successors.end() && "Not a current successor!");
790 
791  // If probability list is empty it means we don't use it (disabled
792  // optimization).
793  if (!Probs.empty()) {
794  probability_iterator WI = getProbabilityIterator(I);
795  Probs.erase(WI);
796  if (NormalizeSuccProbs)
798  }
799 
800  (*I)->removePredecessor(this);
801  return Successors.erase(I);
802 }
803 
805  MachineBasicBlock *New) {
806  if (Old == New)
807  return;
808 
810  succ_iterator NewI = E;
811  succ_iterator OldI = E;
812  for (succ_iterator I = succ_begin(); I != E; ++I) {
813  if (*I == Old) {
814  OldI = I;
815  if (NewI != E)
816  break;
817  }
818  if (*I == New) {
819  NewI = I;
820  if (OldI != E)
821  break;
822  }
823  }
824  assert(OldI != E && "Old is not a successor of this block");
825 
826  // If New isn't already a successor, let it take Old's place.
827  if (NewI == E) {
828  Old->removePredecessor(this);
829  New->addPredecessor(this);
830  *OldI = New;
831  return;
832  }
833 
834  // New is already a successor.
835  // Update its probability instead of adding a duplicate edge.
836  if (!Probs.empty()) {
837  auto ProbIter = getProbabilityIterator(NewI);
838  if (!ProbIter->isUnknown())
839  *ProbIter += *getProbabilityIterator(OldI);
840  }
841  removeSuccessor(OldI);
842 }
843 
845  succ_iterator I) {
846  if (!Orig->Probs.empty())
847  addSuccessor(*I, Orig->getSuccProbability(I));
848  else
850 }
851 
852 void MachineBasicBlock::addPredecessor(MachineBasicBlock *Pred) {
853  Predecessors.push_back(Pred);
854 }
855 
856 void MachineBasicBlock::removePredecessor(MachineBasicBlock *Pred) {
857  pred_iterator I = find(Predecessors, Pred);
858  assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
859  Predecessors.erase(I);
860 }
861 
863  if (this == FromMBB)
864  return;
865 
866  while (!FromMBB->succ_empty()) {
867  MachineBasicBlock *Succ = *FromMBB->succ_begin();
868 
869  // If probability list is empty it means we don't use it (disabled
870  // optimization).
871  if (!FromMBB->Probs.empty()) {
872  auto Prob = *FromMBB->Probs.begin();
873  addSuccessor(Succ, Prob);
874  } else
876 
877  FromMBB->removeSuccessor(Succ);
878  }
879 }
880 
881 void
883  if (this == FromMBB)
884  return;
885 
886  while (!FromMBB->succ_empty()) {
887  MachineBasicBlock *Succ = *FromMBB->succ_begin();
888  if (!FromMBB->Probs.empty()) {
889  auto Prob = *FromMBB->Probs.begin();
890  addSuccessor(Succ, Prob);
891  } else
893  FromMBB->removeSuccessor(Succ);
894 
895  // Fix up any PHI nodes in the successor.
896  Succ->replacePhiUsesWith(FromMBB, this);
897  }
899 }
900 
901 /// A block emptied (i.e., with all instructions moved out of it) won't be
902 /// sampled at run time. In such cases, AutoFDO will be informed of zero samples
903 /// collected for the block. This is not accurate and could lead to misleading
904 /// weights assigned for the block. A way to mitigate that is to treat such
905 /// block as having unknown counts in the AutoFDO profile loader and allow the
906 /// counts inference tool a chance to calculate a relatively reasonable weight
907 /// for it. This can be done by moving all pseudo probes in the emptied block
908 /// i.e, /c this, to before /c ToMBB and tag them dangling. Note that this is
909 /// not needed for dead blocks which really have a zero weight. It's per
910 /// transforms to decide whether to call this function or not.
913  for (MachineInstr &MI : instrs()) {
914  if (MI.isPseudoProbe()) {
915  MI.addPseudoProbeAttribute(PseudoProbeAttributes::Dangling);
916  ToBeMoved.push_back(&MI);
917  }
918  }
919 
921  for (MachineInstr *MI : ToBeMoved) {
922  MI->removeFromParent();
923  ToMBB->insert(I, MI);
924  }
925 }
926 
928  return is_contained(predecessors(), MBB);
929 }
930 
932  return is_contained(successors(), MBB);
933 }
934 
937  return std::next(I) == MachineFunction::const_iterator(MBB);
938 }
939 
941  MachineFunction::iterator Fallthrough = getIterator();
942  ++Fallthrough;
943  // If FallthroughBlock is off the end of the function, it can't fall through.
944  if (Fallthrough == getParent()->end())
945  return nullptr;
946 
947  // If FallthroughBlock isn't a successor, no fallthrough is possible.
948  if (!isSuccessor(&*Fallthrough))
949  return nullptr;
950 
951  // Analyze the branches, if any, at the end of the block.
952  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
955  if (TII->analyzeBranch(*this, TBB, FBB, Cond)) {
956  // If we couldn't analyze the branch, examine the last instruction.
957  // If the block doesn't end in a known control barrier, assume fallthrough
958  // is possible. The isPredicated check is needed because this code can be
959  // called during IfConversion, where an instruction which is normally a
960  // Barrier is predicated and thus no longer an actual control barrier.
961  return (empty() || !back().isBarrier() || TII->isPredicated(back()))
962  ? &*Fallthrough
963  : nullptr;
964  }
965 
966  // If there is no branch, control always falls through.
967  if (!TBB) return &*Fallthrough;
968 
969  // If there is some explicit branch to the fallthrough block, it can obviously
970  // reach, even though the branch should get folded to fall through implicitly.
971  if (MachineFunction::iterator(TBB) == Fallthrough ||
972  MachineFunction::iterator(FBB) == Fallthrough)
973  return &*Fallthrough;
974 
975  // If it's an unconditional branch to some block not the fall through, it
976  // doesn't fall through.
977  if (Cond.empty()) return nullptr;
978 
979  // Otherwise, if it is conditional and has no explicit false block, it falls
980  // through.
981  return (FBB == nullptr) ? &*Fallthrough : nullptr;
982 }
983 
985  return getFallThrough() != nullptr;
986 }
987 
989  bool UpdateLiveIns,
990  LiveIntervals *LIS) {
991  MachineBasicBlock::iterator SplitPoint(&MI);
992  ++SplitPoint;
993 
994  if (SplitPoint == end()) {
995  // Don't bother with a new block.
996  return this;
997  }
998 
999  MachineFunction *MF = getParent();
1000 
1001  LivePhysRegs LiveRegs;
1002  if (UpdateLiveIns) {
1003  // Make sure we add any physregs we define in the block as liveins to the
1004  // new block.
1006  LiveRegs.init(*MF->getSubtarget().getRegisterInfo());
1007  LiveRegs.addLiveOuts(*this);
1008  for (auto I = rbegin(), E = Prev.getReverse(); I != E; ++I)
1009  LiveRegs.stepBackward(*I);
1010  }
1011 
1013 
1014  MF->insert(++MachineFunction::iterator(this), SplitBB);
1015  SplitBB->splice(SplitBB->begin(), this, SplitPoint, end());
1016 
1017  SplitBB->transferSuccessorsAndUpdatePHIs(this);
1018  addSuccessor(SplitBB);
1019 
1020  if (UpdateLiveIns)
1021  addLiveIns(*SplitBB, LiveRegs);
1022 
1023  if (LIS)
1024  LIS->insertMBBInMaps(SplitBB);
1025 
1026  return SplitBB;
1027 }
1028 
1030  MachineBasicBlock *Succ, Pass &P,
1031  std::vector<SparseBitVector<>> *LiveInSets) {
1032  if (!canSplitCriticalEdge(Succ))
1033  return nullptr;
1034 
1035  MachineFunction *MF = getParent();
1036  MachineBasicBlock *PrevFallthrough = getNextNode();
1037  DebugLoc DL; // FIXME: this is nowhere
1038 
1040  MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
1041  LLVM_DEBUG(dbgs() << "Splitting critical edge: " << printMBBReference(*this)
1042  << " -- " << printMBBReference(*NMBB) << " -- "
1043  << printMBBReference(*Succ) << '\n');
1044 
1045  LiveIntervals *LIS = P.getAnalysisIfAvailable<LiveIntervals>();
1046  SlotIndexes *Indexes = P.getAnalysisIfAvailable<SlotIndexes>();
1047  if (LIS)
1048  LIS->insertMBBInMaps(NMBB);
1049  else if (Indexes)
1050  Indexes->insertMBBInMaps(NMBB);
1051 
1052  // On some targets like Mips, branches may kill virtual registers. Make sure
1053  // that LiveVariables is properly updated after updateTerminator replaces the
1054  // terminators.
1055  LiveVariables *LV = P.getAnalysisIfAvailable<LiveVariables>();
1056 
1057  // Collect a list of virtual registers killed by the terminators.
1058  SmallVector<Register, 4> KilledRegs;
1059  if (LV)
1061  I != E; ++I) {
1062  MachineInstr *MI = &*I;
1063  for (MachineInstr::mop_iterator OI = MI->operands_begin(),
1064  OE = MI->operands_end(); OI != OE; ++OI) {
1065  if (!OI->isReg() || OI->getReg() == 0 ||
1066  !OI->isUse() || !OI->isKill() || OI->isUndef())
1067  continue;
1068  Register Reg = OI->getReg();
1070  LV->getVarInfo(Reg).removeKill(*MI)) {
1071  KilledRegs.push_back(Reg);
1072  LLVM_DEBUG(dbgs() << "Removing terminator kill: " << *MI);
1073  OI->setIsKill(false);
1074  }
1075  }
1076  }
1077 
1078  SmallVector<Register, 4> UsedRegs;
1079  if (LIS) {
1081  I != E; ++I) {
1082  MachineInstr *MI = &*I;
1083 
1084  for (MachineInstr::mop_iterator OI = MI->operands_begin(),
1085  OE = MI->operands_end(); OI != OE; ++OI) {
1086  if (!OI->isReg() || OI->getReg() == 0)
1087  continue;
1088 
1089  Register Reg = OI->getReg();
1090  if (!is_contained(UsedRegs, Reg))
1091  UsedRegs.push_back(Reg);
1092  }
1093  }
1094  }
1095 
1096  ReplaceUsesOfBlockWith(Succ, NMBB);
1097 
1098  // If updateTerminator() removes instructions, we need to remove them from
1099  // SlotIndexes.
1100  SmallVector<MachineInstr*, 4> Terminators;
1101  if (Indexes) {
1103  I != E; ++I)
1104  Terminators.push_back(&*I);
1105  }
1106 
1107  // Since we replaced all uses of Succ with NMBB, that should also be treated
1108  // as the fallthrough successor
1109  if (Succ == PrevFallthrough)
1110  PrevFallthrough = NMBB;
1111  updateTerminator(PrevFallthrough);
1112 
1113  if (Indexes) {
1114  SmallVector<MachineInstr*, 4> NewTerminators;
1116  I != E; ++I)
1117  NewTerminators.push_back(&*I);
1118 
1119  for (MachineInstr *Terminator : Terminators) {
1120  if (!is_contained(NewTerminators, Terminator))
1121  Indexes->removeMachineInstrFromMaps(*Terminator);
1122  }
1123  }
1124 
1125  // Insert unconditional "jump Succ" instruction in NMBB if necessary.
1126  NMBB->addSuccessor(Succ);
1127  if (!NMBB->isLayoutSuccessor(Succ)) {
1130  TII->insertBranch(*NMBB, Succ, nullptr, Cond, DL);
1131 
1132  if (Indexes) {
1133  for (MachineInstr &MI : NMBB->instrs()) {
1134  // Some instructions may have been moved to NMBB by updateTerminator(),
1135  // so we first remove any instruction that already has an index.
1136  if (Indexes->hasIndex(MI))
1137  Indexes->removeMachineInstrFromMaps(MI);
1138  Indexes->insertMachineInstrInMaps(MI);
1139  }
1140  }
1141  }
1142 
1143  // Fix PHI nodes in Succ so they refer to NMBB instead of this.
1144  Succ->replacePhiUsesWith(this, NMBB);
1145 
1146  // Inherit live-ins from the successor
1147  for (const auto &LI : Succ->liveins())
1148  NMBB->addLiveIn(LI);
1149 
1150  // Update LiveVariables.
1152  if (LV) {
1153  // Restore kills of virtual registers that were killed by the terminators.
1154  while (!KilledRegs.empty()) {
1155  Register Reg = KilledRegs.pop_back_val();
1156  for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
1157  if (!(--I)->addRegisterKilled(Reg, TRI, /* AddIfNotFound= */ false))
1158  continue;
1160  LV->getVarInfo(Reg).Kills.push_back(&*I);
1161  LLVM_DEBUG(dbgs() << "Restored terminator kill: " << *I);
1162  break;
1163  }
1164  }
1165  // Update relevant live-through information.
1166  if (LiveInSets != nullptr)
1167  LV->addNewBlock(NMBB, this, Succ, *LiveInSets);
1168  else
1169  LV->addNewBlock(NMBB, this, Succ);
1170  }
1171 
1172  if (LIS) {
1173  // After splitting the edge and updating SlotIndexes, live intervals may be
1174  // in one of two situations, depending on whether this block was the last in
1175  // the function. If the original block was the last in the function, all
1176  // live intervals will end prior to the beginning of the new split block. If
1177  // the original block was not at the end of the function, all live intervals
1178  // will extend to the end of the new split block.
1179 
1180  bool isLastMBB =
1181  std::next(MachineFunction::iterator(NMBB)) == getParent()->end();
1182 
1183  SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
1184  SlotIndex PrevIndex = StartIndex.getPrevSlot();
1185  SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
1186 
1187  // Find the registers used from NMBB in PHIs in Succ.
1188  SmallSet<Register, 8> PHISrcRegs;
1190  I = Succ->instr_begin(), E = Succ->instr_end();
1191  I != E && I->isPHI(); ++I) {
1192  for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
1193  if (I->getOperand(ni+1).getMBB() == NMBB) {
1194  MachineOperand &MO = I->getOperand(ni);
1195  Register Reg = MO.getReg();
1196  PHISrcRegs.insert(Reg);
1197  if (MO.isUndef())
1198  continue;
1199 
1200  LiveInterval &LI = LIS->getInterval(Reg);
1201  VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
1202  assert(VNI &&
1203  "PHI sources should be live out of their predecessors.");
1204  LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
1205  }
1206  }
1207  }
1208 
1210  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1212  if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
1213  continue;
1214 
1215  LiveInterval &LI = LIS->getInterval(Reg);
1216  if (!LI.liveAt(PrevIndex))
1217  continue;
1218 
1219  bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
1220  if (isLiveOut && isLastMBB) {
1221  VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
1222  assert(VNI && "LiveInterval should have VNInfo where it is live.");
1223  LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
1224  } else if (!isLiveOut && !isLastMBB) {
1225  LI.removeSegment(StartIndex, EndIndex);
1226  }
1227  }
1228 
1229  // Update all intervals for registers whose uses may have been modified by
1230  // updateTerminator().
1231  LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
1232  }
1233 
1234  if (MachineDominatorTree *MDT =
1235  P.getAnalysisIfAvailable<MachineDominatorTree>())
1236  MDT->recordSplitCriticalEdge(this, Succ, NMBB);
1237 
1238  if (MachineLoopInfo *MLI = P.getAnalysisIfAvailable<MachineLoopInfo>())
1239  if (MachineLoop *TIL = MLI->getLoopFor(this)) {
1240  // If one or the other blocks were not in a loop, the new block is not
1241  // either, and thus LI doesn't need to be updated.
1242  if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
1243  if (TIL == DestLoop) {
1244  // Both in the same loop, the NMBB joins loop.
1245  DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
1246  } else if (TIL->contains(DestLoop)) {
1247  // Edge from an outer loop to an inner loop. Add to the outer loop.
1248  TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
1249  } else if (DestLoop->contains(TIL)) {
1250  // Edge from an inner loop to an outer loop. Add to the outer loop.
1251  DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
1252  } else {
1253  // Edge from two loops with no containment relation. Because these
1254  // are natural loops, we know that the destination block must be the
1255  // header of its loop (adding a branch into a loop elsewhere would
1256  // create an irreducible loop).
1257  assert(DestLoop->getHeader() == Succ &&
1258  "Should not create irreducible loops!");
1259  if (MachineLoop *P = DestLoop->getParentLoop())
1260  P->addBasicBlockToLoop(NMBB, MLI->getBase());
1261  }
1262  }
1263  }
1264 
1265  return NMBB;
1266 }
1267 
1269  const MachineBasicBlock *Succ) const {
1270  // Splitting the critical edge to a landing pad block is non-trivial. Don't do
1271  // it in this generic function.
1272  if (Succ->isEHPad())
1273  return false;
1274 
1275  // Splitting the critical edge to a callbr's indirect block isn't advised.
1276  // Don't do it in this generic function.
1277  if (Succ->isInlineAsmBrIndirectTarget())
1278  return false;
1279 
1280  const MachineFunction *MF = getParent();
1281  // Performance might be harmed on HW that implements branching using exec mask
1282  // where both sides of the branches are always executed.
1283  if (MF->getTarget().requiresStructuredCFG())
1284  return false;
1285 
1286  // We may need to update this's terminator, but we can't do that if
1287  // analyzeBranch fails. If this uses a jump table, we won't touch it.
1288  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1289  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
1291  // AnalyzeBanch should modify this, since we did not allow modification.
1292  if (TII->analyzeBranch(*const_cast<MachineBasicBlock *>(this), TBB, FBB, Cond,
1293  /*AllowModify*/ false))
1294  return false;
1295 
1296  // Avoid bugpoint weirdness: A block may end with a conditional branch but
1297  // jumps to the same MBB is either case. We have duplicate CFG edges in that
1298  // case that we can't handle. Since this never happens in properly optimized
1299  // code, just skip those edges.
1300  if (TBB && TBB == FBB) {
1301  LLVM_DEBUG(dbgs() << "Won't split critical edge after degenerate "
1302  << printMBBReference(*this) << '\n');
1303  return false;
1304  }
1305  return true;
1306 }
1307 
1308 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
1309 /// neighboring instructions so the bundle won't be broken by removing MI.
1311  // Removing the first instruction in a bundle.
1312  if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
1313  MI->unbundleFromSucc();
1314  // Removing the last instruction in a bundle.
1315  if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
1316  MI->unbundleFromPred();
1317  // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
1318  // are already fine.
1319 }
1320 
1323  unbundleSingleMI(&*I);
1324  return Insts.erase(I);
1325 }
1326 
1329  MI->clearFlag(MachineInstr::BundledPred);
1330  MI->clearFlag(MachineInstr::BundledSucc);
1331  return Insts.remove(MI);
1332 }
1333 
1336  assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
1337  "Cannot insert instruction with bundle flags");
1338  // Set the bundle flags when inserting inside a bundle.
1339  if (I != instr_end() && I->isBundledWithPred()) {
1340  MI->setFlag(MachineInstr::BundledPred);
1341  MI->setFlag(MachineInstr::BundledSucc);
1342  }
1343  return Insts.insert(I, MI);
1344 }
1345 
1346 /// This method unlinks 'this' from the containing function, and returns it, but
1347 /// does not delete it.
1349  assert(getParent() && "Not embedded in a function!");
1350  getParent()->remove(this);
1351  return this;
1352 }
1353 
1354 /// This method unlinks 'this' from the containing function, and deletes it.
1356  assert(getParent() && "Not embedded in a function!");
1357  getParent()->erase(this);
1358 }
1359 
1360 /// Given a machine basic block that branched to 'Old', change the code and CFG
1361 /// so that it branches to 'New' instead.
1363  MachineBasicBlock *New) {
1364  assert(Old != New && "Cannot replace self with self!");
1365 
1367  while (I != instr_begin()) {
1368  --I;
1369  if (!I->isTerminator()) break;
1370 
1371  // Scan the operands of this machine instruction, replacing any uses of Old
1372  // with New.
1373  for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1374  if (I->getOperand(i).isMBB() &&
1375  I->getOperand(i).getMBB() == Old)
1376  I->getOperand(i).setMBB(New);
1377  }
1378 
1379  // Update the successor information.
1380  replaceSuccessor(Old, New);
1381 }
1382 
1384  MachineBasicBlock *New) {
1385  for (MachineInstr &MI : phis())
1386  for (unsigned i = 2, e = MI.getNumOperands() + 1; i != e; i += 2) {
1387  MachineOperand &MO = MI.getOperand(i);
1388  if (MO.getMBB() == Old)
1389  MO.setMBB(New);
1390  }
1391 }
1392 
1393 /// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE
1394 /// instructions. Return UnknownLoc if there is none.
1395 DebugLoc
1397  // Skip debug declarations, we don't want a DebugLoc from them.
1399  if (MBBI != instr_end())
1400  return MBBI->getDebugLoc();
1401  return {};
1402 }
1403 
1405  // Skip debug declarations, we don't want a DebugLoc from them.
1407  if (!MBBI->isDebugInstr())
1408  return MBBI->getDebugLoc();
1409  return {};
1410 }
1411 
1412 /// Find the previous valid DebugLoc preceding MBBI, skipping and DBG_VALUE
1413 /// instructions. Return UnknownLoc if there is none.
1415  if (MBBI == instr_begin()) return {};
1416  // Skip debug instructions, we don't want a DebugLoc from them.
1418  if (!MBBI->isDebugInstr()) return MBBI->getDebugLoc();
1419  return {};
1420 }
1421 
1423  if (MBBI == instr_rend())
1424  return {};
1425  // Skip debug declarations, we don't want a DebugLoc from them.
1427  if (MBBI != instr_rend())
1428  return MBBI->getDebugLoc();
1429  return {};
1430 }
1431 
1432 /// Find and return the merged DebugLoc of the branch instructions of the block.
1433 /// Return UnknownLoc if there is none.
1434 DebugLoc
1436  DebugLoc DL;
1437  auto TI = getFirstTerminator();
1438  while (TI != end() && !TI->isBranch())
1439  ++TI;
1440 
1441  if (TI != end()) {
1442  DL = TI->getDebugLoc();
1443  for (++TI ; TI != end() ; ++TI)
1444  if (TI->isBranch())
1445  DL = DILocation::getMergedLocation(DL, TI->getDebugLoc());
1446  }
1447  return DL;
1448 }
1449 
1450 /// Return probability of the edge from this block to MBB.
1452 MachineBasicBlock::getSuccProbability(const_succ_iterator Succ) const {
1453  if (Probs.empty())
1454  return BranchProbability(1, succ_size());
1455 
1456  const auto &Prob = *getProbabilityIterator(Succ);
1457  if (Prob.isUnknown()) {
1458  // For unknown probabilities, collect the sum of all known ones, and evenly
1459  // ditribute the complemental of the sum to each unknown probability.
1460  unsigned KnownProbNum = 0;
1461  auto Sum = BranchProbability::getZero();
1462  for (auto &P : Probs) {
1463  if (!P.isUnknown()) {
1464  Sum += P;
1465  KnownProbNum++;
1466  }
1467  }
1468  return Sum.getCompl() / (Probs.size() - KnownProbNum);
1469  } else
1470  return Prob;
1471 }
1472 
1473 /// Set successor probability of a given iterator.
1475  BranchProbability Prob) {
1476  assert(!Prob.isUnknown());
1477  if (Probs.empty())
1478  return;
1479  *getProbabilityIterator(I) = Prob;
1480 }
1481 
1482 /// Return probability iterator corresonding to the I successor iterator
1483 MachineBasicBlock::const_probability_iterator
1484 MachineBasicBlock::getProbabilityIterator(
1486  assert(Probs.size() == Successors.size() && "Async probability list!");
1487  const size_t index = std::distance(Successors.begin(), I);
1488  assert(index < Probs.size() && "Not a current successor!");
1489  return Probs.begin() + index;
1490 }
1491 
1492 /// Return probability iterator corresonding to the I successor iterator.
1493 MachineBasicBlock::probability_iterator
1494 MachineBasicBlock::getProbabilityIterator(MachineBasicBlock::succ_iterator I) {
1495  assert(Probs.size() == Successors.size() && "Async probability list!");
1496  const size_t index = std::distance(Successors.begin(), I);
1497  assert(index < Probs.size() && "Not a current successor!");
1498  return Probs.begin() + index;
1499 }
1500 
1501 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1502 /// as of just before "MI".
1503 ///
1504 /// Search is localised to a neighborhood of
1505 /// Neighborhood instructions before (searching for defs or kills) and N
1506 /// instructions after (searching just for defs) MI.
1509  MCRegister Reg, const_iterator Before,
1510  unsigned Neighborhood) const {
1511  unsigned N = Neighborhood;
1512 
1513  // Try searching forwards from Before, looking for reads or defs.
1514  const_iterator I(Before);
1515  for (; I != end() && N > 0; ++I) {
1516  if (I->isDebugInstr())
1517  continue;
1518 
1519  --N;
1520 
1522 
1523  // Register is live when we read it here.
1524  if (Info.Read)
1525  return LQR_Live;
1526  // Register is dead if we can fully overwrite or clobber it here.
1527  if (Info.FullyDefined || Info.Clobbered)
1528  return LQR_Dead;
1529  }
1530 
1531  // If we reached the end, it is safe to clobber Reg at the end of a block of
1532  // no successor has it live in.
1533  if (I == end()) {
1534  for (MachineBasicBlock *S : successors()) {
1535  for (const MachineBasicBlock::RegisterMaskPair &LI : S->liveins()) {
1536  if (TRI->regsOverlap(LI.PhysReg, Reg))
1537  return LQR_Live;
1538  }
1539  }
1540 
1541  return LQR_Dead;
1542  }
1543 
1544 
1545  N = Neighborhood;
1546 
1547  // Start by searching backwards from Before, looking for kills, reads or defs.
1548  I = const_iterator(Before);
1549  // If this is the first insn in the block, don't search backwards.
1550  if (I != begin()) {
1551  do {
1552  --I;
1553 
1554  if (I->isDebugInstr())
1555  continue;
1556 
1557  --N;
1558 
1560 
1561  // Defs happen after uses so they take precedence if both are present.
1562 
1563  // Register is dead after a dead def of the full register.
1564  if (Info.DeadDef)
1565  return LQR_Dead;
1566  // Register is (at least partially) live after a def.
1567  if (Info.Defined) {
1568  if (!Info.PartialDeadDef)
1569  return LQR_Live;
1570  // As soon as we saw a partial definition (dead or not),
1571  // we cannot tell if the value is partial live without
1572  // tracking the lanemasks. We are not going to do this,
1573  // so fall back on the remaining of the analysis.
1574  break;
1575  }
1576  // Register is dead after a full kill or clobber and no def.
1577  if (Info.Killed || Info.Clobbered)
1578  return LQR_Dead;
1579  // Register must be live if we read it.
1580  if (Info.Read)
1581  return LQR_Live;
1582 
1583  } while (I != begin() && N > 0);
1584  }
1585 
1586  // If all the instructions before this in the block are debug instructions,
1587  // skip over them.
1588  while (I != begin() && std::prev(I)->isDebugInstr())
1589  --I;
1590 
1591  // Did we get to the start of the block?
1592  if (I == begin()) {
1593  // If so, the register's state is definitely defined by the live-in state.
1594  for (const MachineBasicBlock::RegisterMaskPair &LI : liveins())
1595  if (TRI->regsOverlap(LI.PhysReg, Reg))
1596  return LQR_Live;
1597 
1598  return LQR_Dead;
1599  }
1600 
1601  // At this point we have no idea of the liveness of the register.
1602  return LQR_Unknown;
1603 }
1604 
1605 const uint32_t *
1607  // EH funclet entry does not preserve any registers.
1608  return isEHFuncletEntry() ? TRI->getNoPreservedMask() : nullptr;
1609 }
1610 
1611 const uint32_t *
1613  // If we see a return block with successors, this must be a funclet return,
1614  // which does not preserve any registers. If there are no successors, we don't
1615  // care what kind of return it is, putting a mask after it is a no-op.
1616  return isReturnBlock() && !succ_empty() ? TRI->getNoPreservedMask() : nullptr;
1617 }
1618 
1620  LiveIns.clear();
1621 }
1622 
1624  assert(getParent()->getProperties().hasProperty(
1626  "Liveness information is accurate");
1627  return LiveIns.begin();
1628 }
1629 
1631 const MBBSectionID
1632  MBBSectionID::ExceptionSectionID(MBBSectionID::SectionType::Exception);
llvm::TargetMachine::requiresStructuredCFG
bool requiresStructuredCFG() const
Definition: TargetMachine.h:213
llvm::LaneBitmask
Definition: LaneBitmask.h:39
llvm::SuccIterator
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i
i
Definition: README.txt:29
llvm::MachineBasicBlock::RegisterMaskPair::PhysReg
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unsigned succ_size() const
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MI
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Definition: IRTranslator.cpp:100
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
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llvm::ModuleSlotTracker::getLocalSlot
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
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llvm::MCSymbol
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Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
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Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:572
llvm::MachineBasicBlock::LivenessQueryResult
LivenessQueryResult
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Definition: MachineBasicBlock.h:926
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:202
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
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Definition: MachineRegisterInfo.cpp:158
llvm::HexagonInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
Definition: HexagonInstrInfo.cpp:561
llvm::DILocation::getMergedLocation
static const DILocation * getMergedLocation(const DILocation *LocA, const DILocation *LocB)
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Definition: DebugInfoMetadata.cpp:93
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Definition: CommandLine.h:161
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Definition: MachineRegisterInfo.h:52
llvm::MachineBasicBlock::ReplaceUsesOfBlockWith
void ReplaceUsesOfBlockWith(MachineBasicBlock *Old, MachineBasicBlock *New)
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Definition: MachineBasicBlock.cpp:1362
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:71
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Definition: Function.h:61
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition: MachineFunction.h:507
llvm::BranchProbability::getNumerator
uint32_t getNumerator() const
Definition: BranchProbability.h:65
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
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virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::HexagonInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition: HexagonInstrInfo.cpp:391
llvm::MachineBasicBlock::instrs
instr_range instrs()
Definition: MachineBasicBlock.h:263
llvm::MachineBasicBlock::isEHFuncletEntry
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
Definition: MachineBasicBlock.h:461
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Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
Definition: LiveVariables.h:89
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MachineBasicBlock * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:288
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This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
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iterator end()
Definition: MachineFunction.h:739
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:118
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This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
llvm::MachineBasicBlock::isEntryBlock
bool isEntryBlock() const
Returns true if this is the entry block of the function.
Definition: MachineBasicBlock.cpp:287
llvm::MachineBasicBlock::setSuccProbability
void setSuccProbability(succ_iterator I, BranchProbability Prob)
Set successor probability of a given iterator.
Definition: MachineBasicBlock.cpp:1474
llvm::MachineFunction::getFunctionNumber
unsigned getFunctionNumber() const
getFunctionNumber - Return a unique ID for the current function.
Definition: MachineFunction.h:530
llvm::MachineBasicBlock::getEHCatchretSymbol
MCSymbol * getEHCatchretSymbol() const
Return the EHCatchret Symbol for this basic block.
Definition: MachineBasicBlock.cpp:90
MachineBasicBlock.h
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Definition: LivePhysRegs.h:48
llvm::MachineBasicBlock::isReturnBlock
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
Definition: MachineBasicBlock.h:714
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virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
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@ Hidden
Definition: CommandLine.h:140
llvm::MachineBasicBlock::findDebugLoc
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
Definition: MachineBasicBlock.cpp:1396
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Definition: TargetRegisterInfo.h:231
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Definition: MachineBasicBlock.h:398
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Decrement It, then continue decrementing it while it points to a debug instruction.
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Move 'this' block before or after the specified block.
Definition: MachineBasicBlock.cpp:630
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static BranchProbability getZero()
Definition: BranchProbability.h:49
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iterator_range< livein_iterator > liveins() const
Definition: MachineBasicBlock.h:412
TargetInstrInfo.h
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Definition: MachineBasicBlock.h:59
llvm::HexagonInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
Definition: HexagonInstrInfo.cpp:1580
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Definition: MachineFunction.h:756
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
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Since we know that Vector is byte aligned and we know the element offset of we should change the load into a lve *x instead of doing a load store lve *x sequence Implement passing vectors by value into calls and receiving them as arguments GCC apparently tries to then a load and vperm of Variable We need a way to teach tblgen that some operands of an intrinsic are required to be constants The verifier should enforce this constraint We currently codegen SCALAR_TO_VECTOR as a store of the scalar to a byte aligned stack slot
Definition: README_ALTIVEC.txt:57
llvm::MachineBasicBlock::getFirstNonDebugInstr
iterator getFirstNonDebugInstr(bool SkipPseudoOp=false)
Returns an iterator to the first non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:258
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unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:757
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pointer remove(iterator &IT)
Definition: ilist.h:251
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::addLiveIns
void addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs)
Adds registers contained in LiveRegs to the block live-in list of MBB.
Definition: LivePhysRegs.cpp:253
llvm::ModuleSlotTracker::incorporateFunction
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:892
llvm::MachineBasicBlock::back
MachineInstr & back()
Definition: MachineBasicBlock.h:248
llvm::MachineBasicBlock::addSuccessorWithoutProb
void addSuccessorWithoutProb(MachineBasicBlock *Succ)
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:753
llvm::MBBSectionID
Definition: MachineBasicBlock.h:52
llvm::MachineBasicBlock::copySuccessor
void copySuccessor(MachineBasicBlock *Orig, succ_iterator I)
Copy a successor (and any probability info) from original block to this block's.
Definition: MachineBasicBlock.cpp:844
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unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:29
llvm::LegalityPredicates::any
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
Definition: LegalizerInfo.h:209
llvm::AnalyzePhysRegInBundle
PhysRegInfo AnalyzePhysRegInBundle(const MachineInstr &MI, Register Reg, const TargetRegisterInfo *TRI)
AnalyzePhysRegInBundle - Analyze how the current instruction or bundle uses a physical register.
Definition: MachineInstrBundle.cpp:308
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#define LLVM_DEBUG(X)
Definition: Debug.h:122
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::MachineLoopInfo
Definition: MachineLoopInfo.h:90
MachineRegisterInfo.h
llvm::iplist_impl::erase
iterator erase(iterator where)
Definition: ilist.h:267
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::MachineBasicBlock::dump
void dump() const
Definition: MachineBasicBlock.cpp:292
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1322
llvm::MachineBasicBlock::isBeginSection
bool isBeginSection() const
Returns true if this block begins any section.
Definition: MachineBasicBlock.h:473
llvm::MachineRegisterInfo::tracksLiveness
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
Definition: MachineRegisterInfo.h:197
llvm::MachineBasicBlock::const_iterator
MachineInstrBundleIterator< const MachineInstr > const_iterator
Definition: MachineBasicBlock.h:234
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::MachineBasicBlock::printName
void printName(raw_ostream &os, unsigned printNameFlags=PrintNameIr, ModuleSlotTracker *moduleSlotTracker=nullptr) const
Print the basic block's name as:
Definition: MachineBasicBlock.cpp:475
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static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
Definition: SIOptimizeExecMasking.cpp:286
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:743
PrintSlotIndexes
static cl::opt< bool > PrintSlotIndexes("print-slotindexes", cl::desc("When printing machine IR, annotate instructions and blocks with " "SlotIndexes when available"), cl::init(true), cl::Hidden)
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:59
llvm::SparseBitVector
Definition: SparseBitVector.h:255
bb
< i1 > br i1 label label bb bb
Definition: README.txt:978
llvm::MachineBasicBlock::getFirstInstrTerminator
instr_iterator getFirstInstrTerminator()
Same getFirstTerminator but it ignores bundles and return an instr_iterator instead.
Definition: MachineBasicBlock.cpp:248
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:157
llvm::LiveVariables::VarInfo::removeKill
bool removeKill(MachineInstr &MI)
removeKill - Delete a kill corresponding to the specified machine instruction.
Definition: LiveVariables.h:94
llvm::SlotIndexes::hasIndex
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:380
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineBasicBlock::removeFromParent
MachineBasicBlock * removeFromParent()
This method unlinks 'this' from the containing function, and returns it, but does not delete it.
Definition: MachineBasicBlock.cpp:1348
MachineLoopInfo.h
llvm::skipDebugInstructionsBackward
IterT skipDebugInstructionsBackward(IterT It, IterT Begin, bool SkipPseudoOp=false)
Decrement It until it points to a non-debug instruction or to Begin and return the resulting iterator...
Definition: MachineBasicBlock.h:1128
llvm::LiveRange::liveAt
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:393
TargetMachine.h
llvm::BranchProbability::getDenominator
static uint32_t getDenominator()
Definition: BranchProbability.h:66
llvm::LiveIntervals::getMBBStartIdx
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
Definition: LiveIntervals.h:236
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::PseudoProbeAttributes::Dangling
@ Dangling
llvm::MachineBasicBlock::succ_end
succ_iterator succ_end()
Definition: MachineBasicBlock.h:334
llvm::LiveRange::addSegment
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
Definition: LiveInterval.cpp:548
MCContext.h
llvm::MachineBasicBlock::isSuccessor
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
Definition: MachineBasicBlock.cpp:931
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MachineBasicBlock::eraseFromParent
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Definition: MachineBasicBlock.cpp:1355
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::LivePhysRegs::addLiveOuts
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
Definition: LivePhysRegs.cpp:230
LiveVariables.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineBasicBlock::isLegalToHoistInto
bool isLegalToHoistInto() const
Returns true if it is legal to hoist instructions into this block.
Definition: MachineBasicBlock.cpp:305
llvm::MachineBasicBlock::RegisterMaskPair
Pair of physical register and lane mask.
Definition: MachineBasicBlock.h:101
llvm::MachineBasicBlock::splitAt
MachineBasicBlock * splitAt(MachineInstr &SplitInst, bool UpdateLiveIns=true, LiveIntervals *LIS=nullptr)
Split a basic block into 2 pieces at SplitPoint.
Definition: MachineBasicBlock.cpp:988
llvm::SlotIndexes::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:385
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
llvm::PrintLaneMask
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:93
llvm::HexagonInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
Definition: HexagonInstrInfo.cpp:584
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register regA, Register regB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:402
llvm::MachineFunction::addToMBBNumbering
unsigned addToMBBNumbering(MachineBasicBlock *MBB)
Adds the MBB to the internal numbering.
Definition: MachineFunction.h:792
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:737
llvm::SlotIndexes
SlotIndexes pass.
Definition: SlotIndexes.h:314
llvm::MachineBasicBlock::moveAndDanglePseudoProbes
void moveAndDanglePseudoProbes(MachineBasicBlock *ToMBB)
move all pseudo probes in this block to the end of /c ToMBB To and tag them dangling.
Definition: MachineBasicBlock.cpp:911
SmallPtrSet.h
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
llvm::BranchProbability::getUnknown
static BranchProbability getUnknown()
Definition: BranchProbability.h:51
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:49
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineBasicBlock::findPrevDebugLoc
DebugLoc findPrevDebugLoc(instr_iterator MBBI)
Find the previous valid DebugLoc preceding MBBI, skipping and DBG_VALUE instructions.
Definition: MachineBasicBlock.cpp:1414
llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:125
llvm::LiveIntervals::insertMBBInMaps
void insertMBBInMaps(MachineBasicBlock *MBB)
Definition: LiveIntervals.h:259
llvm::ilist_traits
Template traits for intrusive list.
Definition: ilist.h:89
llvm::MachineBasicBlock::succ_iterator
std::vector< MachineBasicBlock * >::iterator succ_iterator
Definition: MachineBasicBlock.h:306
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
BasicBlock.h
llvm::cl::opt< bool >
llvm::MachineBasicBlock::mayHaveInlineAsmBr
bool mayHaveInlineAsmBr() const
Returns true if this block may have an INLINEASM_BR (overestimate, by checking if any of the successo...
Definition: MachineBasicBlock.cpp:297
llvm::LiveVariables::addNewBlock
void addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB, MachineBasicBlock *SuccBB)
addNewBlock - Add a new basic block BB between DomBB and SuccBB.
Definition: LiveVariables.cpp:757
llvm::MachineLoop
Definition: MachineLoopInfo.h:45
llvm::LivePhysRegs::stepBackward
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
Definition: LivePhysRegs.cpp:68
llvm::MachineBasicBlock::printAsOperand
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
Definition: MachineBasicBlock.cpp:548
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:392
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
llvm::MachineInstrBundleIterator::getReverse
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Definition: MachineInstrBundleIterator.h:283
llvm::SlotIndexes::getMBBStartIdx
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:466
llvm::MachineBasicBlock::instr_rend
reverse_instr_iterator instr_rend()
Definition: MachineBasicBlock.h:258
llvm::MachineFunctionProperties::Property::TracksLiveness
@ TracksLiveness
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
index
splat index
Definition: README_ALTIVEC.txt:181
LiveIntervals.h
llvm::MCContext::getAsmInfo
const MCAsmInfo * getAsmInfo() const
Definition: MCContext.h:406
llvm::MachineBasicBlock::hasAddressTaken
bool hasAddressTaken() const
Test whether this block is potentially the target of an indirect branch.
Definition: MachineBasicBlock.h:211
llvm::find
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1525
llvm::MachineFunction::splice
void splice(iterator InsertPt, iterator MBBI)
Definition: MachineFunction.h:759
llvm::MachineBasicBlock::SkipPHIsAndLabels
iterator SkipPHIsAndLabels(iterator I)
Return the first instruction in MBB after I that is not a PHI or a label.
Definition: MachineBasicBlock.cpp:209
llvm::skipDebugInstructionsForward
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=false)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
Definition: MachineBasicBlock.h:1115
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:58
llvm::MachineBasicBlock::instr_rbegin
reverse_instr_iterator instr_rbegin()
Definition: MachineBasicBlock.h:256
llvm::MachineBasicBlock::LQR_Live
@ LQR_Live
Register is known to be (at least partially) live.
Definition: MachineBasicBlock.h:927
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
llvm::CallingConv::Cold
@ Cold
Definition: CallingConv.h:48
llvm::MachineBasicBlock::getFirstNonPHI
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Definition: MachineBasicBlock.cpp:199
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1570
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:414
llvm::MachineBasicBlock::getAlignment
Align getAlignment() const
Return alignment of the basic block.
Definition: MachineBasicBlock.h:428
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineBasicBlock::SkipPHIsLabelsAndDebug
iterator SkipPHIsLabelsAndDebug(iterator I)
Return the first instruction in MBB after I that is not a PHI, label or debug.
Definition: MachineBasicBlock.cpp:224
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:522
llvm::MBBSectionID::ExceptionSectionID
const static MBBSectionID ExceptionSectionID
Definition: MachineBasicBlock.h:65
llvm::BranchProbability::isUnknown
bool isUnknown() const
Definition: BranchProbability.h:47
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::canFallThrough
bool canFallThrough()
Return true if the block can implicitly transfer control to the block after it by falling off the end...
Definition: MachineBasicBlock.cpp:984
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:332
llvm::IndexedInstrProf::HashT::Last
@ Last
llvm::PhysRegInfo
Information about how a physical register Reg is used by a set of operands.
Definition: MachineInstrBundle.h:246
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineFunction::const_iterator
BasicBlockListType::const_iterator const_iterator
Definition: MachineFunction.h:720
llvm::MachineFunction::erase
void erase(iterator MBBI)
Definition: MachineFunction.h:771
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:98
llvm::MachineBasicBlock::livein_end
livein_iterator livein_end() const
Definition: MachineBasicBlock.h:410
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::MachineBasicBlock::predecessors
iterator_range< pred_iterator > predecessors()
Definition: MachineBasicBlock.h:349
llvm::MachineBasicBlock::reverse_instr_iterator
Instructions::reverse_iterator reverse_instr_iterator
Definition: MachineBasicBlock.h:230
llvm::MachineBasicBlock::LQR_Dead
@ LQR_Dead
Register is known to be fully dead.
Definition: MachineBasicBlock.h:928
llvm::MachineBasicBlock::instr_begin
instr_iterator instr_begin()
Definition: MachineBasicBlock.h:252
llvm::MachineBasicBlock::pred_empty
bool pred_empty() const
Definition: MachineBasicBlock.h:331
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
llvm::MachineBasicBlock::instr_end
instr_iterator instr_end()
Definition: MachineBasicBlock.h:254
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::MachineBasicBlock::moveAfter
void moveAfter(MachineBasicBlock *NewBefore)
Definition: MachineBasicBlock.cpp:634
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:347
llvm::MachineBasicBlock::PrintNameIr
@ PrintNameIr
Add IR name where available.
Definition: MachineBasicBlock.h:953
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:239
llvm::MachineBasicBlock::getBeginClobberMask
const uint32_t * getBeginClobberMask(const TargetRegisterInfo *TRI) const
Get the clobber mask for the start of this basic block.
Definition: MachineBasicBlock.cpp:1606
llvm::MachineBasicBlock::phis
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
Definition: MachineBasicBlock.h:296
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:549
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition: MachineBasicBlock.h:965
MCAsmInfo.h
DataLayout.h
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:167
llvm::MachineBasicBlock::PrintNameAttributes
@ PrintNameAttributes
Print attributes.
Definition: MachineBasicBlock.h:954
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:355
llvm::MachineBasicBlock::isEHPad
bool isEHPad() const
Returns true if the block is a landing pad.
Definition: MachineBasicBlock.h:435
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineBasicBlock::rbegin
reverse_iterator rbegin()
Definition: MachineBasicBlock.h:272
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:859
llvm::MachineBasicBlock::hasEHPadSuccessor
bool hasEHPadSuccessor() const
Definition: MachineBasicBlock.cpp:280
llvm::LivePhysRegs::init
void init(const TargetRegisterInfo &TRI)
(re-)initializes and clears the set.
Definition: LivePhysRegs.h:66
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=false)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:264
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineBasicBlock::getFullName
std::string getFullName() const
Return a formatted string to identify this block and its parent function.
Definition: MachineBasicBlock.cpp:319
llvm::MachineBasicBlock::findBranchDebugLoc
DebugLoc findBranchDebugLoc()
Find and return the merged DebugLoc of the branch instructions of the block.
Definition: MachineBasicBlock.cpp:1435
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MachineBasicBlock::removeLiveIn
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
Definition: MachineBasicBlock.cpp:554
llvm::MBBSectionID::Type
enum llvm::MBBSectionID::SectionType Type
llvm::MachineBasicBlock::rfindDebugLoc
DebugLoc rfindDebugLoc(reverse_instr_iterator MBBI)
Has exact same behavior as findDebugLoc (it also searches from the first to the last MI of this MBB) ...
Definition: MachineBasicBlock.cpp:1404
Number
uint32_t Number
Definition: Profile.cpp:47
llvm::ilist_callback_traits::addNodeToList
void addNodeToList(NodeTy *)
When an MBB is added to an MF, we need to update the parent pointer of the MBB, the MBB numbering,...
Definition: ilist.h:65
uint32_t
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineBasicBlock, Options... >::type >::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MachineFunction::hasBBSections
bool hasBBSections() const
Returns true if this function has basic block sections enabled.
Definition: MachineFunction.h:533
llvm::MachineBasicBlock::splitSuccessor
void splitSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New, bool NormalizeSuccProbs=false)
Split the old successor into old plus new and updates the probability info.
Definition: MachineBasicBlock.cpp:762
llvm::format
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
llvm::PredIterator
Definition: CFG.h:43
llvm::Value::getName
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:298
llvm::MachineBasicBlock::transferSuccessors
void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
Definition: MachineBasicBlock.cpp:862
llvm::MachineBasicBlock::getSectionID
MBBSectionID getSectionID() const
Returns the section ID of this basic block.
Definition: MachineBasicBlock.h:483
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::MachineBasicBlock::isPredecessor
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
Definition: MachineBasicBlock.cpp:927
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1532
llvm::MachineBasicBlock::getEndSymbol
MCSymbol * getEndSymbol() const
Returns the MCSymbol marking the end of this basic block.
Definition: MachineBasicBlock.cpp:101
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineBasicBlock::canSplitCriticalEdge
bool canSplitCriticalEdge(const MachineBasicBlock *Succ) const
Check if the edge between this block and the given successor Succ, can be split.
Definition: MachineBasicBlock.cpp:1268
llvm::AMDGPU::HSAMD::Kernel::Key::SymbolName
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
Definition: AMDGPUMetadata.h:381
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
llvm::MachineBasicBlock::replaceSuccessor
void replaceSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New)
Replace successor OLD with NEW and update probability info.
Definition: MachineBasicBlock.cpp:804
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::MachineBasicBlock::replacePhiUsesWith
void replacePhiUsesWith(MachineBasicBlock *Old, MachineBasicBlock *New)
Update all phi nodes in this basic block to refer to basic block New instead of basic block Old.
Definition: MachineBasicBlock.cpp:1383
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::MachineBasicBlock::sortUniqueLiveIns
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
Definition: MachineBasicBlock.cpp:578
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:551
llvm::MachineBasicBlock::removeSuccessor
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:781
llvm::MBBSectionID::ColdSectionID
const static MBBSectionID ColdSectionID
Definition: MachineBasicBlock.h:64
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1335
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::MachineBasicBlock::computeRegisterLiveness
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, MCRegister Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been defined and not killed as of just before Before.
Definition: MachineBasicBlock.cpp:1508
llvm::SlotIndex::getPrevSlot
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:289
llvm::MachineBasicBlock::instr_iterator
Instructions::iterator instr_iterator
Definition: MachineBasicBlock.h:228
llvm::AArch64CC::LS
@ LS
Definition: AArch64BaseInfo.h:245
llvm::MCAsmInfo::getPrivateLabelPrefix
StringRef getPrivateLabelPrefix() const
Definition: MCAsmInfo.h:584
llvm::next_nodbg
IterT next_nodbg(IterT It, IterT End, bool SkipPseudoOp=false)
Increment It, then continue incrementing it while it points to a debug instruction.
Definition: MachineBasicBlock.h:1139
llvm::ilist_callback_traits::removeNodeFromList
void removeNodeFromList(NodeTy *)
Definition: ilist.h:66
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:247
llvm::sort
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:1446
llvm::MachineBasicBlock::livein_begin
livein_iterator livein_begin() const
Definition: MachineBasicBlock.cpp:1623
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::LiveRange::getVNInfoAt
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:413
unbundleSingleMI
static void unbundleSingleMI(MachineInstr *MI)
Prepare MI to be removed from its bundle.
Definition: MachineBasicBlock.cpp:1310
llvm::MachineBasicBlock::isLayoutSuccessor
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
Definition: MachineBasicBlock.cpp:935
llvm::MachineBasicBlock::rfindPrevDebugLoc
DebugLoc rfindPrevDebugLoc(reverse_instr_iterator MBBI)
Has exact same behavior as findPrevDebugLoc (it also searches from the last to the first MI of this M...
Definition: MachineBasicBlock.cpp:1422
llvm::MachineBasicBlock::normalizeSuccProbs
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
Definition: MachineBasicBlock.h:563
llvm::TargetRegisterInfo::getNoPreservedMask
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
Definition: TargetRegisterInfo.h:485
llvm::MachineBasicBlock::livein_empty
bool livein_empty() const
Definition: MachineBasicBlock.h:411
llvm::MachineBasicBlock::getFallThrough
MachineBasicBlock * getFallThrough()
Return the fallthrough block if the block can implicitly transfer control to the block after it by fa...
Definition: MachineBasicBlock.cpp:940
llvm::LiveRange::removeSegment
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
Definition: LiveInterval.cpp:583
llvm::iplist_impl::insert
iterator insert(iterator where, pointer New)
Definition: ilist.h:228
llvm::MachineBasicBlock::validateSuccProbs
void validateSuccProbs() const
Validate successors' probabilities and check if the sum of them is approximate one.
Definition: MachineBasicBlock.cpp:729
llvm::MachineBasicBlock::getEndClobberMask
const uint32_t * getEndClobberMask(const TargetRegisterInfo *TRI) const
Get the clobber mask for the end of the basic block.
Definition: MachineBasicBlock.cpp:1612
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::HexagonInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
Definition: HexagonInstrInfo.cpp:1547
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::MachineBasicBlock::isInlineAsmBrIndirectTarget
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
Definition: MachineBasicBlock.h:503
llvm::raw_ostream::indent
raw_ostream & indent(unsigned NumSpaces)
indent - Insert 'NumSpaces' spaces.
Definition: raw_ostream.cpp:497
llvm::ilist_alloc_traits::deleteNode
static void deleteNode(NodeTy *V)
Definition: ilist.h:41
llvm::Printable
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:37
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:329
N
#define N
llvm::MachineInstr::BundledSucc
@ BundledSucc
Definition: MachineInstr.h:87
llvm::LiveVariables::getVarInfo
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
Definition: LiveVariables.cpp:84
llvm::MachineOperand::setMBB
void setMBB(MachineBasicBlock *MBB)
Definition: MachineOperand.h:686
llvm::MachineBasicBlock::const_succ_iterator
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
Definition: MachineBasicBlock.h:307
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:647
llvm::MachineBasicBlock::clearLiveIns
void clearLiveIns()
Clear live in list.
Definition: MachineBasicBlock.cpp:1619
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:85
ModuleSlotTracker.h
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:882
DataTypes.h
llvm::LiveIntervals::repairIntervalsInRange
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< Register > OrigRegs)
Update live intervals for instructions in a range of iterators.
Definition: LiveIntervals.cpp:1657
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::LiveVariables
Definition: LiveVariables.h:46
llvm::MachineBasicBlock::LQR_Unknown
@ LQR_Unknown
Register liveness not decidable from local neighborhood.
Definition: MachineBasicBlock.h:929
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:125
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineBasicBlock::print
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
Definition: MachineBasicBlock.cpp:330
SlotIndexes.h
llvm::cl::desc
Definition: CommandLine.h:411
llvm::ilist_callback_traits::transferNodesFromList
void transferNodesFromList(ilist_callback_traits &OldList, Iterator, Iterator)
Callback before transferring nodes to this list.
Definition: ilist.h:71
llvm::MachineBasicBlock::updateTerminator
void updateTerminator(MachineBasicBlock *PreviousLayoutSuccessor)
Update the terminator instructions in block to account for changes to block layout which may have bee...
Definition: MachineBasicBlock.cpp:638
raw_ostream.h
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineInstr::BundledPred
@ BundledPred
Definition: MachineInstr.h:86
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1272
llvm::MachineBasicBlock::SplitCriticalEdge
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P, std::vector< SparseBitVector<>> *LiveInSets=nullptr)
Split the critical edge from this block to the given successor block, and return the newly created bl...
Definition: MachineBasicBlock.cpp:1029
llvm::MCID::Terminator
@ Terminator
Definition: MCInstrDesc.h:156
llvm::MachineBasicBlock::remove_instr
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
Definition: MachineBasicBlock.cpp:1327
TargetRegisterInfo.h
llvm::MachineBasicBlock::getName
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
Definition: MachineBasicBlock.cpp:311
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::Optional::getValue
constexpr const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:280
MachineDominators.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22