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27 #include "llvm/Config/llvm-config.h"
39 #define DEBUG_TYPE "codegen"
43 cl::desc(
"When printing machine IR, annotate instructions and blocks with "
44 "SlotIndexes when available"),
51 IrrLoopHeaderWeight =
B->getIrrLoopHeaderWeight();
54 MachineBasicBlock::~MachineBasicBlock() =
default;
57 MCSymbol *MachineBasicBlock::getSymbol()
const {
58 if (!CachedMCSymbol) {
85 return CachedMCSymbol;
89 if (!CachedEHCatchretMCSymbol) {
96 return CachedEHCatchretMCSymbol;
100 if (!CachedEndMCSymbol) {
108 return CachedEndMCSymbol;
135 MI.addRegOperandsToUseLists(RegInfo);
140 N->getParent()->removeFromMBBNumbering(
N->Number);
147 assert(!
N->getParent() &&
"machine instruction already in a basic block");
148 N->setParent(Parent);
154 MF->handleInsertion(*
N);
160 assert(
N->getParent() &&
"machine instruction not in a basic block");
164 MF->handleRemoval(*
N);
165 N->removeRegOperandsFromUseLists(MF->
getRegInfo());
168 N->setParent(
nullptr);
174 instr_iterator First,
175 instr_iterator Last) {
176 assert(Parent->getParent() == FromList.Parent->getParent() &&
177 "cannot transfer MachineInstrs between MachineFunctions");
180 if (
this == &FromList)
183 assert(Parent != FromList.Parent &&
"Two lists have the same parent?");
188 First->setParent(Parent);
192 assert(!
MI->getParent() &&
"MI is still in a block!");
193 Parent->getParent()->deleteMachineInstr(
MI);
198 while (
I !=
E &&
I->isPHI())
200 assert((
I ==
E || !
I->isInsideBundle()) &&
201 "First non-phi MI cannot be inside a bundle!");
210 while (
I !=
E && (
I->isPHI() ||
I->isPosition() ||
211 TII->isBasicBlockPrologue(*
I)))
215 assert((
I ==
E || !
I->isInsideBundle()) &&
216 "First non-phi / non-label instruction is inside a bundle!");
226 while (
I !=
E && (
I->isPHI() ||
I->isPosition() ||
I->isDebugInstr() ||
227 (SkipPseudoOp &&
I->isPseudoProbe()) ||
228 TII->isBasicBlockPrologue(*
I)))
232 assert((
I ==
E || !
I->isInsideBundle()) &&
233 "First non-phi / non-label / non-debug "
234 "instruction is inside a bundle!");
240 while (
I !=
B && ((--
I)->isTerminator() ||
I->isDebugInstr()))
242 while (
I !=
E && !
I->isTerminator())
249 while (
I !=
B && ((--
I)->isTerminator() ||
I->isDebugInstr()))
251 while (
I !=
E && !
I->isTerminator())
269 if (
I->isDebugInstr() ||
I->isInsideBundle())
271 if (SkipPseudoOp &&
I->isPseudoProbe())
290 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
298 if (Succ->isInlineAsmBrIndirectTarget())
312 return LBB->getName();
330 bool IsStandalone)
const {
333 OS <<
"Can't print out MachineBasicBlock because parent MachineFunction"
341 print(OS, MST, Indexes, IsStandalone);
346 bool IsStandalone)
const {
349 OS <<
"Can't print out MachineBasicBlock because parent MachineFunction"
363 bool HasLineAttributes =
false;
367 if (Indexes) OS <<
'\t';
369 OS <<
"; predecessors: ";
374 HasLineAttributes =
true;
378 if (Indexes) OS <<
'\t';
380 OS.
indent(2) <<
"successors: ";
389 if (!Probs.empty() && IsStandalone) {
405 HasLineAttributes =
true;
409 if (Indexes) OS <<
'\t';
410 OS.
indent(2) <<
"liveins: ";
413 for (
const auto &LI :
liveins()) {
415 if (!LI.LaneMask.all())
418 HasLineAttributes =
true;
421 if (HasLineAttributes)
424 bool IsInBundle =
false;
432 if (IsInBundle && !
MI.isInsideBundle()) {
437 OS.
indent(IsInBundle ? 4 : 2);
438 MI.
print(OS, MST, IsStandalone,
false,
false,
451 if (IrrLoopHeaderWeight && IsStandalone) {
452 if (Indexes) OS <<
'\t';
453 OS.
indent(2) <<
"; Irreducible loop header weight: "
454 << IrrLoopHeaderWeight.
getValue() <<
'\n';
477 bool hasAttributes =
false;
482 os <<
'.' <<
bb->getName();
484 hasAttributes =
true;
489 if (moduleSlotTracker) {
491 }
else if (
bb->getParent()) {
498 os <<
"<ir-block badref>";
507 os << (hasAttributes ?
", " :
" (");
508 os <<
"address-taken";
509 hasAttributes =
true;
512 os << (hasAttributes ?
", " :
" (");
514 hasAttributes =
true;
517 os << (hasAttributes ?
", " :
" (");
518 os <<
"inlineasm-br-indirect-target";
519 hasAttributes =
true;
522 os << (hasAttributes ?
", " :
" (");
523 os <<
"ehfunclet-entry";
524 hasAttributes =
true;
527 os << (hasAttributes ?
", " :
" (");
529 hasAttributes =
true;
532 os << (hasAttributes ?
", " :
" (");
535 case MBBSectionID::SectionType::Exception:
544 hasAttributes =
true;
561 if (
I == LiveIns.end())
564 I->LaneMask &= ~LaneMask;
565 if (
I->LaneMask.none())
572 LiveInVector::iterator LI = LiveIns.begin() + (
I - LiveIns.begin());
573 return LiveIns.erase(LI);
588 LiveInVector::const_iterator
I = LiveIns.begin();
589 LiveInVector::const_iterator J;
590 LiveInVector::iterator Out = LiveIns.begin();
591 for (;
I != LiveIns.end(); ++Out,
I = J) {
594 for (J = std::next(
I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J)
595 LaneMask |= J->LaneMask;
596 Out->PhysReg = PhysReg;
597 Out->LaneMask = LaneMask;
599 LiveIns.erase(Out, LiveIns.end());
606 assert(RC &&
"Register class is required");
608 "Only the entry block and landing pads can have physreg live ins");
617 for (;
I !=
E &&
I->isCopy(); ++
I)
618 if (
I->getOperand(1).getReg() == PhysReg) {
619 Register VirtReg =
I->getOperand(0).getReg();
657 assert(!
B &&
"UpdateTerminators requires analyzable predecessors!");
672 if (!PreviousLayoutSuccessor || !
isSuccessor(PreviousLayoutSuccessor) ||
673 PreviousLayoutSuccessor->
isEHPad())
701 assert(PreviousLayoutSuccessor);
705 if (PreviousLayoutSuccessor == TBB) {
736 for (
auto Prob : Probs)
737 Sum += Prob.getNumerator();
743 "The sum of successors's probabilities exceeds one.");
751 if (!(Probs.empty() && !Successors.empty()))
752 Probs.push_back(Prob);
753 Successors.push_back(Succ);
754 Succ->addPredecessor(
this);
762 Successors.push_back(Succ);
763 Succ->addPredecessor(
this);
768 bool NormalizeSuccProbs) {
770 assert(OldI !=
succ_end() &&
"Old is not a successor of this block!");
772 "New is already a successor of this block!");
780 : *getProbabilityIterator(OldI));
781 if (NormalizeSuccProbs)
786 bool NormalizeSuccProbs) {
793 assert(
I != Successors.end() &&
"Not a current successor!");
797 if (!Probs.empty()) {
798 probability_iterator WI = getProbabilityIterator(
I);
800 if (NormalizeSuccProbs)
804 (*I)->removePredecessor(
this);
805 return Successors.erase(
I);
828 assert(OldI !=
E &&
"Old is not a successor of this block");
832 Old->removePredecessor(
this);
833 New->addPredecessor(
this);
840 if (!Probs.empty()) {
841 auto ProbIter = getProbabilityIterator(NewI);
842 if (!ProbIter->isUnknown())
843 *ProbIter += *getProbabilityIterator(OldI);
850 if (!Orig->Probs.empty())
857 Predecessors.push_back(Pred);
862 assert(
I != Predecessors.end() &&
"Pred is not a predecessor of this block!");
863 Predecessors.erase(
I);
875 if (!FromMBB->Probs.empty()) {
876 auto Prob = *FromMBB->Probs.begin();
892 if (!FromMBB->Probs.empty()) {
893 auto Prob = *FromMBB->Probs.begin();
945 if (!TBB)
return &*Fallthrough;
951 return &*Fallthrough;
955 if (
Cond.empty())
return nullptr;
959 return (FBB ==
nullptr) ? &*Fallthrough :
nullptr;
972 if (SplitPoint ==
end()) {
1028 Indexes->insertMBBInMaps(NMBB);
1041 if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse() || !MO.isKill() ||
1047 KilledRegs.push_back(
Reg);
1049 MO.setIsKill(
false);
1059 if (!MO.isReg() || MO.getReg() == 0)
1064 UsedRegs.push_back(
Reg);
1077 Terminators.push_back(&
MI);
1082 if (Succ == PrevFallthrough)
1083 PrevFallthrough = NMBB;
1090 NewTerminators.push_back(&
MI);
1094 Indexes->removeMachineInstrFromMaps(*
Terminator);
1109 if (Indexes->hasIndex(
MI))
1110 Indexes->removeMachineInstrFromMaps(
MI);
1111 Indexes->insertMachineInstrInMaps(
MI);
1120 for (
const auto &LI : Succ->
liveins())
1127 while (!KilledRegs.empty()) {
1130 if (!(--
I)->addRegisterKilled(
Reg,
TRI,
false))
1139 if (LiveInSets !=
nullptr)
1156 SlotIndex StartIndex = Indexes->getMBBEndIdx(
this);
1158 SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
1164 I !=
E &&
I->isPHI(); ++
I) {
1165 for (
unsigned ni = 1, ne =
I->getNumOperands(); ni != ne; ni += 2) {
1166 if (
I->getOperand(ni+1).getMBB() == NMBB) {
1176 "PHI sources should be live out of their predecessors.");
1189 if (!LI.
liveAt(PrevIndex))
1195 assert(VNI &&
"LiveInterval should have VNInfo where it is live.");
1209 MDT->recordSplitCriticalEdge(
this, Succ, NMBB);
1215 if (
MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
1216 if (TIL == DestLoop) {
1218 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
1219 }
else if (TIL->contains(DestLoop)) {
1221 TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
1222 }
else if (DestLoop->contains(TIL)) {
1224 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
1230 assert(DestLoop->getHeader() == Succ &&
1231 "Should not create irreducible loops!");
1233 P->addBasicBlockToLoop(NMBB, MLI->getBase());
1273 if (TBB && TBB == FBB) {
1274 LLVM_DEBUG(
dbgs() <<
"Won't split critical edge after degenerate "
1285 if (
MI->isBundledWithSucc() && !
MI->isBundledWithPred())
1286 MI->unbundleFromSucc();
1288 if (
MI->isBundledWithPred() && !
MI->isBundledWithSucc())
1289 MI->unbundleFromPred();
1309 assert(!
MI->isBundledWithPred() && !
MI->isBundledWithSucc() &&
1310 "Cannot insert instruction with bundle flags");
1337 assert(Old != New &&
"Cannot replace self with self!");
1342 if (!
I->isTerminator())
break;
1346 for (
unsigned i = 0,
e =
I->getNumOperands();
i !=
e; ++
i)
1347 if (
I->getOperand(
i).isMBB() &&
1348 I->getOperand(
i).getMBB() == Old)
1349 I->getOperand(
i).setMBB(New);
1359 for (
unsigned i = 2,
e =
MI.getNumOperands() + 1;
i !=
e;
i += 2) {
1373 return MBBI->getDebugLoc();
1380 if (!
MBBI->isDebugInstr())
1381 return MBBI->getDebugLoc();
1391 if (!
MBBI->isDebugInstr())
return MBBI->getDebugLoc();
1401 return MBBI->getDebugLoc();
1411 while (TI !=
end() && !TI->isBranch())
1415 DL = TI->getDebugLoc();
1416 for (++TI ; TI !=
end() ; ++TI)
1429 const auto &Prob = *getProbabilityIterator(Succ);
1430 if (Prob.isUnknown()) {
1433 unsigned KnownProbNum = 0;
1435 for (
auto &
P : Probs) {
1436 if (!
P.isUnknown()) {
1441 return Sum.getCompl() / (Probs.size() - KnownProbNum);
1452 *getProbabilityIterator(
I) = Prob;
1456 MachineBasicBlock::const_probability_iterator
1457 MachineBasicBlock::getProbabilityIterator(
1459 assert(Probs.size() == Successors.size() &&
"Async probability list!");
1460 const size_t index = std::distance(Successors.begin(),
I);
1461 assert(
index < Probs.size() &&
"Not a current successor!");
1462 return Probs.begin() +
index;
1466 MachineBasicBlock::probability_iterator
1468 assert(Probs.size() == Successors.size() &&
"Async probability list!");
1469 const size_t index = std::distance(Successors.begin(),
I);
1470 assert(
index < Probs.size() &&
"Not a current successor!");
1471 return Probs.begin() +
index;
1483 unsigned Neighborhood)
const {
1484 unsigned N = Neighborhood;
1488 for (;
I !=
end() &&
N > 0; ++
I) {
1489 if (
I->isDebugOrPseudoInstr())
1500 if (
Info.FullyDefined ||
Info.Clobbered)
1527 if (
I->isDebugOrPseudoInstr())
1541 if (!
Info.PartialDeadDef)
1556 }
while (
I !=
begin() &&
N > 0);
1561 while (
I !=
begin() && std::prev(
I)->isDebugOrPseudoInstr())
1599 "Liveness information is accurate");
1600 return LiveIns.begin();
1607 "Liveness information is accurate");
1610 MCPhysReg ExceptionPointer = 0, ExceptionSelector = 0;
1617 return liveout_iterator(*
this, ExceptionPointer, ExceptionSelector,
false);
bool requiresStructuredCFG() const
IterT next_nodbg(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It, then continue incrementing it while it points to a debug instruction.
void remove(iterator MBBI)
unsigned succ_size() const
bool hasProperty(Property P) const
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
This is an optimization pass for GlobalISel generic memory operations.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
LivenessQueryResult
Possible outcome of a register liveness query to computeRegisterLiveness()
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
static const DILocation * getMergedLocation(const DILocation *LocA, const DILocation *LocB)
When two instructions are combined into a single instruction we also need to combine the original loc...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void ReplaceUsesOfBlockWith(MachineBasicBlock *Old, MachineBasicBlock *New)
Given a machine basic block that branched to 'Old', change the code and CFG so that it branches to 'N...
Context object for machine code objects.
MCContext & getContext() const
uint32_t getNumerator() const
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
virtual const TargetInstrInfo * getInstrInfo() const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
MachineBasicBlock * getNextNode()
Get the next node, or nullptr for the list tail.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Reg
All possible values of the reg field in the ModR/M byte.
This represents a simple continuous liveness interval for a value.
bool isEntryBlock() const
Returns true if this is the entry block of the function.
void setSuccProbability(succ_iterator I, BranchProbability Prob)
Set successor probability of a given iterator.
unsigned getFunctionNumber() const
getFunctionNumber - Return a unique ID for the current function.
MCSymbol * getEHCatchretSymbol() const
Return the EHCatchret Symbol for this basic block.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LiveInVector::const_iterator livein_iterator
void moveBefore(MachineBasicBlock *NewAfter)
Move 'this' block before or after the specified block.
static BranchProbability getZero()
iterator_range< livein_iterator > liveins() const
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
void insert(iterator MBBI, MachineBasicBlock *MBB)
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Since we know that Vector is byte aligned and we know the element offset of we should change the load into a lve *x instead of doing a load store lve *x sequence Implement passing vectors by value into calls and receiving them as arguments GCC apparently tries to then a load and vperm of Variable We need a way to teach tblgen that some operands of an intrinsic are required to be constants The verifier should enforce this constraint We currently codegen SCALAR_TO_VECTOR as a store of the scalar to a byte aligned stack slot
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
pointer remove(iterator &IT)
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
void addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs)
Adds registers contained in LiveRegs to the block live-in list of MBB.
void incorporateFunction(const Function &F)
Incorporate the given function.
void addSuccessorWithoutProb(MachineBasicBlock *Succ)
Add Succ as a successor of this MachineBasicBlock.
void copySuccessor(MachineBasicBlock *Orig, succ_iterator I)
Copy a successor (and any probability info) from original block to this block's.
unsigned const TargetRegisterInfo * TRI
Manage lifetime of a slot tracker for printing IR.
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
PhysRegInfo AnalyzePhysRegInBundle(const MachineInstr &MI, Register Reg, const TargetRegisterInfo *TRI)
AnalyzePhysRegInBundle - Analyze how the current instruction or bundle uses a physical register.
iterator erase(iterator where)
LLVM Basic Block Representation.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool isBeginSection() const
Returns true if this block begins any section.
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
MachineInstrBundleIterator< const MachineInstr > const_iterator
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void printName(raw_ostream &os, unsigned printNameFlags=PrintNameIr, ModuleSlotTracker *moduleSlotTracker=nullptr) const
Print the basic block's name as:
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
static cl::opt< bool > PrintSlotIndexes("print-slotindexes", cl::desc("When printing machine IR, annotate instructions and blocks with " "SlotIndexes when available"), cl::init(true), cl::Hidden)
< i1 > br i1 label label bb bb
instr_iterator getFirstInstrTerminator()
Same getFirstTerminator but it ignores bundles and return an instr_iterator instead.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
bool removeKill(MachineInstr &MI)
removeKill - Delete a kill corresponding to the specified machine instruction.
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
TargetInstrInfo - Interface to description of machine instruction set.
MachineBasicBlock * removeFromParent()
This method unlinks 'this' from the containing function, and returns it, but does not delete it.
bool liveAt(SlotIndex index) const
static uint32_t getDenominator()
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
@ Kill
The last use of a register.
const MachineFunctionProperties & getProperties() const
Get the function properties.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
const HexagonInstrInfo * TII
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
into llvm powi allowing the code generator to produce balanced multiplication trees First
MachineOperand class - Representation of each machine instruction operand.
bool isLegalToHoistInto() const
Returns true if it is legal to hoist instructions into this block.
Pair of physical register and lane mask.
MachineBasicBlock * splitAt(MachineInstr &SplitInst, bool UpdateLiveIns=true, LiveIntervals *LIS=nullptr)
Split a basic block into 2 pieces at SplitPoint.
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
This class implements an extremely fast bulk output stream that can only output to a stream.
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
bool hasPersonalityFn() const
Check whether this function has a personality function.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
unsigned addToMBBNumbering(MachineBasicBlock *MBB)
Adds the MBB to the internal numbering.
Analysis containing CSE Info
LiveInterval - This class represents the liveness of a register, or stack slot.
SlotIndex - An opaque wrapper around machine indexes.
static BranchProbability getUnknown()
DebugLoc findPrevDebugLoc(instr_iterator MBBI)
Find the previous valid DebugLoc preceding MBBI, skipping and DBG_VALUE instructions.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
void insertMBBInMaps(MachineBasicBlock *MBB)
Template traits for intrusive list.
std::vector< MachineBasicBlock * >::iterator succ_iterator
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
BranchProbability getSuccProbability(const_succ_iterator Succ) const
Return probability of the edge from this block to MBB.
bool mayHaveInlineAsmBr() const
Returns true if this block may have an INLINEASM_BR (overestimate, by checking if any of the successo...
void addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB, MachineBasicBlock *SuccBB)
addNewBlock - Add a new basic block BB between DomBB and SuccBB.
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
reverse_instr_iterator instr_rend()
Representation of each machine instruction.
const MCAsmInfo * getAsmInfo() const
bool hasAddressTaken() const
Test whether this block is potentially the target of an indirect branch.
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
void splice(iterator InsertPt, iterator MBBI)
iterator SkipPHIsAndLabels(iterator I)
Return the first instruction in MBB after I that is not a PHI or a label.
reverse_instr_iterator instr_rbegin()
@ LQR_Live
Register is known to be (at least partially) live.
initializer< Ty > init(const Ty &Val)
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
IterT prev_nodbg(IterT It, IterT Begin, bool SkipPseudoOp=true)
Decrement It, then continue decrementing it while it points to a debug instruction.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Align getAlignment() const
Return alignment of the basic block.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
const static MBBSectionID ExceptionSectionID
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool canFallThrough()
Return true if the block can implicitly transfer control to the block after it by falling off the end...
constexpr const T & getValue() const &
succ_iterator succ_begin()
Information about how a physical register Reg is used by a set of operands.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
BasicBlockListType::const_iterator const_iterator
void erase(iterator MBBI)
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
livein_iterator livein_end() const
Register getReg() const
getReg - Returns the register number.
A Module instance is used to store all the information related to an LLVM module.
iterator_range< pred_iterator > predecessors()
Instructions::reverse_iterator reverse_instr_iterator
@ LQR_Dead
Register is known to be fully dead.
instr_iterator instr_begin()
LiveInterval & getInterval(Register Reg)
instr_iterator instr_end()
void moveAfter(MachineBasicBlock *NewBefore)
@ PrintNameIr
Add IR name where available.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
const uint32_t * getBeginClobberMask(const TargetRegisterInfo *TRI) const
Get the clobber mask for the start of this basic block.
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
MachineBasicBlock * getMBB() const
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
SmallVector< MachineOperand, 4 > Cond
@ PrintNameAttributes
Print attributes.
iterator_range< succ_iterator > successors()
iterator getFirstNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the first non-debug instruction in the basic block, or end().
bool isEHPad() const
Returns true if the block is a landing pad.
StringRef - Represent a constant reference to a string, i.e.
reverse_iterator rbegin()
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
bool hasEHPadSuccessor() const
void init(const TargetRegisterInfo &TRI)
(re-)initializes and clears the set.
MachineBasicBlock MachineBasicBlock::iterator MBBI
std::string getFullName() const
Return a formatted string to identify this block and its parent function.
DebugLoc findBranchDebugLoc()
Find and return the merged DebugLoc of the branch instructions of the block.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
enum llvm::MBBSectionID::SectionType Type
DebugLoc rfindDebugLoc(reverse_instr_iterator MBBI)
Has exact same behavior as findDebugLoc (it also searches from the first to the last MI of this MBB) ...
void addNodeToList(NodeTy *)
When an MBB is added to an MF, we need to update the parent pointer of the MBB, the MBB numbering,...
self_iterator getIterator()
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
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bool hasBBSections() const
Returns true if this function has basic block sections enabled.
void splitSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New, bool NormalizeSuccProbs=false)
Split the old successor into old plus new and updates the probability info.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
liveout_iterator liveout_begin() const
Iterator scanning successor basic blocks' liveins to determine the registers potentially live at the ...
StringRef getName() const
Return a constant reference to the value's name.
void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
MBBSectionID getSectionID() const
Returns the section ID of this basic block.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
MCSymbol * getEndSymbol() const
Returns the MCSymbol marking the end of this basic block.
bool canSplitCriticalEdge(const MachineBasicBlock *Succ) const
Check if the edge between this block and the given successor Succ, can be split.
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
virtual Register getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
void replaceSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New)
Replace successor OLD with NEW and update probability info.
void replacePhiUsesWith(MachineBasicBlock *Old, MachineBasicBlock *New)
Update all phi nodes in this basic block to refer to basic block New instead of basic block Old.
Function & getFunction()
Return the LLVM function that this machine code represents.
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
const static MBBSectionID ColdSectionID
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Iterator for intrusive lists based on ilist_node.
uint64_t value() const
This is a hole in the type system and should not be abused.
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, MCRegister Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been defined and not killed as of just before Before.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Instructions::iterator instr_iterator
StringRef getPrivateLabelPrefix() const
void removeNodeFromList(NodeTy *)
void sort(IteratorTy Start, IteratorTy End)
livein_iterator livein_begin() const
VNInfo - Value Number Information.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
static void unbundleSingleMI(MachineInstr *MI)
Prepare MI to be removed from its bundle.
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
DebugLoc rfindPrevDebugLoc(reverse_instr_iterator MBBI)
Has exact same behavior as findPrevDebugLoc (it also searches from the last to the first MI of this M...
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
Constant * getPersonalityFn() const
Get the personality function associated with this function.
bool livein_empty() const
MachineBasicBlock * getFallThrough()
Return the fallthrough block if the block can implicitly transfer control to the block after it by fa...
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
iterator insert(iterator where, pointer New)
void validateSuccProbs() const
Validate successors' probabilities and check if the sum of them is approximate one.
const uint32_t * getEndClobberMask(const TargetRegisterInfo *TRI) const
Get the clobber mask for the end of the basic block.
Pass interface - Implemented by all 'passes'.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
virtual const TargetLowering * getTargetLowering() const
IterT skipDebugInstructionsBackward(IterT It, IterT Begin, bool SkipPseudoOp=true)
Decrement It until it points to a non-debug instruction or to Begin and return the resulting iterator...
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
raw_ostream & indent(unsigned NumSpaces)
indent - Insert 'NumSpaces' spaces.
static void deleteNode(NodeTy *V)
Simple wrapper around std::function<void(raw_ostream&)>.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
void setMBB(MachineBasicBlock *MBB)
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
A raw_ostream that writes to an SmallVector or SmallString.
void clearLiveIns()
Clear live in list.
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< Register > OrigRegs)
Update live intervals for instructions in a range of iterators.
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@ LQR_Unknown
Register liveness not decidable from local neighborhood.
iterator SkipPHIsLabelsAndDebug(iterator I, bool SkipPseudoOp=true)
Return the first instruction in MBB after I that is not a PHI, label or debug.
bool hasInterval(Register Reg) const
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
void transferNodesFromList(ilist_callback_traits &OldList, Iterator, Iterator)
Callback before transferring nodes to this list.
void updateTerminator(MachineBasicBlock *PreviousLayoutSuccessor)
Update the terminator instructions in block to account for changes to block layout which may have bee...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P, std::vector< SparseBitVector<>> *LiveInSets=nullptr)
Split the critical edge from this block to the given successor block, and return the newly created bl...
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
Wrapper class representing physical registers. Should be passed by value.