LLVM  14.0.0git
MachineBasicBlock.cpp
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1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Collect the sequence of machine instructions for a basic block.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/SmallPtrSet.h"
27 #include "llvm/Config/llvm-config.h"
28 #include "llvm/IR/BasicBlock.h"
29 #include "llvm/IR/DataLayout.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MCContext.h"
34 #include "llvm/Support/DataTypes.h"
35 #include "llvm/Support/Debug.h"
38 #include <algorithm>
39 using namespace llvm;
40 
41 #define DEBUG_TYPE "codegen"
42 
44  "print-slotindexes",
45  cl::desc("When printing machine IR, annotate instructions and blocks with "
46  "SlotIndexes when available"),
47  cl::init(true), cl::Hidden);
48 
49 MachineBasicBlock::MachineBasicBlock(MachineFunction &MF, const BasicBlock *B)
50  : BB(B), Number(-1), xParent(&MF) {
51  Insts.Parent = this;
52  if (B)
53  IrrLoopHeaderWeight = B->getIrrLoopHeaderWeight();
54 }
55 
56 MachineBasicBlock::~MachineBasicBlock() {
57 }
58 
59 /// Return the MCSymbol for this basic block.
61  if (!CachedMCSymbol) {
62  const MachineFunction *MF = getParent();
63  MCContext &Ctx = MF->getContext();
64 
65  // We emit a non-temporary symbol -- with a descriptive name -- if it begins
66  // a section (with basic block sections). Otherwise we fall back to use temp
67  // label.
68  if (MF->hasBBSections() && isBeginSection()) {
69  SmallString<5> Suffix;
70  if (SectionID == MBBSectionID::ColdSectionID) {
71  Suffix += ".cold";
72  } else if (SectionID == MBBSectionID::ExceptionSectionID) {
73  Suffix += ".eh";
74  } else {
75  // For symbols that represent basic block sections, we add ".__part." to
76  // allow tools like symbolizers to know that this represents a part of
77  // the original function.
78  Suffix = (Suffix + Twine(".__part.") + Twine(SectionID.Number)).str();
79  }
80  CachedMCSymbol = Ctx.getOrCreateSymbol(MF->getName() + Suffix);
81  } else {
83  CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
84  Twine(MF->getFunctionNumber()) +
85  "_" + Twine(getNumber()));
86  }
87  }
88  return CachedMCSymbol;
89 }
90 
92  if (!CachedEHCatchretMCSymbol) {
93  const MachineFunction *MF = getParent();
96  << "$ehgcr_" << MF->getFunctionNumber() << '_' << getNumber();
97  CachedEHCatchretMCSymbol = MF->getContext().getOrCreateSymbol(SymbolName);
98  }
99  return CachedEHCatchretMCSymbol;
100 }
101 
103  if (!CachedEndMCSymbol) {
104  const MachineFunction *MF = getParent();
105  MCContext &Ctx = MF->getContext();
106  auto Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
107  CachedEndMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB_END" +
108  Twine(MF->getFunctionNumber()) +
109  "_" + Twine(getNumber()));
110  }
111  return CachedEndMCSymbol;
112 }
113 
115  MBB.print(OS);
116  return OS;
117 }
118 
120  return Printable([&MBB](raw_ostream &OS) { return MBB.printAsOperand(OS); });
121 }
122 
123 /// When an MBB is added to an MF, we need to update the parent pointer of the
124 /// MBB, the MBB numbering, and any instructions in the MBB to be on the right
125 /// operand list for registers.
126 ///
127 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
128 /// gets the next available unique MBB number. If it is removed from a
129 /// MachineFunction, it goes back to being #-1.
131  MachineBasicBlock *N) {
132  MachineFunction &MF = *N->getParent();
133  N->Number = MF.addToMBBNumbering(N);
134 
135  // Make sure the instructions have their operands in the reginfo lists.
136  MachineRegisterInfo &RegInfo = MF.getRegInfo();
137  for (MachineInstr &MI : N->instrs())
138  MI.AddRegOperandsToUseLists(RegInfo);
139 }
140 
142  MachineBasicBlock *N) {
143  N->getParent()->removeFromMBBNumbering(N->Number);
144  N->Number = -1;
145 }
146 
147 /// When we add an instruction to a basic block list, we update its parent
148 /// pointer and add its operands from reg use/def lists if appropriate.
150  assert(!N->getParent() && "machine instruction already in a basic block");
151  N->setParent(Parent);
152 
153  // Add the instruction's register operands to their corresponding
154  // use/def lists.
155  MachineFunction *MF = Parent->getParent();
156  N->AddRegOperandsToUseLists(MF->getRegInfo());
157  MF->handleInsertion(*N);
158 }
159 
160 /// When we remove an instruction from a basic block list, we update its parent
161 /// pointer and remove its operands from reg use/def lists if appropriate.
163  assert(N->getParent() && "machine instruction not in a basic block");
164 
165  // Remove from the use/def lists.
166  if (MachineFunction *MF = N->getMF()) {
167  MF->handleRemoval(*N);
168  N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
169  }
170 
171  N->setParent(nullptr);
172 }
173 
174 /// When moving a range of instructions from one MBB list to another, we need to
175 /// update the parent pointers and the use/def lists.
177  instr_iterator First,
178  instr_iterator Last) {
179  assert(Parent->getParent() == FromList.Parent->getParent() &&
180  "cannot transfer MachineInstrs between MachineFunctions");
181 
182  // If it's within the same BB, there's nothing to do.
183  if (this == &FromList)
184  return;
185 
186  assert(Parent != FromList.Parent && "Two lists have the same parent?");
187 
188  // If splicing between two blocks within the same function, just update the
189  // parent pointers.
190  for (; First != Last; ++First)
191  First->setParent(Parent);
192 }
193 
195  assert(!MI->getParent() && "MI is still in a block!");
196  Parent->getParent()->DeleteMachineInstr(MI);
197 }
198 
201  while (I != E && I->isPHI())
202  ++I;
203  assert((I == E || !I->isInsideBundle()) &&
204  "First non-phi MI cannot be inside a bundle!");
205  return I;
206 }
207 
211 
212  iterator E = end();
213  while (I != E && (I->isPHI() || I->isPosition() ||
214  TII->isBasicBlockPrologue(*I)))
215  ++I;
216  // FIXME: This needs to change if we wish to bundle labels
217  // inside the bundle.
218  assert((I == E || !I->isInsideBundle()) &&
219  "First non-phi / non-label instruction is inside a bundle!");
220  return I;
221 }
222 
225  bool SkipPseudoOp) {
227 
228  iterator E = end();
229  while (I != E && (I->isPHI() || I->isPosition() || I->isDebugInstr() ||
230  (SkipPseudoOp && I->isPseudoProbe()) ||
231  TII->isBasicBlockPrologue(*I)))
232  ++I;
233  // FIXME: This needs to change if we wish to bundle labels / dbg_values
234  // inside the bundle.
235  assert((I == E || !I->isInsideBundle()) &&
236  "First non-phi / non-label / non-debug "
237  "instruction is inside a bundle!");
238  return I;
239 }
240 
242  iterator B = begin(), E = end(), I = E;
243  while (I != B && ((--I)->isTerminator() || I->isDebugInstr()))
244  ; /*noop */
245  while (I != E && !I->isTerminator())
246  ++I;
247  return I;
248 }
249 
251  instr_iterator B = instr_begin(), E = instr_end(), I = E;
252  while (I != B && ((--I)->isTerminator() || I->isDebugInstr()))
253  ; /*noop */
254  while (I != E && !I->isTerminator())
255  ++I;
256  return I;
257 }
258 
261  // Skip over begin-of-block dbg_value instructions.
262  return skipDebugInstructionsForward(begin(), end(), SkipPseudoOp);
263 }
264 
267  // Skip over end-of-block dbg_value instructions.
269  while (I != B) {
270  --I;
271  // Return instruction that starts a bundle.
272  if (I->isDebugInstr() || I->isInsideBundle())
273  continue;
274  if (SkipPseudoOp && I->isPseudoProbe())
275  continue;
276  return I;
277  }
278  // The block is all debug values.
279  return end();
280 }
281 
283  for (const MachineBasicBlock *Succ : successors())
284  if (Succ->isEHPad())
285  return true;
286  return false;
287 }
288 
290  return getParent()->begin() == getIterator();
291 }
292 
293 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
295  print(dbgs());
296 }
297 #endif
298 
300  for (const MachineBasicBlock *Succ : successors()) {
301  if (Succ->isInlineAsmBrIndirectTarget())
302  return true;
303  }
304  return false;
305 }
306 
309  return false;
310  return true;
311 }
312 
314  if (const BasicBlock *LBB = getBasicBlock())
315  return LBB->getName();
316  else
317  return StringRef("", 0);
318 }
319 
320 /// Return a hopefully unique identifier for this block.
321 std::string MachineBasicBlock::getFullName() const {
322  std::string Name;
323  if (getParent())
324  Name = (getParent()->getName() + ":").str();
325  if (getBasicBlock())
326  Name += getBasicBlock()->getName();
327  else
328  Name += ("BB" + Twine(getNumber())).str();
329  return Name;
330 }
331 
333  bool IsStandalone) const {
334  const MachineFunction *MF = getParent();
335  if (!MF) {
336  OS << "Can't print out MachineBasicBlock because parent MachineFunction"
337  << " is null\n";
338  return;
339  }
340  const Function &F = MF->getFunction();
341  const Module *M = F.getParent();
342  ModuleSlotTracker MST(M);
343  MST.incorporateFunction(F);
344  print(OS, MST, Indexes, IsStandalone);
345 }
346 
348  const SlotIndexes *Indexes,
349  bool IsStandalone) const {
350  const MachineFunction *MF = getParent();
351  if (!MF) {
352  OS << "Can't print out MachineBasicBlock because parent MachineFunction"
353  << " is null\n";
354  return;
355  }
356 
357  if (Indexes && PrintSlotIndexes)
358  OS << Indexes->getMBBStartIdx(this) << '\t';
359 
361  OS << ":\n";
362 
364  const MachineRegisterInfo &MRI = MF->getRegInfo();
366  bool HasLineAttributes = false;
367 
368  // Print the preds of this block according to the CFG.
369  if (!pred_empty() && IsStandalone) {
370  if (Indexes) OS << '\t';
371  // Don't indent(2), align with previous line attributes.
372  OS << "; predecessors: ";
373  ListSeparator LS;
374  for (auto *Pred : predecessors())
375  OS << LS << printMBBReference(*Pred);
376  OS << '\n';
377  HasLineAttributes = true;
378  }
379 
380  if (!succ_empty()) {
381  if (Indexes) OS << '\t';
382  // Print the successors
383  OS.indent(2) << "successors: ";
384  ListSeparator LS;
385  for (auto I = succ_begin(), E = succ_end(); I != E; ++I) {
386  OS << LS << printMBBReference(**I);
387  if (!Probs.empty())
388  OS << '('
389  << format("0x%08" PRIx32, getSuccProbability(I).getNumerator())
390  << ')';
391  }
392  if (!Probs.empty() && IsStandalone) {
393  // Print human readable probabilities as comments.
394  OS << "; ";
395  ListSeparator LS;
396  for (auto I = succ_begin(), E = succ_end(); I != E; ++I) {
397  const BranchProbability &BP = getSuccProbability(I);
398  OS << LS << printMBBReference(**I) << '('
399  << format("%.2f%%",
400  rint(((double)BP.getNumerator() / BP.getDenominator()) *
401  100.0 * 100.0) /
402  100.0)
403  << ')';
404  }
405  }
406 
407  OS << '\n';
408  HasLineAttributes = true;
409  }
410 
411  if (!livein_empty() && MRI.tracksLiveness()) {
412  if (Indexes) OS << '\t';
413  OS.indent(2) << "liveins: ";
414 
415  ListSeparator LS;
416  for (const auto &LI : liveins()) {
417  OS << LS << printReg(LI.PhysReg, TRI);
418  if (!LI.LaneMask.all())
419  OS << ":0x" << PrintLaneMask(LI.LaneMask);
420  }
421  HasLineAttributes = true;
422  }
423 
424  if (HasLineAttributes)
425  OS << '\n';
426 
427  bool IsInBundle = false;
428  for (const MachineInstr &MI : instrs()) {
429  if (Indexes && PrintSlotIndexes) {
430  if (Indexes->hasIndex(MI))
431  OS << Indexes->getInstructionIndex(MI);
432  OS << '\t';
433  }
434 
435  if (IsInBundle && !MI.isInsideBundle()) {
436  OS.indent(2) << "}\n";
437  IsInBundle = false;
438  }
439 
440  OS.indent(IsInBundle ? 4 : 2);
441  MI.print(OS, MST, IsStandalone, /*SkipOpers=*/false, /*SkipDebugLoc=*/false,
442  /*AddNewLine=*/false, &TII);
443 
444  if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
445  OS << " {";
446  IsInBundle = true;
447  }
448  OS << '\n';
449  }
450 
451  if (IsInBundle)
452  OS.indent(2) << "}\n";
453 
454  if (IrrLoopHeaderWeight && IsStandalone) {
455  if (Indexes) OS << '\t';
456  OS.indent(2) << "; Irreducible loop header weight: "
457  << IrrLoopHeaderWeight.getValue() << '\n';
458  }
459 }
460 
461 /// Print the basic block's name as:
462 ///
463 /// bb.{number}[.{ir-name}] [(attributes...)]
464 ///
465 /// The {ir-name} is only printed when the \ref PrintNameIr flag is passed
466 /// (which is the default). If the IR block has no name, it is identified
467 /// numerically using the attribute syntax as "(%ir-block.{ir-slot})".
468 ///
469 /// When the \ref PrintNameAttributes flag is passed, additional attributes
470 /// of the block are printed when set.
471 ///
472 /// \param printNameFlags Combination of \ref PrintNameFlag flags indicating
473 /// the parts to print.
474 /// \param moduleSlotTracker Optional ModuleSlotTracker. This method will
475 /// incorporate its own tracker when necessary to
476 /// determine the block's IR name.
477 void MachineBasicBlock::printName(raw_ostream &os, unsigned printNameFlags,
478  ModuleSlotTracker *moduleSlotTracker) const {
479  os << "bb." << getNumber();
480  bool hasAttributes = false;
481 
482  if (printNameFlags & PrintNameIr) {
483  if (const auto *bb = getBasicBlock()) {
484  if (bb->hasName()) {
485  os << '.' << bb->getName();
486  } else {
487  hasAttributes = true;
488  os << " (";
489 
490  int slot = -1;
491 
492  if (moduleSlotTracker) {
493  slot = moduleSlotTracker->getLocalSlot(bb);
494  } else if (bb->getParent()) {
495  ModuleSlotTracker tmpTracker(bb->getModule(), false);
496  tmpTracker.incorporateFunction(*bb->getParent());
497  slot = tmpTracker.getLocalSlot(bb);
498  }
499 
500  if (slot == -1)
501  os << "<ir-block badref>";
502  else
503  os << (Twine("%ir-block.") + Twine(slot)).str();
504  }
505  }
506  }
507 
508  if (printNameFlags & PrintNameAttributes) {
509  if (hasAddressTaken()) {
510  os << (hasAttributes ? ", " : " (");
511  os << "address-taken";
512  hasAttributes = true;
513  }
514  if (isEHPad()) {
515  os << (hasAttributes ? ", " : " (");
516  os << "landing-pad";
517  hasAttributes = true;
518  }
520  os << (hasAttributes ? ", " : " (");
521  os << "inlineasm-br-indirect-target";
522  hasAttributes = true;
523  }
524  if (isEHFuncletEntry()) {
525  os << (hasAttributes ? ", " : " (");
526  os << "ehfunclet-entry";
527  hasAttributes = true;
528  }
529  if (getAlignment() != Align(1)) {
530  os << (hasAttributes ? ", " : " (");
531  os << "align " << getAlignment().value();
532  hasAttributes = true;
533  }
534  if (getSectionID() != MBBSectionID(0)) {
535  os << (hasAttributes ? ", " : " (");
536  os << "bbsections ";
537  switch (getSectionID().Type) {
538  case MBBSectionID::SectionType::Exception:
539  os << "Exception";
540  break;
542  os << "Cold";
543  break;
544  default:
545  os << getSectionID().Number;
546  }
547  hasAttributes = true;
548  }
549  }
550 
551  if (hasAttributes)
552  os << ')';
553 }
554 
556  bool /*PrintType*/) const {
557  OS << '%';
558  printName(OS, 0);
559 }
560 
562  LiveInVector::iterator I = find_if(
563  LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
564  if (I == LiveIns.end())
565  return;
566 
567  I->LaneMask &= ~LaneMask;
568  if (I->LaneMask.none())
569  LiveIns.erase(I);
570 }
571 
574  // Get non-const version of iterator.
575  LiveInVector::iterator LI = LiveIns.begin() + (I - LiveIns.begin());
576  return LiveIns.erase(LI);
577 }
578 
581  LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
582  return I != livein_end() && (I->LaneMask & LaneMask).any();
583 }
584 
586  llvm::sort(LiveIns,
587  [](const RegisterMaskPair &LI0, const RegisterMaskPair &LI1) {
588  return LI0.PhysReg < LI1.PhysReg;
589  });
590  // Liveins are sorted by physreg now we can merge their lanemasks.
591  LiveInVector::const_iterator I = LiveIns.begin();
592  LiveInVector::const_iterator J;
593  LiveInVector::iterator Out = LiveIns.begin();
594  for (; I != LiveIns.end(); ++Out, I = J) {
595  MCRegister PhysReg = I->PhysReg;
596  LaneBitmask LaneMask = I->LaneMask;
597  for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J)
598  LaneMask |= J->LaneMask;
599  Out->PhysReg = PhysReg;
600  Out->LaneMask = LaneMask;
601  }
602  LiveIns.erase(Out, LiveIns.end());
603 }
604 
605 Register
607  assert(getParent() && "MBB must be inserted in function");
608  assert(Register::isPhysicalRegister(PhysReg) && "Expected physreg");
609  assert(RC && "Register class is required");
610  assert((isEHPad() || this == &getParent()->front()) &&
611  "Only the entry block and landing pads can have physreg live ins");
612 
613  bool LiveIn = isLiveIn(PhysReg);
617 
618  // Look for an existing copy.
619  if (LiveIn)
620  for (;I != E && I->isCopy(); ++I)
621  if (I->getOperand(1).getReg() == PhysReg) {
622  Register VirtReg = I->getOperand(0).getReg();
623  if (!MRI.constrainRegClass(VirtReg, RC))
624  llvm_unreachable("Incompatible live-in register class.");
625  return VirtReg;
626  }
627 
628  // No luck, create a virtual register.
629  Register VirtReg = MRI.createVirtualRegister(RC);
630  BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
631  .addReg(PhysReg, RegState::Kill);
632  if (!LiveIn)
633  addLiveIn(PhysReg);
634  return VirtReg;
635 }
636 
638  getParent()->splice(NewAfter->getIterator(), getIterator());
639 }
640 
642  getParent()->splice(++NewBefore->getIterator(), getIterator());
643 }
644 
646  MachineBasicBlock *PreviousLayoutSuccessor) {
647  LLVM_DEBUG(dbgs() << "Updating terminators on " << printMBBReference(*this)
648  << "\n");
649 
651  // A block with no successors has no concerns with fall-through edges.
652  if (this->succ_empty())
653  return;
654 
655  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
658  bool B = TII->analyzeBranch(*this, TBB, FBB, Cond);
659  (void) B;
660  assert(!B && "UpdateTerminators requires analyzable predecessors!");
661  if (Cond.empty()) {
662  if (TBB) {
663  // The block has an unconditional branch. If its successor is now its
664  // layout successor, delete the branch.
665  if (isLayoutSuccessor(TBB))
666  TII->removeBranch(*this);
667  } else {
668  // The block has an unconditional fallthrough, or the end of the block is
669  // unreachable.
670 
671  // Unfortunately, whether the end of the block is unreachable is not
672  // immediately obvious; we must fall back to checking the successor list,
673  // and assuming that if the passed in block is in the succesor list and
674  // not an EHPad, it must be the intended target.
675  if (!PreviousLayoutSuccessor || !isSuccessor(PreviousLayoutSuccessor) ||
676  PreviousLayoutSuccessor->isEHPad())
677  return;
678 
679  // If the unconditional successor block is not the current layout
680  // successor, insert a branch to jump to it.
681  if (!isLayoutSuccessor(PreviousLayoutSuccessor))
682  TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL);
683  }
684  return;
685  }
686 
687  if (FBB) {
688  // The block has a non-fallthrough conditional branch. If one of its
689  // successors is its layout successor, rewrite it to a fallthrough
690  // conditional branch.
691  if (isLayoutSuccessor(TBB)) {
693  return;
694  TII->removeBranch(*this);
695  TII->insertBranch(*this, FBB, nullptr, Cond, DL);
696  } else if (isLayoutSuccessor(FBB)) {
697  TII->removeBranch(*this);
698  TII->insertBranch(*this, TBB, nullptr, Cond, DL);
699  }
700  return;
701  }
702 
703  // We now know we're going to fallthrough to PreviousLayoutSuccessor.
704  assert(PreviousLayoutSuccessor);
705  assert(!PreviousLayoutSuccessor->isEHPad());
706  assert(isSuccessor(PreviousLayoutSuccessor));
707 
708  if (PreviousLayoutSuccessor == TBB) {
709  // We had a fallthrough to the same basic block as the conditional jump
710  // targets. Remove the conditional jump, leaving an unconditional
711  // fallthrough or an unconditional jump.
712  TII->removeBranch(*this);
713  if (!isLayoutSuccessor(TBB)) {
714  Cond.clear();
715  TII->insertBranch(*this, TBB, nullptr, Cond, DL);
716  }
717  return;
718  }
719 
720  // The block has a fallthrough conditional branch.
721  if (isLayoutSuccessor(TBB)) {
723  // We can't reverse the condition, add an unconditional branch.
724  Cond.clear();
725  TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL);
726  return;
727  }
728  TII->removeBranch(*this);
729  TII->insertBranch(*this, PreviousLayoutSuccessor, nullptr, Cond, DL);
730  } else if (!isLayoutSuccessor(PreviousLayoutSuccessor)) {
731  TII->removeBranch(*this);
732  TII->insertBranch(*this, TBB, PreviousLayoutSuccessor, Cond, DL);
733  }
734 }
735 
737 #ifndef NDEBUG
738  int64_t Sum = 0;
739  for (auto Prob : Probs)
740  Sum += Prob.getNumerator();
741  // Due to precision issue, we assume that the sum of probabilities is one if
742  // the difference between the sum of their numerators and the denominator is
743  // no greater than the number of successors.
745  Probs.size() &&
746  "The sum of successors's probabilities exceeds one.");
747 #endif // NDEBUG
748 }
749 
751  BranchProbability Prob) {
752  // Probability list is either empty (if successor list isn't empty, this means
753  // disabled optimization) or has the same size as successor list.
754  if (!(Probs.empty() && !Successors.empty()))
755  Probs.push_back(Prob);
756  Successors.push_back(Succ);
757  Succ->addPredecessor(this);
758 }
759 
761  // We need to make sure probability list is either empty or has the same size
762  // of successor list. When this function is called, we can safely delete all
763  // probability in the list.
764  Probs.clear();
765  Successors.push_back(Succ);
766  Succ->addPredecessor(this);
767 }
768 
770  MachineBasicBlock *New,
771  bool NormalizeSuccProbs) {
772  succ_iterator OldI = llvm::find(successors(), Old);
773  assert(OldI != succ_end() && "Old is not a successor of this block!");
775  "New is already a successor of this block!");
776 
777  // Add a new successor with equal probability as the original one. Note
778  // that we directly copy the probability using the iterator rather than
779  // getting a potentially synthetic probability computed when unknown. This
780  // preserves the probabilities as-is and then we can renormalize them and
781  // query them effectively afterward.
782  addSuccessor(New, Probs.empty() ? BranchProbability::getUnknown()
783  : *getProbabilityIterator(OldI));
784  if (NormalizeSuccProbs)
786 }
787 
789  bool NormalizeSuccProbs) {
790  succ_iterator I = find(Successors, Succ);
791  removeSuccessor(I, NormalizeSuccProbs);
792 }
793 
796  assert(I != Successors.end() && "Not a current successor!");
797 
798  // If probability list is empty it means we don't use it (disabled
799  // optimization).
800  if (!Probs.empty()) {
801  probability_iterator WI = getProbabilityIterator(I);
802  Probs.erase(WI);
803  if (NormalizeSuccProbs)
805  }
806 
807  (*I)->removePredecessor(this);
808  return Successors.erase(I);
809 }
810 
812  MachineBasicBlock *New) {
813  if (Old == New)
814  return;
815 
817  succ_iterator NewI = E;
818  succ_iterator OldI = E;
819  for (succ_iterator I = succ_begin(); I != E; ++I) {
820  if (*I == Old) {
821  OldI = I;
822  if (NewI != E)
823  break;
824  }
825  if (*I == New) {
826  NewI = I;
827  if (OldI != E)
828  break;
829  }
830  }
831  assert(OldI != E && "Old is not a successor of this block");
832 
833  // If New isn't already a successor, let it take Old's place.
834  if (NewI == E) {
835  Old->removePredecessor(this);
836  New->addPredecessor(this);
837  *OldI = New;
838  return;
839  }
840 
841  // New is already a successor.
842  // Update its probability instead of adding a duplicate edge.
843  if (!Probs.empty()) {
844  auto ProbIter = getProbabilityIterator(NewI);
845  if (!ProbIter->isUnknown())
846  *ProbIter += *getProbabilityIterator(OldI);
847  }
848  removeSuccessor(OldI);
849 }
850 
852  succ_iterator I) {
853  if (!Orig->Probs.empty())
854  addSuccessor(*I, Orig->getSuccProbability(I));
855  else
857 }
858 
859 void MachineBasicBlock::addPredecessor(MachineBasicBlock *Pred) {
860  Predecessors.push_back(Pred);
861 }
862 
863 void MachineBasicBlock::removePredecessor(MachineBasicBlock *Pred) {
864  pred_iterator I = find(Predecessors, Pred);
865  assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
866  Predecessors.erase(I);
867 }
868 
870  if (this == FromMBB)
871  return;
872 
873  while (!FromMBB->succ_empty()) {
874  MachineBasicBlock *Succ = *FromMBB->succ_begin();
875 
876  // If probability list is empty it means we don't use it (disabled
877  // optimization).
878  if (!FromMBB->Probs.empty()) {
879  auto Prob = *FromMBB->Probs.begin();
880  addSuccessor(Succ, Prob);
881  } else
883 
884  FromMBB->removeSuccessor(Succ);
885  }
886 }
887 
888 void
890  if (this == FromMBB)
891  return;
892 
893  while (!FromMBB->succ_empty()) {
894  MachineBasicBlock *Succ = *FromMBB->succ_begin();
895  if (!FromMBB->Probs.empty()) {
896  auto Prob = *FromMBB->Probs.begin();
897  addSuccessor(Succ, Prob);
898  } else
900  FromMBB->removeSuccessor(Succ);
901 
902  // Fix up any PHI nodes in the successor.
903  Succ->replacePhiUsesWith(FromMBB, this);
904  }
906 }
907 
909  return is_contained(predecessors(), MBB);
910 }
911 
913  return is_contained(successors(), MBB);
914 }
915 
918  return std::next(I) == MachineFunction::const_iterator(MBB);
919 }
920 
922  MachineFunction::iterator Fallthrough = getIterator();
923  ++Fallthrough;
924  // If FallthroughBlock is off the end of the function, it can't fall through.
925  if (Fallthrough == getParent()->end())
926  return nullptr;
927 
928  // If FallthroughBlock isn't a successor, no fallthrough is possible.
929  if (!isSuccessor(&*Fallthrough))
930  return nullptr;
931 
932  // Analyze the branches, if any, at the end of the block.
933  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
936  if (TII->analyzeBranch(*this, TBB, FBB, Cond)) {
937  // If we couldn't analyze the branch, examine the last instruction.
938  // If the block doesn't end in a known control barrier, assume fallthrough
939  // is possible. The isPredicated check is needed because this code can be
940  // called during IfConversion, where an instruction which is normally a
941  // Barrier is predicated and thus no longer an actual control barrier.
942  return (empty() || !back().isBarrier() || TII->isPredicated(back()))
943  ? &*Fallthrough
944  : nullptr;
945  }
946 
947  // If there is no branch, control always falls through.
948  if (!TBB) return &*Fallthrough;
949 
950  // If there is some explicit branch to the fallthrough block, it can obviously
951  // reach, even though the branch should get folded to fall through implicitly.
952  if (MachineFunction::iterator(TBB) == Fallthrough ||
953  MachineFunction::iterator(FBB) == Fallthrough)
954  return &*Fallthrough;
955 
956  // If it's an unconditional branch to some block not the fall through, it
957  // doesn't fall through.
958  if (Cond.empty()) return nullptr;
959 
960  // Otherwise, if it is conditional and has no explicit false block, it falls
961  // through.
962  return (FBB == nullptr) ? &*Fallthrough : nullptr;
963 }
964 
966  return getFallThrough() != nullptr;
967 }
968 
970  bool UpdateLiveIns,
971  LiveIntervals *LIS) {
972  MachineBasicBlock::iterator SplitPoint(&MI);
973  ++SplitPoint;
974 
975  if (SplitPoint == end()) {
976  // Don't bother with a new block.
977  return this;
978  }
979 
980  MachineFunction *MF = getParent();
981 
982  LivePhysRegs LiveRegs;
983  if (UpdateLiveIns) {
984  // Make sure we add any physregs we define in the block as liveins to the
985  // new block.
987  LiveRegs.init(*MF->getSubtarget().getRegisterInfo());
988  LiveRegs.addLiveOuts(*this);
989  for (auto I = rbegin(), E = Prev.getReverse(); I != E; ++I)
990  LiveRegs.stepBackward(*I);
991  }
992 
994 
995  MF->insert(++MachineFunction::iterator(this), SplitBB);
996  SplitBB->splice(SplitBB->begin(), this, SplitPoint, end());
997 
998  SplitBB->transferSuccessorsAndUpdatePHIs(this);
999  addSuccessor(SplitBB);
1000 
1001  if (UpdateLiveIns)
1002  addLiveIns(*SplitBB, LiveRegs);
1003 
1004  if (LIS)
1005  LIS->insertMBBInMaps(SplitBB);
1006 
1007  return SplitBB;
1008 }
1009 
1011  MachineBasicBlock *Succ, Pass &P,
1012  std::vector<SparseBitVector<>> *LiveInSets) {
1013  if (!canSplitCriticalEdge(Succ))
1014  return nullptr;
1015 
1016  MachineFunction *MF = getParent();
1017  MachineBasicBlock *PrevFallthrough = getNextNode();
1018  DebugLoc DL; // FIXME: this is nowhere
1019 
1021  MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
1022  LLVM_DEBUG(dbgs() << "Splitting critical edge: " << printMBBReference(*this)
1023  << " -- " << printMBBReference(*NMBB) << " -- "
1024  << printMBBReference(*Succ) << '\n');
1025 
1026  LiveIntervals *LIS = P.getAnalysisIfAvailable<LiveIntervals>();
1027  SlotIndexes *Indexes = P.getAnalysisIfAvailable<SlotIndexes>();
1028  if (LIS)
1029  LIS->insertMBBInMaps(NMBB);
1030  else if (Indexes)
1031  Indexes->insertMBBInMaps(NMBB);
1032 
1033  // On some targets like Mips, branches may kill virtual registers. Make sure
1034  // that LiveVariables is properly updated after updateTerminator replaces the
1035  // terminators.
1036  LiveVariables *LV = P.getAnalysisIfAvailable<LiveVariables>();
1037 
1038  // Collect a list of virtual registers killed by the terminators.
1039  SmallVector<Register, 4> KilledRegs;
1040  if (LV)
1042  I != E; ++I) {
1043  MachineInstr *MI = &*I;
1044  for (MachineOperand &MO : MI->operands()) {
1045  if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse() || !MO.isKill() ||
1046  MO.isUndef())
1047  continue;
1048  Register Reg = MO.getReg();
1050  LV->getVarInfo(Reg).removeKill(*MI)) {
1051  KilledRegs.push_back(Reg);
1052  LLVM_DEBUG(dbgs() << "Removing terminator kill: " << MI);
1053  MO.setIsKill(false);
1054  }
1055  }
1056  }
1057 
1058  SmallVector<Register, 4> UsedRegs;
1059  if (LIS) {
1061  I != E; ++I) {
1062  MachineInstr *MI = &*I;
1063 
1064  for (const MachineOperand &MO : MI->operands()) {
1065  if (!MO.isReg() || MO.getReg() == 0)
1066  continue;
1067 
1068  Register Reg = MO.getReg();
1069  if (!is_contained(UsedRegs, Reg))
1070  UsedRegs.push_back(Reg);
1071  }
1072  }
1073  }
1074 
1075  ReplaceUsesOfBlockWith(Succ, NMBB);
1076 
1077  // If updateTerminator() removes instructions, we need to remove them from
1078  // SlotIndexes.
1079  SmallVector<MachineInstr*, 4> Terminators;
1080  if (Indexes) {
1082  I != E; ++I)
1083  Terminators.push_back(&*I);
1084  }
1085 
1086  // Since we replaced all uses of Succ with NMBB, that should also be treated
1087  // as the fallthrough successor
1088  if (Succ == PrevFallthrough)
1089  PrevFallthrough = NMBB;
1090  updateTerminator(PrevFallthrough);
1091 
1092  if (Indexes) {
1093  SmallVector<MachineInstr*, 4> NewTerminators;
1095  I != E; ++I)
1096  NewTerminators.push_back(&*I);
1097 
1098  for (MachineInstr *Terminator : Terminators) {
1099  if (!is_contained(NewTerminators, Terminator))
1100  Indexes->removeMachineInstrFromMaps(*Terminator);
1101  }
1102  }
1103 
1104  // Insert unconditional "jump Succ" instruction in NMBB if necessary.
1105  NMBB->addSuccessor(Succ);
1106  if (!NMBB->isLayoutSuccessor(Succ)) {
1109  TII->insertBranch(*NMBB, Succ, nullptr, Cond, DL);
1110 
1111  if (Indexes) {
1112  for (MachineInstr &MI : NMBB->instrs()) {
1113  // Some instructions may have been moved to NMBB by updateTerminator(),
1114  // so we first remove any instruction that already has an index.
1115  if (Indexes->hasIndex(MI))
1116  Indexes->removeMachineInstrFromMaps(MI);
1117  Indexes->insertMachineInstrInMaps(MI);
1118  }
1119  }
1120  }
1121 
1122  // Fix PHI nodes in Succ so they refer to NMBB instead of this.
1123  Succ->replacePhiUsesWith(this, NMBB);
1124 
1125  // Inherit live-ins from the successor
1126  for (const auto &LI : Succ->liveins())
1127  NMBB->addLiveIn(LI);
1128 
1129  // Update LiveVariables.
1131  if (LV) {
1132  // Restore kills of virtual registers that were killed by the terminators.
1133  while (!KilledRegs.empty()) {
1134  Register Reg = KilledRegs.pop_back_val();
1135  for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
1136  if (!(--I)->addRegisterKilled(Reg, TRI, /* AddIfNotFound= */ false))
1137  continue;
1139  LV->getVarInfo(Reg).Kills.push_back(&*I);
1140  LLVM_DEBUG(dbgs() << "Restored terminator kill: " << *I);
1141  break;
1142  }
1143  }
1144  // Update relevant live-through information.
1145  if (LiveInSets != nullptr)
1146  LV->addNewBlock(NMBB, this, Succ, *LiveInSets);
1147  else
1148  LV->addNewBlock(NMBB, this, Succ);
1149  }
1150 
1151  if (LIS) {
1152  // After splitting the edge and updating SlotIndexes, live intervals may be
1153  // in one of two situations, depending on whether this block was the last in
1154  // the function. If the original block was the last in the function, all
1155  // live intervals will end prior to the beginning of the new split block. If
1156  // the original block was not at the end of the function, all live intervals
1157  // will extend to the end of the new split block.
1158 
1159  bool isLastMBB =
1160  std::next(MachineFunction::iterator(NMBB)) == getParent()->end();
1161 
1162  SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
1163  SlotIndex PrevIndex = StartIndex.getPrevSlot();
1164  SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
1165 
1166  // Find the registers used from NMBB in PHIs in Succ.
1167  SmallSet<Register, 8> PHISrcRegs;
1169  I = Succ->instr_begin(), E = Succ->instr_end();
1170  I != E && I->isPHI(); ++I) {
1171  for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
1172  if (I->getOperand(ni+1).getMBB() == NMBB) {
1173  MachineOperand &MO = I->getOperand(ni);
1174  Register Reg = MO.getReg();
1175  PHISrcRegs.insert(Reg);
1176  if (MO.isUndef())
1177  continue;
1178 
1179  LiveInterval &LI = LIS->getInterval(Reg);
1180  VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
1181  assert(VNI &&
1182  "PHI sources should be live out of their predecessors.");
1183  LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
1184  }
1185  }
1186  }
1187 
1189  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1191  if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
1192  continue;
1193 
1194  LiveInterval &LI = LIS->getInterval(Reg);
1195  if (!LI.liveAt(PrevIndex))
1196  continue;
1197 
1198  bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
1199  if (isLiveOut && isLastMBB) {
1200  VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
1201  assert(VNI && "LiveInterval should have VNInfo where it is live.");
1202  LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
1203  } else if (!isLiveOut && !isLastMBB) {
1204  LI.removeSegment(StartIndex, EndIndex);
1205  }
1206  }
1207 
1208  // Update all intervals for registers whose uses may have been modified by
1209  // updateTerminator().
1210  LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
1211  }
1212 
1213  if (MachineDominatorTree *MDT =
1214  P.getAnalysisIfAvailable<MachineDominatorTree>())
1215  MDT->recordSplitCriticalEdge(this, Succ, NMBB);
1216 
1217  if (MachineLoopInfo *MLI = P.getAnalysisIfAvailable<MachineLoopInfo>())
1218  if (MachineLoop *TIL = MLI->getLoopFor(this)) {
1219  // If one or the other blocks were not in a loop, the new block is not
1220  // either, and thus LI doesn't need to be updated.
1221  if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
1222  if (TIL == DestLoop) {
1223  // Both in the same loop, the NMBB joins loop.
1224  DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
1225  } else if (TIL->contains(DestLoop)) {
1226  // Edge from an outer loop to an inner loop. Add to the outer loop.
1227  TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
1228  } else if (DestLoop->contains(TIL)) {
1229  // Edge from an inner loop to an outer loop. Add to the outer loop.
1230  DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
1231  } else {
1232  // Edge from two loops with no containment relation. Because these
1233  // are natural loops, we know that the destination block must be the
1234  // header of its loop (adding a branch into a loop elsewhere would
1235  // create an irreducible loop).
1236  assert(DestLoop->getHeader() == Succ &&
1237  "Should not create irreducible loops!");
1238  if (MachineLoop *P = DestLoop->getParentLoop())
1239  P->addBasicBlockToLoop(NMBB, MLI->getBase());
1240  }
1241  }
1242  }
1243 
1244  return NMBB;
1245 }
1246 
1248  const MachineBasicBlock *Succ) const {
1249  // Splitting the critical edge to a landing pad block is non-trivial. Don't do
1250  // it in this generic function.
1251  if (Succ->isEHPad())
1252  return false;
1253 
1254  // Splitting the critical edge to a callbr's indirect block isn't advised.
1255  // Don't do it in this generic function.
1256  if (Succ->isInlineAsmBrIndirectTarget())
1257  return false;
1258 
1259  const MachineFunction *MF = getParent();
1260  // Performance might be harmed on HW that implements branching using exec mask
1261  // where both sides of the branches are always executed.
1262  if (MF->getTarget().requiresStructuredCFG())
1263  return false;
1264 
1265  // We may need to update this's terminator, but we can't do that if
1266  // analyzeBranch fails. If this uses a jump table, we won't touch it.
1267  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1268  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
1270  // AnalyzeBanch should modify this, since we did not allow modification.
1271  if (TII->analyzeBranch(*const_cast<MachineBasicBlock *>(this), TBB, FBB, Cond,
1272  /*AllowModify*/ false))
1273  return false;
1274 
1275  // Avoid bugpoint weirdness: A block may end with a conditional branch but
1276  // jumps to the same MBB is either case. We have duplicate CFG edges in that
1277  // case that we can't handle. Since this never happens in properly optimized
1278  // code, just skip those edges.
1279  if (TBB && TBB == FBB) {
1280  LLVM_DEBUG(dbgs() << "Won't split critical edge after degenerate "
1281  << printMBBReference(*this) << '\n');
1282  return false;
1283  }
1284  return true;
1285 }
1286 
1287 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
1288 /// neighboring instructions so the bundle won't be broken by removing MI.
1290  // Removing the first instruction in a bundle.
1291  if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
1292  MI->unbundleFromSucc();
1293  // Removing the last instruction in a bundle.
1294  if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
1295  MI->unbundleFromPred();
1296  // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
1297  // are already fine.
1298 }
1299 
1302  unbundleSingleMI(&*I);
1303  return Insts.erase(I);
1304 }
1305 
1308  MI->clearFlag(MachineInstr::BundledPred);
1309  MI->clearFlag(MachineInstr::BundledSucc);
1310  return Insts.remove(MI);
1311 }
1312 
1315  assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
1316  "Cannot insert instruction with bundle flags");
1317  // Set the bundle flags when inserting inside a bundle.
1318  if (I != instr_end() && I->isBundledWithPred()) {
1319  MI->setFlag(MachineInstr::BundledPred);
1320  MI->setFlag(MachineInstr::BundledSucc);
1321  }
1322  return Insts.insert(I, MI);
1323 }
1324 
1325 /// This method unlinks 'this' from the containing function, and returns it, but
1326 /// does not delete it.
1328  assert(getParent() && "Not embedded in a function!");
1329  getParent()->remove(this);
1330  return this;
1331 }
1332 
1333 /// This method unlinks 'this' from the containing function, and deletes it.
1335  assert(getParent() && "Not embedded in a function!");
1336  getParent()->erase(this);
1337 }
1338 
1339 /// Given a machine basic block that branched to 'Old', change the code and CFG
1340 /// so that it branches to 'New' instead.
1342  MachineBasicBlock *New) {
1343  assert(Old != New && "Cannot replace self with self!");
1344 
1346  while (I != instr_begin()) {
1347  --I;
1348  if (!I->isTerminator()) break;
1349 
1350  // Scan the operands of this machine instruction, replacing any uses of Old
1351  // with New.
1352  for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1353  if (I->getOperand(i).isMBB() &&
1354  I->getOperand(i).getMBB() == Old)
1355  I->getOperand(i).setMBB(New);
1356  }
1357 
1358  // Update the successor information.
1359  replaceSuccessor(Old, New);
1360 }
1361 
1363  MachineBasicBlock *New) {
1364  for (MachineInstr &MI : phis())
1365  for (unsigned i = 2, e = MI.getNumOperands() + 1; i != e; i += 2) {
1366  MachineOperand &MO = MI.getOperand(i);
1367  if (MO.getMBB() == Old)
1368  MO.setMBB(New);
1369  }
1370 }
1371 
1372 /// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE
1373 /// instructions. Return UnknownLoc if there is none.
1374 DebugLoc
1376  // Skip debug declarations, we don't want a DebugLoc from them.
1378  if (MBBI != instr_end())
1379  return MBBI->getDebugLoc();
1380  return {};
1381 }
1382 
1384  // Skip debug declarations, we don't want a DebugLoc from them.
1386  if (!MBBI->isDebugInstr())
1387  return MBBI->getDebugLoc();
1388  return {};
1389 }
1390 
1391 /// Find the previous valid DebugLoc preceding MBBI, skipping and DBG_VALUE
1392 /// instructions. Return UnknownLoc if there is none.
1394  if (MBBI == instr_begin()) return {};
1395  // Skip debug instructions, we don't want a DebugLoc from them.
1397  if (!MBBI->isDebugInstr()) return MBBI->getDebugLoc();
1398  return {};
1399 }
1400 
1402  if (MBBI == instr_rend())
1403  return {};
1404  // Skip debug declarations, we don't want a DebugLoc from them.
1406  if (MBBI != instr_rend())
1407  return MBBI->getDebugLoc();
1408  return {};
1409 }
1410 
1411 /// Find and return the merged DebugLoc of the branch instructions of the block.
1412 /// Return UnknownLoc if there is none.
1413 DebugLoc
1415  DebugLoc DL;
1416  auto TI = getFirstTerminator();
1417  while (TI != end() && !TI->isBranch())
1418  ++TI;
1419 
1420  if (TI != end()) {
1421  DL = TI->getDebugLoc();
1422  for (++TI ; TI != end() ; ++TI)
1423  if (TI->isBranch())
1424  DL = DILocation::getMergedLocation(DL, TI->getDebugLoc());
1425  }
1426  return DL;
1427 }
1428 
1429 /// Return probability of the edge from this block to MBB.
1431 MachineBasicBlock::getSuccProbability(const_succ_iterator Succ) const {
1432  if (Probs.empty())
1433  return BranchProbability(1, succ_size());
1434 
1435  const auto &Prob = *getProbabilityIterator(Succ);
1436  if (Prob.isUnknown()) {
1437  // For unknown probabilities, collect the sum of all known ones, and evenly
1438  // ditribute the complemental of the sum to each unknown probability.
1439  unsigned KnownProbNum = 0;
1440  auto Sum = BranchProbability::getZero();
1441  for (auto &P : Probs) {
1442  if (!P.isUnknown()) {
1443  Sum += P;
1444  KnownProbNum++;
1445  }
1446  }
1447  return Sum.getCompl() / (Probs.size() - KnownProbNum);
1448  } else
1449  return Prob;
1450 }
1451 
1452 /// Set successor probability of a given iterator.
1454  BranchProbability Prob) {
1455  assert(!Prob.isUnknown());
1456  if (Probs.empty())
1457  return;
1458  *getProbabilityIterator(I) = Prob;
1459 }
1460 
1461 /// Return probability iterator corresonding to the I successor iterator
1462 MachineBasicBlock::const_probability_iterator
1463 MachineBasicBlock::getProbabilityIterator(
1465  assert(Probs.size() == Successors.size() && "Async probability list!");
1466  const size_t index = std::distance(Successors.begin(), I);
1467  assert(index < Probs.size() && "Not a current successor!");
1468  return Probs.begin() + index;
1469 }
1470 
1471 /// Return probability iterator corresonding to the I successor iterator.
1472 MachineBasicBlock::probability_iterator
1473 MachineBasicBlock::getProbabilityIterator(MachineBasicBlock::succ_iterator I) {
1474  assert(Probs.size() == Successors.size() && "Async probability list!");
1475  const size_t index = std::distance(Successors.begin(), I);
1476  assert(index < Probs.size() && "Not a current successor!");
1477  return Probs.begin() + index;
1478 }
1479 
1480 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1481 /// as of just before "MI".
1482 ///
1483 /// Search is localised to a neighborhood of
1484 /// Neighborhood instructions before (searching for defs or kills) and N
1485 /// instructions after (searching just for defs) MI.
1488  MCRegister Reg, const_iterator Before,
1489  unsigned Neighborhood) const {
1490  unsigned N = Neighborhood;
1491 
1492  // Try searching forwards from Before, looking for reads or defs.
1493  const_iterator I(Before);
1494  for (; I != end() && N > 0; ++I) {
1495  if (I->isDebugOrPseudoInstr())
1496  continue;
1497 
1498  --N;
1499 
1501 
1502  // Register is live when we read it here.
1503  if (Info.Read)
1504  return LQR_Live;
1505  // Register is dead if we can fully overwrite or clobber it here.
1506  if (Info.FullyDefined || Info.Clobbered)
1507  return LQR_Dead;
1508  }
1509 
1510  // If we reached the end, it is safe to clobber Reg at the end of a block of
1511  // no successor has it live in.
1512  if (I == end()) {
1513  for (MachineBasicBlock *S : successors()) {
1514  for (const MachineBasicBlock::RegisterMaskPair &LI : S->liveins()) {
1515  if (TRI->regsOverlap(LI.PhysReg, Reg))
1516  return LQR_Live;
1517  }
1518  }
1519 
1520  return LQR_Dead;
1521  }
1522 
1523 
1524  N = Neighborhood;
1525 
1526  // Start by searching backwards from Before, looking for kills, reads or defs.
1527  I = const_iterator(Before);
1528  // If this is the first insn in the block, don't search backwards.
1529  if (I != begin()) {
1530  do {
1531  --I;
1532 
1533  if (I->isDebugOrPseudoInstr())
1534  continue;
1535 
1536  --N;
1537 
1539 
1540  // Defs happen after uses so they take precedence if both are present.
1541 
1542  // Register is dead after a dead def of the full register.
1543  if (Info.DeadDef)
1544  return LQR_Dead;
1545  // Register is (at least partially) live after a def.
1546  if (Info.Defined) {
1547  if (!Info.PartialDeadDef)
1548  return LQR_Live;
1549  // As soon as we saw a partial definition (dead or not),
1550  // we cannot tell if the value is partial live without
1551  // tracking the lanemasks. We are not going to do this,
1552  // so fall back on the remaining of the analysis.
1553  break;
1554  }
1555  // Register is dead after a full kill or clobber and no def.
1556  if (Info.Killed || Info.Clobbered)
1557  return LQR_Dead;
1558  // Register must be live if we read it.
1559  if (Info.Read)
1560  return LQR_Live;
1561 
1562  } while (I != begin() && N > 0);
1563  }
1564 
1565  // If all the instructions before this in the block are debug instructions,
1566  // skip over them.
1567  while (I != begin() && std::prev(I)->isDebugOrPseudoInstr())
1568  --I;
1569 
1570  // Did we get to the start of the block?
1571  if (I == begin()) {
1572  // If so, the register's state is definitely defined by the live-in state.
1573  for (const MachineBasicBlock::RegisterMaskPair &LI : liveins())
1574  if (TRI->regsOverlap(LI.PhysReg, Reg))
1575  return LQR_Live;
1576 
1577  return LQR_Dead;
1578  }
1579 
1580  // At this point we have no idea of the liveness of the register.
1581  return LQR_Unknown;
1582 }
1583 
1584 const uint32_t *
1586  // EH funclet entry does not preserve any registers.
1587  return isEHFuncletEntry() ? TRI->getNoPreservedMask() : nullptr;
1588 }
1589 
1590 const uint32_t *
1592  // If we see a return block with successors, this must be a funclet return,
1593  // which does not preserve any registers. If there are no successors, we don't
1594  // care what kind of return it is, putting a mask after it is a no-op.
1595  return isReturnBlock() && !succ_empty() ? TRI->getNoPreservedMask() : nullptr;
1596 }
1597 
1599  LiveIns.clear();
1600 }
1601 
1603  assert(getParent()->getProperties().hasProperty(
1605  "Liveness information is accurate");
1606  return LiveIns.begin();
1607 }
1608 
1610  const MachineFunction &MF = *getParent();
1613  "Liveness information is accurate");
1614 
1615  const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
1616  MCPhysReg ExceptionPointer = 0, ExceptionSelector = 0;
1617  if (MF.getFunction().hasPersonalityFn()) {
1618  auto PersonalityFn = MF.getFunction().getPersonalityFn();
1619  ExceptionPointer = TLI.getExceptionPointerRegister(PersonalityFn);
1620  ExceptionSelector = TLI.getExceptionSelectorRegister(PersonalityFn);
1621  }
1622 
1623  return liveout_iterator(*this, ExceptionPointer, ExceptionSelector, false);
1624 }
1625 
1627 const MBBSectionID
1628  MBBSectionID::ExceptionSectionID(MBBSectionID::SectionType::Exception);
llvm::TargetMachine::requiresStructuredCFG
bool requiresStructuredCFG() const
Definition: TargetMachine.h:219
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::SuccIterator
Definition: CFG.h:139
i
i
Definition: README.txt:29
llvm::next_nodbg
IterT next_nodbg(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It, then continue incrementing it while it points to a debug instruction.
Definition: MachineBasicBlock.h:1230
llvm::MachineBasicBlock::RegisterMaskPair::PhysReg
MCPhysReg PhysReg
Definition: MachineBasicBlock.h:103
llvm::MachineFunction::remove
void remove(iterator MBBI)
Definition: MachineFunction.h:848
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unsigned succ_size() const
Definition: MachineBasicBlock.h:344
llvm::MachineFunctionProperties::hasProperty
bool hasProperty(Property P) const
Definition: MachineFunction.h:169
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:506
llvm::ModuleSlotTracker::getLocalSlot
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:865
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:579
llvm::MachineBasicBlock::LivenessQueryResult
LivenessQueryResult
Possible outcome of a register liveness query to computeRegisterLiveness()
Definition: MachineBasicBlock.h:1017
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:202
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::HexagonInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
Definition: HexagonInstrInfo.cpp:559
llvm::DILocation::getMergedLocation
static const DILocation * getMergedLocation(const DILocation *LocA, const DILocation *LocB)
When two instructions are combined into a single instruction we also need to combine the original loc...
Definition: DebugInfoMetadata.cpp:100
DebugInfoMetadata.h
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@ Prefix
Definition: CommandLine.h:164
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineBasicBlock::ReplaceUsesOfBlockWith
void ReplaceUsesOfBlockWith(MachineBasicBlock *Old, MachineBasicBlock *New)
Given a machine basic block that branched to 'Old', change the code and CFG so that it branches to 'N...
Definition: MachineBasicBlock.cpp:1341
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Function
Definition: Function.h:62
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition: MachineFunction.h:586
llvm::BranchProbability::getNumerator
uint32_t getNumerator() const
Definition: BranchProbability.h:65
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::HexagonInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition: HexagonInstrInfo.cpp:389
llvm::MachineBasicBlock::instrs
instr_range instrs()
Definition: MachineBasicBlock.h:263
llvm::MachineBasicBlock::isEHFuncletEntry
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
Definition: MachineBasicBlock.h:552
llvm::LiveVariables::VarInfo::Kills
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
Definition: LiveVariables.h:89
llvm::ilist_node_with_parent< MachineBasicBlock, MachineFunction >::getNextNode
MachineBasicBlock * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:288
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineFunction::end
iterator end()
Definition: MachineFunction.h:818
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:119
llvm::LiveRange::Segment
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
llvm::MachineBasicBlock::isEntryBlock
bool isEntryBlock() const
Returns true if this is the entry block of the function.
Definition: MachineBasicBlock.cpp:289
llvm::MachineBasicBlock::setSuccProbability
void setSuccProbability(succ_iterator I, BranchProbability Prob)
Set successor probability of a given iterator.
Definition: MachineBasicBlock.cpp:1453
llvm::MachineFunction::getFunctionNumber
unsigned getFunctionNumber() const
getFunctionNumber - Return a unique ID for the current function.
Definition: MachineFunction.h:609
llvm::MachineBasicBlock::getEHCatchretSymbol
MCSymbol * getEHCatchretSymbol() const
Return the EHCatchret Symbol for this basic block.
Definition: MachineBasicBlock.cpp:91
MachineBasicBlock.h
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
llvm::MachineBasicBlock::isReturnBlock
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
Definition: MachineBasicBlock.h:805
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MachineBasicBlock::findDebugLoc
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
Definition: MachineBasicBlock.cpp:1375
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::MachineBasicBlock::livein_iterator
LiveInVector::const_iterator livein_iterator
Definition: MachineBasicBlock.h:398
llvm::MachineBasicBlock::moveBefore
void moveBefore(MachineBasicBlock *NewAfter)
Move 'this' block before or after the specified block.
Definition: MachineBasicBlock.cpp:637
llvm::BranchProbability::getZero
static BranchProbability getZero()
Definition: BranchProbability.h:49
llvm::MachineBasicBlock::liveins
iterator_range< livein_iterator > liveins() const
Definition: MachineBasicBlock.h:412
TargetInstrInfo.h
llvm::MBBSectionID::Number
unsigned Number
Definition: MachineBasicBlock.h:59
llvm::HexagonInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
Definition: HexagonInstrInfo.cpp:1578
llvm::TargetLoweringBase::getExceptionPointerRegister
virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: TargetLowering.h:1762
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:835
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
slot
Since we know that Vector is byte aligned and we know the element offset of we should change the load into a lve *x instead of doing a load store lve *x sequence Implement passing vectors by value into calls and receiving them as arguments GCC apparently tries to then a load and vperm of Variable We need a way to teach tblgen that some operands of an intrinsic are required to be constants The verifier should enforce this constraint We currently codegen SCALAR_TO_VECTOR as a store of the scalar to a byte aligned stack slot
Definition: README_ALTIVEC.txt:57
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:757
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::iplist_impl::remove
pointer remove(iterator &IT)
Definition: ilist.h:251
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::addLiveIns
void addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs)
Adds registers contained in LiveRegs to the block live-in list of MBB.
Definition: LivePhysRegs.cpp:259
llvm::ModuleSlotTracker::incorporateFunction
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:851
llvm::MachineBasicBlock::back
MachineInstr & back()
Definition: MachineBasicBlock.h:248
llvm::MachineBasicBlock::addSuccessorWithoutProb
void addSuccessorWithoutProb(MachineBasicBlock *Succ)
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:760
llvm::MBBSectionID
Definition: MachineBasicBlock.h:52
llvm::MachineBasicBlock::copySuccessor
void copySuccessor(MachineBasicBlock *Orig, succ_iterator I)
Copy a successor (and any probability info) from original block to this block's.
Definition: MachineBasicBlock.cpp:851
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
llvm::LegalityPredicates::any
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
Definition: LegalizerInfo.h:239
llvm::AnalyzePhysRegInBundle
PhysRegInfo AnalyzePhysRegInBundle(const MachineInstr &MI, Register Reg, const TargetRegisterInfo *TRI)
AnalyzePhysRegInBundle - Analyze how the current instruction or bundle uses a physical register.
Definition: MachineInstrBundle.cpp:308
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::MachineLoopInfo
Definition: MachineLoopInfo.h:90
MachineRegisterInfo.h
llvm::iplist_impl::erase
iterator erase(iterator where)
Definition: ilist.h:267
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::MachineBasicBlock::dump
void dump() const
Definition: MachineBasicBlock.cpp:294
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1301
llvm::MachineBasicBlock::isBeginSection
bool isBeginSection() const
Returns true if this block begins any section.
Definition: MachineBasicBlock.h:564
llvm::MachineRegisterInfo::tracksLiveness
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
Definition: MachineRegisterInfo.h:197
llvm::MachineBasicBlock::const_iterator
MachineInstrBundleIterator< const MachineInstr > const_iterator
Definition: MachineBasicBlock.h:234
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachineBasicBlock::printName
void printName(raw_ostream &os, unsigned printNameFlags=PrintNameIr, ModuleSlotTracker *moduleSlotTracker=nullptr) const
Print the basic block's name as:
Definition: MachineBasicBlock.cpp:477
isLiveOut
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
Definition: SIOptimizeExecMasking.cpp:286
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:750
PrintSlotIndexes
static cl::opt< bool > PrintSlotIndexes("print-slotindexes", cl::desc("When printing machine IR, annotate instructions and blocks with " "SlotIndexes when available"), cl::init(true), cl::Hidden)
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:60
TargetLowering.h
llvm::SparseBitVector
Definition: SparseBitVector.h:255
bb
< i1 > br i1 label label bb bb
Definition: README.txt:978
llvm::MachineBasicBlock::getFirstInstrTerminator
instr_iterator getFirstInstrTerminator()
Same getFirstTerminator but it ignores bundles and return an instr_iterator instead.
Definition: MachineBasicBlock.cpp:250
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:644
llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:191
llvm::LiveVariables::VarInfo::removeKill
bool removeKill(MachineInstr &MI)
removeKill - Delete a kill corresponding to the specified machine instruction.
Definition: LiveVariables.h:94
llvm::SlotIndexes::hasIndex
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:380
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineBasicBlock::removeFromParent
MachineBasicBlock * removeFromParent()
This method unlinks 'this' from the containing function, and returns it, but does not delete it.
Definition: MachineBasicBlock.cpp:1327
MachineLoopInfo.h
llvm::LiveRange::liveAt
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:393
TargetMachine.h
llvm::BranchProbability::getDenominator
static uint32_t getDenominator()
Definition: BranchProbability.h:66
llvm::LiveIntervals::getMBBStartIdx
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
Definition: LiveIntervals.h:236
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineBasicBlock::succ_end
succ_iterator succ_end()
Definition: MachineBasicBlock.h:334
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3254
llvm::LiveRange::addSegment
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
Definition: LiveInterval.cpp:548
MCContext.h
llvm::MachineBasicBlock::isSuccessor
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
Definition: MachineBasicBlock.cpp:912
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MachineBasicBlock::eraseFromParent
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Definition: MachineBasicBlock.cpp:1334
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:725
llvm::LivePhysRegs::addLiveOuts
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
Definition: LivePhysRegs.cpp:232
LiveVariables.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineBasicBlock::isLegalToHoistInto
bool isLegalToHoistInto() const
Returns true if it is legal to hoist instructions into this block.
Definition: MachineBasicBlock.cpp:307
llvm::MachineBasicBlock::RegisterMaskPair
Pair of physical register and lane mask.
Definition: MachineBasicBlock.h:101
llvm::MachineBasicBlock::splitAt
MachineBasicBlock * splitAt(MachineInstr &SplitInst, bool UpdateLiveIns=true, LiveIntervals *LIS=nullptr)
Split a basic block into 2 pieces at SplitPoint.
Definition: MachineBasicBlock.cpp:969
llvm::SlotIndexes::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:385
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::PrintLaneMask
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:94
llvm::Function::hasPersonalityFn
bool hasPersonalityFn() const
Check whether this function has a personality function.
Definition: Function.h:775
llvm::HexagonInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
Definition: HexagonInstrInfo.cpp:582
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register regA, Register regB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:418
llvm::MachineFunction::addToMBBNumbering
unsigned addToMBBNumbering(MachineBasicBlock *MBB)
Adds the MBB to the internal numbering.
Definition: MachineFunction.h:871
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:816
llvm::SlotIndexes
SlotIndexes pass.
Definition: SlotIndexes.h:314
SmallPtrSet.h
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
llvm::BranchProbability::getUnknown
static BranchProbability getUnknown()
Definition: BranchProbability.h:51
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineBasicBlock::findPrevDebugLoc
DebugLoc findPrevDebugLoc(instr_iterator MBBI)
Find the previous valid DebugLoc preceding MBBI, skipping and DBG_VALUE instructions.
Definition: MachineBasicBlock.cpp:1393
llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:125
llvm::LiveIntervals::insertMBBInMaps
void insertMBBInMaps(MachineBasicBlock *MBB)
Definition: LiveIntervals.h:259
llvm::ilist_traits
Template traits for intrusive list.
Definition: ilist.h:89
llvm::MachineBasicBlock::succ_iterator
std::vector< MachineBasicBlock * >::iterator succ_iterator
Definition: MachineBasicBlock.h:306
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:634
BasicBlock.h
llvm::cl::opt< bool >
llvm::MachineBasicBlock::mayHaveInlineAsmBr
bool mayHaveInlineAsmBr() const
Returns true if this block may have an INLINEASM_BR (overestimate, by checking if any of the successo...
Definition: MachineBasicBlock.cpp:299
llvm::LiveVariables::addNewBlock
void addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB, MachineBasicBlock *SuccBB)
addNewBlock - Add a new basic block BB between DomBB and SuccBB.
Definition: LiveVariables.cpp:833
llvm::MachineLoop
Definition: MachineLoopInfo.h:45
llvm::LivePhysRegs::stepBackward
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
Definition: LivePhysRegs.cpp:68
llvm::MachineBasicBlock::printAsOperand
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
Definition: MachineBasicBlock.cpp:555
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:395
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
llvm::MachineInstrBundleIterator::getReverse
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Definition: MachineInstrBundleIterator.h:283
llvm::SlotIndexes::getMBBStartIdx
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:466
llvm::MachineBasicBlock::instr_rend
reverse_instr_iterator instr_rend()
Definition: MachineBasicBlock.h:258
llvm::MachineFunctionProperties::Property::TracksLiveness
@ TracksLiveness
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
index
splat index
Definition: README_ALTIVEC.txt:181
uint64_t
LiveIntervals.h
llvm::MCContext::getAsmInfo
const MCAsmInfo * getAsmInfo() const
Definition: MCContext.h:423
llvm::MachineBasicBlock::hasAddressTaken
bool hasAddressTaken() const
Test whether this block is potentially the target of an indirect branch.
Definition: MachineBasicBlock.h:211
llvm::find
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1620
llvm::MachineFunction::splice
void splice(iterator InsertPt, iterator MBBI)
Definition: MachineFunction.h:838
llvm::MachineBasicBlock::SkipPHIsAndLabels
iterator SkipPHIsAndLabels(iterator I)
Return the first instruction in MBB after I that is not a PHI or a label.
Definition: MachineBasicBlock.cpp:209
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::MachineBasicBlock::instr_rbegin
reverse_instr_iterator instr_rbegin()
Definition: MachineBasicBlock.h:256
llvm::MachineBasicBlock::LQR_Live
@ LQR_Live
Register is known to be (at least partially) live.
Definition: MachineBasicBlock.h:1018
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::MachineBasicBlock::getFirstNonPHI
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Definition: MachineBasicBlock.cpp:199
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1665
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:415
llvm::prev_nodbg
IterT prev_nodbg(IterT It, IterT Begin, bool SkipPseudoOp=true)
Decrement It, then continue decrementing it while it points to a debug instruction.
Definition: MachineBasicBlock.h:1237
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:266
llvm::MachineBasicBlock::getAlignment
Align getAlignment() const
Return alignment of the basic block.
Definition: MachineBasicBlock.h:519
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:542
llvm::MBBSectionID::ExceptionSectionID
const static MBBSectionID ExceptionSectionID
Definition: MachineBasicBlock.h:65
llvm::BranchProbability::isUnknown
bool isUnknown() const
Definition: BranchProbability.h:47
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::canFallThrough
bool canFallThrough()
Return true if the block can implicitly transfer control to the block after it by falling off the end...
Definition: MachineBasicBlock.cpp:965
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:332
llvm::IndexedInstrProf::HashT::Last
@ Last
llvm::PhysRegInfo
Information about how a physical register Reg is used by a set of operands.
Definition: MachineInstrBundle.h:246
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineFunction::const_iterator
BasicBlockListType::const_iterator const_iterator
Definition: MachineFunction.h:799
llvm::MachineFunction::erase
void erase(iterator MBBI)
Definition: MachineFunction.h:850
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineBasicBlock::livein_end
livein_iterator livein_end() const
Definition: MachineBasicBlock.h:410
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::MachineBasicBlock::predecessors
iterator_range< pred_iterator > predecessors()
Definition: MachineBasicBlock.h:349
llvm::MachineBasicBlock::reverse_instr_iterator
Instructions::reverse_iterator reverse_instr_iterator
Definition: MachineBasicBlock.h:230
llvm::MachineBasicBlock::LQR_Dead
@ LQR_Dead
Register is known to be fully dead.
Definition: MachineBasicBlock.h:1019
llvm::MachineBasicBlock::instr_begin
instr_iterator instr_begin()
Definition: MachineBasicBlock.h:252
llvm::MachineBasicBlock::pred_empty
bool pred_empty() const
Definition: MachineBasicBlock.h:331
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
llvm::MachineBasicBlock::instr_end
instr_iterator instr_end()
Definition: MachineBasicBlock.h:254
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::MachineBasicBlock::moveAfter
void moveAfter(MachineBasicBlock *NewBefore)
Definition: MachineBasicBlock.cpp:641
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:347
llvm::MachineBasicBlock::PrintNameIr
@ PrintNameIr
Add IR name where available.
Definition: MachineBasicBlock.h:1044
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:241
llvm::skipDebugInstructionsForward
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
Definition: MachineBasicBlock.h:1206
llvm::MachineBasicBlock::getBeginClobberMask
const uint32_t * getBeginClobberMask(const TargetRegisterInfo *TRI) const
Get the clobber mask for the start of this basic block.
Definition: MachineBasicBlock.cpp:1585
llvm::MachineBasicBlock::phis
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
Definition: MachineBasicBlock.h:296
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition: MachineBasicBlock.h:1056
MCAsmInfo.h
DataLayout.h
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::MachineBasicBlock::PrintNameAttributes
@ PrintNameAttributes
Print attributes.
Definition: MachineBasicBlock.h:1045
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:355
llvm::MachineBasicBlock::getFirstNonDebugInstr
iterator getFirstNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the first non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:260
llvm::MachineBasicBlock::isEHPad
bool isEHPad() const
Returns true if the block is a landing pad.
Definition: MachineBasicBlock.h:526
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineBasicBlock::rbegin
reverse_iterator rbegin()
Definition: MachineBasicBlock.h:272
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:950
llvm::MachineBasicBlock::hasEHPadSuccessor
bool hasEHPadSuccessor() const
Definition: MachineBasicBlock.cpp:282
llvm::LivePhysRegs::init
void init(const TargetRegisterInfo &TRI)
(re-)initializes and clears the set.
Definition: LivePhysRegs.h:66
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineBasicBlock::getFullName
std::string getFullName() const
Return a formatted string to identify this block and its parent function.
Definition: MachineBasicBlock.cpp:321
llvm::MachineBasicBlock::findBranchDebugLoc
DebugLoc findBranchDebugLoc()
Find and return the merged DebugLoc of the branch instructions of the block.
Definition: MachineBasicBlock.cpp:1414
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::MachineBasicBlock::removeLiveIn
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
Definition: MachineBasicBlock.cpp:561
llvm::MBBSectionID::Type
enum llvm::MBBSectionID::SectionType Type
llvm::MachineBasicBlock::rfindDebugLoc
DebugLoc rfindDebugLoc(reverse_instr_iterator MBBI)
Has exact same behavior as findDebugLoc (it also searches from the first to the last MI of this MBB) ...
Definition: MachineBasicBlock.cpp:1383
Number
uint32_t Number
Definition: Profile.cpp:47
llvm::ilist_callback_traits::addNodeToList
void addNodeToList(NodeTy *)
When an MBB is added to an MF, we need to update the parent pointer of the MBB, the MBB numbering,...
Definition: ilist.h:65
uint32_t
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineBasicBlock, Options... >::type >::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MachineFunction::hasBBSections
bool hasBBSections() const
Returns true if this function has basic block sections enabled.
Definition: MachineFunction.h:612
llvm::MachineBasicBlock::splitSuccessor
void splitSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New, bool NormalizeSuccProbs=false)
Split the old successor into old plus new and updates the probability info.
Definition: MachineBasicBlock.cpp:769
llvm::CallingConv::Cold
@ Cold
Definition: CallingConv.h:48
llvm::format
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
llvm::MachineBasicBlock::liveout_begin
liveout_iterator liveout_begin() const
Iterator scanning successor basic blocks' liveins to determine the registers potentially live at the ...
Definition: MachineBasicBlock.cpp:1609
llvm::PredIterator
Definition: CFG.h:43
llvm::Value::getName
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:309
llvm::MachineBasicBlock::transferSuccessors
void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
Definition: MachineBasicBlock.cpp:869
llvm::MachineBasicBlock::getSectionID
MBBSectionID getSectionID() const
Returns the section ID of this basic block.
Definition: MachineBasicBlock.h:574
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::MachineBasicBlock::isPredecessor
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
Definition: MachineBasicBlock.cpp:908
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1627
llvm::MachineBasicBlock::getEndSymbol
MCSymbol * getEndSymbol() const
Returns the MCSymbol marking the end of this basic block.
Definition: MachineBasicBlock.cpp:102
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineBasicBlock::canSplitCriticalEdge
bool canSplitCriticalEdge(const MachineBasicBlock *Succ) const
Check if the edge between this block and the given successor Succ, can be split.
Definition: MachineBasicBlock.cpp:1247
llvm::AMDGPU::HSAMD::Kernel::Key::SymbolName
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
Definition: AMDGPUMetadata.h:381
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::TargetLoweringBase::getExceptionSelectorRegister
virtual Register getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: TargetLowering.h:1769
llvm::MachineBasicBlock::replaceSuccessor
void replaceSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New)
Replace successor OLD with NEW and update probability info.
Definition: MachineBasicBlock.cpp:811
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::MachineBasicBlock::replacePhiUsesWith
void replacePhiUsesWith(MachineBasicBlock *Old, MachineBasicBlock *New)
Update all phi nodes in this basic block to refer to basic block New instead of basic block Old.
Definition: MachineBasicBlock.cpp:1362
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:600
llvm::MachineBasicBlock::sortUniqueLiveIns
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
Definition: MachineBasicBlock.cpp:585
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:630
llvm::MachineBasicBlock::removeSuccessor
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:788
llvm::MBBSectionID::ColdSectionID
const static MBBSectionID ColdSectionID
Definition: MachineBasicBlock.h:64
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1314
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::MachineBasicBlock::computeRegisterLiveness
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, MCRegister Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been defined and not killed as of just before Before.
Definition: MachineBasicBlock.cpp:1487
llvm::SlotIndex::getPrevSlot
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:289
llvm::MachineBasicBlock::liveout_iterator
Definition: MachineBasicBlock.h:419
llvm::MachineBasicBlock::instr_iterator
Instructions::iterator instr_iterator
Definition: MachineBasicBlock.h:228
llvm::AArch64CC::LS
@ LS
Definition: AArch64BaseInfo.h:264
llvm::MCAsmInfo::getPrivateLabelPrefix
StringRef getPrivateLabelPrefix() const
Definition: MCAsmInfo.h:655
llvm::ilist_callback_traits::removeNodeFromList
void removeNodeFromList(NodeTy *)
Definition: ilist.h:66
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:247
llvm::sort
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:1541
llvm::MachineBasicBlock::livein_begin
livein_iterator livein_begin() const
Definition: MachineBasicBlock.cpp:1602
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::LiveRange::getVNInfoAt
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:413
unbundleSingleMI
static void unbundleSingleMI(MachineInstr *MI)
Prepare MI to be removed from its bundle.
Definition: MachineBasicBlock.cpp:1289
llvm::MachineBasicBlock::isLayoutSuccessor
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
Definition: MachineBasicBlock.cpp:916
llvm::MachineBasicBlock::rfindPrevDebugLoc
DebugLoc rfindPrevDebugLoc(reverse_instr_iterator MBBI)
Has exact same behavior as findPrevDebugLoc (it also searches from the last to the first MI of this M...
Definition: MachineBasicBlock.cpp:1401
llvm::MachineBasicBlock::normalizeSuccProbs
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
Definition: MachineBasicBlock.h:654
llvm::TargetRegisterInfo::getNoPreservedMask
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
Definition: TargetRegisterInfo.h:501
llvm::Function::getPersonalityFn
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1834
llvm::MachineBasicBlock::livein_empty
bool livein_empty() const
Definition: MachineBasicBlock.h:411
llvm::MachineBasicBlock::getFallThrough
MachineBasicBlock * getFallThrough()
Return the fallthrough block if the block can implicitly transfer control to the block after it by fa...
Definition: MachineBasicBlock.cpp:921
llvm::LiveRange::removeSegment
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
Definition: LiveInterval.cpp:583
llvm::iplist_impl::insert
iterator insert(iterator where, pointer New)
Definition: ilist.h:228
llvm::MachineBasicBlock::validateSuccProbs
void validateSuccProbs() const
Validate successors' probabilities and check if the sum of them is approximate one.
Definition: MachineBasicBlock.cpp:736
llvm::MachineBasicBlock::getEndClobberMask
const uint32_t * getEndClobberMask(const TargetRegisterInfo *TRI) const
Get the clobber mask for the end of the basic block.
Definition: MachineBasicBlock.cpp:1591
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::HexagonInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
Definition: HexagonInstrInfo.cpp:1545
llvm::TargetSubtargetInfo::getTargetLowering
virtual const TargetLowering * getTargetLowering() const
Definition: TargetSubtargetInfo.h:96
llvm::skipDebugInstructionsBackward
IterT skipDebugInstructionsBackward(IterT It, IterT Begin, bool SkipPseudoOp=true)
Decrement It until it points to a non-debug instruction or to Begin and return the resulting iterator...
Definition: MachineBasicBlock.h:1219
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::MachineBasicBlock::isInlineAsmBrIndirectTarget
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
Definition: MachineBasicBlock.h:594
llvm::raw_ostream::indent
raw_ostream & indent(unsigned NumSpaces)
indent - Insert 'NumSpaces' spaces.
Definition: raw_ostream.cpp:497
llvm::ilist_alloc_traits::deleteNode
static void deleteNode(NodeTy *V)
Definition: ilist.h:41
llvm::Printable
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
llvm::MachineInstr::BundledSucc
@ BundledSucc
Definition: MachineInstr.h:87
llvm::LiveVariables::getVarInfo
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
Definition: LiveVariables.cpp:84
llvm::MachineOperand::setMBB
void setMBB(MachineBasicBlock *MBB)
Definition: MachineOperand.h:689
llvm::MachineBasicBlock::const_succ_iterator
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
Definition: MachineBasicBlock.h:307
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:658
llvm::MachineBasicBlock::clearLiveIns
void clearLiveIns()
Clear live in list.
Definition: MachineBasicBlock.cpp:1598
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:85
ModuleSlotTracker.h
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:889
DataTypes.h
llvm::LiveIntervals::repairIntervalsInRange
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< Register > OrigRegs)
Update live intervals for instructions in a range of iterators.
Definition: LiveIntervals.cpp:1654
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::LiveVariables
Definition: LiveVariables.h:46
llvm::MachineBasicBlock::LQR_Unknown
@ LQR_Unknown
Register liveness not decidable from local neighborhood.
Definition: MachineBasicBlock.h:1020
llvm::MachineBasicBlock::SkipPHIsLabelsAndDebug
iterator SkipPHIsLabelsAndDebug(iterator I, bool SkipPseudoOp=true)
Return the first instruction in MBB after I that is not a PHI, label or debug.
Definition: MachineBasicBlock.cpp:224
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:125
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineBasicBlock::print
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
Definition: MachineBasicBlock.cpp:332
SlotIndexes.h
llvm::cl::desc
Definition: CommandLine.h:412
llvm::ilist_callback_traits::transferNodesFromList
void transferNodesFromList(ilist_callback_traits &OldList, Iterator, Iterator)
Callback before transferring nodes to this list.
Definition: ilist.h:71
llvm::MachineBasicBlock::updateTerminator
void updateTerminator(MachineBasicBlock *PreviousLayoutSuccessor)
Update the terminator instructions in block to account for changes to block layout which may have bee...
Definition: MachineBasicBlock.cpp:645
raw_ostream.h
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:46
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineInstr::BundledPred
@ BundledPred
Definition: MachineInstr.h:86
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1282
llvm::MachineBasicBlock::SplitCriticalEdge
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P, std::vector< SparseBitVector<>> *LiveInSets=nullptr)
Split the critical edge from this block to the given successor block, and return the newly created bl...
Definition: MachineBasicBlock.cpp:1010
llvm::MCID::Terminator
@ Terminator
Definition: MCInstrDesc.h:155
llvm::MachineBasicBlock::remove_instr
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
Definition: MachineBasicBlock.cpp:1306
TargetRegisterInfo.h
llvm::MachineBasicBlock::getName
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
Definition: MachineBasicBlock.cpp:313
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::Optional::getValue
constexpr const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:282
MachineDominators.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24