27 for (
unsigned i = 0, e =
MI->getNumOperands(); i != e; ++i) {
48 if (
MI->getOpcode() == SPIRV::OpExtInst && i == 2) {
This file contains the declarations for the subclasses of Constant, which represent the different fla...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
float convertToFloat() const
Converts this APFloat to host float value.
const APFloat & getValueAPF() const
Instances of this class represent a single low-level machine instruction.
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
static MCOperand createDFPImm(uint64_t Val)
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
MachineBasicBlock * getMBB() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Register getReg() const
getReg - Returns the register number.
const ConstantFP * getFPImm() const
@ MO_Immediate
Immediate operand.
@ MO_GlobalAddress
Address of a global value.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_FPImmediate
Floating-point immediate operand.
Wrapper class representing virtual and physical registers.
constexpr bool isValid() const
void lower(const MachineInstr *MI, MCInst &OutMI, SPIRV::ModuleAnalysisInfo *MAI) const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Register getRegisterAlias(const MachineFunction *MF, Register Reg)
Register getExtInstSetReg(unsigned SetNum)
Register getOrCreateMBBRegister(const MachineBasicBlock &MBB)
Register getFuncReg(const Function *F)