LLVM  16.0.0git
SPIRVModuleAnalysis.h
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1 //===- SPIRVModuleAnalysis.h - analysis of global instrs & regs -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // The analysis collects instructions that should be output at the module level
10 // and performs the global register numbering.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_SPIRV_SPIRVMODULEANALYSIS_H
15 #define LLVM_LIB_TARGET_SPIRV_SPIRVMODULEANALYSIS_H
16 
18 #include "SPIRVGlobalRegistry.h"
19 #include "SPIRVUtils.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/SmallSet.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringMap.h"
24 
25 namespace llvm {
26 class SPIRVSubtarget;
27 class MachineFunction;
28 class MachineModuleInfo;
29 
30 namespace SPIRV {
31 // The enum contains logical module sections for the instruction collection.
33  // MB_Capabilities, MB_Extensions, MB_ExtInstImports, MB_MemoryModel,
34  MB_EntryPoints, // All OpEntryPoint instructions (if any).
35  // MB_ExecutionModes, MB_DebugSourceAndStrings,
36  MB_DebugNames, // All OpName and OpMemberName intrs.
37  MB_DebugModuleProcessed, // All OpModuleProcessed instructions.
38  MB_Annotations, // OpDecorate, OpMemberDecorate etc.
39  MB_TypeConstVars, // OpTypeXXX, OpConstantXXX, and global OpVariables.
40  MB_ExtFuncDecls, // OpFunction etc. to declare for external funcs.
41  NUM_MODULE_SECTIONS // Total number of sections requiring basic blocks.
42 };
43 
44 struct Requirements {
45  const bool IsSatisfiable;
46  const std::optional<Capability::Capability> Cap;
48  const unsigned MinVer; // 0 if no min version is required.
49  const unsigned MaxVer; // 0 if no max version is required.
50 
52  std::optional<Capability::Capability> Cap = {},
53  ExtensionList Exts = {}, unsigned MinVer = 0,
54  unsigned MaxVer = 0)
56  MaxVer(MaxVer) {}
57  Requirements(Capability::Capability Cap) : Requirements(true, {Cap}) {}
58 };
59 
61 private:
62  CapabilityList MinimalCaps;
65  unsigned MinVersion; // 0 if no min version is defined.
66  unsigned MaxVersion; // 0 if no max version is defined.
67  DenseSet<unsigned> AvailableCaps;
68  // Remove a list of capabilities from dedupedCaps and add them to AllCaps,
69  // recursing through their implicitly declared capabilities too.
70  void pruneCapabilities(const CapabilityList &ToPrune);
71 
72 public:
73  RequirementHandler() : MinVersion(0), MaxVersion(0) {}
74  void clear() {
75  MinimalCaps.clear();
76  AllCaps.clear();
77  AvailableCaps.clear();
78  AllExtensions.clear();
79  MinVersion = 0;
80  MaxVersion = 0;
81  }
82  unsigned getMinVersion() const { return MinVersion; }
83  unsigned getMaxVersion() const { return MaxVersion; }
84  const CapabilityList &getMinimalCapabilities() const { return MinimalCaps; }
86  return AllExtensions;
87  }
88  // Add a list of capabilities, ensuring AllCaps captures all the implicitly
89  // declared capabilities, and MinimalCaps has the minimal set of required
90  // capabilities (so all implicitly declared ones are removed).
91  void addCapabilities(const CapabilityList &ToAdd);
92  void addCapability(Capability::Capability ToAdd) { addCapabilities({ToAdd}); }
93  void addExtensions(const ExtensionList &ToAdd) {
94  AllExtensions.insert(ToAdd.begin(), ToAdd.end());
95  }
96  void addExtension(Extension::Extension ToAdd) { AllExtensions.insert(ToAdd); }
97  // Add the given requirements to the lists. If constraints conflict, or these
98  // requirements cannot be satisfied, then abort the compilation.
99  void addRequirements(const Requirements &Req);
100  // Get requirement and add it to the list.
101  void getAndAddRequirements(SPIRV::OperandCategory::OperandCategory Category,
102  uint32_t i, const SPIRVSubtarget &ST);
103  // Check if all the requirements can be satisfied for the given subtarget, and
104  // if not abort compilation.
105  void checkSatisfiable(const SPIRVSubtarget &ST) const;
107  // Add the given capabilities to available and all their implicitly defined
108  // capabilities too.
109  void addAvailableCaps(const CapabilityList &ToAdd);
110  bool isCapabilityAvailable(Capability::Capability Cap) const {
111  return AvailableCaps.contains(Cap);
112  }
113 };
114 
116 // Maps a local register to the corresponding global alias.
117 using LocalToGlobalRegTable = std::map<Register, Register>;
118 using RegisterAliasMapTy =
119  std::map<const MachineFunction *, LocalToGlobalRegTable>;
120 
121 // The struct contains results of the module analysis and methods
122 // to access them.
125  MemoryModel::MemoryModel Mem;
126  AddressingModel::AddressingModel Addr;
128  unsigned SrcLangVersion;
130  // Maps ExtInstSet to corresponding ID register.
132  // Contains the list of all global OpVariables in the module.
134  // Maps function names to coresponding function ID registers.
136  // The set contains machine instructions which are necessary
137  // for correct MIR but will not be emitted in function bodies.
139  // The set contains machine basic blocks which are necessary
140  // for correct MIR but will not be emitted.
142  // The table contains global aliases of local registers for each machine
143  // function. The aliases are used to substitute local registers during
144  // code emission.
146  // The counter holds the maximum ID we have in the module.
147  unsigned MaxID;
148  // The array contains lists of MIs for each module section.
150  // The table maps MBB number to SPIR-V unique ID register.
152 
154  assert(F && "Function is null");
155  auto FuncReg = FuncNameMap.find(getFunctionGlobalIdentifier(F));
156  assert(FuncReg != FuncNameMap.end() && "Cannot find function Id");
157  return FuncReg->second;
158  }
159  Register getExtInstSetReg(unsigned SetNum) { return ExtInstSetMap[SetNum]; }
160  InstrList &getMSInstrs(unsigned MSType) { return MS[MSType]; }
163  return InstrsToDelete.contains(MI);
164  }
166  Register AliasReg) {
167  RegisterAliasTable[MF][Reg] = AliasReg;
168  }
170  auto RI = RegisterAliasTable[MF].find(Reg);
171  if (RI == RegisterAliasTable[MF].end()) {
172  return Register(0);
173  }
174  return RegisterAliasTable[MF][Reg];
175  }
177  return RegisterAliasTable.find(MF) != RegisterAliasTable.end() &&
178  RegisterAliasTable[MF].find(Reg) != RegisterAliasTable[MF].end();
179  }
180  unsigned getNextID() { return MaxID++; }
182  return BBNumToRegMap.find(MBB.getNumber()) != BBNumToRegMap.end();
183  }
184  // Convert MBB's number to corresponding ID register.
186  auto f = BBNumToRegMap.find(MBB.getNumber());
187  if (f != BBNumToRegMap.end())
188  return f->second;
190  BBNumToRegMap[MBB.getNumber()] = NewReg;
191  return NewReg;
192  }
193 };
194 } // namespace SPIRV
195 
197  static char ID;
198 
199 public:
201 
202  bool runOnModule(Module &M) override;
203  void getAnalysisUsage(AnalysisUsage &AU) const override;
205 
206 private:
207  void setBaseInfo(const Module &M);
208  void collectGlobalEntities(
209  const std::vector<SPIRV::DTSortableEntry *> &DepsGraph,
211  std::function<bool(const SPIRV::DTSortableEntry *)> Pred,
212  bool UsePreOrder);
213  void processDefInstrs(const Module &M);
214  void collectFuncNames(MachineInstr &MI, const Function &F);
215  void processOtherInstrs(const Module &M);
216  void numberRegistersGlobally(const Module &M);
217 
218  const SPIRVSubtarget *ST;
220  const SPIRVInstrInfo *TII;
221  MachineModuleInfo *MMI;
222 };
223 } // namespace llvm
224 #endif // LLVM_LIB_TARGET_SPIRV_SPIRVMODULEANALYSIS_H
llvm::SPIRV::ModuleAnalysisInfo::setRegisterAlias
void setRegisterAlias(const MachineFunction *MF, Register Reg, Register AliasReg)
Definition: SPIRVModuleAnalysis.h:165
i
i
Definition: README.txt:29
llvm::SPIRV::ModuleSectionType
ModuleSectionType
Definition: SPIRVModuleAnalysis.h:32
llvm::SPIRV::RequirementHandler::getMaxVersion
unsigned getMaxVersion() const
Definition: SPIRVModuleAnalysis.h:83
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::ModulePass
ModulePass class - This class is used to implement unstructured interprocedural optimizations and ana...
Definition: Pass.h:248
llvm::SPIRV::MB_TypeConstVars
@ MB_TypeConstVars
Definition: SPIRVModuleAnalysis.h:39
llvm::Function
Definition: Function.h:60
llvm::SPIRV::NUM_MODULE_SECTIONS
@ NUM_MODULE_SECTIONS
Definition: SPIRVModuleAnalysis.h:41
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::SPIRV::RequirementHandler::initAvailableCapabilities
void initAvailableCapabilities(const SPIRVSubtarget &ST)
llvm::SPIRV::RequirementHandler::addExtensions
void addExtensions(const ExtensionList &ToAdd)
Definition: SPIRVModuleAnalysis.h:93
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SPIRV::Requirements::Exts
const ExtensionList Exts
Definition: SPIRVModuleAnalysis.h:47
llvm::SPIRV::Requirements::Cap
const std::optional< Capability::Capability > Cap
Definition: SPIRVModuleAnalysis.h:46
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1794
DenseMap.h
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::SPIRV::ModuleAnalysisInfo::getFuncReg
Register getFuncReg(const Function *F)
Definition: SPIRVModuleAnalysis.h:153
llvm::SPIRVSubtarget
Definition: SPIRVSubtarget.h:35
llvm::SmallSet< Capability::Capability, 8 >
llvm::SPIRV::LocalToGlobalRegTable
std::map< Register, Register > LocalToGlobalRegTable
Definition: SPIRVModuleAnalysis.h:117
llvm::SPIRV::ModuleAnalysisInfo::MaxID
unsigned MaxID
Definition: SPIRVModuleAnalysis.h:147
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::SPIRV::ModuleAnalysisInfo
Definition: SPIRVModuleAnalysis.h:123
llvm::SPIRV::ModuleAnalysisInfo::SrcExt
StringSet SrcExt
Definition: SPIRVModuleAnalysis.h:129
llvm::SPIRV::ModuleAnalysisInfo::getMSInstrs
InstrList & getMSInstrs(unsigned MSType)
Definition: SPIRVModuleAnalysis.h:160
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::SPIRV::DTSortableEntry
Definition: SPIRVDuplicatesTracker.h:31
llvm::SPIRV::ModuleAnalysisInfo::setSkipEmission
void setSkipEmission(MachineInstr *MI)
Definition: SPIRVModuleAnalysis.h:161
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
SPIRVBaseInfo.h
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::SPIRV::RequirementHandler
Definition: SPIRVModuleAnalysis.h:60
llvm::SPIRVModuleAnalysis::MAI
static struct SPIRV::ModuleAnalysisInfo MAI
Definition: SPIRVModuleAnalysis.h:204
llvm::SPIRV::ModuleAnalysisInfo::getNextID
unsigned getNextID()
Definition: SPIRVModuleAnalysis.h:180
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineModuleInfo
This class contains meta information specific to a module.
Definition: MachineModuleInfo.h:74
llvm::SPIRV::ModuleAnalysisInfo::SrcLangVersion
unsigned SrcLangVersion
Definition: SPIRVModuleAnalysis.h:128
SPIRVUtils.h
llvm::SPIRV::MB_Annotations
@ MB_Annotations
Definition: SPIRVModuleAnalysis.h:38
llvm::SPIRV::ModuleAnalysisInfo::RegisterAliasTable
RegisterAliasMapTy RegisterAliasTable
Definition: SPIRVModuleAnalysis.h:145
llvm::SPIRV::MB_DebugModuleProcessed
@ MB_DebugModuleProcessed
Definition: SPIRVModuleAnalysis.h:37
llvm::SPIRV::Requirements::MaxVer
const unsigned MaxVer
Definition: SPIRVModuleAnalysis.h:49
llvm::SPIRV::ModuleAnalysisInfo::MBBsToSkip
DenseSet< MachineBasicBlock * > MBBsToSkip
Definition: SPIRVModuleAnalysis.h:141
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::SPIRV::ModuleAnalysisInfo::getSkipEmission
bool getSkipEmission(const MachineInstr *MI)
Definition: SPIRVModuleAnalysis.h:162
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::StringMap
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
Definition: StringMap.h:110
llvm::SPIRV::MB_ExtFuncDecls
@ MB_ExtFuncDecls
Definition: SPIRVModuleAnalysis.h:40
llvm::SPIRV::ModuleAnalysisInfo::hasRegisterAlias
bool hasRegisterAlias(const MachineFunction *MF, Register Reg)
Definition: SPIRVModuleAnalysis.h:176
llvm::SPIRV::RequirementHandler::RequirementHandler
RequirementHandler()
Definition: SPIRVModuleAnalysis.h:73
llvm::DenseSet< unsigned >
llvm::SPIRV::ModuleAnalysisInfo::ExtInstSetMap
DenseMap< unsigned, Register > ExtInstSetMap
Definition: SPIRVModuleAnalysis.h:131
llvm::SPIRVModuleAnalysis::ID
static char ID
Definition: SPIRVModuleAnalysis.h:197
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
SPIRVGlobalRegistry.h
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::SPIRV::ModuleAnalysisInfo::GlobalVarList
SmallVector< MachineInstr *, 4 > GlobalVarList
Definition: SPIRVModuleAnalysis.h:133
llvm::SPIRV::RequirementHandler::addCapabilities
void addCapabilities(const CapabilityList &ToAdd)
llvm::DenseMap
Definition: DenseMap.h:714
llvm::SPIRV::ModuleAnalysisInfo::FuncNameMap
StringMap< Register > FuncNameMap
Definition: SPIRVModuleAnalysis.h:135
llvm::SPIRV::RequirementHandler::addCapability
void addCapability(Capability::Capability ToAdd)
Definition: SPIRVModuleAnalysis.h:92
llvm::SPIRV::Requirements::Requirements
Requirements(Capability::Capability Cap)
Definition: SPIRVModuleAnalysis.h:57
llvm::SPIRV::Requirements::IsSatisfiable
const bool IsSatisfiable
Definition: SPIRVModuleAnalysis.h:45
llvm::SPIRV::ModuleAnalysisInfo::MS
InstrList MS[NUM_MODULE_SECTIONS]
Definition: SPIRVModuleAnalysis.h:149
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SPIRV::RequirementHandler::clear
void clear()
Definition: SPIRVModuleAnalysis.h:74
llvm::SPIRV::RequirementHandler::getExtensions
const SmallSet< Extension::Extension, 4 > & getExtensions() const
Definition: SPIRVModuleAnalysis.h:85
llvm::SPIRV::MB_DebugNames
@ MB_DebugNames
Definition: SPIRVModuleAnalysis.h:36
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::SPIRVGlobalRegistry
Definition: SPIRVGlobalRegistry.h:27
llvm::SPIRV::RequirementHandler::addExtension
void addExtension(Extension::Extension ToAdd)
Definition: SPIRVModuleAnalysis.h:96
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::SPIRV::ModuleAnalysisInfo::hasMBBRegister
bool hasMBBRegister(const MachineBasicBlock &MBB)
Definition: SPIRVModuleAnalysis.h:181
llvm::SPIRV::Requirements::MinVer
const unsigned MinVer
Definition: SPIRVModuleAnalysis.h:48
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::detail::DenseSetImpl::clear
void clear()
Definition: DenseSet.h:92
llvm::dwarf::SourceLanguage
SourceLanguage
Definition: Dwarf.h:201
llvm::StringSet
StringSet - A wrapper for StringMap that provides set-like functionality.
Definition: StringSet.h:23
llvm::SPIRVInstrInfo
Definition: SPIRVInstrInfo.h:24
llvm::detail::DenseSetImpl::contains
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
Definition: DenseSet.h:185
uint32_t
llvm::SPIRVModuleAnalysis
Definition: SPIRVModuleAnalysis.h:196
llvm::SPIRV::ModuleAnalysisInfo::getRegisterAlias
Register getRegisterAlias(const MachineFunction *MF, Register Reg)
Definition: SPIRVModuleAnalysis.h:169
llvm::SPIRV::ModuleAnalysisInfo::getExtInstSetReg
Register getExtInstSetReg(unsigned SetNum)
Definition: SPIRVModuleAnalysis.h:159
llvm::SPIRV::RequirementHandler::isCapabilityAvailable
bool isCapabilityAvailable(Capability::Capability Cap) const
Definition: SPIRVModuleAnalysis.h:110
llvm::SPIRV::Requirements::Requirements
Requirements(bool IsSatisfiable=false, std::optional< Capability::Capability > Cap={}, ExtensionList Exts={}, unsigned MinVer=0, unsigned MaxVer=0)
Definition: SPIRVModuleAnalysis.h:51
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SPIRV::RequirementHandler::addAvailableCaps
void addAvailableCaps(const CapabilityList &ToAdd)
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SPIRVModuleAnalysis::SPIRVModuleAnalysis
SPIRVModuleAnalysis()
Definition: SPIRVModuleAnalysis.h:200
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:614
llvm::SPIRV::ModuleAnalysisInfo::Addr
AddressingModel::AddressingModel Addr
Definition: SPIRVModuleAnalysis.h:126
llvm::SmallSet::insert
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:178
llvm::SPIRV::ModuleAnalysisInfo::BBNumToRegMap
DenseMap< int, Register > BBNumToRegMap
Definition: SPIRVModuleAnalysis.h:151
llvm::SPIRV::RequirementHandler::checkSatisfiable
void checkSatisfiable(const SPIRVSubtarget &ST) const
llvm::SPIRV::MB_EntryPoints
@ MB_EntryPoints
Definition: SPIRVModuleAnalysis.h:34
SmallVector.h
llvm::getFunctionGlobalIdentifier
std::string getFunctionGlobalIdentifier(const Function *F)
Definition: SPIRVUtils.cpp:358
llvm::SPIRVModuleAnalysis::runOnModule
bool runOnModule(Module &M) override
runOnModule - Virtual method overriden by subclasses to process the module being operated on.
Definition: SPIRVModuleAnalysis.cpp:1009
llvm::SmallSet::clear
void clear()
Definition: SmallSet.h:217
llvm::SPIRV::ModuleAnalysisInfo::Mem
MemoryModel::MemoryModel Mem
Definition: SPIRVModuleAnalysis.h:125
llvm::SPIRV::RequirementHandler::getMinVersion
unsigned getMinVersion() const
Definition: SPIRVModuleAnalysis.h:82
llvm::SPIRV::Requirements
Definition: SPIRVModuleAnalysis.h:44
llvm::SPIRV::ModuleAnalysisInfo::SrcLang
SourceLanguage::SourceLanguage SrcLang
Definition: SPIRVModuleAnalysis.h:127
StringMap.h
llvm::SPIRV::RequirementHandler::getAndAddRequirements
void getAndAddRequirements(SPIRV::OperandCategory::OperandCategory Category, uint32_t i, const SPIRVSubtarget &ST)
llvm::SPIRV::RequirementHandler::addRequirements
void addRequirements(const Requirements &Req)
llvm::SPIRV::ModuleAnalysisInfo::InstrsToDelete
DenseSet< MachineInstr * > InstrsToDelete
Definition: SPIRVModuleAnalysis.h:138
llvm::SPIRV::RegisterAliasMapTy
std::map< const MachineFunction *, LocalToGlobalRegTable > RegisterAliasMapTy
Definition: SPIRVModuleAnalysis.h:119
llvm::SPIRV::RequirementHandler::getMinimalCapabilities
const CapabilityList & getMinimalCapabilities() const
Definition: SPIRVModuleAnalysis.h:84
llvm::SPIRVModuleAnalysis::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Definition: SPIRVModuleAnalysis.cpp:1004
llvm::SPIRV::ModuleAnalysisInfo::getOrCreateMBBRegister
Register getOrCreateMBBRegister(const MachineBasicBlock &MBB)
Definition: SPIRVModuleAnalysis.h:185
SmallSet.h
llvm::SPIRV::ModuleAnalysisInfo::Reqs
RequirementHandler Reqs
Definition: SPIRVModuleAnalysis.h:124