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23 #define DEBUG_TYPE "systemz-disassembler"
33 ~SystemZDisassembler()
override =
default;
45 return new SystemZDisassembler(STI, Ctx);
82 const unsigned *Regs,
unsigned Size) {
83 assert(RegNo < Size &&
"Invalid register");
188 return decodeUImmOperand<1>(Inst,
Imm);
194 return decodeUImmOperand<2>(Inst,
Imm);
200 return decodeUImmOperand<3>(Inst,
Imm);
206 return decodeUImmOperand<4>(Inst,
Imm);
212 return decodeUImmOperand<6>(Inst,
Imm);
218 return decodeUImmOperand<8>(Inst,
Imm);
224 return decodeUImmOperand<12>(Inst,
Imm);
230 return decodeUImmOperand<16>(Inst,
Imm);
236 return decodeUImmOperand<32>(Inst,
Imm);
242 return decodeSImmOperand<8>(Inst,
Imm);
248 return decodeSImmOperand<16>(Inst,
Imm);
254 return decodeSImmOperand<32>(Inst,
Imm);
257 template <
unsigned N>
261 assert(isUInt<N>(
Imm) &&
"Invalid PC-relative offset");
274 return decodePCDBLOperand<12>(Inst,
Imm, Address,
true, Decoder);
280 return decodePCDBLOperand<16>(Inst,
Imm, Address,
true, Decoder);
286 return decodePCDBLOperand<24>(Inst,
Imm, Address,
true, Decoder);
292 return decodePCDBLOperand<32>(Inst,
Imm, Address,
true, Decoder);
298 return decodePCDBLOperand<32>(Inst,
Imm, Address,
false, Decoder);
302 const unsigned *Regs) {
312 const unsigned *Regs) {
322 const unsigned *Regs) {
334 const unsigned *Regs) {
346 const unsigned *Regs) {
350 assert(Length < 16 &&
"Invalid BDLAddr12Len4");
358 const unsigned *Regs) {
362 assert(Length < 256 &&
"Invalid BDLAddr12Len8");
370 const unsigned *Regs) {
374 assert(Length < 16 &&
"Invalid BDRAddr12");
382 const unsigned *Regs) {
453 #include "SystemZGenDisassemblerTables.inc"
461 if (Bytes.
size() < 2)
465 const uint8_t *Table;
466 if (Bytes[0] < 0x40) {
468 Table = DecoderTable16;
469 }
else if (Bytes[0] < 0xc0) {
471 Table = DecoderTable32;
474 Table = DecoderTable48;
478 if (Bytes.
size() < Size) {
486 Inst = (Inst << 8) | Bytes[
I];
488 return decodeInstruction(Table,
MI, Inst, Address,
this, STI);
const unsigned GR128Regs[16]
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const MCDisassembler *Decoder)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
This is an optimization pass for GlobalISel generic memory operations.
static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static MCOperand createImm(int64_t Val)
Context object for machine code objects.
static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Target - Wrapper for Target specific information.
const unsigned VR128Regs[32]
const unsigned FP32Regs[16]
static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDVAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
const unsigned GR64Regs[16]
MCDisassembler::DecodeStatus DecodeStatus
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
const unsigned FP128Regs[16]
Instances of this class represent a single low-level machine instruction.
const unsigned AR32Regs[16]
static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, bool isBranch, const MCDisassembler *Decoder)
const unsigned CR64Regs[16]
static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Target & getTheSystemZTarget()
static DecodeStatus decodeBDRAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
const unsigned GR32Regs[16]
This class implements an extremely fast bulk output stream that can only output to a stream.
static DecodeStatus decodeU12ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm)
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm)
DecodeStatus
Ternary decode status.
static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
void addOperand(const MCOperand Op)
static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZDisassembler()
static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
#define LLVM_EXTERNAL_VISIBILITY
static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
Superclass for all disassemblers.
static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static bool isBranch(unsigned Opcode)
const unsigned FP64Regs[16]
static MCDisassembler * createSystemZDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
const unsigned GRH32Regs[16]
static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static MCOperand createReg(unsigned Reg)
static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodePC12DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDLAddr12Len4Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
const unsigned VR64Regs[32]
static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned *Regs, unsigned Size)
static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeU3ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
size_t size() const
size - Get the array size.
static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Generic base class for all target subtargets.
static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
LLVM Value Representation.
static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
const unsigned VR32Regs[32]
static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)