LLVM  15.0.0git
SystemZDisassembler.cpp
Go to the documentation of this file.
1 //===-- SystemZDisassembler.cpp - Disassembler for SystemZ ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "SystemZ.h"
12 #include "llvm/MC/MCDecoderOps.h"
14 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/TargetRegistry.h"
18 #include <cassert>
19 #include <cstdint>
20 
21 using namespace llvm;
22 
23 #define DEBUG_TYPE "systemz-disassembler"
24 
26 
27 namespace {
28 
29 class SystemZDisassembler : public MCDisassembler {
30 public:
31  SystemZDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
32  : MCDisassembler(STI, Ctx) {}
33  ~SystemZDisassembler() override = default;
34 
35  DecodeStatus getInstruction(MCInst &instr, uint64_t &Size,
36  ArrayRef<uint8_t> Bytes, uint64_t Address,
37  raw_ostream &CStream) const override;
38 };
39 
40 } // end anonymous namespace
41 
43  const MCSubtargetInfo &STI,
44  MCContext &Ctx) {
45  return new SystemZDisassembler(STI, Ctx);
46 }
47 
49  // Register the disassembler.
52 }
53 
54 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
55 /// immediate Value in the MCInst.
56 ///
57 /// @param Value - The immediate Value, has had any PC adjustment made by
58 /// the caller.
59 /// @param isBranch - If the instruction is a branch instruction
60 /// @param Address - The starting address of the instruction
61 /// @param Offset - The byte offset to this immediate in the instruction
62 /// @param Width - The byte width of this immediate in the instruction
63 ///
64 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
65 /// called then that function is called to get any symbolic information for the
66 /// immediate in the instruction using the Address, Offset and Width. If that
67 /// returns non-zero then the symbolic information it returns is used to create
68 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
69 /// returns zero and isBranch is true then a symbol look up for immediate Value
70 /// is done and if a symbol is found an MCExpr is created with that, else
71 /// an MCExpr with the immediate Value is created. This function returns true
72 /// if it adds an operand to the MCInst and false otherwise.
73 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
74  uint64_t Address, uint64_t Offset,
76  const MCDisassembler *Decoder) {
77  return Decoder->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset,
78  Width, /*InstSize=*/0);
79 }
80 
82  const unsigned *Regs, unsigned Size) {
83  assert(RegNo < Size && "Invalid register");
84  RegNo = Regs[RegNo];
85  if (RegNo == 0)
86  return MCDisassembler::Fail;
87  Inst.addOperand(MCOperand::createReg(RegNo));
89 }
90 
92  uint64_t Address,
93  const MCDisassembler *Decoder) {
94  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16);
95 }
96 
98  uint64_t Address,
99  const MCDisassembler *Decoder) {
100  return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16);
101 }
102 
104  uint64_t Address,
105  const MCDisassembler *Decoder) {
106  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
107 }
108 
110  uint64_t Address,
111  const MCDisassembler *Decoder) {
112  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16);
113 }
114 
115 static DecodeStatus
117  const MCDisassembler *Decoder) {
118  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
119 }
120 
122  uint64_t Address,
123  const MCDisassembler *Decoder) {
124  return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs, 16);
125 }
126 
128  uint64_t Address,
129  const MCDisassembler *Decoder) {
130  return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs, 16);
131 }
132 
134  uint64_t Address,
135  const MCDisassembler *Decoder) {
136  return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs, 16);
137 }
138 
140  uint64_t Address,
141  const MCDisassembler *Decoder) {
142  return decodeRegisterClass(Inst, RegNo, SystemZMC::VR32Regs, 32);
143 }
144 
146  uint64_t Address,
147  const MCDisassembler *Decoder) {
148  return decodeRegisterClass(Inst, RegNo, SystemZMC::VR64Regs, 32);
149 }
150 
152  uint64_t Address,
153  const MCDisassembler *Decoder) {
154  return decodeRegisterClass(Inst, RegNo, SystemZMC::VR128Regs, 32);
155 }
156 
158  uint64_t Address,
159  const MCDisassembler *Decoder) {
160  return decodeRegisterClass(Inst, RegNo, SystemZMC::AR32Regs, 16);
161 }
162 
164  uint64_t Address,
165  const MCDisassembler *Decoder) {
166  return decodeRegisterClass(Inst, RegNo, SystemZMC::CR64Regs, 16);
167 }
168 
169 template<unsigned N>
171  if (!isUInt<N>(Imm))
172  return MCDisassembler::Fail;
175 }
176 
177 template<unsigned N>
179  if (!isUInt<N>(Imm))
180  return MCDisassembler::Fail;
181  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
183 }
184 
186  uint64_t Address,
187  const MCDisassembler *Decoder) {
188  return decodeUImmOperand<1>(Inst, Imm);
189 }
190 
192  uint64_t Address,
193  const MCDisassembler *Decoder) {
194  return decodeUImmOperand<2>(Inst, Imm);
195 }
196 
198  uint64_t Address,
199  const MCDisassembler *Decoder) {
200  return decodeUImmOperand<3>(Inst, Imm);
201 }
202 
204  uint64_t Address,
205  const MCDisassembler *Decoder) {
206  return decodeUImmOperand<4>(Inst, Imm);
207 }
208 
210  uint64_t Address,
211  const MCDisassembler *Decoder) {
212  return decodeUImmOperand<6>(Inst, Imm);
213 }
214 
216  uint64_t Address,
217  const MCDisassembler *Decoder) {
218  return decodeUImmOperand<8>(Inst, Imm);
219 }
220 
222  uint64_t Address,
223  const MCDisassembler *Decoder) {
224  return decodeUImmOperand<12>(Inst, Imm);
225 }
226 
228  uint64_t Address,
229  const MCDisassembler *Decoder) {
230  return decodeUImmOperand<16>(Inst, Imm);
231 }
232 
234  uint64_t Address,
235  const MCDisassembler *Decoder) {
236  return decodeUImmOperand<32>(Inst, Imm);
237 }
238 
240  uint64_t Address,
241  const MCDisassembler *Decoder) {
242  return decodeSImmOperand<8>(Inst, Imm);
243 }
244 
246  uint64_t Address,
247  const MCDisassembler *Decoder) {
248  return decodeSImmOperand<16>(Inst, Imm);
249 }
250 
252  uint64_t Address,
253  const MCDisassembler *Decoder) {
254  return decodeSImmOperand<32>(Inst, Imm);
255 }
256 
257 template <unsigned N>
259  uint64_t Address, bool isBranch,
260  const MCDisassembler *Decoder) {
261  assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
262  uint64_t Value = SignExtend64<N>(Imm) * 2 + Address;
263 
264  if (!tryAddingSymbolicOperand(Value, isBranch, Address, 2, N / 8,
265  Inst, Decoder))
267 
269 }
270 
272  uint64_t Address,
273  const MCDisassembler *Decoder) {
274  return decodePCDBLOperand<12>(Inst, Imm, Address, true, Decoder);
275 }
276 
278  uint64_t Address,
279  const MCDisassembler *Decoder) {
280  return decodePCDBLOperand<16>(Inst, Imm, Address, true, Decoder);
281 }
282 
284  uint64_t Address,
285  const MCDisassembler *Decoder) {
286  return decodePCDBLOperand<24>(Inst, Imm, Address, true, Decoder);
287 }
288 
290  uint64_t Address,
291  const MCDisassembler *Decoder) {
292  return decodePCDBLOperand<32>(Inst, Imm, Address, true, Decoder);
293 }
294 
296  uint64_t Address,
297  const MCDisassembler *Decoder) {
298  return decodePCDBLOperand<32>(Inst, Imm, Address, false, Decoder);
299 }
300 
302  const unsigned *Regs) {
303  uint64_t Base = Field >> 12;
304  uint64_t Disp = Field & 0xfff;
305  assert(Base < 16 && "Invalid BDAddr12");
306  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
307  Inst.addOperand(MCOperand::createImm(Disp));
309 }
310 
312  const unsigned *Regs) {
313  uint64_t Base = Field >> 20;
314  uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
315  assert(Base < 16 && "Invalid BDAddr20");
316  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
317  Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
319 }
320 
322  const unsigned *Regs) {
323  uint64_t Index = Field >> 16;
324  uint64_t Base = (Field >> 12) & 0xf;
325  uint64_t Disp = Field & 0xfff;
326  assert(Index < 16 && "Invalid BDXAddr12");
327  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
328  Inst.addOperand(MCOperand::createImm(Disp));
329  Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
331 }
332 
334  const unsigned *Regs) {
335  uint64_t Index = Field >> 24;
336  uint64_t Base = (Field >> 20) & 0xf;
337  uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
338  assert(Index < 16 && "Invalid BDXAddr20");
339  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
340  Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
341  Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
343 }
344 
346  const unsigned *Regs) {
347  uint64_t Length = Field >> 16;
348  uint64_t Base = (Field >> 12) & 0xf;
349  uint64_t Disp = Field & 0xfff;
350  assert(Length < 16 && "Invalid BDLAddr12Len4");
351  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
352  Inst.addOperand(MCOperand::createImm(Disp));
353  Inst.addOperand(MCOperand::createImm(Length + 1));
355 }
356 
358  const unsigned *Regs) {
359  uint64_t Length = Field >> 16;
360  uint64_t Base = (Field >> 12) & 0xf;
361  uint64_t Disp = Field & 0xfff;
362  assert(Length < 256 && "Invalid BDLAddr12Len8");
363  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
364  Inst.addOperand(MCOperand::createImm(Disp));
365  Inst.addOperand(MCOperand::createImm(Length + 1));
367 }
368 
370  const unsigned *Regs) {
371  uint64_t Length = Field >> 16;
372  uint64_t Base = (Field >> 12) & 0xf;
373  uint64_t Disp = Field & 0xfff;
374  assert(Length < 16 && "Invalid BDRAddr12");
375  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
376  Inst.addOperand(MCOperand::createImm(Disp));
377  Inst.addOperand(MCOperand::createReg(Regs[Length]));
379 }
380 
382  const unsigned *Regs) {
383  uint64_t Index = Field >> 16;
384  uint64_t Base = (Field >> 12) & 0xf;
385  uint64_t Disp = Field & 0xfff;
386  assert(Index < 32 && "Invalid BDVAddr12");
387  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
388  Inst.addOperand(MCOperand::createImm(Disp));
391 }
392 
394  uint64_t Address,
395  const MCDisassembler *Decoder) {
397 }
398 
400  uint64_t Address,
401  const MCDisassembler *Decoder) {
403 }
404 
406  uint64_t Address,
407  const MCDisassembler *Decoder) {
409 }
410 
412  uint64_t Address,
413  const MCDisassembler *Decoder) {
415 }
416 
417 static DecodeStatus
419  const MCDisassembler *Decoder) {
421 }
422 
423 static DecodeStatus
425  const MCDisassembler *Decoder) {
427 }
428 
429 static DecodeStatus
431  const MCDisassembler *Decoder) {
433 }
434 
435 static DecodeStatus
437  const MCDisassembler *Decoder) {
439 }
440 
441 static DecodeStatus
443  const MCDisassembler *Decoder) {
445 }
446 
447 static DecodeStatus
449  const MCDisassembler *Decoder) {
451 }
452 
453 #include "SystemZGenDisassemblerTables.inc"
454 
455 DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
456  ArrayRef<uint8_t> Bytes,
457  uint64_t Address,
458  raw_ostream &CS) const {
459  // Get the first two bytes of the instruction.
460  Size = 0;
461  if (Bytes.size() < 2)
462  return MCDisassembler::Fail;
463 
464  // The top 2 bits of the first byte specify the size.
465  const uint8_t *Table;
466  if (Bytes[0] < 0x40) {
467  Size = 2;
468  Table = DecoderTable16;
469  } else if (Bytes[0] < 0xc0) {
470  Size = 4;
471  Table = DecoderTable32;
472  } else {
473  Size = 6;
474  Table = DecoderTable48;
475  }
476 
477  // Read any remaining bytes.
478  if (Bytes.size() < Size) {
479  Size = Bytes.size();
480  return MCDisassembler::Fail;
481  }
482 
483  // Construct the instruction.
484  uint64_t Inst = 0;
485  for (uint64_t I = 0; I < Size; ++I)
486  Inst = (Inst << 8) | Bytes[I];
487 
488  return decodeInstruction(Table, MI, Inst, Address, this, STI);
489 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:77
llvm::SystemZMC::GR128Regs
const unsigned GR128Regs[16]
Definition: SystemZMCTargetDesc.cpp:55
tryAddingSymbolicOperand
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const MCDisassembler *Decoder)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
Definition: SystemZDisassembler.cpp:73
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MathExtras.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
decodeBDLAddr64Disp12Len4Operand
static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:430
MCDisassembler.h
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
DecodeAR32BitRegisterClass
static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:157
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
llvm::SystemZMC::VR128Regs
const unsigned VR128Regs[32]
Definition: SystemZMCTargetDesc.cpp:105
llvm::SystemZMC::FP32Regs
const unsigned FP32Regs[16]
Definition: SystemZMCTargetDesc.cpp:62
DecodeADDR64BitRegisterClass
static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:116
decodeBDVAddr12Operand
static DecodeStatus decodeBDVAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:381
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
Definition: MCDisassembler.cpp:23
llvm::SystemZMC::GR64Regs
const unsigned GR64Regs[16]
Definition: SystemZMCTargetDesc.cpp:48
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: SystemZDisassembler.cpp:25
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:951
SystemZMCTargetDesc.h
decodePC32DBLOperand
static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:295
llvm::SystemZMC::FP128Regs
const unsigned FP128Regs[16]
Definition: SystemZMCTargetDesc.cpp:76
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::SystemZMC::AR32Regs
const unsigned AR32Regs[16]
Definition: SystemZMCTargetDesc.cpp:116
decodeU1ImmOperand
static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:185
MCDecoderOps.h
decodeBDXAddr64Disp12Operand
static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:418
SystemZTargetInfo.h
decodeBDAddr32Disp20Operand
static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:399
decodeU16ImmOperand
static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:227
decodeS32ImmOperand
static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:251
decodeU32ImmOperand
static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:233
decodePCDBLOperand
static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, bool isBranch, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:258
llvm::SystemZMC::CR64Regs
const unsigned CR64Regs[16]
Definition: SystemZMCTargetDesc.cpp:123
decodeBDAddr20Operand
static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:311
llvm::getTheSystemZTarget
Target & getTheSystemZTarget()
Definition: SystemZTargetInfo.cpp:14
decodeBDRAddr12Operand
static DecodeStatus decodeBDRAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:369
DecodeVR32BitRegisterClass
static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:139
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:112
MCInst.h
decodeU4ImmOperand
static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:203
llvm::SystemZMC::GR32Regs
const unsigned GR32Regs[16]
Definition: SystemZMCTargetDesc.cpp:34
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
MCSubtargetInfo.h
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
decodeU12ImmOperand
static DecodeStatus decodeU12ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:221
decodeUImmOperand
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm)
Definition: SystemZDisassembler.cpp:170
SystemZ.h
decodeSImmOperand
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm)
Definition: SystemZDisassembler.cpp:178
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:109
decodeS8ImmOperand
static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:239
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
decodeBDAddr64Disp20Operand
static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:411
decodeBDRAddr64Disp12Operand
static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:442
LLVMInitializeSystemZDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZDisassembler()
Definition: SystemZDisassembler.cpp:48
decodePC32DBLBranchOperand
static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:289
uint64_t
decodeU2ImmOperand
static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:191
decodeBDXAddr64Disp20Operand
static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:424
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
decodeBDLAddr64Disp12Len8Operand
static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:436
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:85
DecodeFP64BitRegisterClass
static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:127
I
#define I(x, y, z)
Definition: MD5.cpp:58
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
decodePC16DBLBranchOperand
static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:277
DecodeFP128BitRegisterClass
static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:133
isBranch
static bool isBranch(unsigned Opcode)
Definition: R600InstrInfo.cpp:642
llvm::SystemZMC::FP64Regs
const unsigned FP64Regs[16]
Definition: SystemZMCTargetDesc.cpp:69
createSystemZDisassembler
static MCDisassembler * createSystemZDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: SystemZDisassembler.cpp:42
llvm::SystemZMC::GRH32Regs
const unsigned GRH32Regs[16]
Definition: SystemZMCTargetDesc.cpp:41
llvm::ArrayRef< uint8_t >
decodeU8ImmOperand
static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:215
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
decodeBDXAddr20Operand
static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:333
decodePC12DBLBranchOperand
static DecodeStatus decodePC12DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:271
DecodeCR64BitRegisterClass
static DecodeStatus DecodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:163
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:110
decodeBDXAddr12Operand
static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:321
DecodeGR32BitRegisterClass
static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:91
decodeBDLAddr12Len4Operand
static DecodeStatus decodeBDLAddr12Len4Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:345
decodeU6ImmOperand
static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:209
llvm::SystemZMC::VR64Regs
const unsigned VR64Regs[32]
Definition: SystemZMCTargetDesc.cpp:94
DecodeVR128BitRegisterClass
static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:151
decodeBDAddr32Disp12Operand
static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:393
DecodeFP32BitRegisterClass
static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:121
decodeRegisterClass
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned *Regs, unsigned Size)
Definition: SystemZDisassembler.cpp:81
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:436
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
DecodeGR128BitRegisterClass
static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:109
decodeBDVAddr64Disp12Operand
static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:448
N
#define N
decodeBDLAddr12Len8Operand
static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:357
decodeU3ImmOperand
static DecodeStatus decodeU3ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:197
decodeBDAddr64Disp12Operand
static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:405
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
DecodeGRH32BitRegisterClass
static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:97
llvm::OptimizedStructLayoutField
A field in a structure.
Definition: OptimizedStructLayout.h:45
DecodeGR64BitRegisterClass
static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:103
DecodeVR64BitRegisterClass
static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:145
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
decodeS16ImmOperand
static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:245
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
decodePC24DBLBranchOperand
static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: SystemZDisassembler.cpp:283
llvm::SystemZMC::VR32Regs
const unsigned VR32Regs[32]
Definition: SystemZMCTargetDesc.cpp:83
decodeBDAddr12Operand
static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:301
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58