33 #define DEBUG_TYPE "aarch64-disassembler"
41 unsigned RegNo, uint64_t Address,
70 unsigned RegNo, uint64_t Address,
76 unsigned RegNo, uint64_t Address,
101 const void *Decoder);
104 const void *Decoder);
107 const void *Decoder);
110 const void *Decoder);
113 const void *Decoder);
116 const void *Decoder);
119 const void *Decoder);
123 const void *Decoder);
126 const void *Decoder);
128 uint64_t Address,
const void *Decoder);
130 uint64_t Address,
const void *Decoder);
132 uint64_t Address,
const void *Decoder);
134 uint64_t Address,
const void *Decoder);
137 const void *Decoder);
140 const void *Decoder);
143 const void *Decoder);
146 const void *Decoder);
149 const void *Decoder);
152 const void *Decoder);
155 const void *Decoder);
158 const void *Decoder);
161 const void *Decoder);
164 const void *Decoder);
167 const void *Decoder);
169 uint64_t Address,
const void *Decoder);
171 uint64_t Address,
const void *Decoder);
174 const void *Decoder);
177 const void *Decoder);
179 uint64_t Address,
const void *Decoder);
183 const void *Decoder);
185 uint64_t
Addr,
const void *Decoder);
188 const void *Decoder);
190 uint64_t
Addr,
const void *Decoder);
193 const void *Decoder);
195 uint64_t
Addr,
const void *Decoder);
198 const void *Decoder);
200 uint64_t
Addr,
const void *Decoder);
202 uint64_t
Addr,
const void *Decoder);
204 uint64_t
Addr,
const void *Decoder);
206 uint64_t
Addr,
const void *Decoder);
208 uint64_t
Addr,
const void *Decoder);
212 const void *Decoder);
216 const void *Decoder);
220 const void *Decoder);
223 uint64_t Address,
const void *Decoder);
224 template <
int ElementW
idth>
226 uint64_t
Addr,
const void *Decoder);
228 uint64_t
Addr,
const void *Decoder);
245 #include "AArch64GenDisassemblerTables.inc"
246 #include "AArch64GenInstrInfo.inc"
248 #define Success MCDisassembler::Success
249 #define Fail MCDisassembler::Fail
250 #define SoftFail MCDisassembler::SoftFail
266 if (Bytes.
size() < 4)
272 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
274 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
276 for (
auto Table : Tables) {
290 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
292 SymbolLookUp, DisInfo);
320 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
321 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
322 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
323 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
324 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
325 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
326 AArch64::Q30, AArch64::Q31
331 const void *Decoder) {
342 const void *Decoder) {
349 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
350 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
351 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
352 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
353 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
354 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
355 AArch64::D30, AArch64::D31
360 const void *Decoder) {
370 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
371 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
372 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
373 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
374 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
375 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
376 AArch64::S30, AArch64::S31
381 const void *Decoder) {
391 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
392 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
393 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
394 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
395 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
396 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
397 AArch64::H30, AArch64::H31
402 const void *Decoder) {
412 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
413 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
414 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
415 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
416 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
417 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
418 AArch64::B30, AArch64::B31
423 const void *Decoder) {
433 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
434 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
435 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
436 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
437 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
438 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
439 AArch64::LR, AArch64::XZR
444 const void *Decoder) {
455 const void *Decoder) {
465 AArch64::X0_X1_X2_X3_X4_X5_X6_X7,
466 AArch64::X2_X3_X4_X5_X6_X7_X8_X9,
467 AArch64::X4_X5_X6_X7_X8_X9_X10_X11,
468 AArch64::X6_X7_X8_X9_X10_X11_X12_X13,
469 AArch64::X8_X9_X10_X11_X12_X13_X14_X15,
470 AArch64::X10_X11_X12_X13_X14_X15_X16_X17,
471 AArch64::X12_X13_X14_X15_X16_X17_X18_X19,
472 AArch64::X14_X15_X16_X17_X18_X19_X20_X21,
473 AArch64::X16_X17_X18_X19_X20_X21_X22_X23,
474 AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
475 AArch64::X20_X21_X22_X23_X24_X25_X26_X27,
476 AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
482 const void *Decoder) {
495 const void *Decoder) {
506 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
507 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
508 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
509 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
510 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
511 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
512 AArch64::W30, AArch64::WZR
517 const void *Decoder) {
528 const void *Decoder) {
539 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3,
540 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
541 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11,
542 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
543 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19,
544 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23,
545 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27,
546 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31
551 const void* Decoder) {
562 const void *Decoder) {
570 const void *Decoder) {
577 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4,
578 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8,
579 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12,
580 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
581 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20,
582 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24,
583 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28,
584 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0
589 const void* Decoder) {
598 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4,
599 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7,
600 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10,
601 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13,
602 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16,
603 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19,
604 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22,
605 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25,
606 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28,
607 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31,
608 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1
613 const void* Decoder) {
622 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5,
623 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8,
624 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11,
625 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14,
626 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17,
627 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20,
628 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23,
629 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26,
630 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29,
631 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0,
632 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2
637 const void* Decoder) {
646 AArch64::P0, AArch64::P1,
AArch64::P2, AArch64::P3,
647 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
648 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11,
649 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15
653 uint64_t
Addr,
const void *Decoder) {
664 const void* Decoder) {
673 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
674 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
675 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
676 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
677 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
678 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
679 AArch64::Q30, AArch64::Q31
684 const void *Decoder) {
694 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
695 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
696 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
697 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
698 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
699 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
700 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
701 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
705 uint64_t
Addr,
const void *Decoder) {
714 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
715 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
716 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
717 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
718 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
719 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
720 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
721 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
722 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
723 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
724 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
728 uint64_t
Addr,
const void *Decoder) {
737 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
738 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
739 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
740 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
741 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
742 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
743 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
744 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
745 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
746 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
747 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
752 const void *Decoder) {
761 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
762 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
763 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
764 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
765 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
766 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
767 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
768 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
772 uint64_t
Addr,
const void *Decoder) {
781 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
782 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
783 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
784 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
785 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
786 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
787 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
788 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
789 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
790 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
791 AArch64::D30_D31_D0, AArch64::D31_D0_D1
795 uint64_t
Addr,
const void *Decoder) {
804 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
805 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
806 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
807 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
808 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
809 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
810 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
811 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
812 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
813 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
814 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
819 const void *Decoder) {
829 const void *Decoder) {
838 const void *Decoder) {
844 uint64_t
Addr,
const void *Decoder) {
845 int64_t ImmVal = Imm;
850 if (ImmVal & (1 << (19 - 1)))
851 ImmVal |= ~((1LL << 19) - 1);
854 Inst.
getOpcode() != AArch64::LDRXl, 0, 4))
860 uint64_t Address,
const void *Decoder) {
868 const void *Decoder) {
878 const void *Decoder) {
886 const void *Decoder) {
889 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
890 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
891 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
920 uint64_t
Addr,
const void *Decoder) {
926 const void *Decoder) {
931 uint64_t
Addr,
const void *Decoder) {
937 const void *Decoder) {
942 uint64_t
Addr,
const void *Decoder) {
948 const void *Decoder) {
953 uint64_t
Addr,
const void *Decoder) {
958 uint64_t
Addr,
const void *Decoder) {
963 uint64_t
Addr,
const void *Decoder) {
968 uint64_t
Addr,
const void *Decoder) {
973 uint64_t
Addr,
const void *Decoder) {
979 const void *Decoder) {
980 unsigned Rd = fieldFromInstruction(insn, 0, 5);
981 unsigned Rn = fieldFromInstruction(insn, 5, 5);
982 unsigned Rm = fieldFromInstruction(insn, 16, 5);
983 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
984 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
985 unsigned shift = (shiftHi << 6) | shiftLo;
989 case AArch64::ADDWrs:
990 case AArch64::ADDSWrs:
991 case AArch64::SUBWrs:
992 case AArch64::SUBSWrs:
997 case AArch64::ANDWrs:
998 case AArch64::ANDSWrs:
999 case AArch64::BICWrs:
1000 case AArch64::BICSWrs:
1001 case AArch64::ORRWrs:
1002 case AArch64::ORNWrs:
1003 case AArch64::EORWrs:
1004 case AArch64::EONWrs: {
1006 if (shiftLo >> 5 == 1)
1013 case AArch64::ADDXrs:
1014 case AArch64::ADDSXrs:
1015 case AArch64::SUBXrs:
1016 case AArch64::SUBSXrs:
1021 case AArch64::ANDXrs:
1022 case AArch64::ANDSXrs:
1023 case AArch64::BICXrs:
1024 case AArch64::BICSXrs:
1025 case AArch64::ORRXrs:
1026 case AArch64::ORNXrs:
1027 case AArch64::EORXrs:
1028 case AArch64::EONXrs:
1041 const void *Decoder) {
1042 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1043 unsigned imm = fieldFromInstruction(insn, 5, 16);
1044 unsigned shift = fieldFromInstruction(insn, 21, 2);
1049 case AArch64::MOVZWi:
1050 case AArch64::MOVNWi:
1051 case AArch64::MOVKWi:
1052 if (
shift & (1U << 5))
1056 case AArch64::MOVZXi:
1057 case AArch64::MOVNXi:
1058 case AArch64::MOVKXi:
1063 if (Inst.
getOpcode() == AArch64::MOVKWi ||
1074 const void *Decoder) {
1075 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1076 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1077 unsigned offset = fieldFromInstruction(insn, 10, 12);
1084 case AArch64::PRFMui:
1088 case AArch64::STRBBui:
1089 case AArch64::LDRBBui:
1090 case AArch64::LDRSBWui:
1091 case AArch64::STRHHui:
1092 case AArch64::LDRHHui:
1093 case AArch64::LDRSHWui:
1094 case AArch64::STRWui:
1095 case AArch64::LDRWui:
1098 case AArch64::LDRSBXui:
1099 case AArch64::LDRSHXui:
1100 case AArch64::LDRSWui:
1101 case AArch64::STRXui:
1102 case AArch64::LDRXui:
1105 case AArch64::LDRQui:
1106 case AArch64::STRQui:
1109 case AArch64::LDRDui:
1110 case AArch64::STRDui:
1113 case AArch64::LDRSui:
1114 case AArch64::STRSui:
1117 case AArch64::LDRHui:
1118 case AArch64::STRHui:
1121 case AArch64::LDRBui:
1122 case AArch64::STRBui:
1135 const void *Decoder) {
1136 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1137 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1138 int64_t offset = fieldFromInstruction(insn, 12, 9);
1142 if (offset & (1 << (9 - 1)))
1143 offset |= ~((1LL << 9) - 1);
1149 case AArch64::LDRSBWpre:
1150 case AArch64::LDRSHWpre:
1151 case AArch64::STRBBpre:
1152 case AArch64::LDRBBpre:
1153 case AArch64::STRHHpre:
1154 case AArch64::LDRHHpre:
1155 case AArch64::STRWpre:
1156 case AArch64::LDRWpre:
1157 case AArch64::LDRSBWpost:
1158 case AArch64::LDRSHWpost:
1159 case AArch64::STRBBpost:
1160 case AArch64::LDRBBpost:
1161 case AArch64::STRHHpost:
1162 case AArch64::LDRHHpost:
1163 case AArch64::STRWpost:
1164 case AArch64::LDRWpost:
1165 case AArch64::LDRSBXpre:
1166 case AArch64::LDRSHXpre:
1167 case AArch64::STRXpre:
1168 case AArch64::LDRSWpre:
1169 case AArch64::LDRXpre:
1170 case AArch64::LDRSBXpost:
1171 case AArch64::LDRSHXpost:
1172 case AArch64::STRXpost:
1173 case AArch64::LDRSWpost:
1174 case AArch64::LDRXpost:
1175 case AArch64::LDRQpre:
1176 case AArch64::STRQpre:
1177 case AArch64::LDRQpost:
1178 case AArch64::STRQpost:
1179 case AArch64::LDRDpre:
1180 case AArch64::STRDpre:
1181 case AArch64::LDRDpost:
1182 case AArch64::STRDpost:
1183 case AArch64::LDRSpre:
1184 case AArch64::STRSpre:
1185 case AArch64::LDRSpost:
1186 case AArch64::STRSpost:
1187 case AArch64::LDRHpre:
1188 case AArch64::STRHpre:
1189 case AArch64::LDRHpost:
1190 case AArch64::STRHpost:
1191 case AArch64::LDRBpre:
1192 case AArch64::STRBpre:
1193 case AArch64::LDRBpost:
1194 case AArch64::STRBpost:
1202 case AArch64::PRFUMi:
1206 case AArch64::STURBBi:
1207 case AArch64::LDURBBi:
1208 case AArch64::LDURSBWi:
1209 case AArch64::STURHHi:
1210 case AArch64::LDURHHi:
1211 case AArch64::LDURSHWi:
1212 case AArch64::STURWi:
1213 case AArch64::LDURWi:
1214 case AArch64::LDTRSBWi:
1215 case AArch64::LDTRSHWi:
1216 case AArch64::STTRWi:
1217 case AArch64::LDTRWi:
1218 case AArch64::STTRHi:
1219 case AArch64::LDTRHi:
1220 case AArch64::LDTRBi:
1221 case AArch64::STTRBi:
1222 case AArch64::LDRSBWpre:
1223 case AArch64::LDRSHWpre:
1224 case AArch64::STRBBpre:
1225 case AArch64::LDRBBpre:
1226 case AArch64::STRHHpre:
1227 case AArch64::LDRHHpre:
1228 case AArch64::STRWpre:
1229 case AArch64::LDRWpre:
1230 case AArch64::LDRSBWpost:
1231 case AArch64::LDRSHWpost:
1232 case AArch64::STRBBpost:
1233 case AArch64::LDRBBpost:
1234 case AArch64::STRHHpost:
1235 case AArch64::LDRHHpost:
1236 case AArch64::STRWpost:
1237 case AArch64::LDRWpost:
1238 case AArch64::STLURBi:
1239 case AArch64::STLURHi:
1240 case AArch64::STLURWi:
1241 case AArch64::LDAPURBi:
1242 case AArch64::LDAPURSBWi:
1243 case AArch64::LDAPURHi:
1244 case AArch64::LDAPURSHWi:
1245 case AArch64::LDAPURi:
1248 case AArch64::LDURSBXi:
1249 case AArch64::LDURSHXi:
1250 case AArch64::LDURSWi:
1251 case AArch64::STURXi:
1252 case AArch64::LDURXi:
1253 case AArch64::LDTRSBXi:
1254 case AArch64::LDTRSHXi:
1255 case AArch64::LDTRSWi:
1256 case AArch64::STTRXi:
1257 case AArch64::LDTRXi:
1258 case AArch64::LDRSBXpre:
1259 case AArch64::LDRSHXpre:
1260 case AArch64::STRXpre:
1261 case AArch64::LDRSWpre:
1262 case AArch64::LDRXpre:
1263 case AArch64::LDRSBXpost:
1264 case AArch64::LDRSHXpost:
1265 case AArch64::STRXpost:
1266 case AArch64::LDRSWpost:
1267 case AArch64::LDRXpost:
1268 case AArch64::LDAPURSWi:
1269 case AArch64::LDAPURSHXi:
1270 case AArch64::LDAPURSBXi:
1271 case AArch64::STLURXi:
1272 case AArch64::LDAPURXi:
1275 case AArch64::LDURQi:
1276 case AArch64::STURQi:
1277 case AArch64::LDRQpre:
1278 case AArch64::STRQpre:
1279 case AArch64::LDRQpost:
1280 case AArch64::STRQpost:
1283 case AArch64::LDURDi:
1284 case AArch64::STURDi:
1285 case AArch64::LDRDpre:
1286 case AArch64::STRDpre:
1287 case AArch64::LDRDpost:
1288 case AArch64::STRDpost:
1291 case AArch64::LDURSi:
1292 case AArch64::STURSi:
1293 case AArch64::LDRSpre:
1294 case AArch64::STRSpre:
1295 case AArch64::LDRSpost:
1296 case AArch64::STRSpost:
1299 case AArch64::LDURHi:
1300 case AArch64::STURHi:
1301 case AArch64::LDRHpre:
1302 case AArch64::STRHpre:
1303 case AArch64::LDRHpost:
1304 case AArch64::STRHpost:
1307 case AArch64::LDURBi:
1308 case AArch64::STURBi:
1309 case AArch64::LDRBpre:
1310 case AArch64::STRBpre:
1311 case AArch64::LDRBpost:
1312 case AArch64::STRBpost:
1320 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1321 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1322 bool IsFP = fieldFromInstruction(insn, 26, 1);
1325 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1333 const void *Decoder) {
1334 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1335 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1336 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1337 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1343 case AArch64::STLXRW:
1344 case AArch64::STLXRB:
1345 case AArch64::STLXRH:
1346 case AArch64::STXRW:
1347 case AArch64::STXRB:
1348 case AArch64::STXRH:
1351 case AArch64::LDARW:
1352 case AArch64::LDARB:
1353 case AArch64::LDARH:
1354 case AArch64::LDAXRW:
1355 case AArch64::LDAXRB:
1356 case AArch64::LDAXRH:
1357 case AArch64::LDXRW:
1358 case AArch64::LDXRB:
1359 case AArch64::LDXRH:
1360 case AArch64::STLRW:
1361 case AArch64::STLRB:
1362 case AArch64::STLRH:
1363 case AArch64::STLLRW:
1364 case AArch64::STLLRB:
1365 case AArch64::STLLRH:
1366 case AArch64::LDLARW:
1367 case AArch64::LDLARB:
1368 case AArch64::LDLARH:
1371 case AArch64::STLXRX:
1372 case AArch64::STXRX:
1375 case AArch64::LDARX:
1376 case AArch64::LDAXRX:
1377 case AArch64::LDXRX:
1378 case AArch64::STLRX:
1379 case AArch64::LDLARX:
1380 case AArch64::STLLRX:
1383 case AArch64::STLXPW:
1384 case AArch64::STXPW:
1387 case AArch64::LDAXPW:
1388 case AArch64::LDXPW:
1392 case AArch64::STLXPX:
1393 case AArch64::STXPX:
1396 case AArch64::LDAXPX:
1397 case AArch64::LDXPX:
1406 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1407 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1416 const void *Decoder) {
1417 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1418 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1419 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1420 int64_t offset = fieldFromInstruction(insn, 15, 7);
1421 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1425 if (offset & (1 << (7 - 1)))
1426 offset |= ~((1LL << 7) - 1);
1429 bool NeedsDisjointWritebackTransfer =
false;
1435 case AArch64::LDPXpost:
1436 case AArch64::STPXpost:
1437 case AArch64::LDPSWpost:
1438 case AArch64::LDPXpre:
1439 case AArch64::STPXpre:
1440 case AArch64::LDPSWpre:
1441 case AArch64::LDPWpost:
1442 case AArch64::STPWpost:
1443 case AArch64::LDPWpre:
1444 case AArch64::STPWpre:
1445 case AArch64::LDPQpost:
1446 case AArch64::STPQpost:
1447 case AArch64::LDPQpre:
1448 case AArch64::STPQpre:
1449 case AArch64::LDPDpost:
1450 case AArch64::STPDpost:
1451 case AArch64::LDPDpre:
1452 case AArch64::STPDpre:
1453 case AArch64::LDPSpost:
1454 case AArch64::STPSpost:
1455 case AArch64::LDPSpre:
1456 case AArch64::STPSpre:
1457 case AArch64::STGPpre:
1458 case AArch64::STGPpost:
1466 case AArch64::LDPXpost:
1467 case AArch64::STPXpost:
1468 case AArch64::LDPSWpost:
1469 case AArch64::LDPXpre:
1470 case AArch64::STPXpre:
1471 case AArch64::LDPSWpre:
1472 case AArch64::STGPpre:
1473 case AArch64::STGPpost:
1474 NeedsDisjointWritebackTransfer =
true;
1476 case AArch64::LDNPXi:
1477 case AArch64::STNPXi:
1478 case AArch64::LDPXi:
1479 case AArch64::STPXi:
1480 case AArch64::LDPSWi:
1481 case AArch64::STGPi:
1485 case AArch64::LDPWpost:
1486 case AArch64::STPWpost:
1487 case AArch64::LDPWpre:
1488 case AArch64::STPWpre:
1489 NeedsDisjointWritebackTransfer =
true;
1491 case AArch64::LDNPWi:
1492 case AArch64::STNPWi:
1493 case AArch64::LDPWi:
1494 case AArch64::STPWi:
1498 case AArch64::LDNPQi:
1499 case AArch64::STNPQi:
1500 case AArch64::LDPQpost:
1501 case AArch64::STPQpost:
1502 case AArch64::LDPQi:
1503 case AArch64::STPQi:
1504 case AArch64::LDPQpre:
1505 case AArch64::STPQpre:
1509 case AArch64::LDNPDi:
1510 case AArch64::STNPDi:
1511 case AArch64::LDPDpost:
1512 case AArch64::STPDpost:
1513 case AArch64::LDPDi:
1514 case AArch64::STPDi:
1515 case AArch64::LDPDpre:
1516 case AArch64::STPDpre:
1520 case AArch64::LDNPSi:
1521 case AArch64::STNPSi:
1522 case AArch64::LDPSpost:
1523 case AArch64::STPSpost:
1524 case AArch64::LDPSi:
1525 case AArch64::STPSi:
1526 case AArch64::LDPSpre:
1527 case AArch64::STPSpre:
1537 if (IsLoad && Rt == Rt2)
1542 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1550 const void *Decoder) {
1551 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1552 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1553 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1554 fieldFromInstruction(insn, 12, 9);
1555 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1560 case AArch64::LDRAAwriteback:
1561 case AArch64::LDRABwriteback:
1565 case AArch64::LDRAAindexed:
1566 case AArch64::LDRABindexed:
1572 DecodeSImm<10>(Inst, offset,
Addr, Decoder);
1574 if (writeback && Rt == Rn && Rn != 31) {
1583 const void *Decoder) {
1584 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1585 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1586 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1587 unsigned extend = fieldFromInstruction(insn, 10, 6);
1596 case AArch64::ADDWrx:
1597 case AArch64::SUBWrx:
1602 case AArch64::ADDSWrx:
1603 case AArch64::SUBSWrx:
1608 case AArch64::ADDXrx:
1609 case AArch64::SUBXrx:
1614 case AArch64::ADDSXrx:
1615 case AArch64::SUBSXrx:
1620 case AArch64::ADDXrx64:
1621 case AArch64::SUBXrx64:
1626 case AArch64::SUBSXrx64:
1627 case AArch64::ADDSXrx64:
1640 const void *Decoder) {
1641 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1642 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1643 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1647 if (Inst.
getOpcode() == AArch64::ANDSXri)
1652 imm = fieldFromInstruction(insn, 10, 13);
1656 if (Inst.
getOpcode() == AArch64::ANDSWri)
1661 imm = fieldFromInstruction(insn, 10, 12);
1671 const void *Decoder) {
1672 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1673 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1674 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1675 imm |= fieldFromInstruction(insn, 5, 5);
1687 case AArch64::MOVIv4i16:
1688 case AArch64::MOVIv8i16:
1689 case AArch64::MVNIv4i16:
1690 case AArch64::MVNIv8i16:
1691 case AArch64::MOVIv2i32:
1692 case AArch64::MOVIv4i32:
1693 case AArch64::MVNIv2i32:
1694 case AArch64::MVNIv4i32:
1697 case AArch64::MOVIv2s_msl:
1698 case AArch64::MOVIv4s_msl:
1699 case AArch64::MVNIv2s_msl:
1700 case AArch64::MVNIv4s_msl:
1710 const void *Decoder) {
1711 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1712 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1713 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1714 imm |= fieldFromInstruction(insn, 5, 5);
1727 uint64_t
Addr,
const void *Decoder) {
1728 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1729 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1730 imm |= fieldFromInstruction(insn, 29, 2);
1735 if (imm & (1 << (21 - 1)))
1736 imm |= ~((1LL << 21) - 1);
1746 uint64_t
Addr,
const void *Decoder) {
1747 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1748 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1749 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1750 unsigned S = fieldFromInstruction(insn, 29, 1);
1751 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1753 unsigned ShifterVal = (Imm >> 12) & 3;
1754 unsigned ImmVal = Imm & 0xFFF;
1758 if (ShifterVal != 0 && ShifterVal != 1)
1783 const void *Decoder) {
1784 int64_t imm = fieldFromInstruction(insn, 0, 26);
1789 if (imm & (1 << (26 - 1)))
1790 imm |= ~((1LL << 26) - 1);
1800 const void *Decoder) {
1801 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1802 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1803 uint64_t crm = fieldFromInstruction(insn, 8, 4);
1804 uint64_t pstate_field = (op1 << 3) | op2;
1806 switch (pstate_field) {
1812 if ((pstate_field == AArch64PState::PAN ||
1813 pstate_field == AArch64PState::UAO ||
1814 pstate_field == AArch64PState::SSBS) && crm > 1)
1822 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1829 uint64_t
Addr,
const void *Decoder) {
1830 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1831 uint64_t
bit = fieldFromInstruction(insn, 31, 1) << 5;
1832 bit |= fieldFromInstruction(insn, 19, 5);
1833 int64_t dst = fieldFromInstruction(insn, 5, 14);
1838 if (dst & (1 << (14 - 1)))
1839 dst |= ~((1LL << 14) - 1);
1841 if (fieldFromInstruction(insn, 31, 1) == 0)
1853 unsigned RegClassID,
1856 const void *Decoder) {
1861 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1869 const void *Decoder) {
1871 AArch64::WSeqPairsClassRegClassID,
1872 RegNo,
Addr, Decoder);
1878 const void *Decoder) {
1880 AArch64::XSeqPairsClassRegClassID,
1881 RegNo,
Addr, Decoder);
1887 const void *Decoder) {
1888 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1889 unsigned imm = fieldFromInstruction(insn, 5, 13);
1895 if (Inst.
getOpcode() != AArch64::DUPM_ZI)
1903 uint64_t Address,
const void *Decoder) {
1904 if (Imm & ~((1LL <<
Bits) - 1))
1908 if (Imm & (1 << (
Bits - 1)))
1909 Imm |= ~((1LL <<
Bits) - 1);
1916 template <
int ElementW
idth>
1918 uint64_t
Addr,
const void *Decoder) {
1919 unsigned Val = (uint8_t)Imm;
1920 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1921 if (ElementWidth == 8 &&
Shift)
1930 uint64_t
Addr,
const void *Decoder) {