LLVM 18.0.0git
AArch64Disassembler.cpp
Go to the documentation of this file.
1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "AArch64Disassembler.h"
13#include "AArch64ExternalSymbolizer.h"
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "MCTargetDesc/AArch64MCTargetDesc.h"
16#include "TargetInfo/AArch64TargetInfo.h"
17#include "Utils/AArch64BaseInfo.h"
18#include "llvm-c/Disassembler.h"
19#include "llvm/MC/MCDecoderOps.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstrDesc.h"
23#include "llvm/MC/MCRegisterInfo.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/MC/TargetRegistry.h"
26#include "llvm/Support/Compiler.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/Support/ErrorHandling.h"
29#include <algorithm>
30#include <memory>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "aarch64-disassembler"
35
36// Pull DecodeStatus and its enum values into the global namespace.
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39// Forward declare these because the autogenerated code will reference them.
40// Definitions are further down.
41static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
42 uint64_t Address,
43 const MCDisassembler *Decoder);
44static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
45 uint64_t Address,
46 const MCDisassembler *Decoder);
47static DecodeStatus
48DecodeFPR128_0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
49 const MCDisassembler *Decoder);
50static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
51 uint64_t Address,
52 const MCDisassembler *Decoder);
53static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
54 uint64_t Address,
55 const MCDisassembler *Decoder);
56static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
57 uint64_t Address,
58 const MCDisassembler *Decoder);
59static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
60 uint64_t Address,
61 const MCDisassembler *Decoder);
62static DecodeStatus
63DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
64 const MCDisassembler *Decoder);
65static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
66 uint64_t Address,
67 const MCDisassembler *Decoder);
68static DecodeStatus
69DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
70 const MCDisassembler *Decoder);
71static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
72 uint64_t Address,
73 const MCDisassembler *Decoder);
74static DecodeStatus
75DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo,
76 uint64_t Address, const void *Decoder);
77static DecodeStatus
78DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo,
79 uint64_t Address,
80 const MCDisassembler *Decoder);
81static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
82 uint64_t Address,
83 const MCDisassembler *Decoder);
84static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
85 uint64_t Address,
86 const MCDisassembler *Decoder);
87static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
88 uint64_t Address,
89 const MCDisassembler *Decoder);
90static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
91 uint64_t Address,
92 const MCDisassembler *Decoder);
93static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
94 uint64_t Address,
95 const MCDisassembler *Decoder);
96static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
97 uint64_t Address,
98 const MCDisassembler *Decoder);
99static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
100 uint64_t Address,
101 const MCDisassembler *Decoder);
102static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
103 uint64_t Address,
104 const MCDisassembler *Decoder);
105static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
106 uint64_t Address,
107 const MCDisassembler *Decoder);
108static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
109 uint64_t Address,
110 const MCDisassembler *Decoder);
111static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
112 uint64_t Address,
113 const MCDisassembler *Decoder);
114static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
115 uint64_t Address,
116 const MCDisassembler *Decoder);
117static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
118 uint64_t Address,
119 const MCDisassembler *Decoder);
120static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
121 uint64_t Address,
122 const MCDisassembler *Decoder);
123static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
124 uint64_t Address,
125 const void *Decoder);
126static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
127 uint64_t Address,
128 const void *Decoder);
129static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo,
130 uint64_t Address,
131 const void *Decoder);
132static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo,
133 uint64_t Address,
134 const void *Decoder);
135template <unsigned NumBitsForTile>
136static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
137 uint64_t Address,
138 const MCDisassembler *Decoder);
139static DecodeStatus
140DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
141 uint64_t Address,
142 const MCDisassembler *Decoder);
143static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
144 uint64_t Address,
145 const MCDisassembler *Decoder);
146static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo,
147 uint64_t Address,
148 const MCDisassembler *Decoder);
149static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
150 uint64_t Address,
151 const MCDisassembler *Decoder);
152static DecodeStatus
153DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
154 const MCDisassembler *Decoder);
155static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
156 uint64_t Address,
157 const void *Decoder);
158static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
159 uint64_t Address,
160 const void *Decoder);
161
162static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
163 uint64_t Address,
164 const MCDisassembler *Decoder);
165static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
166 uint64_t Address,
167 const MCDisassembler *Decoder);
168static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
169 uint64_t Address,
170 const MCDisassembler *Decoder);
171static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
172 uint64_t Address,
173 const MCDisassembler *Decoder);
174static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
175 uint64_t Address,
176 const MCDisassembler *Decoder);
177static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
178 uint64_t Address,
179 const MCDisassembler *Decoder);
180static DecodeStatus
181DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
182 const MCDisassembler *Decoder);
183static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
184 uint64_t Address,
185 const MCDisassembler *Decoder);
186static DecodeStatus
187DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
188 const MCDisassembler *Decoder);
189static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
190 uint64_t Address,
191 const MCDisassembler *Decoder);
192static DecodeStatus
193DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
194 const MCDisassembler *Decoder);
195static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
196 uint64_t Address,
197 const MCDisassembler *Decoder);
198static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
199 uint64_t Address,
200 const MCDisassembler *Decoder);
201static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
202 uint64_t Address,
203 const MCDisassembler *Decoder);
204static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
205 uint64_t Address,
206 const MCDisassembler *Decoder);
207static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
208 uint64_t Address,
209 const MCDisassembler *Decoder);
210static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
211 uint64_t Address,
212 const MCDisassembler *Decoder);
213static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
214 uint64_t Address,
215 const MCDisassembler *Decoder);
216static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
217 uint64_t Address,
218 const MCDisassembler *Decoder);
219static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
220 uint64_t Address,
221 const MCDisassembler *Decoder);
222static DecodeStatus
223DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn,
224 uint64_t Address,
225 const MCDisassembler *Decoder);
226static DecodeStatus
227DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn,
228 uint64_t Address,
229 const MCDisassembler *Decoder);
230static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
231 uint64_t Address,
232 const MCDisassembler *Decoder);
233
234static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
235 uint64_t Address,
236 const MCDisassembler *Decoder);
237static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
238 uint64_t Addr,
239 const MCDisassembler *Decoder);
240static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
241 uint64_t Addr,
242 const MCDisassembler *Decoder);
243static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
244 uint64_t Addr,
245 const MCDisassembler *Decoder);
246static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
247 uint64_t Addr,
248 const MCDisassembler *Decoder);
249static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
250 uint64_t Addr,
251 const MCDisassembler *Decoder);
252static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
253 uint64_t Addr,
254 const MCDisassembler *Decoder);
255static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
256 uint64_t Addr,
257 const MCDisassembler *Decoder);
258static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
259 uint64_t Addr,
260 const MCDisassembler *Decoder);
261static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
262 uint64_t Addr,
263 const MCDisassembler *Decoder);
264static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
265 uint64_t Addr,
266 const MCDisassembler *Decoder);
267static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
268 uint64_t Addr,
269 const MCDisassembler *Decoder);
270static DecodeStatus
271DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
272 const MCDisassembler *Decoder);
273static DecodeStatus
274DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
275 const MCDisassembler *Decoder);
276static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
277 uint64_t Addr,
278 const MCDisassembler *Decoder);
279static DecodeStatus
280DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
281 const MCDisassembler *Decoder);
282template <int Bits>
283static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
284 const MCDisassembler *Decoder);
285template <int ElementWidth>
286static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
287 const MCDisassembler *Decoder);
288static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
289 uint64_t Addr,
290 const MCDisassembler *Decoder);
291static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
292 const MCDisassembler *Decoder);
293static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
294 uint64_t Addr,
295 const MCDisassembler *Decoder);
296static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
297 uint64_t Addr,
298 const MCDisassembler *Decoder);
299static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
300 uint64_t Address,
301 const MCDisassembler *Decoder);
302
303#include "AArch64GenDisassemblerTables.inc"
304#include "AArch64GenInstrInfo.inc"
305
306#define Success MCDisassembler::Success
307#define Fail MCDisassembler::Fail
308#define SoftFail MCDisassembler::SoftFail
309
310static MCDisassembler *createAArch64Disassembler(const Target &T,
311 const MCSubtargetInfo &STI,
312 MCContext &Ctx) {
313
314 return new AArch64Disassembler(STI, Ctx, T.createMCInstrInfo());
315}
316
317DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
318 ArrayRef<uint8_t> Bytes,
319 uint64_t Address,
320 raw_ostream &CS) const {
321 CommentStream = &CS;
322
323 Size = 0;
324 // We want to read exactly 4 bytes of data.
325 if (Bytes.size() < 4)
326 return Fail;
327 Size = 4;
328
329 // Encoded as a small-endian 32-bit word in the stream.
330 uint32_t Insn =
331 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
332
333 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
334
335 for (const auto *Table : Tables) {
336 DecodeStatus Result =
337 decodeInstruction(Table, MI, Insn, Address, this, STI);
338
339 const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
340
341 // For Scalable Matrix Extension (SME) instructions that have an implicit
342 // operand for the accumulator (ZA) or implicit immediate zero which isn't
343 // encoded, manually insert operand.
344 for (unsigned i = 0; i < Desc.getNumOperands(); i++) {
345 if (Desc.operands()[i].OperandType == MCOI::OPERAND_REGISTER) {
346 switch (Desc.operands()[i].RegClass) {
347 default:
348 break;
349 case AArch64::MPRRegClassID:
350 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA));
351 break;
352 case AArch64::MPR8RegClassID:
353 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0));
354 break;
355 case AArch64::ZTRRegClassID:
356 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0));
357 break;
358 }
359 } else if (Desc.operands()[i].OperandType ==
360 AArch64::OPERAND_IMPLICIT_IMM_0) {
361 MI.insert(MI.begin() + i, MCOperand::createImm(0));
362 }
363 }
364
365 if (MI.getOpcode() == AArch64::LDR_ZA ||
366 MI.getOpcode() == AArch64::STR_ZA) {
367 // Spill and fill instructions have a single immediate used for both
368 // the vector select offset and optional memory offset. Replicate
369 // the decoded immediate.
370 const MCOperand &Imm4Op = MI.getOperand(2);
371 assert(Imm4Op.isImm() && "Unexpected operand type!");
372 MI.addOperand(Imm4Op);
373 }
374
375 if (Result != MCDisassembler::Fail)
376 return Result;
377 }
378
379 return MCDisassembler::Fail;
380}
381
382uint64_t AArch64Disassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
383 uint64_t Address) const {
384 // AArch64 instructions are always 4 bytes wide, so there's no point
385 // in skipping any smaller number of bytes if an instruction can't
386 // be decoded.
387 return 4;
388}
389
390static MCSymbolizer *
391createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
392 LLVMSymbolLookupCallback SymbolLookUp,
393 void *DisInfo, MCContext *Ctx,
394 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
395 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
396 SymbolLookUp, DisInfo);
397}
398
399extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() {
400 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
401 createAArch64Disassembler);
402 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
403 createAArch64Disassembler);
404 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
405 createAArch64ExternalSymbolizer);
406 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
407 createAArch64ExternalSymbolizer);
408 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(),
409 createAArch64Disassembler);
410 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(),
411 createAArch64ExternalSymbolizer);
412
413 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
414 createAArch64Disassembler);
415 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
416 createAArch64ExternalSymbolizer);
417 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
418 createAArch64Disassembler);
419 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
420 createAArch64ExternalSymbolizer);
421}
422
423static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
424 uint64_t Addr,
425 const MCDisassembler *Decoder) {
426 if (RegNo > 31)
427 return Fail;
428
429 unsigned Register =
430 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
431 Inst.addOperand(MCOperand::createReg(Register));
432 return Success;
433}
434
435static DecodeStatus
436DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
437 const MCDisassembler *Decoder) {
438 if (RegNo > 15)
439 return Fail;
440 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
441}
442
443static DecodeStatus
444DecodeFPR128_0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
445 const MCDisassembler *Decoder) {
446 if (RegNo > 7)
447 return Fail;
448 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
449}
450
451static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
452 uint64_t Addr,
453 const MCDisassembler *Decoder) {
454 if (RegNo > 31)
455 return Fail;
456
457 unsigned Register =
458 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
459 Inst.addOperand(MCOperand::createReg(Register));
460 return Success;
461}
462
463static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
464 uint64_t Addr,
465 const MCDisassembler *Decoder) {
466 if (RegNo > 31)
467 return Fail;
468
469 unsigned Register =
470 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
471 Inst.addOperand(MCOperand::createReg(Register));
472 return Success;
473}
474
475static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
476 uint64_t Addr,
477 const MCDisassembler *Decoder) {
478 if (RegNo > 31)
479 return Fail;
480
481 unsigned Register =
482 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
483 Inst.addOperand(MCOperand::createReg(Register));
484 return Success;
485}
486
487static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
488 uint64_t Addr,
489 const MCDisassembler *Decoder) {
490 if (RegNo > 31)
491 return Fail;
492
493 unsigned Register =
494 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
495 Inst.addOperand(MCOperand::createReg(Register));
496 return Success;
497}
498
499static DecodeStatus
500DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
501 const MCDisassembler *Decoder) {
502 if (RegNo > 30)
503 return Fail;
504
505 unsigned Register =
506 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
507 RegNo);
508 Inst.addOperand(MCOperand::createReg(Register));
509 return Success;
510}
511
512static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
513 uint64_t Addr,
514 const MCDisassembler *Decoder) {
515 if (RegNo > 31)
516 return Fail;
517
518 unsigned Register =
519 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
520 Inst.addOperand(MCOperand::createReg(Register));
521 return Success;
522}
523
524static DecodeStatus
525DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
526 const MCDisassembler *Decoder) {
527 if (RegNo > 22)
528 return Fail;
529 if (RegNo & 1)
530 return Fail;
531
532 unsigned Register =
533 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
534 RegNo >> 1);
535 Inst.addOperand(MCOperand::createReg(Register));
536 return Success;
537}
538
539static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
540 uint64_t Addr,
541 const MCDisassembler *Decoder) {
542 if (RegNo > 31)
543 return Fail;
544 unsigned Register =
545 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
546 Inst.addOperand(MCOperand::createReg(Register));
547 return Success;
548}
549
550static DecodeStatus
551DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo,
552 uint64_t Addr, const void *Decoder) {
553 if (RegNo > 3)
554 return Fail;
555
556 unsigned Register =
557 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_8_11RegClassID]
558 .getRegister(RegNo);
559 Inst.addOperand(MCOperand::createReg(Register));
560 return Success;
561}
562
563static DecodeStatus
564DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo,
565 uint64_t Addr,
566 const MCDisassembler *Decoder) {
567 if (RegNo > 3)
568 return Fail;
569
570 unsigned Register =
571 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
572 .getRegister(RegNo);
573 Inst.addOperand(MCOperand::createReg(Register));
574 return Success;
575}
576
577static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
578 uint64_t Addr,
579 const MCDisassembler *Decoder) {
580 if (RegNo > 31)
581 return Fail;
582
583 unsigned Register =
584 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
585 Inst.addOperand(MCOperand::createReg(Register));
586 return Success;
587}
588
589static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
590 uint64_t Addr,
591 const MCDisassembler *Decoder) {
592 if (RegNo > 31)
593 return Fail;
594
595 unsigned Register =
596 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
597 Inst.addOperand(MCOperand::createReg(Register));
598 return Success;
599}
600
601static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
602 uint64_t Address,
603 const MCDisassembler *Decoder) {
604 if (RegNo > 31)
605 return Fail;
606
607 unsigned Register =
608 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
609 Inst.addOperand(MCOperand::createReg(Register));
610 return Success;
611}
612
613static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
614 uint64_t Address,
615 const MCDisassembler *Decoder) {
616 if (RegNo > 15)
617 return Fail;
618 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
619}
620
621static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
622 uint64_t Address,
623 const MCDisassembler *Decoder) {
624 if (RegNo > 7)
625 return Fail;
626 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
627}
628
629static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
630 uint64_t Address,
631 const MCDisassembler *Decoder) {
632 if (RegNo > 31)
633 return Fail;
634 unsigned Register =
635 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
636 Inst.addOperand(MCOperand::createReg(Register));
637 return Success;
638}
639
640static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
641 uint64_t Address,
642 const MCDisassembler *Decoder) {
643 if (RegNo > 31)
644 return Fail;
645 unsigned Register =
646 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
647 Inst.addOperand(MCOperand::createReg(Register));
648 return Success;
649}
650
651static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
652 uint64_t Address,
653 const MCDisassembler *Decoder) {
654 if (RegNo > 31)
655 return Fail;
656 unsigned Register =
657 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
658 Inst.addOperand(MCOperand::createReg(Register));
659 return Success;
660}
661
662static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
663 uint64_t Address,
664 const void *Decoder) {
665 if (RegNo * 2 > 30)
666 return Fail;
667 unsigned Register =
668 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2);
669 Inst.addOperand(MCOperand::createReg(Register));
670 return Success;
671}
672
673static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
674 uint64_t Address,
675 const void *Decoder) {
676 if (RegNo * 4 > 28)
677 return Fail;
678 unsigned Register =
679 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
680 Inst.addOperand(MCOperand::createReg(Register));
681 return Success;
682}
683
684static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo,
685 uint64_t Address,
686 const void *Decoder) {
687 if (RegNo > 15)
688 return Fail;
689 unsigned Register =
690 AArch64MCRegisterClasses[AArch64::ZPR2StridedRegClassID].getRegister(
691 RegNo);
692 Inst.addOperand(MCOperand::createReg(Register));
693 return Success;
694}
695
696static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo,
697 uint64_t Address,
698 const void *Decoder) {
699 if (RegNo > 7)
700 return Fail;
701 unsigned Register =
702 AArch64MCRegisterClasses[AArch64::ZPR4StridedRegClassID].getRegister(
703 RegNo);
704 Inst.addOperand(MCOperand::createReg(Register));
705 return Success;
706}
707
708static DecodeStatus
709DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
710 uint64_t Address,
711 const MCDisassembler *Decoder) {
712 if (RegMask > 0xFF)
713 return Fail;
714 Inst.addOperand(MCOperand::createImm(RegMask));
715 return Success;
716}
717
718static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
719 {AArch64::ZAB0},
720 {AArch64::ZAH0, AArch64::ZAH1},
721 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
722 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4,
723 AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
724 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4,
725 AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9,
726 AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
727 AArch64::ZAQ14, AArch64::ZAQ15}};
728
729template <unsigned NumBitsForTile>
730static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
731 uint64_t Address,
732 const MCDisassembler *Decoder) {
733 unsigned LastReg = (1 << NumBitsForTile) - 1;
734 if (RegNo > LastReg)
735 return Fail;
736 Inst.addOperand(
737 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo]));
738 return Success;
739}
740
741static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
742 uint64_t Addr,
743 const MCDisassembler *Decoder) {
744 if (RegNo > 15)
745 return Fail;
746
747 unsigned Register =
748 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
749 Inst.addOperand(MCOperand::createReg(Register));
750 return Success;
751}
752
753static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo,
754 uint64_t Addr,
755 const MCDisassembler *Decoder) {
756 if (RegNo > 15)
757 return Fail;
758
759 unsigned Register =
760 AArch64MCRegisterClasses[AArch64::PNRRegClassID].getRegister(RegNo);
761 Inst.addOperand(MCOperand::createReg(Register));
762 return Success;
763}
764
765static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
766 uint64_t Addr,
767 const MCDisassembler *Decoder) {
768 if (RegNo > 7)
769 return Fail;
770
771 // Just reuse the PPR decode table
772 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
773}
774
775static DecodeStatus
776DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
777 const MCDisassembler *Decoder) {
778 if (RegNo > 7)
779 return Fail;
780
781 // Just reuse the PPR decode table
782 return DecodePNRRegisterClass(Inst, RegNo + 8, Addr, Decoder);
783}
784
785static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
786 uint64_t Address,
787 const void *Decoder) {
788 if (RegNo > 15)
789 return Fail;
790
791 unsigned Register =
792 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo);
793 Inst.addOperand(MCOperand::createReg(Register));
794 return Success;
795}
796
797static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
798 uint64_t Address,
799 const void *Decoder) {
800 if ((RegNo * 2) > 14)
801 return Fail;
802 unsigned Register =
803 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
804 Inst.addOperand(MCOperand::createReg(Register));
805 return Success;
806}
807
808static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
809 uint64_t Addr,
810 const MCDisassembler *Decoder) {
811 if (RegNo > 31)
812 return Fail;
813 unsigned Register =
814 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
815 Inst.addOperand(MCOperand::createReg(Register));
816 return Success;
817}
818
819static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
820 uint64_t Addr,
821 const MCDisassembler *Decoder) {
822 if (RegNo > 31)
823 return Fail;
824 unsigned Register =
825 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
826 Inst.addOperand(MCOperand::createReg(Register));
827 return Success;
828}
829
830static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
831 uint64_t Addr,
832 const MCDisassembler *Decoder) {
833 if (RegNo > 31)
834 return Fail;
835 unsigned Register =
836 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
837 Inst.addOperand(MCOperand::createReg(Register));
838 return Success;
839}
840
841static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
842 uint64_t Addr,
843 const MCDisassembler *Decoder) {
844 if (RegNo > 31)
845 return Fail;
846 unsigned Register =
847 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
848 Inst.addOperand(MCOperand::createReg(Register));
849 return Success;
850}
851
852static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
853 uint64_t Addr,
854 const MCDisassembler *Decoder) {
855 if (RegNo > 31)
856 return Fail;
857 unsigned Register =
858 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
859 Inst.addOperand(MCOperand::createReg(Register));
860 return Success;
861}
862
863static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
864 uint64_t Addr,
865 const MCDisassembler *Decoder) {
866 if (RegNo > 31)
867 return Fail;
868 unsigned Register =
869 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
870 Inst.addOperand(MCOperand::createReg(Register));
871 return Success;
872}
873
874static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
875 uint64_t Addr,
876 const MCDisassembler *Decoder) {
877 // scale{5} is asserted as 1 in tblgen.
878 Imm |= 0x20;
879 Inst.addOperand(MCOperand::createImm(64 - Imm));
880 return Success;
881}
882
883static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
884 uint64_t Addr,
885 const MCDisassembler *Decoder) {
886 Inst.addOperand(MCOperand::createImm(64 - Imm));
887 return Success;
888}
889
890static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
891 uint64_t Addr,
892 const MCDisassembler *Decoder) {
893 int64_t ImmVal = Imm;
894
895 // Sign-extend 19-bit immediate.
896 if (ImmVal & (1 << (19 - 1)))
897 ImmVal |= ~((1LL << 19) - 1);
898
899 if (!Decoder->tryAddingSymbolicOperand(
900 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4))
901 Inst.addOperand(MCOperand::createImm(ImmVal));
902 return Success;
903}
904
905static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
906 uint64_t Address,
907 const MCDisassembler *Decoder) {
908 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
909 Inst.addOperand(MCOperand::createImm(Imm & 1));
910 return Success;
911}
912
913static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
914 uint64_t Address,
915 const MCDisassembler *Decoder) {
916 Inst.addOperand(MCOperand::createImm(Imm));
917
918 // Every system register in the encoding space is valid with the syntax
919 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
920 return Success;
921}
922
923static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
924 uint64_t Address,
925 const MCDisassembler *Decoder) {
926 Inst.addOperand(MCOperand::createImm(Imm));
927
928 return Success;
929}
930
931static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
932 uint64_t Address,
933 const MCDisassembler *Decoder) {
934 // This decoder exists to add the dummy Lane operand to the MCInst, which must
935 // be 1 in assembly but has no other real manifestation.
936 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
937 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
938 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
939
940 if (IsToVec) {
941 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
942 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
943 } else {
944 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
945 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
946 }
947
948 // Add the lane
949 Inst.addOperand(MCOperand::createImm(1));
950
951 return Success;
952}
953
954static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
955 unsigned Add) {
956 Inst.addOperand(MCOperand::createImm(Add - Imm));
957 return Success;
958}
959
960static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
961 unsigned Add) {
962 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
963 return Success;
964}
965
966static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
967 uint64_t Addr,
968 const MCDisassembler *Decoder) {
969 return DecodeVecShiftRImm(Inst, Imm, 64);
970}
971
972static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
973 uint64_t Addr,
974 const MCDisassembler *Decoder) {
975 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
976}
977
978static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
979 uint64_t Addr,
980 const MCDisassembler *Decoder) {
981 return DecodeVecShiftRImm(Inst, Imm, 32);
982}
983
984static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
985 uint64_t Addr,
986 const MCDisassembler *Decoder) {
987 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
988}
989
990static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
991 uint64_t Addr,
992 const MCDisassembler *Decoder) {
993 return DecodeVecShiftRImm(Inst, Imm, 16);
994}
995
996static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
997 uint64_t Addr,
998 const MCDisassembler *Decoder) {
999 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
1000}
1001
1002static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
1003 uint64_t Addr,
1004 const MCDisassembler *Decoder) {
1005 return DecodeVecShiftRImm(Inst, Imm, 8);
1006}
1007
1008static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
1009 uint64_t Addr,
1010 const MCDisassembler *Decoder) {
1011 return DecodeVecShiftLImm(Inst, Imm, 64);
1012}
1013
1014static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
1015 uint64_t Addr,
1016 const MCDisassembler *Decoder) {
1017 return DecodeVecShiftLImm(Inst, Imm, 32);
1018}
1019
1020static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
1021 uint64_t Addr,
1022 const MCDisassembler *Decoder) {
1023 return DecodeVecShiftLImm(Inst, Imm, 16);
1024}
1025
1026static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
1027 uint64_t Addr,
1028 const MCDisassembler *Decoder) {
1029 return DecodeVecShiftLImm(Inst, Imm, 8);
1030}
1031
1032static DecodeStatus
1033DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1034 const MCDisassembler *Decoder) {
1035 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1036 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1037 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1038 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
1039 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
1040 unsigned shift = (shiftHi << 6) | shiftLo;
1041 switch (Inst.getOpcode()) {
1042 default:
1043 return Fail;
1044 case AArch64::ADDWrs:
1045 case AArch64::ADDSWrs:
1046 case AArch64::SUBWrs:
1047 case AArch64::SUBSWrs:
1048 // if shift == '11' then ReservedValue()
1049 if (shiftHi == 0x3)
1050 return Fail;
1051 [[fallthrough]];
1052 case AArch64::ANDWrs:
1053 case AArch64::ANDSWrs:
1054 case AArch64::BICWrs:
1055 case AArch64::BICSWrs:
1056 case AArch64::ORRWrs:
1057 case AArch64::ORNWrs:
1058 case AArch64::EORWrs:
1059 case AArch64::EONWrs: {
1060 // if sf == '0' and imm6<5> == '1' then ReservedValue()
1061 if (shiftLo >> 5 == 1)
1062 return Fail;
1063 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1064 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1065 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1066 break;
1067 }
1068 case AArch64::ADDXrs:
1069 case AArch64::ADDSXrs:
1070 case AArch64::SUBXrs:
1071 case AArch64::SUBSXrs:
1072 // if shift == '11' then ReservedValue()
1073 if (shiftHi == 0x3)
1074 return Fail;
1075 [[fallthrough]];
1076 case AArch64::ANDXrs:
1077 case AArch64::ANDSXrs:
1078 case AArch64::BICXrs:
1079 case AArch64::BICSXrs:
1080 case AArch64::ORRXrs:
1081 case AArch64::ORNXrs:
1082 case AArch64::EORXrs:
1083 case AArch64::EONXrs:
1084 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1085 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1086 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1087 break;
1088 }
1089
1090 Inst.addOperand(MCOperand::createImm(shift));
1091 return Success;
1092}
1093
1094static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
1095 uint64_t Addr,
1096 const MCDisassembler *Decoder) {
1097 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1098 unsigned imm = fieldFromInstruction(insn, 5, 16);
1099 unsigned shift = fieldFromInstruction(insn, 21, 2);
1100 shift <<= 4;
1101 switch (Inst.getOpcode()) {
1102 default:
1103 return Fail;
1104 case AArch64::MOVZWi:
1105 case AArch64::MOVNWi:
1106 case AArch64::MOVKWi:
1107 if (shift & (1U << 5))
1108 return Fail;
1109 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1110 break;
1111 case AArch64::MOVZXi:
1112 case AArch64::MOVNXi:
1113 case AArch64::MOVKXi:
1114 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1115 break;
1116 }
1117
1118 if (Inst.getOpcode() == AArch64::MOVKWi ||
1119 Inst.getOpcode() == AArch64::MOVKXi)
1120 Inst.addOperand(Inst.getOperand(0));
1121
1122 Inst.addOperand(MCOperand::createImm(imm));
1123 Inst.addOperand(MCOperand::createImm(shift));
1124 return Success;
1125}
1126
1127static DecodeStatus
1128DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1129 const MCDisassembler *Decoder) {
1130 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1131 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1132 unsigned offset = fieldFromInstruction(insn, 10, 12);
1133
1134 switch (Inst.getOpcode()) {
1135 default:
1136 return Fail;
1137 case AArch64::PRFMui:
1138 // Rt is an immediate in prefetch.
1139 Inst.addOperand(MCOperand::createImm(Rt));
1140 break;
1141 case AArch64::STRBBui:
1142 case AArch64::LDRBBui:
1143 case AArch64::LDRSBWui:
1144 case AArch64::STRHHui:
1145 case AArch64::LDRHHui:
1146 case AArch64::LDRSHWui:
1147 case AArch64::STRWui:
1148 case AArch64::LDRWui:
1149 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1150 break;
1151 case AArch64::LDRSBXui:
1152 case AArch64::LDRSHXui:
1153 case AArch64::LDRSWui:
1154 case AArch64::STRXui:
1155 case AArch64::LDRXui:
1156 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1157 break;
1158 case AArch64::LDRQui:
1159 case AArch64::STRQui:
1160 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1161 break;
1162 case AArch64::LDRDui:
1163 case AArch64::STRDui:
1164 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1165 break;
1166 case AArch64::LDRSui:
1167 case AArch64::STRSui:
1168 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1169 break;
1170 case AArch64::LDRHui:
1171 case AArch64::STRHui:
1172 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1173 break;
1174 case AArch64::LDRBui:
1175 case AArch64::STRBui:
1176 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1177 break;
1178 }
1179
1180 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1181 if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 0, 4))
1182 Inst.addOperand(MCOperand::createImm(offset));
1183 return Success;
1184}
1185
1186static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1187 uint64_t Addr,
1188 const MCDisassembler *Decoder) {
1189 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1190 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1191 int64_t offset = fieldFromInstruction(insn, 12, 9);
1192
1193 // offset is a 9-bit signed immediate, so sign extend it to
1194 // fill the unsigned.
1195 if (offset & (1 << (9 - 1)))
1196 offset |= ~((1LL << 9) - 1);
1197
1198 // First operand is always the writeback to the address register, if needed.
1199 switch (Inst.getOpcode()) {
1200 default:
1201 break;
1202 case AArch64::LDRSBWpre:
1203 case AArch64::LDRSHWpre:
1204 case AArch64::STRBBpre:
1205 case AArch64::LDRBBpre:
1206 case AArch64::STRHHpre:
1207 case AArch64::LDRHHpre:
1208 case AArch64::STRWpre:
1209 case AArch64::LDRWpre:
1210 case AArch64::LDRSBWpost:
1211 case AArch64::LDRSHWpost:
1212 case AArch64::STRBBpost:
1213 case AArch64::LDRBBpost:
1214 case AArch64::STRHHpost:
1215 case AArch64::LDRHHpost:
1216 case AArch64::STRWpost:
1217 case AArch64::LDRWpost:
1218 case AArch64::LDRSBXpre:
1219 case AArch64::LDRSHXpre:
1220 case AArch64::STRXpre:
1221 case AArch64::LDRSWpre:
1222 case AArch64::LDRXpre:
1223 case AArch64::LDRSBXpost:
1224 case AArch64::LDRSHXpost:
1225 case AArch64::STRXpost:
1226 case AArch64::LDRSWpost:
1227 case AArch64::LDRXpost:
1228 case AArch64::LDRQpre:
1229 case AArch64::STRQpre:
1230 case AArch64::LDRQpost:
1231 case AArch64::STRQpost:
1232 case AArch64::LDRDpre:
1233 case AArch64::STRDpre:
1234 case AArch64::LDRDpost:
1235 case AArch64::STRDpost:
1236 case AArch64::LDRSpre:
1237 case AArch64::STRSpre:
1238 case AArch64::LDRSpost:
1239 case AArch64::STRSpost:
1240 case AArch64::LDRHpre:
1241 case AArch64::STRHpre:
1242 case AArch64::LDRHpost:
1243 case AArch64::STRHpost:
1244 case AArch64::LDRBpre:
1245 case AArch64::STRBpre:
1246 case AArch64::LDRBpost:
1247 case AArch64::STRBpost:
1248 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1249 break;
1250 }
1251
1252 switch (Inst.getOpcode()) {
1253 default:
1254 return Fail;
1255 case AArch64::PRFUMi:
1256 // Rt is an immediate in prefetch.
1257 Inst.addOperand(MCOperand::createImm(Rt));
1258 break;
1259 case AArch64::STURBBi:
1260 case AArch64::LDURBBi:
1261 case AArch64::LDURSBWi:
1262 case AArch64::STURHHi:
1263 case AArch64::LDURHHi:
1264 case AArch64::LDURSHWi:
1265 case AArch64::STURWi:
1266 case AArch64::LDURWi:
1267 case AArch64::LDTRSBWi:
1268 case AArch64::LDTRSHWi:
1269 case AArch64::STTRWi:
1270 case AArch64::LDTRWi:
1271 case AArch64::STTRHi:
1272 case AArch64::LDTRHi:
1273 case AArch64::LDTRBi:
1274 case AArch64::STTRBi:
1275 case AArch64::LDRSBWpre:
1276 case AArch64::LDRSHWpre:
1277 case AArch64::STRBBpre:
1278 case AArch64::LDRBBpre:
1279 case AArch64::STRHHpre:
1280 case AArch64::LDRHHpre:
1281 case AArch64::STRWpre:
1282 case AArch64::LDRWpre:
1283 case AArch64::LDRSBWpost:
1284 case AArch64::LDRSHWpost:
1285 case AArch64::STRBBpost:
1286 case AArch64::LDRBBpost:
1287 case AArch64::STRHHpost:
1288 case AArch64::LDRHHpost:
1289 case AArch64::STRWpost:
1290 case AArch64::LDRWpost:
1291 case AArch64::STLURBi:
1292 case AArch64::STLURHi:
1293 case AArch64::STLURWi:
1294 case AArch64::LDAPURBi:
1295 case AArch64::LDAPURSBWi:
1296 case AArch64::LDAPURHi:
1297 case AArch64::LDAPURSHWi:
1298 case AArch64::LDAPURi:
1299 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1300 break;
1301 case AArch64::LDURSBXi:
1302 case AArch64::LDURSHXi:
1303 case AArch64::LDURSWi:
1304 case AArch64::STURXi:
1305 case AArch64::LDURXi:
1306 case AArch64::LDTRSBXi:
1307 case AArch64::LDTRSHXi:
1308 case AArch64::LDTRSWi:
1309 case AArch64::STTRXi:
1310 case AArch64::LDTRXi:
1311 case AArch64::LDRSBXpre:
1312 case AArch64::LDRSHXpre:
1313 case AArch64::STRXpre:
1314 case AArch64::LDRSWpre:
1315 case AArch64::LDRXpre:
1316 case AArch64::LDRSBXpost:
1317 case AArch64::LDRSHXpost:
1318 case AArch64::STRXpost:
1319 case AArch64::LDRSWpost:
1320 case AArch64::LDRXpost:
1321 case AArch64::LDAPURSWi:
1322 case AArch64::LDAPURSHXi:
1323 case AArch64::LDAPURSBXi:
1324 case AArch64::STLURXi:
1325 case AArch64::LDAPURXi:
1326 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1327 break;
1328 case AArch64::LDURQi:
1329 case AArch64::STURQi:
1330 case AArch64::LDRQpre:
1331 case AArch64::STRQpre:
1332 case AArch64::LDRQpost:
1333 case AArch64::STRQpost:
1334 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1335 break;
1336 case AArch64::LDURDi:
1337 case AArch64::STURDi:
1338 case AArch64::LDRDpre:
1339 case AArch64::STRDpre:
1340 case AArch64::LDRDpost:
1341 case AArch64::STRDpost:
1342 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1343 break;
1344 case AArch64::LDURSi:
1345 case AArch64::STURSi:
1346 case AArch64::LDRSpre:
1347 case AArch64::STRSpre:
1348 case AArch64::LDRSpost:
1349 case AArch64::STRSpost:
1350 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1351 break;
1352 case AArch64::LDURHi:
1353 case AArch64::STURHi:
1354 case AArch64::LDRHpre:
1355 case AArch64::STRHpre:
1356 case AArch64::LDRHpost:
1357 case AArch64::STRHpost:
1358 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1359 break;
1360 case AArch64::LDURBi:
1361 case AArch64::STURBi:
1362 case AArch64::LDRBpre:
1363 case AArch64::STRBpre:
1364 case AArch64::LDRBpost:
1365 case AArch64::STRBpost:
1366 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1367 break;
1368 }
1369
1370 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1371 Inst.addOperand(MCOperand::createImm(offset));
1372
1373 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1374 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1375 bool IsFP = fieldFromInstruction(insn, 26, 1);
1376
1377 // Cannot write back to a transfer register (but xzr != sp).
1378 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1379 return SoftFail;
1380
1381 return Success;
1382}
1383
1384static DecodeStatus
1385DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1386 const MCDisassembler *Decoder) {
1387 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1388 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1389 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1390 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1391
1392 unsigned Opcode = Inst.getOpcode();
1393 switch (Opcode) {
1394 default:
1395 return Fail;
1396 case AArch64::STLXRW:
1397 case AArch64::STLXRB:
1398 case AArch64::STLXRH:
1399 case AArch64::STXRW:
1400 case AArch64::STXRB:
1401 case AArch64::STXRH:
1402 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1403 [[fallthrough]];
1404 case AArch64::LDARW:
1405 case AArch64::LDARB:
1406 case AArch64::LDARH:
1407 case AArch64::LDAXRW:
1408 case AArch64::LDAXRB:
1409 case AArch64::LDAXRH:
1410 case AArch64::LDXRW:
1411 case AArch64::LDXRB:
1412 case AArch64::LDXRH:
1413 case AArch64::STLRW:
1414 case AArch64::STLRB:
1415 case AArch64::STLRH:
1416 case AArch64::STLLRW:
1417 case AArch64::STLLRB:
1418 case AArch64::STLLRH:
1419 case AArch64::LDLARW:
1420 case AArch64::LDLARB:
1421 case AArch64::LDLARH:
1422 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1423 break;
1424 case AArch64::STLXRX:
1425 case AArch64::STXRX:
1426 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1427 [[fallthrough]];
1428 case AArch64::LDARX:
1429 case AArch64::LDAXRX:
1430 case AArch64::LDXRX:
1431 case AArch64::STLRX:
1432 case AArch64::LDLARX:
1433 case AArch64::STLLRX:
1434 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1435 break;
1436 case AArch64::STLXPW:
1437 case AArch64::STXPW:
1438 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1439 [[fallthrough]];
1440 case AArch64::LDAXPW:
1441 case AArch64::LDXPW:
1442 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1443 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1444 break;
1445 case AArch64::STLXPX:
1446 case AArch64::STXPX:
1447 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1448 [[fallthrough]];
1449 case AArch64::LDAXPX:
1450 case AArch64::LDXPX:
1451 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1452 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1453 break;
1454 }
1455
1456 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1457
1458 // You shouldn't load to the same register twice in an instruction...
1459 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1460 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1461 Rt == Rt2)
1462 return SoftFail;
1463
1464 return Success;
1465}
1466
1467static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
1468 uint64_t Addr,
1469 const MCDisassembler *Decoder) {
1470 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1471 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1472 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1473 int64_t offset = fieldFromInstruction(insn, 15, 7);
1474 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1475
1476 // offset is a 7-bit signed immediate, so sign extend it to
1477 // fill the unsigned.
1478 if (offset & (1 << (7 - 1)))
1479 offset |= ~((1LL << 7) - 1);
1480
1481 unsigned Opcode = Inst.getOpcode();
1482 bool NeedsDisjointWritebackTransfer = false;
1483
1484 // First operand is always writeback of base register.
1485 switch (Opcode) {
1486 default:
1487 break;
1488 case AArch64::LDPXpost:
1489 case AArch64::STPXpost:
1490 case AArch64::LDPSWpost:
1491 case AArch64::LDPXpre:
1492 case AArch64::STPXpre:
1493 case AArch64::LDPSWpre:
1494 case AArch64::LDPWpost:
1495 case AArch64::STPWpost:
1496 case AArch64::LDPWpre:
1497 case AArch64::STPWpre:
1498 case AArch64::LDPQpost:
1499 case AArch64::STPQpost:
1500 case AArch64::LDPQpre:
1501 case AArch64::STPQpre:
1502 case AArch64::LDPDpost:
1503 case AArch64::STPDpost:
1504 case AArch64::LDPDpre:
1505 case AArch64::STPDpre:
1506 case AArch64::LDPSpost:
1507 case AArch64::STPSpost:
1508 case AArch64::LDPSpre:
1509 case AArch64::STPSpre:
1510 case AArch64::STGPpre:
1511 case AArch64::STGPpost:
1512 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1513 break;
1514 }
1515
1516 switch (Opcode) {
1517 default:
1518 return Fail;
1519 case AArch64::LDPXpost:
1520 case AArch64::STPXpost:
1521 case AArch64::LDPSWpost:
1522 case AArch64::LDPXpre:
1523 case AArch64::STPXpre:
1524 case AArch64::LDPSWpre:
1525 case AArch64::STGPpre:
1526 case AArch64::STGPpost:
1527 NeedsDisjointWritebackTransfer = true;
1528 [[fallthrough]];
1529 case AArch64::LDNPXi:
1530 case AArch64::STNPXi:
1531 case AArch64::LDPXi:
1532 case AArch64::STPXi:
1533 case AArch64::LDPSWi:
1534 case AArch64::STGPi:
1535 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1536 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1537 break;
1538 case AArch64::LDPWpost:
1539 case AArch64::STPWpost:
1540 case AArch64::LDPWpre:
1541 case AArch64::STPWpre:
1542 NeedsDisjointWritebackTransfer = true;
1543 [[fallthrough]];
1544 case AArch64::LDNPWi:
1545 case AArch64::STNPWi:
1546 case AArch64::LDPWi:
1547 case AArch64::STPWi:
1548 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1549 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1550 break;
1551 case AArch64::LDNPQi:
1552 case AArch64::STNPQi:
1553 case AArch64::LDPQpost:
1554 case AArch64::STPQpost:
1555 case AArch64::LDPQi:
1556 case AArch64::STPQi:
1557 case AArch64::LDPQpre:
1558 case AArch64::STPQpre:
1559 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1560 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1561 break;
1562 case AArch64::LDNPDi:
1563 case AArch64::STNPDi:
1564 case AArch64::LDPDpost:
1565 case AArch64::STPDpost:
1566 case AArch64::LDPDi:
1567 case AArch64::STPDi:
1568 case AArch64::LDPDpre:
1569 case AArch64::STPDpre:
1570 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1571 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1572 break;
1573 case AArch64::LDNPSi:
1574 case AArch64::STNPSi:
1575 case AArch64::LDPSpost:
1576 case AArch64::STPSpost:
1577 case AArch64::LDPSi:
1578 case AArch64::STPSi:
1579 case AArch64::LDPSpre:
1580 case AArch64::STPSpre:
1581 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1582 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1583 break;
1584 }
1585
1586 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1587 Inst.addOperand(MCOperand::createImm(offset));
1588
1589 // You shouldn't load to the same register twice in an instruction...
1590 if (IsLoad && Rt == Rt2)
1591 return SoftFail;
1592
1593 // ... or do any operation that writes-back to a transfer register. But note
1594 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1595 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1596 return SoftFail;
1597
1598 return Success;
1599}
1600
1601static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
1602 uint64_t Addr,
1603 const MCDisassembler *Decoder) {
1604 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1605 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1606 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1607 fieldFromInstruction(insn, 12, 9);
1608 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1609
1610 switch (Inst.getOpcode()) {
1611 default:
1612 return Fail;
1613 case AArch64::LDRAAwriteback:
1614 case AArch64::LDRABwriteback:
1615 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr,
1616 Decoder);
1617 break;
1618 case AArch64::LDRAAindexed:
1619 case AArch64::LDRABindexed:
1620 break;
1621 }
1622
1623 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1624 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1625 DecodeSImm<10>(Inst, offset, Addr, Decoder);
1626
1627 if (writeback && Rt == Rn && Rn != 31) {
1628 return SoftFail;
1629 }
1630
1631 return Success;
1632}
1633
1634static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1635 uint64_t Addr,
1636 const MCDisassembler *Decoder) {
1637 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1638 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1639 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1640 unsigned extend = fieldFromInstruction(insn, 10, 6);
1641
1642 unsigned shift = extend & 0x7;
1643 if (shift > 4)
1644 return Fail;
1645
1646 switch (Inst.getOpcode()) {
1647 default:
1648 return Fail;
1649 case AArch64::ADDWrx:
1650 case AArch64::SUBWrx:
1651 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1652 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1653 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1654 break;
1655 case AArch64::ADDSWrx:
1656 case AArch64::SUBSWrx:
1657 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1658 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1659 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1660 break;
1661 case AArch64::ADDXrx:
1662 case AArch64::SUBXrx:
1663 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1664 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1665 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1666 break;
1667 case AArch64::ADDSXrx:
1668 case AArch64::SUBSXrx:
1669 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1670 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1671 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1672 break;
1673 case AArch64::ADDXrx64:
1674 case AArch64::SUBXrx64:
1675 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1676 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1677 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1678 break;
1679 case AArch64::SUBSXrx64:
1680 case AArch64::ADDSXrx64:
1681 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1682 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1683 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1684 break;
1685 }
1686
1687 Inst.addOperand(MCOperand::createImm(extend));
1688 return Success;
1689}
1690
1691static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1692 uint64_t Addr,
1693 const MCDisassembler *Decoder) {
1694 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1695 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1696 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1697 unsigned imm;
1698
1699 if (Datasize) {
1700 if (Inst.getOpcode() == AArch64::ANDSXri)
1701 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1702 else
1703 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1704 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1705 imm = fieldFromInstruction(insn, 10, 13);
1706 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1707 return Fail;
1708 } else {
1709 if (Inst.getOpcode() == AArch64::ANDSWri)
1710 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1711 else
1712 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1713 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1714 imm = fieldFromInstruction(insn, 10, 12);
1715 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1716 return Fail;
1717 }
1718 Inst.addOperand(MCOperand::createImm(imm));
1719 return Success;
1720}
1721
1722static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
1723 uint64_t Addr,
1724 const MCDisassembler *Decoder) {
1725 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1726 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1727 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1728 imm |= fieldFromInstruction(insn, 5, 5);
1729
1730 if (Inst.getOpcode() == AArch64::MOVID)
1731 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1732 else
1733 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1734
1735 Inst.addOperand(MCOperand::createImm(imm));
1736
1737 switch (Inst.getOpcode()) {
1738 default:
1739 break;
1740 case AArch64::MOVIv4i16:
1741 case AArch64::MOVIv8i16:
1742 case AArch64::MVNIv4i16:
1743 case AArch64::MVNIv8i16:
1744 case AArch64::MOVIv2i32:
1745 case AArch64::MOVIv4i32:
1746 case AArch64::MVNIv2i32:
1747 case AArch64::MVNIv4i32:
1748 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1749 break;
1750 case AArch64::MOVIv2s_msl:
1751 case AArch64::MOVIv4s_msl:
1752 case AArch64::MVNIv2s_msl:
1753 case AArch64::MVNIv4s_msl:
1754 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1755 break;
1756 }
1757
1758 return Success;
1759}
1760
1761static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1762 uint64_t Addr,
1763 const MCDisassembler *Decoder) {
1764 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1765 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1766 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1767 imm |= fieldFromInstruction(insn, 5, 5);
1768
1769 // Tied operands added twice.
1770 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1771 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1772
1773 Inst.addOperand(MCOperand::createImm(imm));
1774 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1775
1776 return Success;
1777}
1778
1779static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
1780 uint64_t Addr,
1781 const MCDisassembler *Decoder) {
1782 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1783 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1784 imm |= fieldFromInstruction(insn, 29, 2);
1785
1786 // Sign-extend the 21-bit immediate.
1787 if (imm & (1 << (21 - 1)))
1788 imm |= ~((1LL << 21) - 1);
1789
1790 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1791 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 0, 4))
1792 Inst.addOperand(MCOperand::createImm(imm));
1793
1794 return Success;
1795}
1796
1797static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1798 uint64_t Addr,
1799 const MCDisassembler *Decoder) {
1800 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1801 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1802 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1803 unsigned S = fieldFromInstruction(insn, 29, 1);
1804 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1805
1806 unsigned ShifterVal = (Imm >> 12) & 3;
1807 unsigned ImmVal = Imm & 0xFFF;
1808
1809 if (ShifterVal != 0 && ShifterVal != 1)
1810 return Fail;
1811
1812 if (Datasize) {
1813 if (Rd == 31 && !S)
1814 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1815 else
1816 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1817 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1818 } else {
1819 if (Rd == 31 && !S)
1820 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1821 else
1822 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1823 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1824 }
1825
1826 if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 0, 4))
1827 Inst.addOperand(MCOperand::createImm(ImmVal));
1828 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1829 return Success;
1830}
1831
1832static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
1833 uint64_t Addr,
1834 const MCDisassembler *Decoder) {
1835 int64_t imm = fieldFromInstruction(insn, 0, 26);
1836
1837 // Sign-extend the 26-bit immediate.
1838 if (imm & (1 << (26 - 1)))
1839 imm |= ~((1LL << 26) - 1);
1840
1841 if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 0, 4))
1842 Inst.addOperand(MCOperand::createImm(imm));
1843
1844 return Success;
1845}
1846
1847static bool isInvalidPState(uint64_t Op1, uint64_t Op2) {
1848 return Op1 == 0b000 && (Op2 == 0b000 || // CFINV
1849 Op2 == 0b001 || // XAFlag
1850 Op2 == 0b010); // AXFlag
1851}
1852
1853static DecodeStatus
1854DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1855 const MCDisassembler *Decoder) {
1856 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1857 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1858 uint64_t imm = fieldFromInstruction(insn, 8, 4);
1859 uint64_t pstate_field = (op1 << 3) | op2;
1860
1861 if (isInvalidPState(op1, op2))
1862 return Fail;
1863
1864 Inst.addOperand(MCOperand::createImm(pstate_field));
1865 Inst.addOperand(MCOperand::createImm(imm));
1866
1867 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1868 if (PState &&
1869 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1870 return Success;
1871 return Fail;
1872}
1873
1874static DecodeStatus
1875DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1876 const MCDisassembler *Decoder) {
1877 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1878 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1879 uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1880 uint64_t imm = fieldFromInstruction(insn, 8, 1);
1881 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1882
1883 if (isInvalidPState(op1, op2))
1884 return Fail;
1885
1886 Inst.addOperand(MCOperand::createImm(pstate_field));
1887 Inst.addOperand(MCOperand::createImm(imm));
1888
1889 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1890 if (PState &&
1891 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1892 return Success;
1893 return Fail;
1894}
1895
1896static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
1897 uint64_t Addr,
1898 const MCDisassembler *Decoder) {
1899 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1900 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1901 bit |= fieldFromInstruction(insn, 19, 5);
1902 int64_t dst = fieldFromInstruction(insn, 5, 14);
1903
1904 // Sign-extend 14-bit immediate.
1905 if (dst & (1 << (14 - 1)))
1906 dst |= ~((1LL << 14) - 1);
1907
1908 if (fieldFromInstruction(insn, 31, 1) == 0)
1909 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1910 else
1911 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1912 Inst.addOperand(MCOperand::createImm(bit));
1913 if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 0, 4))
1914 Inst.addOperand(MCOperand::createImm(dst));
1915
1916 return Success;
1917}
1918
1919static DecodeStatus
1920DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID,
1921 unsigned RegNo, uint64_t Addr,
1922 const MCDisassembler *Decoder) {
1923 // Register number must be even (see CASP instruction)
1924 if (RegNo & 0x1)
1925 return Fail;
1926
1927 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1928 Inst.addOperand(MCOperand::createReg(Reg));
1929 return Success;
1930}
1931
1932static DecodeStatus
1933DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1934 const MCDisassembler *Decoder) {
1935 return DecodeGPRSeqPairsClassRegisterClass(Inst,
1936 AArch64::WSeqPairsClassRegClassID,
1937 RegNo, Addr, Decoder);
1938}
1939
1940static DecodeStatus
1941DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1942 const MCDisassembler *Decoder) {
1943 return DecodeGPRSeqPairsClassRegisterClass(Inst,
1944 AArch64::XSeqPairsClassRegClassID,
1945 RegNo, Addr, Decoder);
1946}
1947
1948static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
1949 uint64_t Addr,
1950 const MCDisassembler *Decoder) {
1951 unsigned op1 = fieldFromInstruction(insn, 16, 3);
1952 unsigned CRn = fieldFromInstruction(insn, 12, 4);
1953 unsigned CRm = fieldFromInstruction(insn, 8, 4);
1954 unsigned op2 = fieldFromInstruction(insn, 5, 3);
1955 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1956 if (Rt != 0b11111)
1957 return Fail;
1958
1959 Inst.addOperand(MCOperand::createImm(op1));
1960 Inst.addOperand(MCOperand::createImm(CRn));
1961 Inst.addOperand(MCOperand::createImm(CRm));
1962 Inst.addOperand(MCOperand::createImm(op2));
1963 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1964
1965 return Success;
1966}
1967
1968static DecodeStatus
1969DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1970 const MCDisassembler *Decoder) {
1971 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1972 unsigned imm = fieldFromInstruction(insn, 5, 13);
1973 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1974 return Fail;
1975
1976 // The same (tied) operand is added twice to the instruction.
1977 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1978 if (Inst.getOpcode() != AArch64::DUPM_ZI)
1979 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1980 Inst.addOperand(MCOperand::createImm(imm));
1981 return Success;
1982}
1983
1984template <int Bits>
1985static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
1986 const MCDisassembler *Decoder) {
1987 if (Imm & ~((1LL << Bits) - 1))
1988 return Fail;
1989
1990 // Imm is a signed immediate, so sign extend it.
1991 if (Imm & (1 << (Bits - 1)))
1992 Imm |= ~((1LL << Bits) - 1);
1993
1994 Inst.addOperand(MCOperand::createImm(Imm));
1995 return Success;
1996}
1997
1998// Decode 8-bit signed/unsigned immediate for a given element width.
1999template <int ElementWidth>
2000static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
2001 const MCDisassembler *Decoder) {
2002 unsigned Val = (uint8_t)Imm;
2003 unsigned Shift = (Imm & 0x100) ? 8 : 0;
2004 if (ElementWidth == 8 && Shift)
2005 return Fail;
2006 Inst.addOperand(MCOperand::createImm(Val));
2007 Inst.addOperand(MCOperand::createImm(Shift));
2008 return Success;
2009}
2010
2011// Decode uimm4 ranged from 1-16.
2012static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
2013 uint64_t Addr,
2014 const MCDisassembler *Decoder) {
2015 Inst.addOperand(MCOperand::createImm(Imm + 1));
2016 return Success;
2017}
2018
2019static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
2020 const MCDisassembler *Decoder) {
2021 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
2022 Inst.addOperand(MCOperand::createImm(Imm));
2023 return Success;
2024 }
2025 return Fail;
2026}
2027
2028static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
2029 uint64_t Addr,
2030 const MCDisassembler *Decoder) {
2031 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2032 unsigned Rs = fieldFromInstruction(insn, 16, 5);
2033 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2034
2035 // None of the registers may alias: if they do, then the instruction is not
2036 // merely unpredictable but actually entirely unallocated.
2037 if (Rd == Rs || Rs == Rn || Rd == Rn)
2038 return MCDisassembler::Fail;
2039
2040 // All three register operands are written back, so they all appear
2041 // twice in the operand list, once as outputs and once as inputs.
2042 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2043 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
2044 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2045 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2046 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
2047 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder))
2048 return MCDisassembler::Fail;
2049
2050 return MCDisassembler::Success;
2051}
2052
2053static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
2054 uint64_t Addr,
2055 const MCDisassembler *Decoder) {
2056 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2057 unsigned Rm = fieldFromInstruction(insn, 16, 5);
2058 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2059
2060 // None of the registers may alias: if they do, then the instruction is not
2061 // merely unpredictable but actually entirely unallocated.
2062 if (Rd == Rm || Rm == Rn || Rd == Rn)
2063 return MCDisassembler::Fail;
2064
2065 // Rd and Rn (not Rm) register operands are written back, so they appear
2066 // twice in the operand list, once as outputs and once as inputs.
2067 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2068 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2069 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2070 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2071 !DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder))
2072 return MCDisassembler::Fail;
2073
2074 return MCDisassembler::Success;
2075}
2076
2077static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
2078 uint64_t Addr,
2079 const MCDisassembler *Decoder) {
2080 // PRFM with Rt = '11xxx' should be decoded as RPRFM.
2081 // Fail to decode and defer to fallback decoder table to decode RPRFM.
2082 unsigned Mask = 0x18;
2083 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
2084 if ((Rt & Mask) == Mask)
2085 return Fail;
2086
2087 uint64_t Rn = fieldFromInstruction(insn, 5, 5);
2088 uint64_t Shift = fieldFromInstruction(insn, 12, 1);
2089 uint64_t Extend = fieldFromInstruction(insn, 15, 1);
2090 uint64_t Rm = fieldFromInstruction(insn, 16, 5);
2091
2092 Inst.addOperand(MCOperand::createImm(Rt));
2093 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
2094
2095 switch (Inst.getOpcode()) {
2096 default:
2097 return Fail;
2098 case AArch64::PRFMroW:
2099 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
2100 break;
2101 case AArch64::PRFMroX:
2102 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
2103 break;
2104 }
2105
2106 DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder);
2107
2108 return Success;
2109}
DecodePPRRegisterClass
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:741
DecodeUnconditionalBranch
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1832
DecodeVecShiftL64Imm
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1008
DecodeVecShiftL32Imm
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1014
createAArch64ExternalSymbolizer
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition: AArch64Disassembler.cpp:391
DecodeCPYMemOpInstruction
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2028
DecodeVecShiftR8Imm
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1002
DecodeQQQQRegisterClass
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:830
DecodeFixedPointScaleImm64
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:883
DecodeGPR32spRegisterClass
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:589
DecodePNRRegisterClass
static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:753
DecodeFPR8RegisterClass
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:487
DecodeZPR4RegisterClass
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:651
DecodeFPR128_loRegisterClass
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:436
DecodeQQRegisterClass
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:808
DecodeZPR3RegisterClass
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:640
DecodeAddSubERegInstruction
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1634
DecodeModImmInstruction
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1722
DecodeDDDRegisterClass
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:852
DecodeLogicalImmInstruction
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1691
DecodeMoveImmInstruction
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1094
DecodeSystemPStateImm0_1Instruction
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1875
DecodeDDRegisterClass
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:841
createAArch64Disassembler
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: AArch64Disassembler.cpp:310
DecodeGPR64x8ClassRegisterClass
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:525
DecodeUnsignedLdStInstruction
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1128
DecodePPR2RegisterClass
static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:785
MatrixZATileDecoderTable
static const MCPhysReg MatrixZATileDecoderTable[5][16]
Definition: AArch64Disassembler.cpp:718
DecodeXSeqPairsClassRegisterClass
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1941
DecodeGPR64commonRegisterClass
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:500
DecodeMatrixIndexGPR32_12_15RegisterClass
static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:564
DecodeQQQRegisterClass
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:819
DecodeZPR2Mul2RegisterClass
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:662
DecodeZPRRegisterClass
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:601
DecodeAuthLoadInstruction
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1601
DecodeVecShiftL16Imm
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1020
DecodePairLdStInstruction
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1467
DecodeFPR16RegisterClass
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:475
SoftFail
#define SoftFail
Definition: AArch64Disassembler.cpp:308
DecodeMatrixTile
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:730
DecodeSImm
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1985
DecodeVecShiftR32ImmNarrow
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:984
DecodePPR2Mul2RegisterClass
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:797
DecodeSystemPStateImm0_15Instruction
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1854
DecodeDDDDRegisterClass
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:863
DecodeGPR64spRegisterClass
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:539
DecodeVecShiftL8Imm
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1026
DecodeSVEIncDecImm
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2012
DecodeFixedPointScaleImm32
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:874
DecodeFPR128_0to7RegisterClass
static DecodeStatus DecodeFPR128_0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:444
DecodeTestAndBranch
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1896
DecodeSVELogicalImmInstruction
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1969
DecodeVecShiftRImm
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:954
DecodePNR_p8to15RegisterClass
static DecodeStatus DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:776
LLVMInitializeAArch64Disassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
Definition: AArch64Disassembler.cpp:399
DecodeVecShiftR64Imm
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:966
DecodeVecShiftLImm
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:960
DecodeVecShiftR16ImmNarrow
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:996
DecodeGPR32RegisterClass
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:577
DecodePPR_3bRegisterClass
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:765
DecodeSVCROp
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2019
DecodeWSeqPairsClassRegisterClass
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1933
DecodeVecShiftR64ImmNarrow
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:972
DecodeZPR4Mul4RegisterClass
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:673
DecodeAddSubImmShift
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1797
Fail
#define Fail
Definition: AArch64Disassembler.cpp:307
DecodeMSRSystemRegister
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:923
DecodeZPR2StridedRegisterClass
static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:684
Success
#define Success
Definition: AArch64Disassembler.cpp:306
DecodeSETMemOpInstruction
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2053
DecodePCRelLabel19
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:890
DecodeThreeAddrSRegInstruction
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1033
DecodeZPR4StridedRegisterClass
static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:696
DecodeMemExtend
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:905
DecodeZPR_3bRegisterClass
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:621
DecodeMatrixIndexGPR32_8_11RegisterClass
static DecodeStatus DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:551
DecodeSignedLdStInstruction
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1186
DecodeExclusiveLdStInstruction
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1385
DecodeSyspXzrInstruction
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1948
DecodeFMOVLaneInstruction
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:931
DecodeGPR64RegisterClass
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:512
isInvalidPState
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
Definition: AArch64Disassembler.cpp:1847
DecodeMatrixTileListRegisterClass
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:709
DecodeAdrInstruction
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1779
DecodePRFMRegInstruction
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2077
DecodeZPR_4bRegisterClass
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:613
DecodeZPR2RegisterClass
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:629
DecodeVecShiftR16Imm
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:990
DecodeVecShiftR32Imm
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:978
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:463
DecodeImm8OptLsl
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2000
DecodeFPR128RegisterClass
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:423
DecodeGPRSeqPairsClassRegisterClass
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1920
DecodeMRSSystemRegister
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:913
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:451
DecodeModImmTiedInstruction
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1761
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:157
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:112
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RegMask
static constexpr uint32_t RegMask
Definition: aarch32.h:221
Opcode
static constexpr uint32_t Opcode
Definition: aarch32.h:200
llvm::AArch64Disassembler::getInstruction
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
Definition: AArch64Disassembler.cpp:317
llvm::AArch64Disassembler::suggestBytesToSkip
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
Definition: AArch64Disassembler.cpp:382
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:83
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
Definition: MCDisassembler.cpp:28
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:218
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:201
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition: MCDisassembler.h:222
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:107
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:154
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint16_t
uint32_t
uint64_t
LLVMSymbolLookupCallback
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: DisassemblerTypes.h:118
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: DisassemblerTypes.h:48
llvm::AArch64_AM::isValidDecodeLogicalImmediate
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
Definition: AArch64AddressingModes.h:321
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:61
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
llvm::RecurKind::Add
@ Add
Sum of integers.
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition: DWARFExpression.h:66
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition: TargetRegistry.h:1090
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:988
Generated on Wed Dec 6 2023 17:37:20 for LLVM by doxygen 1.9.6