LLVM 17.0.0git
AArch64Disassembler.cpp
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1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "AArch64Disassembler.h"
13#include "AArch64ExternalSymbolizer.h"
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "MCTargetDesc/AArch64MCTargetDesc.h"
16#include "TargetInfo/AArch64TargetInfo.h"
17#include "Utils/AArch64BaseInfo.h"
18#include "llvm-c/Disassembler.h"
19#include "llvm/MC/MCDecoderOps.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstrDesc.h"
23#include "llvm/MC/MCRegisterInfo.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/MC/TargetRegistry.h"
26#include "llvm/Support/Compiler.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/Support/ErrorHandling.h"
29#include <algorithm>
30#include <memory>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "aarch64-disassembler"
35
36// Pull DecodeStatus and its enum values into the global namespace.
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39// Forward declare these because the autogenerated code will reference them.
40// Definitions are further down.
41static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
42 uint64_t Address,
43 const MCDisassembler *Decoder);
44static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
45 uint64_t Address,
46 const MCDisassembler *Decoder);
47static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
48 uint64_t Address,
49 const MCDisassembler *Decoder);
50static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
51 uint64_t Address,
52 const MCDisassembler *Decoder);
53static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
54 uint64_t Address,
55 const MCDisassembler *Decoder);
56static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
57 uint64_t Address,
58 const MCDisassembler *Decoder);
59static DecodeStatus
60DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
61 const MCDisassembler *Decoder);
62static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
63 uint64_t Address,
64 const MCDisassembler *Decoder);
65static DecodeStatus
66DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
67 const MCDisassembler *Decoder);
68static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
69 uint64_t Address,
70 const MCDisassembler *Decoder);
71static DecodeStatus
72DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo,
73 uint64_t Address, const void *Decoder);
74static DecodeStatus
75DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo,
76 uint64_t Address,
77 const MCDisassembler *Decoder);
78static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
79 uint64_t Address,
80 const MCDisassembler *Decoder);
81static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
82 uint64_t Address,
83 const MCDisassembler *Decoder);
84static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
85 uint64_t Address,
86 const MCDisassembler *Decoder);
87static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
88 uint64_t Address,
89 const MCDisassembler *Decoder);
90static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
91 uint64_t Address,
92 const MCDisassembler *Decoder);
93static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
94 uint64_t Address,
95 const MCDisassembler *Decoder);
96static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
97 uint64_t Address,
98 const MCDisassembler *Decoder);
99static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
100 uint64_t Address,
101 const MCDisassembler *Decoder);
102static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
103 uint64_t Address,
104 const MCDisassembler *Decoder);
105static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
106 uint64_t Address,
107 const MCDisassembler *Decoder);
108static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
109 uint64_t Address,
110 const MCDisassembler *Decoder);
111static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
112 uint64_t Address,
113 const MCDisassembler *Decoder);
114static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
115 uint64_t Address,
116 const MCDisassembler *Decoder);
117static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
118 uint64_t Address,
119 const MCDisassembler *Decoder);
120static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
121 uint64_t Address,
122 const void *Decoder);
123static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
124 uint64_t Address,
125 const void *Decoder);
126static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo,
127 uint64_t Address,
128 const void *Decoder);
129static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo,
130 uint64_t Address,
131 const void *Decoder);
132template <unsigned NumBitsForTile>
133static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
134 uint64_t Address,
135 const MCDisassembler *Decoder);
136static DecodeStatus
137DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
138 uint64_t Address,
139 const MCDisassembler *Decoder);
140static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
141 uint64_t Address,
142 const MCDisassembler *Decoder);
143static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
144 uint64_t Address,
145 const MCDisassembler *Decoder);
146static DecodeStatus
147DecodePPR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
148 const MCDisassembler *Decoder);
149static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
150 uint64_t Address,
151 const void *Decoder);
152static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
153 uint64_t Address,
154 const void *Decoder);
155
156static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
157 uint64_t Address,
158 const MCDisassembler *Decoder);
159static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
160 uint64_t Address,
161 const MCDisassembler *Decoder);
162static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
163 uint64_t Address,
164 const MCDisassembler *Decoder);
165static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
166 uint64_t Address,
167 const MCDisassembler *Decoder);
168static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
169 uint64_t Address,
170 const MCDisassembler *Decoder);
171static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
172 uint64_t Address,
173 const MCDisassembler *Decoder);
174static DecodeStatus
175DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
176 const MCDisassembler *Decoder);
177static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
178 uint64_t Address,
179 const MCDisassembler *Decoder);
180static DecodeStatus
181DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
182 const MCDisassembler *Decoder);
183static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
184 uint64_t Address,
185 const MCDisassembler *Decoder);
186static DecodeStatus
187DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
188 const MCDisassembler *Decoder);
189static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
190 uint64_t Address,
191 const MCDisassembler *Decoder);
192static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
193 uint64_t Address,
194 const MCDisassembler *Decoder);
195static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
196 uint64_t Address,
197 const MCDisassembler *Decoder);
198static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
199 uint64_t Address,
200 const MCDisassembler *Decoder);
201static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
202 uint64_t Address,
203 const MCDisassembler *Decoder);
204static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
205 uint64_t Address,
206 const MCDisassembler *Decoder);
207static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
208 uint64_t Address,
209 const MCDisassembler *Decoder);
210static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
211 uint64_t Address,
212 const MCDisassembler *Decoder);
213static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
214 uint64_t Address,
215 const MCDisassembler *Decoder);
216static DecodeStatus
217DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn,
218 uint64_t Address,
219 const MCDisassembler *Decoder);
220static DecodeStatus
221DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn,
222 uint64_t Address,
223 const MCDisassembler *Decoder);
224static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
225 uint64_t Address,
226 const MCDisassembler *Decoder);
227
228static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
229 uint64_t Address,
230 const MCDisassembler *Decoder);
231static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
232 uint64_t Addr,
233 const MCDisassembler *Decoder);
234static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
235 uint64_t Addr,
236 const MCDisassembler *Decoder);
237static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
238 uint64_t Addr,
239 const MCDisassembler *Decoder);
240static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
241 uint64_t Addr,
242 const MCDisassembler *Decoder);
243static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
244 uint64_t Addr,
245 const MCDisassembler *Decoder);
246static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
247 uint64_t Addr,
248 const MCDisassembler *Decoder);
249static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
250 uint64_t Addr,
251 const MCDisassembler *Decoder);
252static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
253 uint64_t Addr,
254 const MCDisassembler *Decoder);
255static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
256 uint64_t Addr,
257 const MCDisassembler *Decoder);
258static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
259 uint64_t Addr,
260 const MCDisassembler *Decoder);
261static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
262 uint64_t Addr,
263 const MCDisassembler *Decoder);
264static DecodeStatus
265DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
266 const MCDisassembler *Decoder);
267static DecodeStatus
268DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
269 const MCDisassembler *Decoder);
270static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
271 uint64_t Addr,
272 const MCDisassembler *Decoder);
273static DecodeStatus
274DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
275 const MCDisassembler *Decoder);
276template <int Bits>
277static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
278 const MCDisassembler *Decoder);
279template <int ElementWidth>
280static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
281 const MCDisassembler *Decoder);
282static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
283 uint64_t Addr,
284 const MCDisassembler *Decoder);
285static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
286 const MCDisassembler *Decoder);
287static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
288 uint64_t Addr,
289 const MCDisassembler *Decoder);
290static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
291 uint64_t Addr,
292 const MCDisassembler *Decoder);
293static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
294 uint64_t Address,
295 const MCDisassembler *Decoder);
296
297#include "AArch64GenDisassemblerTables.inc"
298#include "AArch64GenInstrInfo.inc"
299
300#define Success MCDisassembler::Success
301#define Fail MCDisassembler::Fail
302#define SoftFail MCDisassembler::SoftFail
303
304static MCDisassembler *createAArch64Disassembler(const Target &T,
305 const MCSubtargetInfo &STI,
306 MCContext &Ctx) {
307
308 return new AArch64Disassembler(STI, Ctx, T.createMCInstrInfo());
309}
310
311DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
312 ArrayRef<uint8_t> Bytes,
313 uint64_t Address,
314 raw_ostream &CS) const {
315 CommentStream = &CS;
316
317 Size = 0;
318 // We want to read exactly 4 bytes of data.
319 if (Bytes.size() < 4)
320 return Fail;
321 Size = 4;
322
323 // Encoded as a small-endian 32-bit word in the stream.
324 uint32_t Insn =
325 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
326
327 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
328
329 for (const auto *Table : Tables) {
330 DecodeStatus Result =
331 decodeInstruction(Table, MI, Insn, Address, this, STI);
332
333 const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
334
335 // For Scalable Matrix Extension (SME) instructions that have an implicit
336 // operand for the accumulator (ZA) or implicit immediate zero which isn't
337 // encoded, manually insert operand.
338 for (unsigned i = 0; i < Desc.getNumOperands(); i++) {
339 if (Desc.operands()[i].OperandType == MCOI::OPERAND_REGISTER) {
340 switch (Desc.operands()[i].RegClass) {
341 default:
342 break;
343 case AArch64::MPRRegClassID:
344 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA));
345 break;
346 case AArch64::MPR8RegClassID:
347 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0));
348 break;
349 case AArch64::ZTRRegClassID:
350 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0));
351 break;
352 }
353 } else if (Desc.operands()[i].OperandType ==
354 AArch64::OPERAND_IMPLICIT_IMM_0) {
355 MI.insert(MI.begin() + i, MCOperand::createImm(0));
356 }
357 }
358
359 if (MI.getOpcode() == AArch64::LDR_ZA ||
360 MI.getOpcode() == AArch64::STR_ZA) {
361 // Spill and fill instructions have a single immediate used for both
362 // the vector select offset and optional memory offset. Replicate
363 // the decoded immediate.
364 const MCOperand &Imm4Op = MI.getOperand(2);
365 assert(Imm4Op.isImm() && "Unexpected operand type!");
366 MI.addOperand(Imm4Op);
367 }
368
369 if (Result != MCDisassembler::Fail)
370 return Result;
371 }
372
373 return MCDisassembler::Fail;
374}
375
376uint64_t AArch64Disassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
377 uint64_t Address) const {
378 // AArch64 instructions are always 4 bytes wide, so there's no point
379 // in skipping any smaller number of bytes if an instruction can't
380 // be decoded.
381 return 4;
382}
383
384static MCSymbolizer *
385createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
386 LLVMSymbolLookupCallback SymbolLookUp,
387 void *DisInfo, MCContext *Ctx,
388 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
389 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
390 SymbolLookUp, DisInfo);
391}
392
393extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() {
394 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
395 createAArch64Disassembler);
396 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
397 createAArch64Disassembler);
398 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
399 createAArch64ExternalSymbolizer);
400 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
401 createAArch64ExternalSymbolizer);
402 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(),
403 createAArch64Disassembler);
404 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(),
405 createAArch64ExternalSymbolizer);
406
407 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
408 createAArch64Disassembler);
409 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
410 createAArch64ExternalSymbolizer);
411 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
412 createAArch64Disassembler);
413 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
414 createAArch64ExternalSymbolizer);
415}
416
417static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
418 uint64_t Addr,
419 const MCDisassembler *Decoder) {
420 if (RegNo > 31)
421 return Fail;
422
423 unsigned Register =
424 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
425 Inst.addOperand(MCOperand::createReg(Register));
426 return Success;
427}
428
429static DecodeStatus
430DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
431 const MCDisassembler *Decoder) {
432 if (RegNo > 15)
433 return Fail;
434 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
435}
436
437static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
438 uint64_t Addr,
439 const MCDisassembler *Decoder) {
440 if (RegNo > 31)
441 return Fail;
442
443 unsigned Register =
444 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
445 Inst.addOperand(MCOperand::createReg(Register));
446 return Success;
447}
448
449static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
450 uint64_t Addr,
451 const MCDisassembler *Decoder) {
452 if (RegNo > 31)
453 return Fail;
454
455 unsigned Register =
456 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
457 Inst.addOperand(MCOperand::createReg(Register));
458 return Success;
459}
460
461static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
462 uint64_t Addr,
463 const MCDisassembler *Decoder) {
464 if (RegNo > 31)
465 return Fail;
466
467 unsigned Register =
468 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
469 Inst.addOperand(MCOperand::createReg(Register));
470 return Success;
471}
472
473static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
474 uint64_t Addr,
475 const MCDisassembler *Decoder) {
476 if (RegNo > 31)
477 return Fail;
478
479 unsigned Register =
480 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
481 Inst.addOperand(MCOperand::createReg(Register));
482 return Success;
483}
484
485static DecodeStatus
486DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
487 const MCDisassembler *Decoder) {
488 if (RegNo > 30)
489 return Fail;
490
491 unsigned Register =
492 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
493 RegNo);
494 Inst.addOperand(MCOperand::createReg(Register));
495 return Success;
496}
497
498static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
499 uint64_t Addr,
500 const MCDisassembler *Decoder) {
501 if (RegNo > 31)
502 return Fail;
503
504 unsigned Register =
505 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
506 Inst.addOperand(MCOperand::createReg(Register));
507 return Success;
508}
509
510static DecodeStatus
511DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
512 const MCDisassembler *Decoder) {
513 if (RegNo > 22)
514 return Fail;
515 if (RegNo & 1)
516 return Fail;
517
518 unsigned Register =
519 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
520 RegNo >> 1);
521 Inst.addOperand(MCOperand::createReg(Register));
522 return Success;
523}
524
525static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
526 uint64_t Addr,
527 const MCDisassembler *Decoder) {
528 if (RegNo > 31)
529 return Fail;
530 unsigned Register =
531 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
532 Inst.addOperand(MCOperand::createReg(Register));
533 return Success;
534}
535
536static DecodeStatus
537DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo,
538 uint64_t Addr, const void *Decoder) {
539 if (RegNo > 3)
540 return Fail;
541
542 unsigned Register =
543 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_8_11RegClassID]
544 .getRegister(RegNo);
545 Inst.addOperand(MCOperand::createReg(Register));
546 return Success;
547}
548
549static DecodeStatus
550DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo,
551 uint64_t Addr,
552 const MCDisassembler *Decoder) {
553 if (RegNo > 3)
554 return Fail;
555
556 unsigned Register =
557 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
558 .getRegister(RegNo);
559 Inst.addOperand(MCOperand::createReg(Register));
560 return Success;
561}
562
563static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
564 uint64_t Addr,
565 const MCDisassembler *Decoder) {
566 if (RegNo > 31)
567 return Fail;
568
569 unsigned Register =
570 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
571 Inst.addOperand(MCOperand::createReg(Register));
572 return Success;
573}
574
575static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
576 uint64_t Addr,
577 const MCDisassembler *Decoder) {
578 if (RegNo > 31)
579 return Fail;
580
581 unsigned Register =
582 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
583 Inst.addOperand(MCOperand::createReg(Register));
584 return Success;
585}
586
587static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
588 uint64_t Address,
589 const MCDisassembler *Decoder) {
590 if (RegNo > 31)
591 return Fail;
592
593 unsigned Register =
594 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
595 Inst.addOperand(MCOperand::createReg(Register));
596 return Success;
597}
598
599static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
600 uint64_t Address,
601 const MCDisassembler *Decoder) {
602 if (RegNo > 15)
603 return Fail;
604 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
605}
606
607static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
608 uint64_t Address,
609 const MCDisassembler *Decoder) {
610 if (RegNo > 7)
611 return Fail;
612 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
613}
614
615static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
616 uint64_t Address,
617 const MCDisassembler *Decoder) {
618 if (RegNo > 31)
619 return Fail;
620 unsigned Register =
621 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
622 Inst.addOperand(MCOperand::createReg(Register));
623 return Success;
624}
625
626static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
627 uint64_t Address,
628 const MCDisassembler *Decoder) {
629 if (RegNo > 31)
630 return Fail;
631 unsigned Register =
632 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
633 Inst.addOperand(MCOperand::createReg(Register));
634 return Success;
635}
636
637static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
638 uint64_t Address,
639 const MCDisassembler *Decoder) {
640 if (RegNo > 31)
641 return Fail;
642 unsigned Register =
643 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
644 Inst.addOperand(MCOperand::createReg(Register));
645 return Success;
646}
647
648static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
649 uint64_t Address,
650 const void *Decoder) {
651 if (RegNo * 2 > 30)
652 return Fail;
653 unsigned Register =
654 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2);
655 Inst.addOperand(MCOperand::createReg(Register));
656 return Success;
657}
658
659static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
660 uint64_t Address,
661 const void *Decoder) {
662 if (RegNo * 4 > 28)
663 return Fail;
664 unsigned Register =
665 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
666 Inst.addOperand(MCOperand::createReg(Register));
667 return Success;
668}
669
670static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo,
671 uint64_t Address,
672 const void *Decoder) {
673 if (RegNo > 15)
674 return Fail;
675 unsigned Register =
676 AArch64MCRegisterClasses[AArch64::ZPR2StridedRegClassID].getRegister(
677 RegNo);
678 Inst.addOperand(MCOperand::createReg(Register));
679 return Success;
680}
681
682static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo,
683 uint64_t Address,
684 const void *Decoder) {
685 if (RegNo > 7)
686 return Fail;
687 unsigned Register =
688 AArch64MCRegisterClasses[AArch64::ZPR4StridedRegClassID].getRegister(
689 RegNo);
690 Inst.addOperand(MCOperand::createReg(Register));
691 return Success;
692}
693
694static DecodeStatus
695DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
696 uint64_t Address,
697 const MCDisassembler *Decoder) {
698 if (RegMask > 0xFF)
699 return Fail;
700 Inst.addOperand(MCOperand::createImm(RegMask));
701 return Success;
702}
703
704static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
705 {AArch64::ZAB0},
706 {AArch64::ZAH0, AArch64::ZAH1},
707 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
708 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4,
709 AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
710 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4,
711 AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9,
712 AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
713 AArch64::ZAQ14, AArch64::ZAQ15}};
714
715template <unsigned NumBitsForTile>
716static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
717 uint64_t Address,
718 const MCDisassembler *Decoder) {
719 unsigned LastReg = (1 << NumBitsForTile) - 1;
720 if (RegNo > LastReg)
721 return Fail;
722 Inst.addOperand(
723 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo]));
724 return Success;
725}
726
727static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
728 uint64_t Addr,
729 const MCDisassembler *Decoder) {
730 if (RegNo > 15)
731 return Fail;
732
733 unsigned Register =
734 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
735 Inst.addOperand(MCOperand::createReg(Register));
736 return Success;
737}
738
739static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
740 uint64_t Addr,
741 const MCDisassembler *Decoder) {
742 if (RegNo > 7)
743 return Fail;
744
745 // Just reuse the PPR decode table
746 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
747}
748
749static DecodeStatus
750DecodePPR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
751 const MCDisassembler *Decoder) {
752 if (RegNo > 7)
753 return Fail;
754
755 // Just reuse the PPR decode table
756 return DecodePPRRegisterClass(Inst, RegNo + 8, Addr, Decoder);
757}
758
759static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
760 uint64_t Address,
761 const void *Decoder) {
762 if (RegNo > 15)
763 return Fail;
764
765 unsigned Register =
766 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo);
767 Inst.addOperand(MCOperand::createReg(Register));
768 return Success;
769}
770
771static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
772 uint64_t Address,
773 const void *Decoder) {
774 if ((RegNo * 2) > 14)
775 return Fail;
776 unsigned Register =
777 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
778 Inst.addOperand(MCOperand::createReg(Register));
779 return Success;
780}
781
782static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
783 uint64_t Addr,
784 const MCDisassembler *Decoder) {
785 if (RegNo > 31)
786 return Fail;
787 unsigned Register =
788 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
789 Inst.addOperand(MCOperand::createReg(Register));
790 return Success;
791}
792
793static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
794 uint64_t Addr,
795 const MCDisassembler *Decoder) {
796 if (RegNo > 31)
797 return Fail;
798 unsigned Register =
799 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
800 Inst.addOperand(MCOperand::createReg(Register));
801 return Success;
802}
803
804static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
805 uint64_t Addr,
806 const MCDisassembler *Decoder) {
807 if (RegNo > 31)
808 return Fail;
809 unsigned Register =
810 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
811 Inst.addOperand(MCOperand::createReg(Register));
812 return Success;
813}
814
815static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
816 uint64_t Addr,
817 const MCDisassembler *Decoder) {
818 if (RegNo > 31)
819 return Fail;
820 unsigned Register =
821 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
822 Inst.addOperand(MCOperand::createReg(Register));
823 return Success;
824}
825
826static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
827 uint64_t Addr,
828 const MCDisassembler *Decoder) {
829 if (RegNo > 31)
830 return Fail;
831 unsigned Register =
832 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
833 Inst.addOperand(MCOperand::createReg(Register));
834 return Success;
835}
836
837static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
838 uint64_t Addr,
839 const MCDisassembler *Decoder) {
840 if (RegNo > 31)
841 return Fail;
842 unsigned Register =
843 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
844 Inst.addOperand(MCOperand::createReg(Register));
845 return Success;
846}
847
848static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
849 uint64_t Addr,
850 const MCDisassembler *Decoder) {
851 // scale{5} is asserted as 1 in tblgen.
852 Imm |= 0x20;
853 Inst.addOperand(MCOperand::createImm(64 - Imm));
854 return Success;
855}
856
857static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
858 uint64_t Addr,
859 const MCDisassembler *Decoder) {
860 Inst.addOperand(MCOperand::createImm(64 - Imm));
861 return Success;
862}
863
864static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
865 uint64_t Addr,
866 const MCDisassembler *Decoder) {
867 int64_t ImmVal = Imm;
868
869 // Sign-extend 19-bit immediate.
870 if (ImmVal & (1 << (19 - 1)))
871 ImmVal |= ~((1LL << 19) - 1);
872
873 if (!Decoder->tryAddingSymbolicOperand(
874 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4))
875 Inst.addOperand(MCOperand::createImm(ImmVal));
876 return Success;
877}
878
879static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
880 uint64_t Address,
881 const MCDisassembler *Decoder) {
882 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
883 Inst.addOperand(MCOperand::createImm(Imm & 1));
884 return Success;
885}
886
887static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
888 uint64_t Address,
889 const MCDisassembler *Decoder) {
890 Inst.addOperand(MCOperand::createImm(Imm));
891
892 // Every system register in the encoding space is valid with the syntax
893 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
894 return Success;
895}
896
897static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
898 uint64_t Address,
899 const MCDisassembler *Decoder) {
900 Inst.addOperand(MCOperand::createImm(Imm));
901
902 return Success;
903}
904
905static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
906 uint64_t Address,
907 const MCDisassembler *Decoder) {
908 // This decoder exists to add the dummy Lane operand to the MCInst, which must
909 // be 1 in assembly but has no other real manifestation.
910 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
911 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
912 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
913
914 if (IsToVec) {
915 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
916 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
917 } else {
918 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
919 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
920 }
921
922 // Add the lane
923 Inst.addOperand(MCOperand::createImm(1));
924
925 return Success;
926}
927
928static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
929 unsigned Add) {
930 Inst.addOperand(MCOperand::createImm(Add - Imm));
931 return Success;
932}
933
934static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
935 unsigned Add) {
936 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
937 return Success;
938}
939
940static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
941 uint64_t Addr,
942 const MCDisassembler *Decoder) {
943 return DecodeVecShiftRImm(Inst, Imm, 64);
944}
945
946static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
947 uint64_t Addr,
948 const MCDisassembler *Decoder) {
949 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
950}
951
952static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
953 uint64_t Addr,
954 const MCDisassembler *Decoder) {
955 return DecodeVecShiftRImm(Inst, Imm, 32);
956}
957
958static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
959 uint64_t Addr,
960 const MCDisassembler *Decoder) {
961 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
962}
963
964static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
965 uint64_t Addr,
966 const MCDisassembler *Decoder) {
967 return DecodeVecShiftRImm(Inst, Imm, 16);
968}
969
970static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
971 uint64_t Addr,
972 const MCDisassembler *Decoder) {
973 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
974}
975
976static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
977 uint64_t Addr,
978 const MCDisassembler *Decoder) {
979 return DecodeVecShiftRImm(Inst, Imm, 8);
980}
981
982static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
983 uint64_t Addr,
984 const MCDisassembler *Decoder) {
985 return DecodeVecShiftLImm(Inst, Imm, 64);
986}
987
988static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
989 uint64_t Addr,
990 const MCDisassembler *Decoder) {
991 return DecodeVecShiftLImm(Inst, Imm, 32);
992}
993
994static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
995 uint64_t Addr,
996 const MCDisassembler *Decoder) {
997 return DecodeVecShiftLImm(Inst, Imm, 16);
998}
999
1000static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
1001 uint64_t Addr,
1002 const MCDisassembler *Decoder) {
1003 return DecodeVecShiftLImm(Inst, Imm, 8);
1004}
1005
1006static DecodeStatus
1007DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1008 const MCDisassembler *Decoder) {
1009 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1010 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1011 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1012 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
1013 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
1014 unsigned shift = (shiftHi << 6) | shiftLo;
1015 switch (Inst.getOpcode()) {
1016 default:
1017 return Fail;
1018 case AArch64::ADDWrs:
1019 case AArch64::ADDSWrs:
1020 case AArch64::SUBWrs:
1021 case AArch64::SUBSWrs:
1022 // if shift == '11' then ReservedValue()
1023 if (shiftHi == 0x3)
1024 return Fail;
1025 [[fallthrough]];
1026 case AArch64::ANDWrs:
1027 case AArch64::ANDSWrs:
1028 case AArch64::BICWrs:
1029 case AArch64::BICSWrs:
1030 case AArch64::ORRWrs:
1031 case AArch64::ORNWrs:
1032 case AArch64::EORWrs:
1033 case AArch64::EONWrs: {
1034 // if sf == '0' and imm6<5> == '1' then ReservedValue()
1035 if (shiftLo >> 5 == 1)
1036 return Fail;
1037 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1038 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1039 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1040 break;
1041 }
1042 case AArch64::ADDXrs:
1043 case AArch64::ADDSXrs:
1044 case AArch64::SUBXrs:
1045 case AArch64::SUBSXrs:
1046 // if shift == '11' then ReservedValue()
1047 if (shiftHi == 0x3)
1048 return Fail;
1049 [[fallthrough]];
1050 case AArch64::ANDXrs:
1051 case AArch64::ANDSXrs:
1052 case AArch64::BICXrs:
1053 case AArch64::BICSXrs:
1054 case AArch64::ORRXrs:
1055 case AArch64::ORNXrs:
1056 case AArch64::EORXrs:
1057 case AArch64::EONXrs:
1058 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1059 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1060 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1061 break;
1062 }
1063
1064 Inst.addOperand(MCOperand::createImm(shift));
1065 return Success;
1066}
1067
1068static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
1069 uint64_t Addr,
1070 const MCDisassembler *Decoder) {
1071 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1072 unsigned imm = fieldFromInstruction(insn, 5, 16);
1073 unsigned shift = fieldFromInstruction(insn, 21, 2);
1074 shift <<= 4;
1075 switch (Inst.getOpcode()) {
1076 default:
1077 return Fail;
1078 case AArch64::MOVZWi:
1079 case AArch64::MOVNWi:
1080 case AArch64::MOVKWi:
1081 if (shift & (1U << 5))
1082 return Fail;
1083 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1084 break;
1085 case AArch64::MOVZXi:
1086 case AArch64::MOVNXi:
1087 case AArch64::MOVKXi:
1088 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1089 break;
1090 }
1091
1092 if (Inst.getOpcode() == AArch64::MOVKWi ||
1093 Inst.getOpcode() == AArch64::MOVKXi)
1094 Inst.addOperand(Inst.getOperand(0));
1095
1096 Inst.addOperand(MCOperand::createImm(imm));
1097 Inst.addOperand(MCOperand::createImm(shift));
1098 return Success;
1099}
1100
1101static DecodeStatus
1102DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1103 const MCDisassembler *Decoder) {
1104 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1105 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1106 unsigned offset = fieldFromInstruction(insn, 10, 12);
1107
1108 switch (Inst.getOpcode()) {
1109 default:
1110 return Fail;
1111 case AArch64::PRFMui:
1112 // Rt is an immediate in prefetch.
1113 Inst.addOperand(MCOperand::createImm(Rt));
1114 break;
1115 case AArch64::STRBBui:
1116 case AArch64::LDRBBui:
1117 case AArch64::LDRSBWui:
1118 case AArch64::STRHHui:
1119 case AArch64::LDRHHui:
1120 case AArch64::LDRSHWui:
1121 case AArch64::STRWui:
1122 case AArch64::LDRWui:
1123 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1124 break;
1125 case AArch64::LDRSBXui:
1126 case AArch64::LDRSHXui:
1127 case AArch64::LDRSWui:
1128 case AArch64::STRXui:
1129 case AArch64::LDRXui:
1130 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1131 break;
1132 case AArch64::LDRQui:
1133 case AArch64::STRQui:
1134 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1135 break;
1136 case AArch64::LDRDui:
1137 case AArch64::STRDui:
1138 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1139 break;
1140 case AArch64::LDRSui:
1141 case AArch64::STRSui:
1142 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1143 break;
1144 case AArch64::LDRHui:
1145 case AArch64::STRHui:
1146 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1147 break;
1148 case AArch64::LDRBui:
1149 case AArch64::STRBui:
1150 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1151 break;
1152 }
1153
1154 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1155 if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 0, 4))
1156 Inst.addOperand(MCOperand::createImm(offset));
1157 return Success;
1158}
1159
1160static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1161 uint64_t Addr,
1162 const MCDisassembler *Decoder) {
1163 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1164 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1165 int64_t offset = fieldFromInstruction(insn, 12, 9);
1166
1167 // offset is a 9-bit signed immediate, so sign extend it to
1168 // fill the unsigned.
1169 if (offset & (1 << (9 - 1)))
1170 offset |= ~((1LL << 9) - 1);
1171
1172 // First operand is always the writeback to the address register, if needed.
1173 switch (Inst.getOpcode()) {
1174 default:
1175 break;
1176 case AArch64::LDRSBWpre:
1177 case AArch64::LDRSHWpre:
1178 case AArch64::STRBBpre:
1179 case AArch64::LDRBBpre:
1180 case AArch64::STRHHpre:
1181 case AArch64::LDRHHpre:
1182 case AArch64::STRWpre:
1183 case AArch64::LDRWpre:
1184 case AArch64::LDRSBWpost:
1185 case AArch64::LDRSHWpost:
1186 case AArch64::STRBBpost:
1187 case AArch64::LDRBBpost:
1188 case AArch64::STRHHpost:
1189 case AArch64::LDRHHpost:
1190 case AArch64::STRWpost:
1191 case AArch64::LDRWpost:
1192 case AArch64::LDRSBXpre:
1193 case AArch64::LDRSHXpre:
1194 case AArch64::STRXpre:
1195 case AArch64::LDRSWpre:
1196 case AArch64::LDRXpre:
1197 case AArch64::LDRSBXpost:
1198 case AArch64::LDRSHXpost:
1199 case AArch64::STRXpost:
1200 case AArch64::LDRSWpost:
1201 case AArch64::LDRXpost:
1202 case AArch64::LDRQpre:
1203 case AArch64::STRQpre:
1204 case AArch64::LDRQpost:
1205 case AArch64::STRQpost:
1206 case AArch64::LDRDpre:
1207 case AArch64::STRDpre:
1208 case AArch64::LDRDpost:
1209 case AArch64::STRDpost:
1210 case AArch64::LDRSpre:
1211 case AArch64::STRSpre:
1212 case AArch64::LDRSpost:
1213 case AArch64::STRSpost:
1214 case AArch64::LDRHpre:
1215 case AArch64::STRHpre:
1216 case AArch64::LDRHpost:
1217 case AArch64::STRHpost:
1218 case AArch64::LDRBpre:
1219 case AArch64::STRBpre:
1220 case AArch64::LDRBpost:
1221 case AArch64::STRBpost:
1222 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1223 break;
1224 }
1225
1226 switch (Inst.getOpcode()) {
1227 default:
1228 return Fail;
1229 case AArch64::PRFUMi:
1230 // Rt is an immediate in prefetch.
1231 Inst.addOperand(MCOperand::createImm(Rt));
1232 break;
1233 case AArch64::STURBBi:
1234 case AArch64::LDURBBi:
1235 case AArch64::LDURSBWi:
1236 case AArch64::STURHHi:
1237 case AArch64::LDURHHi:
1238 case AArch64::LDURSHWi:
1239 case AArch64::STURWi:
1240 case AArch64::LDURWi:
1241 case AArch64::LDTRSBWi:
1242 case AArch64::LDTRSHWi:
1243 case AArch64::STTRWi:
1244 case AArch64::LDTRWi:
1245 case AArch64::STTRHi:
1246 case AArch64::LDTRHi:
1247 case AArch64::LDTRBi:
1248 case AArch64::STTRBi:
1249 case AArch64::LDRSBWpre:
1250 case AArch64::LDRSHWpre:
1251 case AArch64::STRBBpre:
1252 case AArch64::LDRBBpre:
1253 case AArch64::STRHHpre:
1254 case AArch64::LDRHHpre:
1255 case AArch64::STRWpre:
1256 case AArch64::LDRWpre:
1257 case AArch64::LDRSBWpost:
1258 case AArch64::LDRSHWpost:
1259 case AArch64::STRBBpost:
1260 case AArch64::LDRBBpost:
1261 case AArch64::STRHHpost:
1262 case AArch64::LDRHHpost:
1263 case AArch64::STRWpost:
1264 case AArch64::LDRWpost:
1265 case AArch64::STLURBi:
1266 case AArch64::STLURHi:
1267 case AArch64::STLURWi:
1268 case AArch64::LDAPURBi:
1269 case AArch64::LDAPURSBWi:
1270 case AArch64::LDAPURHi:
1271 case AArch64::LDAPURSHWi:
1272 case AArch64::LDAPURi:
1273 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1274 break;
1275 case AArch64::LDURSBXi:
1276 case AArch64::LDURSHXi:
1277 case AArch64::LDURSWi:
1278 case AArch64::STURXi:
1279 case AArch64::LDURXi:
1280 case AArch64::LDTRSBXi:
1281 case AArch64::LDTRSHXi:
1282 case AArch64::LDTRSWi:
1283 case AArch64::STTRXi:
1284 case AArch64::LDTRXi:
1285 case AArch64::LDRSBXpre:
1286 case AArch64::LDRSHXpre:
1287 case AArch64::STRXpre:
1288 case AArch64::LDRSWpre:
1289 case AArch64::LDRXpre:
1290 case AArch64::LDRSBXpost:
1291 case AArch64::LDRSHXpost:
1292 case AArch64::STRXpost:
1293 case AArch64::LDRSWpost:
1294 case AArch64::LDRXpost:
1295 case AArch64::LDAPURSWi:
1296 case AArch64::LDAPURSHXi:
1297 case AArch64::LDAPURSBXi:
1298 case AArch64::STLURXi:
1299 case AArch64::LDAPURXi:
1300 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1301 break;
1302 case AArch64::LDURQi:
1303 case AArch64::STURQi:
1304 case AArch64::LDRQpre:
1305 case AArch64::STRQpre:
1306 case AArch64::LDRQpost:
1307 case AArch64::STRQpost:
1308 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1309 break;
1310 case AArch64::LDURDi:
1311 case AArch64::STURDi:
1312 case AArch64::LDRDpre:
1313 case AArch64::STRDpre:
1314 case AArch64::LDRDpost:
1315 case AArch64::STRDpost:
1316 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1317 break;
1318 case AArch64::LDURSi:
1319 case AArch64::STURSi:
1320 case AArch64::LDRSpre:
1321 case AArch64::STRSpre:
1322 case AArch64::LDRSpost:
1323 case AArch64::STRSpost:
1324 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1325 break;
1326 case AArch64::LDURHi:
1327 case AArch64::STURHi:
1328 case AArch64::LDRHpre:
1329 case AArch64::STRHpre:
1330 case AArch64::LDRHpost:
1331 case AArch64::STRHpost:
1332 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1333 break;
1334 case AArch64::LDURBi:
1335 case AArch64::STURBi:
1336 case AArch64::LDRBpre:
1337 case AArch64::STRBpre:
1338 case AArch64::LDRBpost:
1339 case AArch64::STRBpost:
1340 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1341 break;
1342 }
1343
1344 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1345 Inst.addOperand(MCOperand::createImm(offset));
1346
1347 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1348 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1349 bool IsFP = fieldFromInstruction(insn, 26, 1);
1350
1351 // Cannot write back to a transfer register (but xzr != sp).
1352 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1353 return SoftFail;
1354
1355 return Success;
1356}
1357
1358static DecodeStatus
1359DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1360 const MCDisassembler *Decoder) {
1361 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1362 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1363 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1364 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1365
1366 unsigned Opcode = Inst.getOpcode();
1367 switch (Opcode) {
1368 default:
1369 return Fail;
1370 case AArch64::STLXRW:
1371 case AArch64::STLXRB:
1372 case AArch64::STLXRH:
1373 case AArch64::STXRW:
1374 case AArch64::STXRB:
1375 case AArch64::STXRH:
1376 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1377 [[fallthrough]];
1378 case AArch64::LDARW:
1379 case AArch64::LDARB:
1380 case AArch64::LDARH:
1381 case AArch64::LDAXRW:
1382 case AArch64::LDAXRB:
1383 case AArch64::LDAXRH:
1384 case AArch64::LDXRW:
1385 case AArch64::LDXRB:
1386 case AArch64::LDXRH:
1387 case AArch64::STLRW:
1388 case AArch64::STLRB:
1389 case AArch64::STLRH:
1390 case AArch64::STLLRW:
1391 case AArch64::STLLRB:
1392 case AArch64::STLLRH:
1393 case AArch64::LDLARW:
1394 case AArch64::LDLARB:
1395 case AArch64::LDLARH:
1396 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1397 break;
1398 case AArch64::STLXRX:
1399 case AArch64::STXRX:
1400 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1401 [[fallthrough]];
1402 case AArch64::LDARX:
1403 case AArch64::LDAXRX:
1404 case AArch64::LDXRX:
1405 case AArch64::STLRX:
1406 case AArch64::LDLARX:
1407 case AArch64::STLLRX:
1408 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1409 break;
1410 case AArch64::STLXPW:
1411 case AArch64::STXPW:
1412 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1413 [[fallthrough]];
1414 case AArch64::LDAXPW:
1415 case AArch64::LDXPW:
1416 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1417 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1418 break;
1419 case AArch64::STLXPX:
1420 case AArch64::STXPX:
1421 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1422 [[fallthrough]];
1423 case AArch64::LDAXPX:
1424 case AArch64::LDXPX:
1425 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1426 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1427 break;
1428 }
1429
1430 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1431
1432 // You shouldn't load to the same register twice in an instruction...
1433 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1434 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1435 Rt == Rt2)
1436 return SoftFail;
1437
1438 return Success;
1439}
1440
1441static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
1442 uint64_t Addr,
1443 const MCDisassembler *Decoder) {
1444 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1445 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1446 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1447 int64_t offset = fieldFromInstruction(insn, 15, 7);
1448 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1449
1450 // offset is a 7-bit signed immediate, so sign extend it to
1451 // fill the unsigned.
1452 if (offset & (1 << (7 - 1)))
1453 offset |= ~((1LL << 7) - 1);
1454
1455 unsigned Opcode = Inst.getOpcode();
1456 bool NeedsDisjointWritebackTransfer = false;
1457
1458 // First operand is always writeback of base register.
1459 switch (Opcode) {
1460 default:
1461 break;
1462 case AArch64::LDPXpost:
1463 case AArch64::STPXpost:
1464 case AArch64::LDPSWpost:
1465 case AArch64::LDPXpre:
1466 case AArch64::STPXpre:
1467 case AArch64::LDPSWpre:
1468 case AArch64::LDPWpost:
1469 case AArch64::STPWpost:
1470 case AArch64::LDPWpre:
1471 case AArch64::STPWpre:
1472 case AArch64::LDPQpost:
1473 case AArch64::STPQpost:
1474 case AArch64::LDPQpre:
1475 case AArch64::STPQpre:
1476 case AArch64::LDPDpost:
1477 case AArch64::STPDpost:
1478 case AArch64::LDPDpre:
1479 case AArch64::STPDpre:
1480 case AArch64::LDPSpost:
1481 case AArch64::STPSpost:
1482 case AArch64::LDPSpre:
1483 case AArch64::STPSpre:
1484 case AArch64::STGPpre:
1485 case AArch64::STGPpost:
1486 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1487 break;
1488 }
1489
1490 switch (Opcode) {
1491 default:
1492 return Fail;
1493 case AArch64::LDPXpost:
1494 case AArch64::STPXpost:
1495 case AArch64::LDPSWpost:
1496 case AArch64::LDPXpre:
1497 case AArch64::STPXpre:
1498 case AArch64::LDPSWpre:
1499 case AArch64::STGPpre:
1500 case AArch64::STGPpost:
1501 NeedsDisjointWritebackTransfer = true;
1502 [[fallthrough]];
1503 case AArch64::LDNPXi:
1504 case AArch64::STNPXi:
1505 case AArch64::LDPXi:
1506 case AArch64::STPXi:
1507 case AArch64::LDPSWi:
1508 case AArch64::STGPi:
1509 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1510 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1511 break;
1512 case AArch64::LDPWpost:
1513 case AArch64::STPWpost:
1514 case AArch64::LDPWpre:
1515 case AArch64::STPWpre:
1516 NeedsDisjointWritebackTransfer = true;
1517 [[fallthrough]];
1518 case AArch64::LDNPWi:
1519 case AArch64::STNPWi:
1520 case AArch64::LDPWi:
1521 case AArch64::STPWi:
1522 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1523 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1524 break;
1525 case AArch64::LDNPQi:
1526 case AArch64::STNPQi:
1527 case AArch64::LDPQpost:
1528 case AArch64::STPQpost:
1529 case AArch64::LDPQi:
1530 case AArch64::STPQi:
1531 case AArch64::LDPQpre:
1532 case AArch64::STPQpre:
1533 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1534 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1535 break;
1536 case AArch64::LDNPDi:
1537 case AArch64::STNPDi:
1538 case AArch64::LDPDpost:
1539 case AArch64::STPDpost:
1540 case AArch64::LDPDi:
1541 case AArch64::STPDi:
1542 case AArch64::LDPDpre:
1543 case AArch64::STPDpre:
1544 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1545 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1546 break;
1547 case AArch64::LDNPSi:
1548 case AArch64::STNPSi:
1549 case AArch64::LDPSpost:
1550 case AArch64::STPSpost:
1551 case AArch64::LDPSi:
1552 case AArch64::STPSi:
1553 case AArch64::LDPSpre:
1554 case AArch64::STPSpre:
1555 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1556 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1557 break;
1558 }
1559
1560 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1561 Inst.addOperand(MCOperand::createImm(offset));
1562
1563 // You shouldn't load to the same register twice in an instruction...
1564 if (IsLoad && Rt == Rt2)
1565 return SoftFail;
1566
1567 // ... or do any operation that writes-back to a transfer register. But note
1568 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1569 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1570 return SoftFail;
1571
1572 return Success;
1573}
1574
1575static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
1576 uint64_t Addr,
1577 const MCDisassembler *Decoder) {
1578 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1579 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1580 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1581 fieldFromInstruction(insn, 12, 9);
1582 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1583
1584 switch (Inst.getOpcode()) {
1585 default:
1586 return Fail;
1587 case AArch64::LDRAAwriteback:
1588 case AArch64::LDRABwriteback:
1589 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr,
1590 Decoder);
1591 break;
1592 case AArch64::LDRAAindexed:
1593 case AArch64::LDRABindexed:
1594 break;
1595 }
1596
1597 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1598 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1599 DecodeSImm<10>(Inst, offset, Addr, Decoder);
1600
1601 if (writeback && Rt == Rn && Rn != 31) {
1602 return SoftFail;
1603 }
1604
1605 return Success;
1606}
1607
1608static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1609 uint64_t Addr,
1610 const MCDisassembler *Decoder) {
1611 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1612 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1613 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1614 unsigned extend = fieldFromInstruction(insn, 10, 6);
1615
1616 unsigned shift = extend & 0x7;
1617 if (shift > 4)
1618 return Fail;
1619
1620 switch (Inst.getOpcode()) {
1621 default:
1622 return Fail;
1623 case AArch64::ADDWrx:
1624 case AArch64::SUBWrx:
1625 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1626 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1627 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1628 break;
1629 case AArch64::ADDSWrx:
1630 case AArch64::SUBSWrx:
1631 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1632 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1633 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1634 break;
1635 case AArch64::ADDXrx:
1636 case AArch64::SUBXrx:
1637 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1638 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1639 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1640 break;
1641 case AArch64::ADDSXrx:
1642 case AArch64::SUBSXrx:
1643 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1644 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1645 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1646 break;
1647 case AArch64::ADDXrx64:
1648 case AArch64::SUBXrx64:
1649 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1650 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1651 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1652 break;
1653 case AArch64::SUBSXrx64:
1654 case AArch64::ADDSXrx64:
1655 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1656 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1657 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1658 break;
1659 }
1660
1661 Inst.addOperand(MCOperand::createImm(extend));
1662 return Success;
1663}
1664
1665static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1666 uint64_t Addr,
1667 const MCDisassembler *Decoder) {
1668 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1669 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1670 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1671 unsigned imm;
1672
1673 if (Datasize) {
1674 if (Inst.getOpcode() == AArch64::ANDSXri)
1675 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1676 else
1677 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1678 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1679 imm = fieldFromInstruction(insn, 10, 13);
1680 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1681 return Fail;
1682 } else {
1683 if (Inst.getOpcode() == AArch64::ANDSWri)
1684 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1685 else
1686 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1687 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1688 imm = fieldFromInstruction(insn, 10, 12);
1689 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1690 return Fail;
1691 }
1692 Inst.addOperand(MCOperand::createImm(imm));
1693 return Success;
1694}
1695
1696static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
1697 uint64_t Addr,
1698 const MCDisassembler *Decoder) {
1699 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1700 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1701 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1702 imm |= fieldFromInstruction(insn, 5, 5);
1703
1704 if (Inst.getOpcode() == AArch64::MOVID)
1705 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1706 else
1707 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1708
1709 Inst.addOperand(MCOperand::createImm(imm));
1710
1711 switch (Inst.getOpcode()) {
1712 default:
1713 break;
1714 case AArch64::MOVIv4i16:
1715 case AArch64::MOVIv8i16:
1716 case AArch64::MVNIv4i16:
1717 case AArch64::MVNIv8i16:
1718 case AArch64::MOVIv2i32:
1719 case AArch64::MOVIv4i32:
1720 case AArch64::MVNIv2i32:
1721 case AArch64::MVNIv4i32:
1722 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1723 break;
1724 case AArch64::MOVIv2s_msl:
1725 case AArch64::MOVIv4s_msl:
1726 case AArch64::MVNIv2s_msl:
1727 case AArch64::MVNIv4s_msl:
1728 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1729 break;
1730 }
1731
1732 return Success;
1733}
1734
1735static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1736 uint64_t Addr,
1737 const MCDisassembler *Decoder) {
1738 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1739 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1740 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1741 imm |= fieldFromInstruction(insn, 5, 5);
1742
1743 // Tied operands added twice.
1744 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1745 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1746
1747 Inst.addOperand(MCOperand::createImm(imm));
1748 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1749
1750 return Success;
1751}
1752
1753static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
1754 uint64_t Addr,
1755 const MCDisassembler *Decoder) {
1756 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1757 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1758 imm |= fieldFromInstruction(insn, 29, 2);
1759
1760 // Sign-extend the 21-bit immediate.
1761 if (imm & (1 << (21 - 1)))
1762 imm |= ~((1LL << 21) - 1);
1763
1764 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1765 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 0, 4))
1766 Inst.addOperand(MCOperand::createImm(imm));
1767
1768 return Success;
1769}
1770
1771static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1772 uint64_t Addr,
1773 const MCDisassembler *Decoder) {
1774 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1775 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1776 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1777 unsigned S = fieldFromInstruction(insn, 29, 1);
1778 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1779
1780 unsigned ShifterVal = (Imm >> 12) & 3;
1781 unsigned ImmVal = Imm & 0xFFF;
1782
1783 if (ShifterVal != 0 && ShifterVal != 1)
1784 return Fail;
1785
1786 if (Datasize) {
1787 if (Rd == 31 && !S)
1788 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1789 else
1790 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1791 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1792 } else {
1793 if (Rd == 31 && !S)
1794 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1795 else
1796 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1797 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1798 }
1799
1800 if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 0, 4))
1801 Inst.addOperand(MCOperand::createImm(ImmVal));
1802 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1803 return Success;
1804}
1805
1806static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
1807 uint64_t Addr,
1808 const MCDisassembler *Decoder) {
1809 int64_t imm = fieldFromInstruction(insn, 0, 26);
1810
1811 // Sign-extend the 26-bit immediate.
1812 if (imm & (1 << (26 - 1)))
1813 imm |= ~((1LL << 26) - 1);
1814
1815 if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 0, 4))
1816 Inst.addOperand(MCOperand::createImm(imm));
1817
1818 return Success;
1819}
1820
1821static bool isInvalidPState(uint64_t Op1, uint64_t Op2) {
1822 return Op1 == 0b000 && (Op2 == 0b000 || // CFINV
1823 Op2 == 0b001 || // XAFlag
1824 Op2 == 0b010); // AXFlag
1825}
1826
1827static DecodeStatus
1828DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1829 const MCDisassembler *Decoder) {
1830 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1831 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1832 uint64_t imm = fieldFromInstruction(insn, 8, 4);
1833 uint64_t pstate_field = (op1 << 3) | op2;
1834
1835 if (isInvalidPState(op1, op2))
1836 return Fail;
1837
1838 Inst.addOperand(MCOperand::createImm(pstate_field));
1839 Inst.addOperand(MCOperand::createImm(imm));
1840
1841 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1842 if (PState &&
1843 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1844 return Success;
1845 return Fail;
1846}
1847
1848static DecodeStatus
1849DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1850 const MCDisassembler *Decoder) {
1851 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1852 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1853 uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1854 uint64_t imm = fieldFromInstruction(insn, 8, 1);
1855 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1856
1857 if (isInvalidPState(op1, op2))
1858 return Fail;
1859
1860 Inst.addOperand(MCOperand::createImm(pstate_field));
1861 Inst.addOperand(MCOperand::createImm(imm));
1862
1863 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1864 if (PState &&
1865 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1866 return Success;
1867 return Fail;
1868}
1869
1870static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
1871 uint64_t Addr,
1872 const MCDisassembler *Decoder) {
1873 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1874 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1875 bit |= fieldFromInstruction(insn, 19, 5);
1876 int64_t dst = fieldFromInstruction(insn, 5, 14);
1877
1878 // Sign-extend 14-bit immediate.
1879 if (dst & (1 << (14 - 1)))
1880 dst |= ~((1LL << 14) - 1);
1881
1882 if (fieldFromInstruction(insn, 31, 1) == 0)
1883 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1884 else
1885 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1886 Inst.addOperand(MCOperand::createImm(bit));
1887 if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 0, 4))
1888 Inst.addOperand(MCOperand::createImm(dst));
1889
1890 return Success;
1891}
1892
1893static DecodeStatus
1894DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID,
1895 unsigned RegNo, uint64_t Addr,
1896 const MCDisassembler *Decoder) {
1897 // Register number must be even (see CASP instruction)
1898 if (RegNo & 0x1)
1899 return Fail;
1900
1901 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1902 Inst.addOperand(MCOperand::createReg(Reg));
1903 return Success;
1904}
1905
1906static DecodeStatus
1907DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1908 const MCDisassembler *Decoder) {
1909 return DecodeGPRSeqPairsClassRegisterClass(Inst,
1910 AArch64::WSeqPairsClassRegClassID,
1911 RegNo, Addr, Decoder);
1912}
1913
1914static DecodeStatus
1915DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1916 const MCDisassembler *Decoder) {
1917 return DecodeGPRSeqPairsClassRegisterClass(Inst,
1918 AArch64::XSeqPairsClassRegClassID,
1919 RegNo, Addr, Decoder);
1920}
1921
1922static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
1923 uint64_t Addr,
1924 const MCDisassembler *Decoder) {
1925 unsigned op1 = fieldFromInstruction(insn, 16, 3);
1926 unsigned CRn = fieldFromInstruction(insn, 12, 4);
1927 unsigned CRm = fieldFromInstruction(insn, 8, 4);
1928 unsigned op2 = fieldFromInstruction(insn, 5, 3);
1929 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1930 if (Rt != 0b11111)
1931 return Fail;
1932
1933 Inst.addOperand(MCOperand::createImm(op1));
1934 Inst.addOperand(MCOperand::createImm(CRn));
1935 Inst.addOperand(MCOperand::createImm(CRm));
1936 Inst.addOperand(MCOperand::createImm(op2));
1937 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1938
1939 return Success;
1940}
1941
1942static DecodeStatus
1943DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1944 const MCDisassembler *Decoder) {
1945 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1946 unsigned imm = fieldFromInstruction(insn, 5, 13);
1947 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1948 return Fail;
1949
1950 // The same (tied) operand is added twice to the instruction.
1951 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1952 if (Inst.getOpcode() != AArch64::DUPM_ZI)
1953 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1954 Inst.addOperand(MCOperand::createImm(imm));
1955 return Success;
1956}
1957
1958template <int Bits>
1959static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
1960 const MCDisassembler *Decoder) {
1961 if (Imm & ~((1LL << Bits) - 1))
1962 return Fail;
1963
1964 // Imm is a signed immediate, so sign extend it.
1965 if (Imm & (1 << (Bits - 1)))
1966 Imm |= ~((1LL << Bits) - 1);
1967
1968 Inst.addOperand(MCOperand::createImm(Imm));
1969 return Success;
1970}
1971
1972// Decode 8-bit signed/unsigned immediate for a given element width.
1973template <int ElementWidth>
1974static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
1975 const MCDisassembler *Decoder) {
1976 unsigned Val = (uint8_t)Imm;
1977 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1978 if (ElementWidth == 8 && Shift)
1979 return Fail;
1980 Inst.addOperand(MCOperand::createImm(Val));
1981 Inst.addOperand(MCOperand::createImm(Shift));
1982 return Success;
1983}
1984
1985// Decode uimm4 ranged from 1-16.
1986static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1987 uint64_t Addr,
1988 const MCDisassembler *Decoder) {
1989 Inst.addOperand(MCOperand::createImm(Imm + 1));
1990 return Success;
1991}
1992
1993static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
1994 const MCDisassembler *Decoder) {
1995 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
1996 Inst.addOperand(MCOperand::createImm(Imm));
1997 return Success;
1998 }
1999 return Fail;
2000}
2001
2002static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
2003 uint64_t Addr,
2004 const MCDisassembler *Decoder) {
2005 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2006 unsigned Rs = fieldFromInstruction(insn, 16, 5);
2007 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2008
2009 // None of the registers may alias: if they do, then the instruction is not
2010 // merely unpredictable but actually entirely unallocated.
2011 if (Rd == Rs || Rs == Rn || Rd == Rn)
2012 return MCDisassembler::Fail;
2013
2014 // All three register operands are written back, so they all appear
2015 // twice in the operand list, once as outputs and once as inputs.
2016 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2017 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
2018 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2019 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2020 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
2021 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder))
2022 return MCDisassembler::Fail;
2023
2024 return MCDisassembler::Success;
2025}
2026
2027static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
2028 uint64_t Addr,
2029 const MCDisassembler *Decoder) {
2030 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2031 unsigned Rm = fieldFromInstruction(insn, 16, 5);
2032 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2033
2034 // None of the registers may alias: if they do, then the instruction is not
2035 // merely unpredictable but actually entirely unallocated.
2036 if (Rd == Rm || Rm == Rn || Rd == Rn)
2037 return MCDisassembler::Fail;
2038
2039 // Rd and Rn (not Rm) register operands are written back, so they appear
2040 // twice in the operand list, once as outputs and once as inputs.
2041 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2042 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2043 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2044 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2045 !DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder))
2046 return MCDisassembler::Fail;
2047
2048 return MCDisassembler::Success;
2049}
2050
2051static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
2052 uint64_t Addr,
2053 const MCDisassembler *Decoder) {
2054 // PRFM with Rt = '11xxx' should be decoded as RPRFM.
2055 // Fail to decode and defer to fallback decoder table to decode RPRFM.
2056 unsigned Mask = 0x18;
2057 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
2058 if ((Rt & Mask) == Mask)
2059 return Fail;
2060
2061 uint64_t Rn = fieldFromInstruction(insn, 5, 5);
2062 uint64_t Shift = fieldFromInstruction(insn, 12, 1);
2063 uint64_t Extend = fieldFromInstruction(insn, 15, 1);
2064 uint64_t Rm = fieldFromInstruction(insn, 16, 5);
2065
2066 Inst.addOperand(MCOperand::createImm(Rt));
2067 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
2068
2069 switch (Inst.getOpcode()) {
2070 default:
2071 return Fail;
2072 case AArch64::PRFMroW:
2073 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
2074 break;
2075 case AArch64::PRFMroX:
2076 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
2077 break;
2078 }
2079
2080 DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder);
2081
2082 return Success;
2083}
DecodePPRRegisterClass
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:727
DecodeUnconditionalBranch
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1806
DecodeVecShiftL64Imm
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:982
DecodeVecShiftL32Imm
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:988
createAArch64ExternalSymbolizer
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition: AArch64Disassembler.cpp:385
DecodeCPYMemOpInstruction
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2002
DecodeVecShiftR8Imm
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:976
DecodeQQQQRegisterClass
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:804
DecodeFixedPointScaleImm64
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:857
DecodeGPR32spRegisterClass
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:575
DecodeFPR8RegisterClass
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:473
DecodeZPR4RegisterClass
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:637
DecodeFPR128_loRegisterClass
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:430
DecodeQQRegisterClass
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:782
DecodeZPR3RegisterClass
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:626
DecodeAddSubERegInstruction
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1608
DecodeModImmInstruction
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1696
DecodeDDDRegisterClass
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:826
DecodeLogicalImmInstruction
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1665
DecodeMoveImmInstruction
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1068
DecodeSystemPStateImm0_1Instruction
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1849
DecodeDDRegisterClass
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:815
createAArch64Disassembler
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: AArch64Disassembler.cpp:304
DecodeGPR64x8ClassRegisterClass
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:511
DecodeUnsignedLdStInstruction
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1102
DecodePPR2RegisterClass
static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:759
MatrixZATileDecoderTable
static const MCPhysReg MatrixZATileDecoderTable[5][16]
Definition: AArch64Disassembler.cpp:704
DecodeXSeqPairsClassRegisterClass
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1915
DecodeGPR64commonRegisterClass
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:486
DecodeMatrixIndexGPR32_12_15RegisterClass
static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:550
DecodeQQQRegisterClass
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:793
DecodeZPR2Mul2RegisterClass
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:648
DecodeZPRRegisterClass
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:587
DecodeAuthLoadInstruction
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1575
DecodeVecShiftL16Imm
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:994
DecodePairLdStInstruction
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1441
DecodeFPR16RegisterClass
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:461
SoftFail
#define SoftFail
Definition: AArch64Disassembler.cpp:302
DecodeMatrixTile
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:716
DecodeSImm
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1959
DecodeVecShiftR32ImmNarrow
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:958
DecodePPR2Mul2RegisterClass
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:771
DecodeSystemPStateImm0_15Instruction
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1828
DecodeDDDDRegisterClass
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:837
DecodeGPR64spRegisterClass
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:525
DecodeVecShiftL8Imm
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1000
DecodeSVEIncDecImm
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1986
DecodeFixedPointScaleImm32
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:848
DecodeTestAndBranch
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1870
DecodeSVELogicalImmInstruction
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1943
DecodeVecShiftRImm
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:928
DecodePPR_p8to15RegisterClass
static DecodeStatus DecodePPR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:750
LLVMInitializeAArch64Disassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
Definition: AArch64Disassembler.cpp:393
DecodeVecShiftR64Imm
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:940
DecodeVecShiftLImm
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:934
DecodeVecShiftR16ImmNarrow
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:970
DecodeGPR32RegisterClass
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:563
DecodePPR_3bRegisterClass
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:739
DecodeSVCROp
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1993
DecodeWSeqPairsClassRegisterClass
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1907
DecodeVecShiftR64ImmNarrow
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:946
DecodeZPR4Mul4RegisterClass
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:659
DecodeAddSubImmShift
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1771
Fail
#define Fail
Definition: AArch64Disassembler.cpp:301
DecodeMSRSystemRegister
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:897
DecodeZPR2StridedRegisterClass
static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:670
Success
#define Success
Definition: AArch64Disassembler.cpp:300
DecodeSETMemOpInstruction
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2027
DecodePCRelLabel19
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:864
DecodeThreeAddrSRegInstruction
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1007
DecodeZPR4StridedRegisterClass
static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:682
DecodeMemExtend
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:879
DecodeZPR_3bRegisterClass
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:607
DecodeMatrixIndexGPR32_8_11RegisterClass
static DecodeStatus DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:537
DecodeSignedLdStInstruction
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1160
DecodeExclusiveLdStInstruction
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1359
DecodeSyspXzrInstruction
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1922
DecodeFMOVLaneInstruction
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:905
DecodeGPR64RegisterClass
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:498
isInvalidPState
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
Definition: AArch64Disassembler.cpp:1821
DecodeMatrixTileListRegisterClass
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:695
DecodeAdrInstruction
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1753
DecodePRFMRegInstruction
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2051
DecodeZPR_4bRegisterClass
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:599
DecodeZPR2RegisterClass
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:615
DecodeVecShiftR16Imm
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:964
DecodeVecShiftR32Imm
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:952
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:449
DecodeImm8OptLsl
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1974
DecodeFPR128RegisterClass
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:417
DecodeGPRSeqPairsClassRegisterClass
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1894
DecodeMRSSystemRegister
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:887
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:437
DecodeModImmTiedInstruction
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1735
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:157
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AArch64Disassembler::getInstruction
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
Definition: AArch64Disassembler.cpp:311
llvm::AArch64Disassembler::suggestBytesToSkip
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
Definition: AArch64Disassembler.cpp:376
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:79
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
Definition: MCDisassembler.cpp:28
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:214
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:197
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition: MCDisassembler.h:218
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:103
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
llvm::MCInstrDesc::operands
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint16_t
uint32_t
uint64_t
LLVMSymbolLookupCallback
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: DisassemblerTypes.h:118
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: DisassemblerTypes.h:48
llvm::AArch64_AM::isValidDecodeLogicalImmediate
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
Definition: AArch64AddressingModes.h:322
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:61
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
llvm::RecurKind::Add
@ Add
Sum of integers.
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition: TargetRegistry.h:1069
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:971
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