34#define DEBUG_TYPE "aarch64-disassembler"
73 uint64_t Address,
const void *Decoder);
122 const void *Decoder);
125 const void *Decoder);
128 const void *Decoder);
131 const void *Decoder);
132template <
unsigned NumBitsForTile>
151 const void *Decoder);
154 const void *Decoder);
279template <
int ElementW
idth>
297#include "AArch64GenDisassemblerTables.inc"
298#include "AArch64GenInstrInfo.inc"
300#define Success MCDisassembler::Success
301#define Fail MCDisassembler::Fail
302#define SoftFail MCDisassembler::SoftFail
319 if (Bytes.
size() < 4)
325 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
327 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
329 for (
const auto *Table : Tables) {
340 switch (Desc.
operands()[i].RegClass) {
343 case AArch64::MPRRegClassID:
346 case AArch64::MPR8RegClassID:
349 case AArch64::ZTRRegClassID:
353 }
else if (Desc.
operands()[i].OperandType ==
359 if (
MI.getOpcode() == AArch64::LDR_ZA ||
360 MI.getOpcode() == AArch64::STR_ZA) {
365 assert(Imm4Op.
isImm() &&
"Unexpected operand type!");
366 MI.addOperand(Imm4Op);
388 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
390 SymbolLookUp, DisInfo);
424 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
444 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
456 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
468 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
480 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
492 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
505 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
519 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
531 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
543 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_8_11RegClassID]
557 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
570 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
582 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
594 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
621 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
632 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
643 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
650 const void *Decoder) {
654 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2);
661 const void *Decoder) {
665 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
672 const void *Decoder) {
676 AArch64MCRegisterClasses[AArch64::ZPR2StridedRegClassID].getRegister(
684 const void *Decoder) {
688 AArch64MCRegisterClasses[AArch64::ZPR4StridedRegClassID].getRegister(
706 {AArch64::ZAH0, AArch64::ZAH1},
707 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
708 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4,
709 AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
710 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4,
711 AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9,
712 AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
713 AArch64::ZAQ14, AArch64::ZAQ15}};
715template <
unsigned NumBitsForTile>
719 unsigned LastReg = (1 << NumBitsForTile) - 1;
734 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
761 const void *Decoder) {
766 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo);
773 const void *Decoder) {
774 if ((RegNo * 2) > 14)
777 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
788 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
799 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
810 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
821 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
832 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
843 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
867 int64_t ImmVal = Imm;
870 if (ImmVal & (1 << (19 - 1)))
871 ImmVal |= ~((1LL << 19) - 1);
874 Inst, ImmVal * 4,
Addr, Inst.
getOpcode() != AArch64::LDRXl, 0, 0, 4))
910 unsigned Rd = fieldFromInstruction(
Insn, 0, 5);
911 unsigned Rn = fieldFromInstruction(
Insn, 5, 5);
912 unsigned IsToVec = fieldFromInstruction(
Insn, 16, 1);
1009 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1010 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1011 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1012 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
1013 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
1014 unsigned shift = (shiftHi << 6) | shiftLo;
1018 case AArch64::ADDWrs:
1019 case AArch64::ADDSWrs:
1020 case AArch64::SUBWrs:
1021 case AArch64::SUBSWrs:
1026 case AArch64::ANDWrs:
1027 case AArch64::ANDSWrs:
1028 case AArch64::BICWrs:
1029 case AArch64::BICSWrs:
1030 case AArch64::ORRWrs:
1031 case AArch64::ORNWrs:
1032 case AArch64::EORWrs:
1033 case AArch64::EONWrs: {
1035 if (shiftLo >> 5 == 1)
1042 case AArch64::ADDXrs:
1043 case AArch64::ADDSXrs:
1044 case AArch64::SUBXrs:
1045 case AArch64::SUBSXrs:
1050 case AArch64::ANDXrs:
1051 case AArch64::ANDSXrs:
1052 case AArch64::BICXrs:
1053 case AArch64::BICSXrs:
1054 case AArch64::ORRXrs:
1055 case AArch64::ORNXrs:
1056 case AArch64::EORXrs:
1057 case AArch64::EONXrs:
1071 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1072 unsigned imm = fieldFromInstruction(insn, 5, 16);
1073 unsigned shift = fieldFromInstruction(insn, 21, 2);
1078 case AArch64::MOVZWi:
1079 case AArch64::MOVNWi:
1080 case AArch64::MOVKWi:
1081 if (shift & (1U << 5))
1085 case AArch64::MOVZXi:
1086 case AArch64::MOVNXi:
1087 case AArch64::MOVKXi:
1092 if (Inst.
getOpcode() == AArch64::MOVKWi ||
1104 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1105 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1106 unsigned offset = fieldFromInstruction(insn, 10, 12);
1111 case AArch64::PRFMui:
1115 case AArch64::STRBBui:
1116 case AArch64::LDRBBui:
1117 case AArch64::LDRSBWui:
1118 case AArch64::STRHHui:
1119 case AArch64::LDRHHui:
1120 case AArch64::LDRSHWui:
1121 case AArch64::STRWui:
1122 case AArch64::LDRWui:
1125 case AArch64::LDRSBXui:
1126 case AArch64::LDRSHXui:
1127 case AArch64::LDRSWui:
1128 case AArch64::STRXui:
1129 case AArch64::LDRXui:
1132 case AArch64::LDRQui:
1133 case AArch64::STRQui:
1136 case AArch64::LDRDui:
1137 case AArch64::STRDui:
1140 case AArch64::LDRSui:
1141 case AArch64::STRSui:
1144 case AArch64::LDRHui:
1145 case AArch64::STRHui:
1148 case AArch64::LDRBui:
1149 case AArch64::STRBui:
1163 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1164 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1165 int64_t offset = fieldFromInstruction(insn, 12, 9);
1169 if (offset & (1 << (9 - 1)))
1170 offset |= ~((1LL << 9) - 1);
1176 case AArch64::LDRSBWpre:
1177 case AArch64::LDRSHWpre:
1178 case AArch64::STRBBpre:
1179 case AArch64::LDRBBpre:
1180 case AArch64::STRHHpre:
1181 case AArch64::LDRHHpre:
1182 case AArch64::STRWpre:
1183 case AArch64::LDRWpre:
1184 case AArch64::LDRSBWpost:
1185 case AArch64::LDRSHWpost:
1186 case AArch64::STRBBpost:
1187 case AArch64::LDRBBpost:
1188 case AArch64::STRHHpost:
1189 case AArch64::LDRHHpost:
1190 case AArch64::STRWpost:
1191 case AArch64::LDRWpost:
1192 case AArch64::LDRSBXpre:
1193 case AArch64::LDRSHXpre:
1194 case AArch64::STRXpre:
1195 case AArch64::LDRSWpre:
1196 case AArch64::LDRXpre:
1197 case AArch64::LDRSBXpost:
1198 case AArch64::LDRSHXpost:
1199 case AArch64::STRXpost:
1200 case AArch64::LDRSWpost:
1201 case AArch64::LDRXpost:
1202 case AArch64::LDRQpre:
1203 case AArch64::STRQpre:
1204 case AArch64::LDRQpost:
1205 case AArch64::STRQpost:
1206 case AArch64::LDRDpre:
1207 case AArch64::STRDpre:
1208 case AArch64::LDRDpost:
1209 case AArch64::STRDpost:
1210 case AArch64::LDRSpre:
1211 case AArch64::STRSpre:
1212 case AArch64::LDRSpost:
1213 case AArch64::STRSpost:
1214 case AArch64::LDRHpre:
1215 case AArch64::STRHpre:
1216 case AArch64::LDRHpost:
1217 case AArch64::STRHpost:
1218 case AArch64::LDRBpre:
1219 case AArch64::STRBpre:
1220 case AArch64::LDRBpost:
1221 case AArch64::STRBpost:
1229 case AArch64::PRFUMi:
1233 case AArch64::STURBBi:
1234 case AArch64::LDURBBi:
1235 case AArch64::LDURSBWi:
1236 case AArch64::STURHHi:
1237 case AArch64::LDURHHi:
1238 case AArch64::LDURSHWi:
1239 case AArch64::STURWi:
1240 case AArch64::LDURWi:
1241 case AArch64::LDTRSBWi:
1242 case AArch64::LDTRSHWi:
1243 case AArch64::STTRWi:
1244 case AArch64::LDTRWi:
1245 case AArch64::STTRHi:
1246 case AArch64::LDTRHi:
1247 case AArch64::LDTRBi:
1248 case AArch64::STTRBi:
1249 case AArch64::LDRSBWpre:
1250 case AArch64::LDRSHWpre:
1251 case AArch64::STRBBpre:
1252 case AArch64::LDRBBpre:
1253 case AArch64::STRHHpre:
1254 case AArch64::LDRHHpre:
1255 case AArch64::STRWpre:
1256 case AArch64::LDRWpre:
1257 case AArch64::LDRSBWpost:
1258 case AArch64::LDRSHWpost:
1259 case AArch64::STRBBpost:
1260 case AArch64::LDRBBpost:
1261 case AArch64::STRHHpost:
1262 case AArch64::LDRHHpost:
1263 case AArch64::STRWpost:
1264 case AArch64::LDRWpost:
1265 case AArch64::STLURBi:
1266 case AArch64::STLURHi:
1267 case AArch64::STLURWi:
1268 case AArch64::LDAPURBi:
1269 case AArch64::LDAPURSBWi:
1270 case AArch64::LDAPURHi:
1271 case AArch64::LDAPURSHWi:
1272 case AArch64::LDAPURi:
1275 case AArch64::LDURSBXi:
1276 case AArch64::LDURSHXi:
1277 case AArch64::LDURSWi:
1278 case AArch64::STURXi:
1279 case AArch64::LDURXi:
1280 case AArch64::LDTRSBXi:
1281 case AArch64::LDTRSHXi:
1282 case AArch64::LDTRSWi:
1283 case AArch64::STTRXi:
1284 case AArch64::LDTRXi:
1285 case AArch64::LDRSBXpre:
1286 case AArch64::LDRSHXpre:
1287 case AArch64::STRXpre:
1288 case AArch64::LDRSWpre:
1289 case AArch64::LDRXpre:
1290 case AArch64::LDRSBXpost:
1291 case AArch64::LDRSHXpost:
1292 case AArch64::STRXpost:
1293 case AArch64::LDRSWpost:
1294 case AArch64::LDRXpost:
1295 case AArch64::LDAPURSWi:
1296 case AArch64::LDAPURSHXi:
1297 case AArch64::LDAPURSBXi:
1298 case AArch64::STLURXi:
1299 case AArch64::LDAPURXi:
1302 case AArch64::LDURQi:
1303 case AArch64::STURQi:
1304 case AArch64::LDRQpre:
1305 case AArch64::STRQpre:
1306 case AArch64::LDRQpost:
1307 case AArch64::STRQpost:
1310 case AArch64::LDURDi:
1311 case AArch64::STURDi:
1312 case AArch64::LDRDpre:
1313 case AArch64::STRDpre:
1314 case AArch64::LDRDpost:
1315 case AArch64::STRDpost:
1318 case AArch64::LDURSi:
1319 case AArch64::STURSi:
1320 case AArch64::LDRSpre:
1321 case AArch64::STRSpre:
1322 case AArch64::LDRSpost:
1323 case AArch64::STRSpost:
1326 case AArch64::LDURHi:
1327 case AArch64::STURHi:
1328 case AArch64::LDRHpre:
1329 case AArch64::STRHpre:
1330 case AArch64::LDRHpost:
1331 case AArch64::STRHpost:
1334 case AArch64::LDURBi:
1335 case AArch64::STURBi:
1336 case AArch64::LDRBpre:
1337 case AArch64::STRBpre:
1338 case AArch64::LDRBpost:
1339 case AArch64::STRBpost:
1347 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1348 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1349 bool IsFP = fieldFromInstruction(insn, 26, 1);
1352 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1361 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1362 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1363 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1364 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1370 case AArch64::STLXRW:
1371 case AArch64::STLXRB:
1372 case AArch64::STLXRH:
1373 case AArch64::STXRW:
1374 case AArch64::STXRB:
1375 case AArch64::STXRH:
1378 case AArch64::LDARW:
1379 case AArch64::LDARB:
1380 case AArch64::LDARH:
1381 case AArch64::LDAXRW:
1382 case AArch64::LDAXRB:
1383 case AArch64::LDAXRH:
1384 case AArch64::LDXRW:
1385 case AArch64::LDXRB:
1386 case AArch64::LDXRH:
1387 case AArch64::STLRW:
1388 case AArch64::STLRB:
1389 case AArch64::STLRH:
1390 case AArch64::STLLRW:
1391 case AArch64::STLLRB:
1392 case AArch64::STLLRH:
1393 case AArch64::LDLARW:
1394 case AArch64::LDLARB:
1395 case AArch64::LDLARH:
1398 case AArch64::STLXRX:
1399 case AArch64::STXRX:
1402 case AArch64::LDARX:
1403 case AArch64::LDAXRX:
1404 case AArch64::LDXRX:
1405 case AArch64::STLRX:
1406 case AArch64::LDLARX:
1407 case AArch64::STLLRX:
1410 case AArch64::STLXPW:
1411 case AArch64::STXPW:
1414 case AArch64::LDAXPW:
1415 case AArch64::LDXPW:
1419 case AArch64::STLXPX:
1420 case AArch64::STXPX:
1423 case AArch64::LDAXPX:
1424 case AArch64::LDXPX:
1433 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1434 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1444 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1445 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1446 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1447 int64_t offset = fieldFromInstruction(insn, 15, 7);
1448 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1452 if (offset & (1 << (7 - 1)))
1453 offset |= ~((1LL << 7) - 1);
1456 bool NeedsDisjointWritebackTransfer =
false;
1462 case AArch64::LDPXpost:
1463 case AArch64::STPXpost:
1464 case AArch64::LDPSWpost:
1465 case AArch64::LDPXpre:
1466 case AArch64::STPXpre:
1467 case AArch64::LDPSWpre:
1468 case AArch64::LDPWpost:
1469 case AArch64::STPWpost:
1470 case AArch64::LDPWpre:
1471 case AArch64::STPWpre:
1472 case AArch64::LDPQpost:
1473 case AArch64::STPQpost:
1474 case AArch64::LDPQpre:
1475 case AArch64::STPQpre:
1476 case AArch64::LDPDpost:
1477 case AArch64::STPDpost:
1478 case AArch64::LDPDpre:
1479 case AArch64::STPDpre:
1480 case AArch64::LDPSpost:
1481 case AArch64::STPSpost:
1482 case AArch64::LDPSpre:
1483 case AArch64::STPSpre:
1484 case AArch64::STGPpre:
1485 case AArch64::STGPpost:
1493 case AArch64::LDPXpost:
1494 case AArch64::STPXpost:
1495 case AArch64::LDPSWpost:
1496 case AArch64::LDPXpre:
1497 case AArch64::STPXpre:
1498 case AArch64::LDPSWpre:
1499 case AArch64::STGPpre:
1500 case AArch64::STGPpost:
1501 NeedsDisjointWritebackTransfer =
true;
1503 case AArch64::LDNPXi:
1504 case AArch64::STNPXi:
1505 case AArch64::LDPXi:
1506 case AArch64::STPXi:
1507 case AArch64::LDPSWi:
1508 case AArch64::STGPi:
1512 case AArch64::LDPWpost:
1513 case AArch64::STPWpost:
1514 case AArch64::LDPWpre:
1515 case AArch64::STPWpre:
1516 NeedsDisjointWritebackTransfer =
true;
1518 case AArch64::LDNPWi:
1519 case AArch64::STNPWi:
1520 case AArch64::LDPWi:
1521 case AArch64::STPWi:
1525 case AArch64::LDNPQi:
1526 case AArch64::STNPQi:
1527 case AArch64::LDPQpost:
1528 case AArch64::STPQpost:
1529 case AArch64::LDPQi:
1530 case AArch64::STPQi:
1531 case AArch64::LDPQpre:
1532 case AArch64::STPQpre:
1536 case AArch64::LDNPDi:
1537 case AArch64::STNPDi:
1538 case AArch64::LDPDpost:
1539 case AArch64::STPDpost:
1540 case AArch64::LDPDi:
1541 case AArch64::STPDi:
1542 case AArch64::LDPDpre:
1543 case AArch64::STPDpre:
1547 case AArch64::LDNPSi:
1548 case AArch64::STNPSi:
1549 case AArch64::LDPSpost:
1550 case AArch64::STPSpost:
1551 case AArch64::LDPSi:
1552 case AArch64::STPSi:
1553 case AArch64::LDPSpre:
1554 case AArch64::STPSpre:
1564 if (IsLoad && Rt == Rt2)
1569 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1578 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1579 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1580 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1581 fieldFromInstruction(insn, 12, 9);
1582 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1587 case AArch64::LDRAAwriteback:
1588 case AArch64::LDRABwriteback:
1592 case AArch64::LDRAAindexed:
1593 case AArch64::LDRABindexed:
1599 DecodeSImm<10>(Inst, offset,
Addr, Decoder);
1601 if (writeback && Rt == Rn && Rn != 31) {
1611 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1612 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1613 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1614 unsigned extend = fieldFromInstruction(insn, 10, 6);
1616 unsigned shift = extend & 0x7;
1623 case AArch64::ADDWrx:
1624 case AArch64::SUBWrx:
1629 case AArch64::ADDSWrx:
1630 case AArch64::SUBSWrx:
1635 case AArch64::ADDXrx:
1636 case AArch64::SUBXrx:
1641 case AArch64::ADDSXrx:
1642 case AArch64::SUBSXrx:
1647 case AArch64::ADDXrx64:
1648 case AArch64::SUBXrx64:
1653 case AArch64::SUBSXrx64:
1654 case AArch64::ADDSXrx64:
1668 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1669 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1670 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1674 if (Inst.
getOpcode() == AArch64::ANDSXri)
1679 imm = fieldFromInstruction(insn, 10, 13);
1683 if (Inst.
getOpcode() == AArch64::ANDSWri)
1688 imm = fieldFromInstruction(insn, 10, 12);
1699 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1700 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1701 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1702 imm |= fieldFromInstruction(insn, 5, 5);
1714 case AArch64::MOVIv4i16:
1715 case AArch64::MOVIv8i16:
1716 case AArch64::MVNIv4i16:
1717 case AArch64::MVNIv8i16:
1718 case AArch64::MOVIv2i32:
1719 case AArch64::MOVIv4i32:
1720 case AArch64::MVNIv2i32:
1721 case AArch64::MVNIv4i32:
1724 case AArch64::MOVIv2s_msl:
1725 case AArch64::MOVIv4s_msl:
1726 case AArch64::MVNIv2s_msl:
1727 case AArch64::MVNIv4s_msl:
1738 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1739 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1740 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1741 imm |= fieldFromInstruction(insn, 5, 5);
1756 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1757 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1758 imm |= fieldFromInstruction(insn, 29, 2);
1761 if (imm & (1 << (21 - 1)))
1762 imm |= ~((1LL << 21) - 1);
1774 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1775 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1776 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1777 unsigned S = fieldFromInstruction(insn, 29, 1);
1778 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1780 unsigned ShifterVal = (Imm >> 12) & 3;
1781 unsigned ImmVal = Imm & 0xFFF;
1783 if (ShifterVal != 0 && ShifterVal != 1)
1809 int64_t imm = fieldFromInstruction(insn, 0, 26);
1812 if (imm & (1 << (26 - 1)))
1813 imm |= ~((1LL << 26) - 1);
1822 return Op1 == 0b000 && (Op2 == 0b000 ||
1830 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1831 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1832 uint64_t imm = fieldFromInstruction(insn, 8, 4);
1833 uint64_t pstate_field = (op1 << 3) | op2;
1841 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1851 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1852 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1853 uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1854 uint64_t imm = fieldFromInstruction(insn, 8, 1);
1855 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1863 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1873 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1874 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1875 bit |= fieldFromInstruction(insn, 19, 5);
1876 int64_t dst = fieldFromInstruction(insn, 5, 14);
1879 if (dst & (1 << (14 - 1)))
1880 dst |= ~((1LL << 14) - 1);
1882 if (fieldFromInstruction(insn, 31, 1) == 0)
1901 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1910 AArch64::WSeqPairsClassRegClassID,
1911 RegNo,
Addr, Decoder);
1918 AArch64::XSeqPairsClassRegClassID,
1919 RegNo,
Addr, Decoder);
1925 unsigned op1 = fieldFromInstruction(insn, 16, 3);
1926 unsigned CRn = fieldFromInstruction(insn, 12, 4);
1927 unsigned CRm = fieldFromInstruction(insn, 8, 4);
1928 unsigned op2 = fieldFromInstruction(insn, 5, 3);
1929 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1945 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1946 unsigned imm = fieldFromInstruction(insn, 5, 13);
1952 if (Inst.
getOpcode() != AArch64::DUPM_ZI)
1961 if (Imm & ~((1LL << Bits) - 1))
1965 if (Imm & (1 << (Bits - 1)))
1966 Imm |= ~((1LL << Bits) - 1);
1973template <
int ElementW
idth>
1976 unsigned Val = (uint8_t)Imm;
1977 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1978 if (ElementWidth == 8 && Shift)
1995 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
2005 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2006 unsigned Rs = fieldFromInstruction(insn, 16, 5);
2007 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2011 if (Rd == Rs || Rs == Rn || Rd == Rn)
2030 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2031 unsigned Rm = fieldFromInstruction(insn, 16, 5);
2032 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2036 if (Rd == Rm || Rm == Rn || Rd == Rn)
2056 unsigned Mask = 0x18;
2057 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
2058 if ((Rt & Mask) == Mask)
2061 uint64_t Rn = fieldFromInstruction(insn, 5, 5);
2062 uint64_t Shift = fieldFromInstruction(insn, 12, 1);
2063 uint64_t Extend = fieldFromInstruction(insn, 15, 1);
2064 uint64_t Rm = fieldFromInstruction(insn, 16, 5);
2072 case AArch64::PRFMroW:
2075 case AArch64::PRFMroX:
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const MCPhysReg MatrixZATileDecoderTable[5][16]
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
static DecodeStatus DecodePPR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Context object for machine code objects.
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
const MCSubtargetInfo & getSubtargetInfo() const
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
Symbolize and annotate disassembled instructions.
Wrapper class representing virtual and physical registers.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
This class implements an extremely fast bulk output stream that can only output to a stream.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheAArch64beTarget()
Target & getTheAArch64leTarget()
Target & getTheAArch64_32Target()
Target & getTheARM64_32Target()
Target & getTheARM64Target()
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.