LLVM 24.0.0git
AArch64Disassembler.cpp
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1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "AArch64Disassembler.h"
13#include "AArch64ExternalSymbolizer.h"
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "MCTargetDesc/AArch64MCTargetDesc.h"
16#include "TargetInfo/AArch64TargetInfo.h"
17#include "Utils/AArch64BaseInfo.h"
18#include "llvm/MC/MCDecoder.h"
19#include "llvm/MC/MCDecoderOps.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstrDesc.h"
23#include "llvm/MC/MCRegisterInfo.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/MC/TargetRegistry.h"
26#include "llvm/Support/Compiler.h"
27#include "llvm/Support/Debug.h"
28#include <memory>
29
30using namespace llvm;
31using namespace llvm::MCD;
32
33#define DEBUG_TYPE "aarch64-disassembler"
34
35// Pull DecodeStatus and its enum values into the global namespace.
36using DecodeStatus = MCDisassembler::DecodeStatus;
37
38template <int Bits>
39static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
40 const MCDisassembler *Decoder);
41
42#define Success MCDisassembler::Success
43#define Fail MCDisassembler::Fail
44#define SoftFail MCDisassembler::SoftFail
45
46template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
47static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo,
48 uint64_t Address,
49 const MCDisassembler *Decoder) {
50 if (RegNo > NumRegsInClass - 1)
51 return Fail;
52
53 MCRegister Register =
54 getAArch64MCRegisterClass(RegClassID).getRegister(RegNo + FirstReg);
55 Inst.addOperand(MCOperand::createReg(Register));
56 return Success;
57}
58
59static DecodeStatus
60DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
61 const MCDisassembler *Decoder) {
62 if (RegNo > 22)
63 return Fail;
64 if (RegNo & 1)
65 return Fail;
66
67 MCRegister Register =
68 getAArch64MCRegisterClass(AArch64::GPR64x8ClassRegClassID)
69 .getRegister(RegNo >> 1);
70 Inst.addOperand(MCOperand::createReg(Register));
71 return Success;
72}
73
74template <unsigned RegClassID, unsigned Multiple, unsigned Min, unsigned Max>
75static DecodeStatus
76DecodeMulMinMaxRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
77 const MCDisassembler *Decoder) {
78 unsigned Reg = (RegNo * Multiple) + Min;
79 if (Reg < Min || Reg > Max || (Reg % Multiple))
80 return Fail;
81 MCRegister Register = getAArch64MCRegisterClass(RegClassID).getRegister(Reg);
82 Inst.addOperand(MCOperand::createReg(Register));
83 return Success;
84}
85
86template <unsigned Min, unsigned Max>
87static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
88 uint64_t Address,
89 const void *Decoder) {
90 unsigned Reg = (RegNo * 2) + Min;
91 if (Reg < Min || Reg > Max || (Reg & 1))
92 return Fail;
93
94 MCRegister Register =
95 getAArch64MCRegisterClass(AArch64::ZPR2RegClassID).getRegister(Reg);
96 Inst.addOperand(MCOperand::createReg(Register));
97 return Success;
98}
99
100static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
101 const MCDisassembler *Decoder) {
102 if (RegNo > 7)
103 return Fail;
104
105 MCRegister Register =
106 getAArch64MCRegisterClass(AArch64::ZPR_KRegClassID).getRegister(RegNo);
107 Inst.addOperand(MCOperand::createReg(Register));
108 return Success;
109}
110
111static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
112 uint64_t Address,
113 const void *Decoder) {
114 if (RegNo * 4 > 28)
115 return Fail;
116 MCRegister Register =
117 getAArch64MCRegisterClass(AArch64::ZPR4RegClassID).getRegister(RegNo * 4);
118 Inst.addOperand(MCOperand::createReg(Register));
119 return Success;
120}
121
122static DecodeStatus
123DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
124 uint64_t Address,
125 const MCDisassembler *Decoder) {
126 if (RegMask > 0xFF)
127 return Fail;
128 Inst.addOperand(MCOperand::createImm(RegMask));
129 return Success;
130}
131
132static DecodeStatus DecodeZTRRegisterClass(MCInst &Inst,
133 const MCDisassembler *Decoder) {
134 Inst.addOperand(MCOperand::createReg(AArch64::ZT0));
135 return Success;
136}
137
138static DecodeStatus DecodeMPRRegisterClass(MCInst &Inst,
139 const MCDisassembler *Decoder) {
140 Inst.addOperand(MCOperand::createReg(AArch64::ZA));
141 return Success;
142}
143
144static DecodeStatus DecodeMPR8RegisterClass(MCInst &Inst,
145 const MCDisassembler *Decoder) {
146 Inst.addOperand(MCOperand::createReg(AArch64::ZAB0));
147 return Success;
148}
149
150static DecodeStatus DecodeMPR16RegisterClass(MCInst &Inst, unsigned RegNo,
151 uint64_t Address,
152 const MCDisassembler *Decoder) {
153 MCRegister Reg =
154 getAArch64MCRegisterClass(AArch64::MPR16RegClassID).getRegister(RegNo);
155 Inst.addOperand(MCOperand::createReg(Reg));
156 return Success;
157}
158
159static DecodeStatus DecodeMPR32RegisterClass(MCInst &Inst, unsigned RegNo,
160 uint64_t Address,
161 const MCDisassembler *Decoder) {
162 MCRegister Reg =
163 getAArch64MCRegisterClass(AArch64::MPR32RegClassID).getRegister(RegNo);
164 Inst.addOperand(MCOperand::createReg(Reg));
165 return Success;
166}
167
168static DecodeStatus DecodeMPR64RegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address,
170 const MCDisassembler *Decoder) {
171 MCRegister Reg =
172 getAArch64MCRegisterClass(AArch64::MPR64RegClassID).getRegister(RegNo);
173 Inst.addOperand(MCOperand::createReg(Reg));
174 return Success;
175}
176
177static DecodeStatus DecodeMPR128RegisterClass(MCInst &Inst, unsigned RegNo,
178 uint64_t Address,
179 const MCDisassembler *Decoder) {
180 MCRegister Reg =
181 getAArch64MCRegisterClass(AArch64::MPR128RegClassID).getRegister(RegNo);
182 Inst.addOperand(MCOperand::createReg(Reg));
183 return Success;
184}
185
186static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
187 uint64_t Address,
188 const void *Decoder) {
189 if ((RegNo * 2) > 14)
190 return Fail;
191 MCRegister Register =
192 getAArch64MCRegisterClass(AArch64::PPR2RegClassID).getRegister(RegNo * 2);
193 Inst.addOperand(MCOperand::createReg(Register));
194 return Success;
195}
196
197static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
198 uint64_t Addr,
199 const MCDisassembler *Decoder) {
200 // scale{5} is asserted as 1 in tblgen.
201 Imm |= 0x20;
202 Inst.addOperand(MCOperand::createImm(64 - Imm));
203 return Success;
204}
205
206static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
207 uint64_t Addr,
208 const MCDisassembler *Decoder) {
209 Inst.addOperand(MCOperand::createImm(64 - Imm));
210 return Success;
211}
212
213static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
214 uint64_t Addr,
215 const MCDisassembler *Decoder) {
216 // Immediate is encoded as the top 16-bits of an unsigned 18-bit negative
217 // PC-relative offset.
218 uint64_t ImmVal = Imm;
219 if (ImmVal > (1 << 16))
220 return Fail;
221 ImmVal = -ImmVal;
222 if (!Decoder->tryAddingSymbolicOperand(Inst, (ImmVal << 2), Addr,
223 /*IsBranch=*/false, 0, 0, 4))
224 Inst.addOperand(MCOperand::createImm(ImmVal));
225 return Success;
226}
227
228static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
229 uint64_t Addr,
230 const MCDisassembler *Decoder) {
231 int64_t ImmVal = SignExtend64<19>(Imm);
232
233 if (!Decoder->tryAddingSymbolicOperand(
234 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4))
235 Inst.addOperand(MCOperand::createImm(ImmVal));
236 return Success;
237}
238
239static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm, uint64_t Addr,
240 const MCDisassembler *Decoder) {
241 int64_t ImmVal = SignExtend64<9>(Imm);
242
243 if (!Decoder->tryAddingSymbolicOperand(Inst, (ImmVal * 4), Addr,
244 /*IsBranch=*/true, 0, 0, 4))
245 Inst.addOperand(MCOperand::createImm(ImmVal));
246 return Success;
247}
248
249static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
250 uint64_t Address,
251 const MCDisassembler *Decoder) {
252 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
253 Inst.addOperand(MCOperand::createImm(Imm & 1));
254 return Success;
255}
256
257static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
258 uint64_t Address,
259 const MCDisassembler *Decoder) {
260 Inst.addOperand(MCOperand::createImm(Imm));
261
262 // Every system register in the encoding space is valid with the syntax
263 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
264 return Success;
265}
266
267static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
268 uint64_t Address,
269 const MCDisassembler *Decoder) {
270 Inst.addOperand(MCOperand::createImm(Imm));
271
272 return Success;
273}
274
275static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
276 uint64_t Address,
277 const MCDisassembler *Decoder) {
278 // This decoder exists to add the dummy Lane operand to the MCInst, which must
279 // be 1 in assembly but has no other real manifestation.
280 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
281 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
282 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
283
284 if (IsToVec) {
285 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(
286 Inst, Rd, Address, Decoder);
287 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
288 Inst, Rn, Address, Decoder);
289 } else {
290 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
291 Inst, Rd, Address, Decoder);
292 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(
293 Inst, Rn, Address, Decoder);
294 }
295
296 // Add the lane
297 Inst.addOperand(MCOperand::createImm(1));
298
299 return Success;
300}
301
302static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
303 unsigned Add) {
304 Inst.addOperand(MCOperand::createImm(Add - Imm));
305 return Success;
306}
307
308static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
309 unsigned Add) {
310 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
311 return Success;
312}
313
314static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
315 uint64_t Addr,
316 const MCDisassembler *Decoder) {
317 return DecodeVecShiftRImm(Inst, Imm, 64);
318}
319
320static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
321 uint64_t Addr,
322 const MCDisassembler *Decoder) {
323 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
324}
325
326static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
327 uint64_t Addr,
328 const MCDisassembler *Decoder) {
329 return DecodeVecShiftRImm(Inst, Imm, 32);
330}
331
332static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
333 uint64_t Addr,
334 const MCDisassembler *Decoder) {
335 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
336}
337
338static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
339 uint64_t Addr,
340 const MCDisassembler *Decoder) {
341 return DecodeVecShiftRImm(Inst, Imm, 16);
342}
343
344static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
345 uint64_t Addr,
346 const MCDisassembler *Decoder) {
347 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
348}
349
350static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
351 uint64_t Addr,
352 const MCDisassembler *Decoder) {
353 return DecodeVecShiftRImm(Inst, Imm, 8);
354}
355
356static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
357 uint64_t Addr,
358 const MCDisassembler *Decoder) {
359 return DecodeVecShiftLImm(Inst, Imm, 64);
360}
361
362static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
363 uint64_t Addr,
364 const MCDisassembler *Decoder) {
365 return DecodeVecShiftLImm(Inst, Imm, 32);
366}
367
368static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
369 uint64_t Addr,
370 const MCDisassembler *Decoder) {
371 return DecodeVecShiftLImm(Inst, Imm, 16);
372}
373
374static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
375 uint64_t Addr,
376 const MCDisassembler *Decoder) {
377 return DecodeVecShiftLImm(Inst, Imm, 8);
378}
379
380static DecodeStatus
381DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
382 const MCDisassembler *Decoder) {
383 unsigned Rd = fieldFromInstruction(insn, 0, 5);
384 unsigned Rn = fieldFromInstruction(insn, 5, 5);
385 unsigned Rm = fieldFromInstruction(insn, 16, 5);
386 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
387 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
388 unsigned shift = (shiftHi << 6) | shiftLo;
389 switch (Inst.getOpcode()) {
390 default:
391 return Fail;
392 case AArch64::ADDWrs:
393 case AArch64::ADDSWrs:
394 case AArch64::SUBWrs:
395 case AArch64::SUBSWrs:
396 // if shift == '11' then ReservedValue()
397 if (shiftHi == 0x3)
398 return Fail;
399 [[fallthrough]];
400 case AArch64::ANDWrs:
401 case AArch64::ANDSWrs:
402 case AArch64::BICWrs:
403 case AArch64::BICSWrs:
404 case AArch64::ORRWrs:
405 case AArch64::ORNWrs:
406 case AArch64::EORWrs:
407 case AArch64::EONWrs: {
408 // if sf == '0' and imm6<5> == '1' then ReservedValue()
409 if (shiftLo >> 5 == 1)
410 return Fail;
411 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
412 Decoder);
413 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rn, Addr,
414 Decoder);
415 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
416 Decoder);
417 break;
418 }
419 case AArch64::ADDXrs:
420 case AArch64::ADDSXrs:
421 case AArch64::SUBXrs:
422 case AArch64::SUBSXrs:
423 // if shift == '11' then ReservedValue()
424 if (shiftHi == 0x3)
425 return Fail;
426 [[fallthrough]];
427 case AArch64::ANDXrs:
428 case AArch64::ANDSXrs:
429 case AArch64::BICXrs:
430 case AArch64::BICSXrs:
431 case AArch64::ORRXrs:
432 case AArch64::ORNXrs:
433 case AArch64::EORXrs:
434 case AArch64::EONXrs:
435 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
436 Decoder);
437 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rn, Addr,
438 Decoder);
439 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
440 Decoder);
441 break;
442 }
443
444 Inst.addOperand(MCOperand::createImm(shift));
445 return Success;
446}
447
448static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
449 uint64_t Addr,
450 const MCDisassembler *Decoder) {
451 unsigned Rd = fieldFromInstruction(insn, 0, 5);
452 unsigned imm = fieldFromInstruction(insn, 5, 16);
453 unsigned shift = fieldFromInstruction(insn, 21, 2);
454 shift <<= 4;
455 switch (Inst.getOpcode()) {
456 default:
457 return Fail;
458 case AArch64::MOVZWi:
459 case AArch64::MOVNWi:
460 case AArch64::MOVKWi:
461 if (shift & (1U << 5))
462 return Fail;
463 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
464 Decoder);
465 break;
466 case AArch64::MOVZXi:
467 case AArch64::MOVNXi:
468 case AArch64::MOVKXi:
469 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
470 Decoder);
471 break;
472 }
473
474 if (Inst.getOpcode() == AArch64::MOVKWi ||
475 Inst.getOpcode() == AArch64::MOVKXi)
476 Inst.addOperand(Inst.getOperand(0));
477
478 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, /*IsBranch*/ false, 0,
479 0, 4))
480 Inst.addOperand(MCOperand::createImm(imm));
481
482 Inst.addOperand(MCOperand::createImm(shift));
483 return Success;
484}
485
486static DecodeStatus
487DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
488 const MCDisassembler *Decoder) {
489 unsigned Rt = fieldFromInstruction(insn, 0, 5);
490 unsigned Rn = fieldFromInstruction(insn, 5, 5);
491 unsigned offset = fieldFromInstruction(insn, 10, 12);
492
493 switch (Inst.getOpcode()) {
494 default:
495 return Fail;
496 case AArch64::PRFMui:
497 // Rt is an immediate in prefetch.
498 Inst.addOperand(MCOperand::createImm(Rt));
499 break;
500 case AArch64::STRBBui:
501 case AArch64::LDRBBui:
502 case AArch64::LDRSBWui:
503 case AArch64::STRHHui:
504 case AArch64::LDRHHui:
505 case AArch64::LDRSHWui:
506 case AArch64::STRWui:
507 case AArch64::LDRWui:
508 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
509 Decoder);
510 break;
511 case AArch64::LDRSBXui:
512 case AArch64::LDRSHXui:
513 case AArch64::LDRSWui:
514 case AArch64::STRXui:
515 case AArch64::LDRXui:
516 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
517 Decoder);
518 break;
519 case AArch64::LDRQui:
520 case AArch64::STRQui:
521 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
522 Decoder);
523 break;
524 case AArch64::LDRDui:
525 case AArch64::STRDui:
526 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
527 Decoder);
528 break;
529 case AArch64::LDRSui:
530 case AArch64::STRSui:
531 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
532 Decoder);
533 break;
534 case AArch64::LDRHui:
535 case AArch64::STRHui:
536 DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>(Inst, Rt, Addr,
537 Decoder);
538 break;
539 case AArch64::LDRBui:
540 case AArch64::STRBui:
541 DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>(Inst, Rt, Addr,
542 Decoder);
543 break;
544 }
545
546 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
547 Decoder);
548 if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 0, 4))
549 Inst.addOperand(MCOperand::createImm(offset));
550 return Success;
551}
552
553static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
554 uint64_t Addr,
555 const MCDisassembler *Decoder) {
556 unsigned Rt = fieldFromInstruction(insn, 0, 5);
557 unsigned Rn = fieldFromInstruction(insn, 5, 5);
558 int64_t offset = SignExtend64<9>(fieldFromInstruction(insn, 12, 9));
559
560 // First operand is always the writeback to the address register, if needed.
561 switch (Inst.getOpcode()) {
562 default:
563 break;
564 case AArch64::LDRSBWpre:
565 case AArch64::LDRSHWpre:
566 case AArch64::STRBBpre:
567 case AArch64::LDRBBpre:
568 case AArch64::STRHHpre:
569 case AArch64::LDRHHpre:
570 case AArch64::STRWpre:
571 case AArch64::LDRWpre:
572 case AArch64::LDRSBWpost:
573 case AArch64::LDRSHWpost:
574 case AArch64::STRBBpost:
575 case AArch64::LDRBBpost:
576 case AArch64::STRHHpost:
577 case AArch64::LDRHHpost:
578 case AArch64::STRWpost:
579 case AArch64::LDRWpost:
580 case AArch64::LDRSBXpre:
581 case AArch64::LDRSHXpre:
582 case AArch64::STRXpre:
583 case AArch64::LDRSWpre:
584 case AArch64::LDRXpre:
585 case AArch64::LDRSBXpost:
586 case AArch64::LDRSHXpost:
587 case AArch64::STRXpost:
588 case AArch64::LDRSWpost:
589 case AArch64::LDRXpost:
590 case AArch64::LDRQpre:
591 case AArch64::STRQpre:
592 case AArch64::LDRQpost:
593 case AArch64::STRQpost:
594 case AArch64::LDRDpre:
595 case AArch64::STRDpre:
596 case AArch64::LDRDpost:
597 case AArch64::STRDpost:
598 case AArch64::LDRSpre:
599 case AArch64::STRSpre:
600 case AArch64::LDRSpost:
601 case AArch64::STRSpost:
602 case AArch64::LDRHpre:
603 case AArch64::STRHpre:
604 case AArch64::LDRHpost:
605 case AArch64::STRHpost:
606 case AArch64::LDRBpre:
607 case AArch64::STRBpre:
608 case AArch64::LDRBpost:
609 case AArch64::STRBpost:
610 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
611 Decoder);
612 break;
613 }
614
615 switch (Inst.getOpcode()) {
616 default:
617 return Fail;
618 case AArch64::PRFUMi:
619 // Rt is an immediate in prefetch.
620 Inst.addOperand(MCOperand::createImm(Rt));
621 break;
622 case AArch64::STURBBi:
623 case AArch64::LDURBBi:
624 case AArch64::LDURSBWi:
625 case AArch64::STURHHi:
626 case AArch64::LDURHHi:
627 case AArch64::LDURSHWi:
628 case AArch64::STURWi:
629 case AArch64::LDURWi:
630 case AArch64::LDTRSBWi:
631 case AArch64::LDTRSHWi:
632 case AArch64::STTRWi:
633 case AArch64::LDTRWi:
634 case AArch64::STTRHi:
635 case AArch64::LDTRHi:
636 case AArch64::LDTRBi:
637 case AArch64::STTRBi:
638 case AArch64::LDRSBWpre:
639 case AArch64::LDRSHWpre:
640 case AArch64::STRBBpre:
641 case AArch64::LDRBBpre:
642 case AArch64::STRHHpre:
643 case AArch64::LDRHHpre:
644 case AArch64::STRWpre:
645 case AArch64::LDRWpre:
646 case AArch64::LDRSBWpost:
647 case AArch64::LDRSHWpost:
648 case AArch64::STRBBpost:
649 case AArch64::LDRBBpost:
650 case AArch64::STRHHpost:
651 case AArch64::LDRHHpost:
652 case AArch64::STRWpost:
653 case AArch64::LDRWpost:
654 case AArch64::STLURBi:
655 case AArch64::STLURHi:
656 case AArch64::STLURWi:
657 case AArch64::LDAPURBi:
658 case AArch64::LDAPURSBWi:
659 case AArch64::LDAPURHi:
660 case AArch64::LDAPURSHWi:
661 case AArch64::LDAPURi:
662 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
663 Decoder);
664 break;
665 case AArch64::LDURSBXi:
666 case AArch64::LDURSHXi:
667 case AArch64::LDURSWi:
668 case AArch64::STURXi:
669 case AArch64::LDURXi:
670 case AArch64::LDTRSBXi:
671 case AArch64::LDTRSHXi:
672 case AArch64::LDTRSWi:
673 case AArch64::STTRXi:
674 case AArch64::LDTRXi:
675 case AArch64::LDRSBXpre:
676 case AArch64::LDRSHXpre:
677 case AArch64::STRXpre:
678 case AArch64::LDRSWpre:
679 case AArch64::LDRXpre:
680 case AArch64::LDRSBXpost:
681 case AArch64::LDRSHXpost:
682 case AArch64::STRXpost:
683 case AArch64::LDRSWpost:
684 case AArch64::LDRXpost:
685 case AArch64::LDAPURSWi:
686 case AArch64::LDAPURSHXi:
687 case AArch64::LDAPURSBXi:
688 case AArch64::STLURXi:
689 case AArch64::LDAPURXi:
690 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
691 Decoder);
692 break;
693 case AArch64::LDURQi:
694 case AArch64::STURQi:
695 case AArch64::LDRQpre:
696 case AArch64::STRQpre:
697 case AArch64::LDRQpost:
698 case AArch64::STRQpost:
699 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
700 Decoder);
701 break;
702 case AArch64::LDURDi:
703 case AArch64::STURDi:
704 case AArch64::LDRDpre:
705 case AArch64::STRDpre:
706 case AArch64::LDRDpost:
707 case AArch64::STRDpost:
708 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
709 Decoder);
710 break;
711 case AArch64::LDURSi:
712 case AArch64::STURSi:
713 case AArch64::LDRSpre:
714 case AArch64::STRSpre:
715 case AArch64::LDRSpost:
716 case AArch64::STRSpost:
717 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
718 Decoder);
719 break;
720 case AArch64::LDURHi:
721 case AArch64::STURHi:
722 case AArch64::LDRHpre:
723 case AArch64::STRHpre:
724 case AArch64::LDRHpost:
725 case AArch64::STRHpost:
726 DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>(Inst, Rt, Addr,
727 Decoder);
728 break;
729 case AArch64::LDURBi:
730 case AArch64::STURBi:
731 case AArch64::LDRBpre:
732 case AArch64::STRBpre:
733 case AArch64::LDRBpost:
734 case AArch64::STRBpost:
735 DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>(Inst, Rt, Addr,
736 Decoder);
737 break;
738 }
739
740 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
741 Decoder);
742 Inst.addOperand(MCOperand::createImm(offset));
743
744 bool IsLoad = fieldFromInstruction(insn, 22, 1);
745 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
746 bool IsFP = fieldFromInstruction(insn, 26, 1);
747
748 // Cannot write back to a transfer register (but xzr != sp).
749 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
750 return SoftFail;
751
752 return Success;
753}
754
755static DecodeStatus
756DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
757 const MCDisassembler *Decoder) {
758 unsigned Rt = fieldFromInstruction(insn, 0, 5);
759 unsigned Rn = fieldFromInstruction(insn, 5, 5);
760 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
761 unsigned Rs = fieldFromInstruction(insn, 16, 5);
762
763 unsigned Opcode = Inst.getOpcode();
764 switch (Opcode) {
765 default:
766 return Fail;
767 case AArch64::STLXRW:
768 case AArch64::STLXRB:
769 case AArch64::STLXRH:
770 case AArch64::STXRW:
771 case AArch64::STXRB:
772 case AArch64::STXRH:
773 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
774 Decoder);
775 [[fallthrough]];
776 case AArch64::LDARW:
777 case AArch64::LDARB:
778 case AArch64::LDARH:
779 case AArch64::LDAXRW:
780 case AArch64::LDAXRB:
781 case AArch64::LDAXRH:
782 case AArch64::LDXRW:
783 case AArch64::LDXRB:
784 case AArch64::LDXRH:
785 case AArch64::STLRW:
786 case AArch64::STLRB:
787 case AArch64::STLRH:
788 case AArch64::STLLRW:
789 case AArch64::STLLRB:
790 case AArch64::STLLRH:
791 case AArch64::LDLARW:
792 case AArch64::LDLARB:
793 case AArch64::LDLARH:
794 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
795 Decoder);
796 break;
797 case AArch64::STLXRX:
798 case AArch64::STXRX:
799 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
800 Decoder);
801 [[fallthrough]];
802 case AArch64::LDARX:
803 case AArch64::LDAXRX:
804 case AArch64::LDXRX:
805 case AArch64::STLRX:
806 case AArch64::LDLARX:
807 case AArch64::STLLRX:
808 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
809 Decoder);
810 break;
811 case AArch64::STLXPW:
812 case AArch64::STXPW:
813 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
814 Decoder);
815 [[fallthrough]];
816 case AArch64::LDAXPW:
817 case AArch64::LDXPW:
818 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
819 Decoder);
820 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
821 Decoder);
822 break;
823 case AArch64::STLXPX:
824 case AArch64::STXPX:
825 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
826 Decoder);
827 [[fallthrough]];
828 case AArch64::LDAXPX:
829 case AArch64::LDXPX:
830 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
831 Decoder);
832 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
833 Decoder);
834 break;
835 }
836
837 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
838 Decoder);
839
840 // You shouldn't load to the same register twice in an instruction...
841 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
842 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
843 Rt == Rt2)
844 return SoftFail;
845
846 return Success;
847}
848
849static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
850 uint64_t Addr,
851 const MCDisassembler *Decoder) {
852 unsigned Rt = fieldFromInstruction(insn, 0, 5);
853 unsigned Rn = fieldFromInstruction(insn, 5, 5);
854 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
855 int64_t offset = SignExtend64<7>(fieldFromInstruction(insn, 15, 7));
856 bool IsLoad = fieldFromInstruction(insn, 22, 1);
857
858 unsigned Opcode = Inst.getOpcode();
859 bool NeedsDisjointWritebackTransfer = false;
860
861 // First operand is always writeback of base register.
862 switch (Opcode) {
863 default:
864 break;
865 case AArch64::LDPXpost:
866 case AArch64::STPXpost:
867 case AArch64::LDPSWpost:
868 case AArch64::LDPXpre:
869 case AArch64::STPXpre:
870 case AArch64::LDPSWpre:
871 case AArch64::LDPWpost:
872 case AArch64::STPWpost:
873 case AArch64::LDPWpre:
874 case AArch64::STPWpre:
875 case AArch64::LDPQpost:
876 case AArch64::STPQpost:
877 case AArch64::LDPQpre:
878 case AArch64::STPQpre:
879 case AArch64::LDPDpost:
880 case AArch64::STPDpost:
881 case AArch64::LDPDpre:
882 case AArch64::STPDpre:
883 case AArch64::LDPSpost:
884 case AArch64::STPSpost:
885 case AArch64::LDPSpre:
886 case AArch64::STPSpre:
887 case AArch64::STGPpre:
888 case AArch64::STGPpost:
889 case AArch64::LDTPpre:
890 case AArch64::LDTPpost:
891 case AArch64::LDTPQpost:
892 case AArch64::LDTPQpre:
893 case AArch64::STTPpost:
894 case AArch64::STTPpre:
895 case AArch64::STTPQpost:
896 case AArch64::STTPQpre:
897 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
898 Decoder);
899 break;
900 }
901
902 switch (Opcode) {
903 default:
904 return Fail;
905 case AArch64::LDPXpost:
906 case AArch64::STPXpost:
907 case AArch64::LDPSWpost:
908 case AArch64::LDPXpre:
909 case AArch64::STPXpre:
910 case AArch64::LDPSWpre:
911 case AArch64::STGPpre:
912 case AArch64::STGPpost:
913 case AArch64::LDTPpost:
914 case AArch64::LDTPpre:
915 case AArch64::STTPpost:
916 case AArch64::STTPpre:
917 NeedsDisjointWritebackTransfer = true;
918 [[fallthrough]];
919 case AArch64::LDNPXi:
920 case AArch64::STNPXi:
921 case AArch64::LDPXi:
922 case AArch64::STPXi:
923 case AArch64::LDPSWi:
924 case AArch64::STGPi:
925 case AArch64::LDTPi:
926 case AArch64::STTPi:
927 case AArch64::STTNPXi:
928 case AArch64::LDTNPXi:
929 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
930 Decoder);
931 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
932 Decoder);
933 break;
934 case AArch64::LDPWpost:
935 case AArch64::STPWpost:
936 case AArch64::LDPWpre:
937 case AArch64::STPWpre:
938 NeedsDisjointWritebackTransfer = true;
939 [[fallthrough]];
940 case AArch64::LDNPWi:
941 case AArch64::STNPWi:
942 case AArch64::LDPWi:
943 case AArch64::STPWi:
944 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
945 Decoder);
946 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
947 Decoder);
948 break;
949 case AArch64::LDNPQi:
950 case AArch64::STNPQi:
951 case AArch64::LDPQpost:
952 case AArch64::STPQpost:
953 case AArch64::LDPQi:
954 case AArch64::STPQi:
955 case AArch64::LDPQpre:
956 case AArch64::STPQpre:
957 case AArch64::LDTPQi:
958 case AArch64::LDTPQpost:
959 case AArch64::LDTPQpre:
960 case AArch64::LDTNPQi:
961 case AArch64::STTPQi:
962 case AArch64::STTPQpost:
963 case AArch64::STTPQpre:
964 case AArch64::STTNPQi:
965 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
966 Decoder);
967 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt2, Addr,
968 Decoder);
969 break;
970 case AArch64::LDNPDi:
971 case AArch64::STNPDi:
972 case AArch64::LDPDpost:
973 case AArch64::STPDpost:
974 case AArch64::LDPDi:
975 case AArch64::STPDi:
976 case AArch64::LDPDpre:
977 case AArch64::STPDpre:
978 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
979 Decoder);
980 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
981 Decoder);
982 break;
983 case AArch64::LDNPSi:
984 case AArch64::STNPSi:
985 case AArch64::LDPSpost:
986 case AArch64::STPSpost:
987 case AArch64::LDPSi:
988 case AArch64::STPSi:
989 case AArch64::LDPSpre:
990 case AArch64::STPSpre:
991 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
992 Decoder);
993 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
994 Decoder);
995 break;
996 }
997
998 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
999 Decoder);
1000 Inst.addOperand(MCOperand::createImm(offset));
1001
1002 // You shouldn't load to the same register twice in an instruction...
1003 if (IsLoad && Rt == Rt2)
1004 return SoftFail;
1005
1006 // ... or do any operation that writes-back to a transfer register. But note
1007 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1008 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1009 return SoftFail;
1010
1011 return Success;
1012}
1013
1014static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
1015 uint64_t Addr,
1016 const MCDisassembler *Decoder) {
1017 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1018 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1019 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1020 fieldFromInstruction(insn, 12, 9);
1021 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1022
1023 switch (Inst.getOpcode()) {
1024 default:
1025 return Fail;
1026 case AArch64::LDRAAwriteback:
1027 case AArch64::LDRABwriteback:
1028 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1029 Inst, Rn /* writeback register */, Addr, Decoder);
1030 break;
1031 case AArch64::LDRAAindexed:
1032 case AArch64::LDRABindexed:
1033 break;
1034 }
1035
1036 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1037 Decoder);
1038 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1039 Decoder);
1040 DecodeSImm<10>(Inst, offset, Addr, Decoder);
1041
1042 if (writeback && Rt == Rn && Rn != 31) {
1043 return SoftFail;
1044 }
1045
1046 return Success;
1047}
1048
1049static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1050 uint64_t Addr,
1051 const MCDisassembler *Decoder) {
1052 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1053 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1054 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1055 unsigned extend = fieldFromInstruction(insn, 10, 6);
1056
1057 unsigned shift = extend & 0x7;
1058 if (shift > 4)
1059 return Fail;
1060
1061 switch (Inst.getOpcode()) {
1062 default:
1063 return Fail;
1064 case AArch64::ADDWrx:
1065 case AArch64::SUBWrx:
1066 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rd, Addr,
1067 Decoder);
1068 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1069 Decoder);
1070 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1071 Decoder);
1072 break;
1073 case AArch64::ADDSWrx:
1074 case AArch64::SUBSWrx:
1075 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1076 Decoder);
1077 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1078 Decoder);
1079 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1080 Decoder);
1081 break;
1082 case AArch64::ADDXrx:
1083 case AArch64::SUBXrx:
1084 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd, Addr,
1085 Decoder);
1086 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1087 Decoder);
1088 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1089 Decoder);
1090 break;
1091 case AArch64::ADDSXrx:
1092 case AArch64::SUBSXrx:
1093 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1094 Decoder);
1095 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1096 Decoder);
1097 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1098 Decoder);
1099 break;
1100 case AArch64::ADDXrx64:
1101 case AArch64::SUBXrx64:
1102 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd, Addr,
1103 Decoder);
1104 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1105 Decoder);
1106 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1107 Decoder);
1108 break;
1109 case AArch64::SUBSXrx64:
1110 case AArch64::ADDSXrx64:
1111 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1112 Decoder);
1113 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1114 Decoder);
1115 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1116 Decoder);
1117 break;
1118 }
1119
1120 Inst.addOperand(MCOperand::createImm(extend));
1121 return Success;
1122}
1123
1124static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1125 uint64_t Addr,
1126 const MCDisassembler *Decoder) {
1127 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1128 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1129 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1130 unsigned imm;
1131
1132 if (Datasize) {
1133 if (Inst.getOpcode() == AArch64::ANDSXri)
1134 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1135 Decoder);
1136 else
1137 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1138 Inst, Rd, Addr, Decoder);
1139 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rn, Addr,
1140 Decoder);
1141 imm = fieldFromInstruction(insn, 10, 13);
1142 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1143 return Fail;
1144 } else {
1145 if (Inst.getOpcode() == AArch64::ANDSWri)
1146 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1147 Decoder);
1148 else
1149 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(
1150 Inst, Rd, Addr, Decoder);
1151 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rn, Addr,
1152 Decoder);
1153 imm = fieldFromInstruction(insn, 10, 12);
1154 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1155 return Fail;
1156 }
1157 Inst.addOperand(MCOperand::createImm(imm));
1158 return Success;
1159}
1160
1161static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
1162 uint64_t Addr,
1163 const MCDisassembler *Decoder) {
1164 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1165 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1166 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1167 imm |= fieldFromInstruction(insn, 5, 5);
1168
1169 if (Inst.getOpcode() == AArch64::MOVID)
1170 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1171 Decoder);
1172 else
1173 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1174 Decoder);
1175
1176 Inst.addOperand(MCOperand::createImm(imm));
1177
1178 switch (Inst.getOpcode()) {
1179 default:
1180 break;
1181 case AArch64::MOVIv4i16:
1182 case AArch64::MOVIv8i16:
1183 case AArch64::MVNIv4i16:
1184 case AArch64::MVNIv8i16:
1185 case AArch64::MOVIv2i32:
1186 case AArch64::MOVIv4i32:
1187 case AArch64::MVNIv2i32:
1188 case AArch64::MVNIv4i32:
1189 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1190 break;
1191 case AArch64::MOVIv2s_msl:
1192 case AArch64::MOVIv4s_msl:
1193 case AArch64::MVNIv2s_msl:
1194 case AArch64::MVNIv4s_msl:
1195 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1196 break;
1197 }
1198
1199 return Success;
1200}
1201
1202static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1203 uint64_t Addr,
1204 const MCDisassembler *Decoder) {
1205 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1206 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1207 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1208 imm |= fieldFromInstruction(insn, 5, 5);
1209
1210 // Tied operands added twice.
1211 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1212 Decoder);
1213 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1214 Decoder);
1215
1216 Inst.addOperand(MCOperand::createImm(imm));
1217 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1218
1219 return Success;
1220}
1221
1222static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
1223 uint64_t Addr,
1224 const MCDisassembler *Decoder) {
1225 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1226 int64_t imm = SignExtend64<21>((fieldFromInstruction(insn, 5, 19) << 2) |
1227 fieldFromInstruction(insn, 29, 2));
1228
1229 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1230 Decoder);
1231 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 0, 4))
1232 Inst.addOperand(MCOperand::createImm(imm));
1233
1234 return Success;
1235}
1236
1237static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1238 uint64_t Addr,
1239 const MCDisassembler *Decoder) {
1240 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1241 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1242 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1243 unsigned S = fieldFromInstruction(insn, 29, 1);
1244 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1245
1246 unsigned ShifterVal = (Imm >> 12) & 3;
1247 unsigned ImmVal = Imm & 0xFFF;
1248
1249 if (ShifterVal != 0 && ShifterVal != 1)
1250 return Fail;
1251
1252 if (Datasize) {
1253 if (Rd == 31 && !S)
1254 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1255 Inst, Rd, Addr, Decoder);
1256 else
1257 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1258 Decoder);
1259 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1260 Decoder);
1261 } else {
1262 if (Rd == 31 && !S)
1263 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(
1264 Inst, Rd, Addr, Decoder);
1265 else
1266 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1267 Decoder);
1268 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1269 Decoder);
1270 }
1271
1272 if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 0, 4))
1273 Inst.addOperand(MCOperand::createImm(ImmVal));
1274 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1275 return Success;
1276}
1277
1278static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
1279 uint64_t Addr,
1280 const MCDisassembler *Decoder) {
1281 int64_t imm = SignExtend64<26>(fieldFromInstruction(insn, 0, 26));
1282
1283 if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 0, 4))
1284 Inst.addOperand(MCOperand::createImm(imm));
1285
1286 return Success;
1287}
1288
1289static bool isInvalidPState(uint64_t Op1, uint64_t Op2) {
1290 return Op1 == 0b000 && (Op2 == 0b000 || // CFINV
1291 Op2 == 0b001 || // XAFlag
1292 Op2 == 0b010); // AXFlag
1293}
1294
1295static DecodeStatus
1296DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1297 const MCDisassembler *Decoder) {
1298 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1299 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1300 uint64_t imm = fieldFromInstruction(insn, 8, 4);
1301 uint64_t pstate_field = (op1 << 3) | op2;
1302
1303 if (isInvalidPState(op1, op2))
1304 return Fail;
1305
1306 Inst.addOperand(MCOperand::createImm(pstate_field));
1307 Inst.addOperand(MCOperand::createImm(imm));
1308
1309 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1310 if (PState &&
1311 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1312 return Success;
1313 return Fail;
1314}
1315
1316static DecodeStatus
1317DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1318 const MCDisassembler *Decoder) {
1319 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1320 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1321 uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1322 uint64_t imm = fieldFromInstruction(insn, 8, 1);
1323 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1324
1325 if (isInvalidPState(op1, op2))
1326 return Fail;
1327
1328 Inst.addOperand(MCOperand::createImm(pstate_field));
1329 Inst.addOperand(MCOperand::createImm(imm));
1330
1331 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1332 if (PState &&
1333 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1334 return Success;
1335 return Fail;
1336}
1337
1338static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
1339 uint64_t Addr,
1340 const MCDisassembler *Decoder) {
1341 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1342 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1343 bit |= fieldFromInstruction(insn, 19, 5);
1344 int64_t dst = SignExtend64<14>(fieldFromInstruction(insn, 5, 14));
1345
1346 if (fieldFromInstruction(insn, 31, 1) == 0)
1347 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1348 Decoder);
1349 else
1350 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1351 Decoder);
1352 Inst.addOperand(MCOperand::createImm(bit));
1353 if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 0, 4))
1354 Inst.addOperand(MCOperand::createImm(dst));
1355
1356 return Success;
1357}
1358
1359static DecodeStatus
1360DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID,
1361 unsigned RegNo, uint64_t Addr,
1362 const MCDisassembler *Decoder) {
1363 // Register number must be even (see CASP instruction)
1364 if (RegNo & 0x1)
1365 return Fail;
1366
1367 MCRegister Reg = getAArch64MCRegisterClass(RegClassID).getRegister(RegNo / 2);
1368 Inst.addOperand(MCOperand::createReg(Reg));
1369 return Success;
1370}
1371
1372static DecodeStatus
1373DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1374 const MCDisassembler *Decoder) {
1375 return DecodeGPRSeqPairsClassRegisterClass(
1376 Inst, AArch64::WSeqPairsClassRegClassID, RegNo, Addr, Decoder);
1377}
1378
1379static DecodeStatus
1380DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1381 const MCDisassembler *Decoder) {
1382 return DecodeGPRSeqPairsClassRegisterClass(
1383 Inst, AArch64::XSeqPairsClassRegClassID, RegNo, Addr, Decoder);
1384}
1385
1386static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
1387 uint64_t Addr,
1388 const MCDisassembler *Decoder) {
1389 unsigned op1 = fieldFromInstruction(insn, 16, 3);
1390 unsigned CRn = fieldFromInstruction(insn, 12, 4);
1391 unsigned CRm = fieldFromInstruction(insn, 8, 4);
1392 unsigned op2 = fieldFromInstruction(insn, 5, 3);
1393 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1394 if (Rt != 0b11111)
1395 return Fail;
1396
1397 Inst.addOperand(MCOperand::createImm(op1));
1398 Inst.addOperand(MCOperand::createImm(CRn));
1399 Inst.addOperand(MCOperand::createImm(CRm));
1400 Inst.addOperand(MCOperand::createImm(op2));
1401 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1402 Decoder);
1403
1404 return Success;
1405}
1406
1407static DecodeStatus
1408DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1409 const MCDisassembler *Decoder) {
1410 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1411 unsigned imm = fieldFromInstruction(insn, 5, 13);
1412 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1413 return Fail;
1414
1415 // The same (tied) operand is added twice to the instruction.
1416 DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>(Inst, Zdn, Addr,
1417 Decoder);
1418 if (Inst.getOpcode() != AArch64::DUPM_ZI)
1419 DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>(Inst, Zdn, Addr,
1420 Decoder);
1421 Inst.addOperand(MCOperand::createImm(imm));
1422 return Success;
1423}
1424
1425static DecodeStatus DecodeZeroImm(MCInst &Inst, const MCDisassembler *Decoder) {
1426 Inst.addOperand(MCOperand::createImm(0));
1427 return Success;
1428}
1429
1430template <int Bits>
1431static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
1432 const MCDisassembler *Decoder) {
1433 if (Imm & ~((1LL << Bits) - 1))
1434 return Fail;
1435
1436 // Imm is a signed immediate, so sign extend it.
1437 if (Imm & (1 << (Bits - 1)))
1438 Imm |= ~((1LL << Bits) - 1);
1439
1440 Inst.addOperand(MCOperand::createImm(Imm));
1441 return Success;
1442}
1443
1444// Decode 8-bit signed/unsigned immediate for a given element width.
1445template <int ElementWidth>
1446static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
1447 const MCDisassembler *Decoder) {
1448 unsigned Val = (uint8_t)Imm;
1449 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1450 if (ElementWidth == 8 && Shift)
1451 return Fail;
1452 Inst.addOperand(MCOperand::createImm(Val));
1453 Inst.addOperand(MCOperand::createImm(Shift));
1454 return Success;
1455}
1456
1457static DecodeStatus DecodeHinteUImm16(MCInst &Inst, unsigned Imm, uint64_t Addr,
1458 const MCDisassembler *Decoder) {
1459 if (Imm > 65535 ||
1460 (Imm >= 12319 && Imm <= 16383 && ((Imm - 12319) % 32) == 0))
1461 return Fail;
1462
1463 Inst.addOperand(MCOperand::createImm(Imm));
1464 return Success;
1465}
1466
1467// Decode uimm4 ranged from 1-16.
1468static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1469 uint64_t Addr,
1470 const MCDisassembler *Decoder) {
1471 Inst.addOperand(MCOperand::createImm(Imm + 1));
1472 return Success;
1473}
1474
1475static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
1476 const MCDisassembler *Decoder) {
1477 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
1478 Inst.addOperand(MCOperand::createImm(Imm));
1479 return Success;
1480 }
1481 return Fail;
1482}
1483
1484static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
1485 uint64_t Addr,
1486 const MCDisassembler *Decoder) {
1487 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1488 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1489 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1490
1491 // None of the registers may alias: if they do, then the instruction is not
1492 // merely unpredictable but actually entirely unallocated.
1493 if (Rd == Rs || Rs == Rn || Rd == Rn)
1494 return MCDisassembler::Fail;
1495
1496 // All three register operands are written back, so they all appear
1497 // twice in the operand list, once as outputs and once as inputs.
1498 if (!DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1499 Inst, Rd, Addr, Decoder) ||
1500 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1501 Inst, Rs, Addr, Decoder) ||
1502 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1503 Inst, Rn, Addr, Decoder) ||
1504 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1505 Inst, Rd, Addr, Decoder) ||
1506 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1507 Inst, Rs, Addr, Decoder) ||
1508 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1509 Inst, Rn, Addr, Decoder))
1510 return MCDisassembler::Fail;
1511
1512 return MCDisassembler::Success;
1513}
1514
1515static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
1516 uint64_t Addr,
1517 const MCDisassembler *Decoder) {
1518 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1519 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1520 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1521
1522 // None of the registers may alias: if they do, then the instruction is not
1523 // merely unpredictable but actually entirely unallocated.
1524 if (Rd == Rm || Rm == Rn || Rd == Rn)
1525 return MCDisassembler::Fail;
1526
1527 // Rd and Rn (not Rm) register operands are written back, so they appear
1528 // twice in the operand list, once as outputs and once as inputs.
1529 if (!DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1530 Inst, Rd, Addr, Decoder) ||
1531 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1532 Inst, Rn, Addr, Decoder) ||
1533 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1534 Inst, Rd, Addr, Decoder) ||
1535 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1536 Inst, Rn, Addr, Decoder) ||
1537 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1538 Inst, Rm, Addr, Decoder))
1539 return MCDisassembler::Fail;
1540
1541 return MCDisassembler::Success;
1542}
1543
1544static DecodeStatus DecodeSETMemGoOpInstruction(MCInst &Inst, uint32_t insn,
1545 uint64_t Addr,
1546 const MCDisassembler *Decoder) {
1547 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1548 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1549
1550 // None of the registers may alias: if they do, then the instruction is not
1551 // merely unpredictable but actually entirely unallocated.
1552 if (Rd == Rn)
1553 return MCDisassembler::Fail;
1554
1555 // Rd and Rn register operands are written back, so they appear
1556 // twice in the operand list, once as outputs and once as inputs.
1557 if (!DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1558 Inst, Rd, Addr, Decoder) ||
1559 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1560 Inst, Rn, Addr, Decoder) ||
1561 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1562 Inst, Rd, Addr, Decoder) ||
1563 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1564 Inst, Rn, Addr, Decoder))
1565 return MCDisassembler::Fail;
1566
1567 return MCDisassembler::Success;
1568}
1569
1570static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
1571 uint64_t Addr,
1572 const MCDisassembler *Decoder) {
1573 // PRFM with Rt = '11xxx' should be decoded as RPRFM.
1574 // Fail to decode and defer to fallback decoder table to decode RPRFM.
1575 unsigned Mask = 0x18;
1576 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1577 if ((Rt & Mask) == Mask)
1578 return Fail;
1579
1580 uint64_t Rn = fieldFromInstruction(insn, 5, 5);
1581 uint64_t Shift = fieldFromInstruction(insn, 12, 1);
1582 uint64_t Extend = fieldFromInstruction(insn, 15, 1);
1583 uint64_t Rm = fieldFromInstruction(insn, 16, 5);
1584
1585 Inst.addOperand(MCOperand::createImm(Rt));
1586 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1587 Decoder);
1588
1589 switch (Inst.getOpcode()) {
1590 default:
1591 return Fail;
1592 case AArch64::PRFMroW:
1593 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1594 Decoder);
1595 break;
1596 case AArch64::PRFMroX:
1597 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1598 Decoder);
1599 break;
1600 }
1601
1602 DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder);
1603
1604 return Success;
1605}
1606
1607static DecodeStatus
1608DecodeSMESpillFillInstruction(MCInst &Inst, uint32_t Bits, uint64_t Addr,
1609 const MCDisassembler *Decoder) {
1610 unsigned RvBits = fieldFromInstruction(Bits, 13, 2);
1611 unsigned RnBits = fieldFromInstruction(Bits, 5, 5);
1612 unsigned Imm4Bits = fieldFromInstruction(Bits, 0, 4);
1613
1614 DecodeMPRRegisterClass(Inst, Decoder);
1615 DecodeSimpleRegisterClass<AArch64::MatrixIndexGPR32_12_15RegClassID, 0, 4>(
1616 Inst, RvBits, Addr, Decoder);
1617 Inst.addOperand(MCOperand::createImm(Imm4Bits));
1618 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, RnBits,
1619 Addr, Decoder);
1620 // Spill and fill instructions have a single immediate used for both
1621 // the vector select offset and optional memory offset. Replicate
1622 // the decoded immediate.
1623 Inst.addOperand(MCOperand::createImm(Imm4Bits));
1624 return Success;
1625}
1626
1627#include "AArch64GenDisassemblerTables.inc"
1628#include "AArch64GenInstrInfo.inc"
1629
1630static MCDisassembler *createAArch64Disassembler(const Target &T,
1631 const MCSubtargetInfo &STI,
1632 MCContext &Ctx) {
1633
1634 return new AArch64Disassembler(STI, Ctx, T.createMCInstrInfo());
1635}
1636
1637DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
1638 ArrayRef<uint8_t> Bytes,
1639 uint64_t Address,
1640 raw_ostream &CS) const {
1641 CommentStream = &CS;
1642
1643 Size = 0;
1644 // We want to read exactly 4 bytes of data.
1645 if (Bytes.size() < 4)
1646 return Fail;
1647 Size = 4;
1648
1649 // Encoded as a small-endian 32-bit word in the stream.
1650 uint32_t Insn =
1651 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
1652
1653 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
1654
1655 for (const auto *Table : Tables) {
1656 DecodeStatus Result =
1657 decodeInstruction(Table, MI, Insn, Address, this, STI);
1658 if (Result != MCDisassembler::Fail)
1659 return Result;
1660 }
1661
1662 return MCDisassembler::Fail;
1663}
1664
1665uint64_t AArch64Disassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
1666 uint64_t Address) const {
1667 // AArch64 instructions are always 4 bytes wide, so there's no point
1668 // in skipping any smaller number of bytes if an instruction can't
1669 // be decoded.
1670 return 4;
1671}
1672
1673static MCSymbolizer *
1674createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
1675 LLVMSymbolLookupCallback SymbolLookUp,
1676 void *DisInfo, MCContext *Ctx,
1677 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1678 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
1679 SymbolLookUp, DisInfo);
1680}
1681
1682extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
DecodeUnconditionalBranch
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1278
DecodeMPR32RegisterClass
static DecodeStatus DecodeMPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:159
DecodePCRelLabel16
static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:213
DecodeMPR8RegisterClass
static DecodeStatus DecodeMPR8RegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:144
DecodeSystemPStateImm0_1Instruction
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1317
DecodeMPR64RegisterClass
static DecodeStatus DecodeMPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:168
DecodeVecShiftL64Imm
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:356
DecodeVecShiftL32Imm
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:362
DecodeHinteUImm16
static DecodeStatus DecodeHinteUImm16(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1457
createAArch64ExternalSymbolizer
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition AArch64Disassembler.cpp:1674
DecodeCPYMemOpInstruction
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1484
DecodeVecShiftR8Imm
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:350
DecodeUnsignedLdStInstruction
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:487
DecodeMPRRegisterClass
static DecodeStatus DecodeMPRRegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:138
DecodeMulMinMaxRegisterClass
static DecodeStatus DecodeMulMinMaxRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:76
DecodeModImmTiedInstruction
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1202
DecodeFixedPointScaleImm64
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:206
DecodeSystemPStateImm0_15Instruction
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1296
DecodeModImmInstruction
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1161
createAArch64Disassembler
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition AArch64Disassembler.cpp:1630
DecodeGPR64x8ClassRegisterClass
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:60
DecodeThreeAddrSRegInstruction
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:381
DecodeSETMemGoOpInstruction
static DecodeStatus DecodeSETMemGoOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1544
DecodeXSeqPairsClassRegisterClass
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1380
DecodeExclusiveLdStInstruction
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:756
DecodeVecShiftL16Imm
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:368
DecodeTestAndBranch
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1338
DecodeZeroImm
static DecodeStatus DecodeZeroImm(MCInst &Inst, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1425
SoftFail
#define SoftFail
Definition AArch64Disassembler.cpp:44
DecodeSImm
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1431
DecodeVecShiftR32ImmNarrow
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:332
DecodeZK
static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:100
DecodeAdrInstruction
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1222
DecodePPR2Mul2RegisterClass
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition AArch64Disassembler.cpp:186
DecodePairLdStInstruction
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:849
DecodeVecShiftL8Imm
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:374
DecodeSVEIncDecImm
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1468
DecodeMPR16RegisterClass
static DecodeStatus DecodeMPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:150
DecodeVecShiftRImm
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition AArch64Disassembler.cpp:302
DecodeFixedPointScaleImm32
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:197
DecodeMoveImmInstruction
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:448
DecodeVecShiftR64Imm
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:314
DecodePCRelLabel9
static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:239
DecodeVecShiftLImm
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition AArch64Disassembler.cpp:308
DecodeVecShiftR16ImmNarrow
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:344
DecodeSVCROp
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1475
DecodeWSeqPairsClassRegisterClass
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1373
DecodeVecShiftR64ImmNarrow
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:320
DecodeZPR4Mul4RegisterClass
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition AArch64Disassembler.cpp:111
DecodeSMESpillFillInstruction
static DecodeStatus DecodeSMESpillFillInstruction(MCInst &Inst, uint32_t Bits, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1608
DecodeLogicalImmInstruction
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1124
Fail
#define Fail
Definition AArch64Disassembler.cpp:43
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition AArch64Disassembler.cpp:36
DecodeMSRSystemRegister
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:267
DecodeZPR2Mul2RegisterClass
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition AArch64Disassembler.cpp:87
LLVMInitializeAArch64Disassembler
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
Definition AArch64Disassembler.cpp:1683
Success
#define Success
Definition AArch64Disassembler.cpp:42
DecodeSETMemOpInstruction
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1515
DecodeSVELogicalImmInstruction
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1408
DecodeMemExtend
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:249
DecodeSignedLdStInstruction
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:553
DecodeAuthLoadInstruction
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1014
DecodeSyspXzrInstruction
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1386
DecodeFMOVLaneInstruction
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:275
DecodeAddSubERegInstruction
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1049
isInvalidPState
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
Definition AArch64Disassembler.cpp:1289
DecodeSimpleRegisterClass
static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:47
DecodeMatrixTileListRegisterClass
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:123
DecodeVecShiftR16Imm
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:338
DecodeVecShiftR32Imm
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:326
DecodeImm8OptLsl
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1446
DecodePRFMRegInstruction
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1570
DecodeAddSubImmShift
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1237
DecodeGPRSeqPairsClassRegisterClass
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:1360
DecodeMPR128RegisterClass
static DecodeStatus DecodeMPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:177
DecodeMRSSystemRegister
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:257
DecodeZTRRegisterClass
static DecodeStatus DecodeZTRRegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:132
DecodePCRelLabel19
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AArch64Disassembler.cpp:228
Imm
unsigned Imm
Definition AMDGPUDisassembler.cpp:482
uint64_t
unsigned uint64_t
Definition AMDGPUDisassembler.cpp:483
Decoder
unsigned const MCDisassembler * Decoder
Definition AMDGPUDisassembler.cpp:484
LLVM_ABI
#define LLVM_ABI
Definition Compiler.h:215
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:866
Reg
Register Reg
Definition MachineSink.cpp:2130
T
#define T
Definition Mips16ISelLowering.cpp:282
llvm::AArch64Disassembler::getInstruction
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
Definition AArch64Disassembler.cpp:1637
llvm::AArch64Disassembler::suggestBytesToSkip
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
Definition AArch64Disassembler.cpp:1665
llvm::ArrayRef
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::ArrayRef::size
size_t size() const
Get the array size.
Definition ArrayRef.h:141
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition MCDisassembler.h:85
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition MCDisassembler.h:213
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition MCDisassembler.h:241
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition MCDisassembler.h:109
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition MCInst.h:202
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition MCInst.h:215
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition MCInst.h:210
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:41
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:141
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition MCSymbolizer.h:40
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::Target
Target - Wrapper for Target specific information.
Definition TargetRegistry.h:148
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition Triple.h:48
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint32_t
uint8_t
LLVMSymbolLookupCallback
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition DisassemblerTypes.h:118
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition DisassemblerTypes.h:48
llvm::AArch64_AM::isValidDecodeLogicalImmediate
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
Definition AArch64AddressingModes.h:334
llvm::MCD::fieldFromInstruction
std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)
Definition MCDecoder.h:37
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition AArch64TargetInfo.cpp:18
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition AArch64TargetInfo.cpp:14
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition AArch64TargetInfo.cpp:22
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition AArch64TargetInfo.cpp:30
llvm::RecurKind::Add
@ Add
Sum of integers.
Definition IVDescriptors.h:38
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition AArch64TargetInfo.cpp:26
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:567
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition TargetRegistry.h:1000
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition TargetRegistry.h:910
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