34#define DEBUG_TYPE "aarch64-disassembler"
76 uint64_t Address,
const void *Decoder);
125 const void *Decoder);
128 const void *Decoder);
131 const void *Decoder);
134 const void *Decoder);
135template <
unsigned NumBitsForTile>
157 const void *Decoder);
160 const void *Decoder);
285template <
int ElementW
idth>
303#include "AArch64GenDisassemblerTables.inc"
304#include "AArch64GenInstrInfo.inc"
306#define Success MCDisassembler::Success
307#define Fail MCDisassembler::Fail
308#define SoftFail MCDisassembler::SoftFail
325 if (Bytes.
size() < 4)
331 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
333 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
335 for (
const auto *Table : Tables) {
344 for (
unsigned i = 0; i <
Desc.getNumOperands(); i++) {
346 switch (
Desc.operands()[i].RegClass) {
349 case AArch64::MPRRegClassID:
352 case AArch64::MPR8RegClassID:
355 case AArch64::ZTRRegClassID:
359 }
else if (
Desc.operands()[i].OperandType ==
365 if (
MI.getOpcode() == AArch64::LDR_ZA ||
366 MI.getOpcode() == AArch64::STR_ZA) {
371 assert(Imm4Op.
isImm() &&
"Unexpected operand type!");
372 MI.addOperand(Imm4Op);
394 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
396 SymbolLookUp, DisInfo);
430 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
458 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
470 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
482 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
494 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
506 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
519 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
533 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
545 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
557 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_8_11RegClassID]
571 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
584 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
596 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
608 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
635 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
646 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
657 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
664 const void *Decoder) {
668 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2);
675 const void *Decoder) {
679 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
686 const void *Decoder) {
690 AArch64MCRegisterClasses[AArch64::ZPR2StridedRegClassID].getRegister(
698 const void *Decoder) {
702 AArch64MCRegisterClasses[AArch64::ZPR4StridedRegClassID].getRegister(
720 {AArch64::ZAH0, AArch64::ZAH1},
721 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
722 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4,
723 AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
724 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4,
725 AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9,
726 AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
727 AArch64::ZAQ14, AArch64::ZAQ15}};
729template <
unsigned NumBitsForTile>
733 unsigned LastReg = (1 << NumBitsForTile) - 1;
748 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
760 AArch64MCRegisterClasses[AArch64::PNRRegClassID].getRegister(RegNo);
787 const void *Decoder) {
792 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo);
799 const void *Decoder) {
800 if ((RegNo * 2) > 14)
803 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
814 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
825 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
836 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
847 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
858 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
869 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
893 int64_t ImmVal = Imm;
896 if (ImmVal & (1 << (19 - 1)))
897 ImmVal |= ~((1LL << 19) - 1);
900 Inst, ImmVal * 4,
Addr, Inst.
getOpcode() != AArch64::LDRXl, 0, 0, 4))
936 unsigned Rd = fieldFromInstruction(
Insn, 0, 5);
937 unsigned Rn = fieldFromInstruction(
Insn, 5, 5);
938 unsigned IsToVec = fieldFromInstruction(
Insn, 16, 1);
1035 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1036 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1037 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1038 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
1039 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
1040 unsigned shift = (shiftHi << 6) | shiftLo;
1044 case AArch64::ADDWrs:
1045 case AArch64::ADDSWrs:
1046 case AArch64::SUBWrs:
1047 case AArch64::SUBSWrs:
1052 case AArch64::ANDWrs:
1053 case AArch64::ANDSWrs:
1054 case AArch64::BICWrs:
1055 case AArch64::BICSWrs:
1056 case AArch64::ORRWrs:
1057 case AArch64::ORNWrs:
1058 case AArch64::EORWrs:
1059 case AArch64::EONWrs: {
1061 if (shiftLo >> 5 == 1)
1068 case AArch64::ADDXrs:
1069 case AArch64::ADDSXrs:
1070 case AArch64::SUBXrs:
1071 case AArch64::SUBSXrs:
1076 case AArch64::ANDXrs:
1077 case AArch64::ANDSXrs:
1078 case AArch64::BICXrs:
1079 case AArch64::BICSXrs:
1080 case AArch64::ORRXrs:
1081 case AArch64::ORNXrs:
1082 case AArch64::EORXrs:
1083 case AArch64::EONXrs:
1097 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1098 unsigned imm = fieldFromInstruction(insn, 5, 16);
1099 unsigned shift = fieldFromInstruction(insn, 21, 2);
1104 case AArch64::MOVZWi:
1105 case AArch64::MOVNWi:
1106 case AArch64::MOVKWi:
1107 if (shift & (1U << 5))
1111 case AArch64::MOVZXi:
1112 case AArch64::MOVNXi:
1113 case AArch64::MOVKXi:
1118 if (Inst.
getOpcode() == AArch64::MOVKWi ||
1130 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1131 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1132 unsigned offset = fieldFromInstruction(insn, 10, 12);
1137 case AArch64::PRFMui:
1141 case AArch64::STRBBui:
1142 case AArch64::LDRBBui:
1143 case AArch64::LDRSBWui:
1144 case AArch64::STRHHui:
1145 case AArch64::LDRHHui:
1146 case AArch64::LDRSHWui:
1147 case AArch64::STRWui:
1148 case AArch64::LDRWui:
1151 case AArch64::LDRSBXui:
1152 case AArch64::LDRSHXui:
1153 case AArch64::LDRSWui:
1154 case AArch64::STRXui:
1155 case AArch64::LDRXui:
1158 case AArch64::LDRQui:
1159 case AArch64::STRQui:
1162 case AArch64::LDRDui:
1163 case AArch64::STRDui:
1166 case AArch64::LDRSui:
1167 case AArch64::STRSui:
1170 case AArch64::LDRHui:
1171 case AArch64::STRHui:
1174 case AArch64::LDRBui:
1175 case AArch64::STRBui:
1189 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1190 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1191 int64_t offset = fieldFromInstruction(insn, 12, 9);
1195 if (offset & (1 << (9 - 1)))
1196 offset |= ~((1LL << 9) - 1);
1202 case AArch64::LDRSBWpre:
1203 case AArch64::LDRSHWpre:
1204 case AArch64::STRBBpre:
1205 case AArch64::LDRBBpre:
1206 case AArch64::STRHHpre:
1207 case AArch64::LDRHHpre:
1208 case AArch64::STRWpre:
1209 case AArch64::LDRWpre:
1210 case AArch64::LDRSBWpost:
1211 case AArch64::LDRSHWpost:
1212 case AArch64::STRBBpost:
1213 case AArch64::LDRBBpost:
1214 case AArch64::STRHHpost:
1215 case AArch64::LDRHHpost:
1216 case AArch64::STRWpost:
1217 case AArch64::LDRWpost:
1218 case AArch64::LDRSBXpre:
1219 case AArch64::LDRSHXpre:
1220 case AArch64::STRXpre:
1221 case AArch64::LDRSWpre:
1222 case AArch64::LDRXpre:
1223 case AArch64::LDRSBXpost:
1224 case AArch64::LDRSHXpost:
1225 case AArch64::STRXpost:
1226 case AArch64::LDRSWpost:
1227 case AArch64::LDRXpost:
1228 case AArch64::LDRQpre:
1229 case AArch64::STRQpre:
1230 case AArch64::LDRQpost:
1231 case AArch64::STRQpost:
1232 case AArch64::LDRDpre:
1233 case AArch64::STRDpre:
1234 case AArch64::LDRDpost:
1235 case AArch64::STRDpost:
1236 case AArch64::LDRSpre:
1237 case AArch64::STRSpre:
1238 case AArch64::LDRSpost:
1239 case AArch64::STRSpost:
1240 case AArch64::LDRHpre:
1241 case AArch64::STRHpre:
1242 case AArch64::LDRHpost:
1243 case AArch64::STRHpost:
1244 case AArch64::LDRBpre:
1245 case AArch64::STRBpre:
1246 case AArch64::LDRBpost:
1247 case AArch64::STRBpost:
1255 case AArch64::PRFUMi:
1259 case AArch64::STURBBi:
1260 case AArch64::LDURBBi:
1261 case AArch64::LDURSBWi:
1262 case AArch64::STURHHi:
1263 case AArch64::LDURHHi:
1264 case AArch64::LDURSHWi:
1265 case AArch64::STURWi:
1266 case AArch64::LDURWi:
1267 case AArch64::LDTRSBWi:
1268 case AArch64::LDTRSHWi:
1269 case AArch64::STTRWi:
1270 case AArch64::LDTRWi:
1271 case AArch64::STTRHi:
1272 case AArch64::LDTRHi:
1273 case AArch64::LDTRBi:
1274 case AArch64::STTRBi:
1275 case AArch64::LDRSBWpre:
1276 case AArch64::LDRSHWpre:
1277 case AArch64::STRBBpre:
1278 case AArch64::LDRBBpre:
1279 case AArch64::STRHHpre:
1280 case AArch64::LDRHHpre:
1281 case AArch64::STRWpre:
1282 case AArch64::LDRWpre:
1283 case AArch64::LDRSBWpost:
1284 case AArch64::LDRSHWpost:
1285 case AArch64::STRBBpost:
1286 case AArch64::LDRBBpost:
1287 case AArch64::STRHHpost:
1288 case AArch64::LDRHHpost:
1289 case AArch64::STRWpost:
1290 case AArch64::LDRWpost:
1291 case AArch64::STLURBi:
1292 case AArch64::STLURHi:
1293 case AArch64::STLURWi:
1294 case AArch64::LDAPURBi:
1295 case AArch64::LDAPURSBWi:
1296 case AArch64::LDAPURHi:
1297 case AArch64::LDAPURSHWi:
1298 case AArch64::LDAPURi:
1301 case AArch64::LDURSBXi:
1302 case AArch64::LDURSHXi:
1303 case AArch64::LDURSWi:
1304 case AArch64::STURXi:
1305 case AArch64::LDURXi:
1306 case AArch64::LDTRSBXi:
1307 case AArch64::LDTRSHXi:
1308 case AArch64::LDTRSWi:
1309 case AArch64::STTRXi:
1310 case AArch64::LDTRXi:
1311 case AArch64::LDRSBXpre:
1312 case AArch64::LDRSHXpre:
1313 case AArch64::STRXpre:
1314 case AArch64::LDRSWpre:
1315 case AArch64::LDRXpre:
1316 case AArch64::LDRSBXpost:
1317 case AArch64::LDRSHXpost:
1318 case AArch64::STRXpost:
1319 case AArch64::LDRSWpost:
1320 case AArch64::LDRXpost:
1321 case AArch64::LDAPURSWi:
1322 case AArch64::LDAPURSHXi:
1323 case AArch64::LDAPURSBXi:
1324 case AArch64::STLURXi:
1325 case AArch64::LDAPURXi:
1328 case AArch64::LDURQi:
1329 case AArch64::STURQi:
1330 case AArch64::LDRQpre:
1331 case AArch64::STRQpre:
1332 case AArch64::LDRQpost:
1333 case AArch64::STRQpost:
1336 case AArch64::LDURDi:
1337 case AArch64::STURDi:
1338 case AArch64::LDRDpre:
1339 case AArch64::STRDpre:
1340 case AArch64::LDRDpost:
1341 case AArch64::STRDpost:
1344 case AArch64::LDURSi:
1345 case AArch64::STURSi:
1346 case AArch64::LDRSpre:
1347 case AArch64::STRSpre:
1348 case AArch64::LDRSpost:
1349 case AArch64::STRSpost:
1352 case AArch64::LDURHi:
1353 case AArch64::STURHi:
1354 case AArch64::LDRHpre:
1355 case AArch64::STRHpre:
1356 case AArch64::LDRHpost:
1357 case AArch64::STRHpost:
1360 case AArch64::LDURBi:
1361 case AArch64::STURBi:
1362 case AArch64::LDRBpre:
1363 case AArch64::STRBpre:
1364 case AArch64::LDRBpost:
1365 case AArch64::STRBpost:
1373 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1374 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1375 bool IsFP = fieldFromInstruction(insn, 26, 1);
1378 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1387 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1388 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1389 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1390 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1396 case AArch64::STLXRW:
1397 case AArch64::STLXRB:
1398 case AArch64::STLXRH:
1399 case AArch64::STXRW:
1400 case AArch64::STXRB:
1401 case AArch64::STXRH:
1404 case AArch64::LDARW:
1405 case AArch64::LDARB:
1406 case AArch64::LDARH:
1407 case AArch64::LDAXRW:
1408 case AArch64::LDAXRB:
1409 case AArch64::LDAXRH:
1410 case AArch64::LDXRW:
1411 case AArch64::LDXRB:
1412 case AArch64::LDXRH:
1413 case AArch64::STLRW:
1414 case AArch64::STLRB:
1415 case AArch64::STLRH:
1416 case AArch64::STLLRW:
1417 case AArch64::STLLRB:
1418 case AArch64::STLLRH:
1419 case AArch64::LDLARW:
1420 case AArch64::LDLARB:
1421 case AArch64::LDLARH:
1424 case AArch64::STLXRX:
1425 case AArch64::STXRX:
1428 case AArch64::LDARX:
1429 case AArch64::LDAXRX:
1430 case AArch64::LDXRX:
1431 case AArch64::STLRX:
1432 case AArch64::LDLARX:
1433 case AArch64::STLLRX:
1436 case AArch64::STLXPW:
1437 case AArch64::STXPW:
1440 case AArch64::LDAXPW:
1441 case AArch64::LDXPW:
1445 case AArch64::STLXPX:
1446 case AArch64::STXPX:
1449 case AArch64::LDAXPX:
1450 case AArch64::LDXPX:
1459 if ((
Opcode == AArch64::LDAXPW ||
Opcode == AArch64::LDXPW ||
1460 Opcode == AArch64::LDAXPX ||
Opcode == AArch64::LDXPX) &&
1470 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1471 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1472 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1473 int64_t offset = fieldFromInstruction(insn, 15, 7);
1474 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1478 if (offset & (1 << (7 - 1)))
1479 offset |= ~((1LL << 7) - 1);
1482 bool NeedsDisjointWritebackTransfer =
false;
1488 case AArch64::LDPXpost:
1489 case AArch64::STPXpost:
1490 case AArch64::LDPSWpost:
1491 case AArch64::LDPXpre:
1492 case AArch64::STPXpre:
1493 case AArch64::LDPSWpre:
1494 case AArch64::LDPWpost:
1495 case AArch64::STPWpost:
1496 case AArch64::LDPWpre:
1497 case AArch64::STPWpre:
1498 case AArch64::LDPQpost:
1499 case AArch64::STPQpost:
1500 case AArch64::LDPQpre:
1501 case AArch64::STPQpre:
1502 case AArch64::LDPDpost:
1503 case AArch64::STPDpost:
1504 case AArch64::LDPDpre:
1505 case AArch64::STPDpre:
1506 case AArch64::LDPSpost:
1507 case AArch64::STPSpost:
1508 case AArch64::LDPSpre:
1509 case AArch64::STPSpre:
1510 case AArch64::STGPpre:
1511 case AArch64::STGPpost:
1519 case AArch64::LDPXpost:
1520 case AArch64::STPXpost:
1521 case AArch64::LDPSWpost:
1522 case AArch64::LDPXpre:
1523 case AArch64::STPXpre:
1524 case AArch64::LDPSWpre:
1525 case AArch64::STGPpre:
1526 case AArch64::STGPpost:
1527 NeedsDisjointWritebackTransfer =
true;
1529 case AArch64::LDNPXi:
1530 case AArch64::STNPXi:
1531 case AArch64::LDPXi:
1532 case AArch64::STPXi:
1533 case AArch64::LDPSWi:
1534 case AArch64::STGPi:
1538 case AArch64::LDPWpost:
1539 case AArch64::STPWpost:
1540 case AArch64::LDPWpre:
1541 case AArch64::STPWpre:
1542 NeedsDisjointWritebackTransfer =
true;
1544 case AArch64::LDNPWi:
1545 case AArch64::STNPWi:
1546 case AArch64::LDPWi:
1547 case AArch64::STPWi:
1551 case AArch64::LDNPQi:
1552 case AArch64::STNPQi:
1553 case AArch64::LDPQpost:
1554 case AArch64::STPQpost:
1555 case AArch64::LDPQi:
1556 case AArch64::STPQi:
1557 case AArch64::LDPQpre:
1558 case AArch64::STPQpre:
1562 case AArch64::LDNPDi:
1563 case AArch64::STNPDi:
1564 case AArch64::LDPDpost:
1565 case AArch64::STPDpost:
1566 case AArch64::LDPDi:
1567 case AArch64::STPDi:
1568 case AArch64::LDPDpre:
1569 case AArch64::STPDpre:
1573 case AArch64::LDNPSi:
1574 case AArch64::STNPSi:
1575 case AArch64::LDPSpost:
1576 case AArch64::STPSpost:
1577 case AArch64::LDPSi:
1578 case AArch64::STPSi:
1579 case AArch64::LDPSpre:
1580 case AArch64::STPSpre:
1590 if (IsLoad && Rt == Rt2)
1595 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1604 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1605 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1606 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1607 fieldFromInstruction(insn, 12, 9);
1608 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1613 case AArch64::LDRAAwriteback:
1614 case AArch64::LDRABwriteback:
1618 case AArch64::LDRAAindexed:
1619 case AArch64::LDRABindexed:
1625 DecodeSImm<10>(Inst, offset,
Addr, Decoder);
1627 if (writeback && Rt == Rn && Rn != 31) {
1637 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1638 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1639 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1640 unsigned extend = fieldFromInstruction(insn, 10, 6);
1642 unsigned shift = extend & 0x7;
1649 case AArch64::ADDWrx:
1650 case AArch64::SUBWrx:
1655 case AArch64::ADDSWrx:
1656 case AArch64::SUBSWrx:
1661 case AArch64::ADDXrx:
1662 case AArch64::SUBXrx:
1667 case AArch64::ADDSXrx:
1668 case AArch64::SUBSXrx:
1673 case AArch64::ADDXrx64:
1674 case AArch64::SUBXrx64:
1679 case AArch64::SUBSXrx64:
1680 case AArch64::ADDSXrx64:
1694 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1695 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1696 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1700 if (Inst.
getOpcode() == AArch64::ANDSXri)
1705 imm = fieldFromInstruction(insn, 10, 13);
1709 if (Inst.
getOpcode() == AArch64::ANDSWri)
1714 imm = fieldFromInstruction(insn, 10, 12);
1725 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1726 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1727 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1728 imm |= fieldFromInstruction(insn, 5, 5);
1740 case AArch64::MOVIv4i16:
1741 case AArch64::MOVIv8i16:
1742 case AArch64::MVNIv4i16:
1743 case AArch64::MVNIv8i16:
1744 case AArch64::MOVIv2i32:
1745 case AArch64::MOVIv4i32:
1746 case AArch64::MVNIv2i32:
1747 case AArch64::MVNIv4i32:
1750 case AArch64::MOVIv2s_msl:
1751 case AArch64::MOVIv4s_msl:
1752 case AArch64::MVNIv2s_msl:
1753 case AArch64::MVNIv4s_msl:
1764 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1765 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1766 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1767 imm |= fieldFromInstruction(insn, 5, 5);
1782 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1783 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1784 imm |= fieldFromInstruction(insn, 29, 2);
1787 if (imm & (1 << (21 - 1)))
1788 imm |= ~((1LL << 21) - 1);
1800 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1801 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1802 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1803 unsigned S = fieldFromInstruction(insn, 29, 1);
1804 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1806 unsigned ShifterVal = (Imm >> 12) & 3;
1807 unsigned ImmVal = Imm & 0xFFF;
1809 if (ShifterVal != 0 && ShifterVal != 1)
1835 int64_t imm = fieldFromInstruction(insn, 0, 26);
1838 if (imm & (1 << (26 - 1)))
1839 imm |= ~((1LL << 26) - 1);
1848 return Op1 == 0b000 && (Op2 == 0b000 ||
1856 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1857 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1858 uint64_t imm = fieldFromInstruction(insn, 8, 4);
1859 uint64_t pstate_field = (op1 << 3) | op2;
1867 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1877 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1878 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1879 uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1880 uint64_t imm = fieldFromInstruction(insn, 8, 1);
1881 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1889 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1899 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1900 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1901 bit |= fieldFromInstruction(insn, 19, 5);
1902 int64_t dst = fieldFromInstruction(insn, 5, 14);
1905 if (dst & (1 << (14 - 1)))
1906 dst |= ~((1LL << 14) - 1);
1908 if (fieldFromInstruction(insn, 31, 1) == 0)
1927 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1936 AArch64::WSeqPairsClassRegClassID,
1937 RegNo,
Addr, Decoder);
1944 AArch64::XSeqPairsClassRegClassID,
1945 RegNo,
Addr, Decoder);
1951 unsigned op1 = fieldFromInstruction(insn, 16, 3);
1952 unsigned CRn = fieldFromInstruction(insn, 12, 4);
1953 unsigned CRm = fieldFromInstruction(insn, 8, 4);
1954 unsigned op2 = fieldFromInstruction(insn, 5, 3);
1955 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1971 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1972 unsigned imm = fieldFromInstruction(insn, 5, 13);
1978 if (Inst.
getOpcode() != AArch64::DUPM_ZI)
1987 if (Imm & ~((1LL << Bits) - 1))
1991 if (Imm & (1 << (Bits - 1)))
1992 Imm |= ~((1LL << Bits) - 1);
1999template <
int ElementW
idth>
2002 unsigned Val = (uint8_t)Imm;
2003 unsigned Shift = (Imm & 0x100) ? 8 : 0;
2004 if (ElementWidth == 8 && Shift)
2021 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
2031 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2032 unsigned Rs = fieldFromInstruction(insn, 16, 5);
2033 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2037 if (Rd == Rs || Rs == Rn || Rd == Rn)
2056 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2057 unsigned Rm = fieldFromInstruction(insn, 16, 5);
2058 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2062 if (Rd == Rm || Rm == Rn || Rd == Rn)
2082 unsigned Mask = 0x18;
2083 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
2084 if ((Rt & Mask) == Mask)
2087 uint64_t Rn = fieldFromInstruction(insn, 5, 5);
2088 uint64_t Shift = fieldFromInstruction(insn, 12, 1);
2089 uint64_t Extend = fieldFromInstruction(insn, 15, 1);
2090 uint64_t Rm = fieldFromInstruction(insn, 16, 5);
2098 case AArch64::PRFMroW:
2101 case AArch64::PRFMroX:
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const MCPhysReg MatrixZATileDecoderTable[5][16]
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR128_0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
static DecodeStatus DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static constexpr uint32_t RegMask
static constexpr uint32_t Opcode
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Context object for machine code objects.
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
const MCSubtargetInfo & getSubtargetInfo() const
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
Symbolize and annotate disassembled instructions.
Wrapper class representing virtual and physical registers.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
This class implements an extremely fast bulk output stream that can only output to a stream.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheAArch64beTarget()
Target & getTheAArch64leTarget()
Target & getTheAArch64_32Target()
Target & getTheARM64_32Target()
Target & getTheARM64Target()
Description of the encoding of one expression Op.
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.