26 #define DEBUG_TYPE "xcore-disassembler"
47 if (Bytes.
size() < 2) {
52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
59 if (Bytes.
size() < 4) {
65 (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);
174 #include "XCoreGenDisassemblerTables.inc"
181 unsigned Reg =
getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
191 unsigned Reg =
getReg(Decoder, XCore::RRegsRegClassID, RegNo);
201 static const unsigned Values[] = {
202 32 , 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
217 unsigned Combined = fieldFromInstruction(
Insn, 6, 5);
220 if (fieldFromInstruction(
Insn, 5, 1)) {
226 unsigned Op1High = Combined % 3;
227 unsigned Op2High = Combined / 3;
228 Op1 = (Op1High << 2) | fieldFromInstruction(
Insn, 2, 2);
229 Op2 = (Op2High << 2) | fieldFromInstruction(
Insn, 0, 2);
236 unsigned Combined = fieldFromInstruction(
Insn, 6, 5);
240 unsigned Op1High = Combined % 3;
241 unsigned Op2High = (Combined / 3) % 3;
242 unsigned Op3High = Combined / 9;
243 Op1 = (Op1High << 2) | fieldFromInstruction(
Insn, 4, 2);
244 Op2 = (Op2High << 2) | fieldFromInstruction(
Insn, 2, 2);
245 Op3 = (Op3High << 2) | fieldFromInstruction(
Insn, 0, 2);
253 unsigned Opcode = fieldFromInstruction(
Insn, 11, 5);
416 unsigned Opcode = fieldFromInstruction(
Insn, 16, 4) |
417 fieldFromInstruction(
Insn, 27, 5) << 4;
514 unsigned Op1, Op2, Op3;
527 unsigned Op1, Op2, Op3;
540 unsigned Op1, Op2, Op3;
553 unsigned Op1, Op2, Op3;
566 unsigned Op1, Op2, Op3;
580 unsigned Op1, Op2, Op3;
595 unsigned Op1, Op2, Op3;
609 unsigned Op1, Op2, Op3;
623 unsigned Op1, Op2, Op3, Op4, Op5, Op6;
645 unsigned Opcode = fieldFromInstruction(
Insn, 27, 5);
657 unsigned Op1, Op2, Op3, Op4, Op5;
677 unsigned Op1, Op2, Op3;
678 unsigned Op4 = fieldFromInstruction(
Insn, 16, 4);
696 unsigned Op1, Op2, Op3;
697 unsigned Op4 = fieldFromInstruction(
Insn, 16, 4);
726 if (Result !=
Fail) {
738 Result = decodeInstruction(DecoderTable32, instr, insn32, Address,
this, STI);
739 if (Result !=
Fail) {
750 return new XCoreDisassembler(STI, Ctx);