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13 #ifndef LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
14 #define LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
19 #define GET_INSTRINFO_HEADER
20 #include "XCoreGenInstrInfo.inc"
26 virtual void anchor();
55 bool AllowModify)
const override;
60 int *BytesAdded =
nullptr)
const override;
63 int *BytesRemoved =
nullptr)
const override;
67 bool KillSrc)
const override;
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
This is an optimization pass for GlobalISel generic memory operations.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
analyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
Reg
All possible values of the reg field in the ModR/M byte.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned const TargetRegisterInfo * TRI
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
Representation of each machine instruction.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
SmallVector< MachineOperand, 4 > Cond
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Wrapper class representing virtual and physical registers.
const TargetRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
LLVM Value Representation.
Wrapper class representing physical registers. Should be passed by value.