LLVM 20.0.0git
XCoreInstrInfo.h
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1//===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the XCore implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
14#define LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
15
16#include "XCoreRegisterInfo.h"
18
19#define GET_INSTRINFO_HEADER
20#include "XCoreGenInstrInfo.inc"
21
22namespace llvm {
23
25 const XCoreRegisterInfo RI;
26 virtual void anchor();
27public:
29
30 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
31 /// such, whenever a client has an instance of instruction info, it should
32 /// always be able to get register info as well (through this method).
33 ///
34 const TargetRegisterInfo &getRegisterInfo() const { return RI; }
35
36 /// isLoadFromStackSlot - If the specified machine instruction is a direct
37 /// load from a stack slot, return the virtual or physical register number of
38 /// the destination along with the FrameIndex of the loaded stack slot. If
39 /// not, return 0. This predicate must return 0 if the instruction has
40 /// any side effects other than loading from the stack slot.
42 int &FrameIndex) const override;
43
44 /// isStoreToStackSlot - If the specified machine instruction is a direct
45 /// store to a stack slot, return the virtual or physical register number of
46 /// the source reg along with the FrameIndex of the loaded stack slot. If
47 /// not, return 0. This predicate must return 0 if the instruction has
48 /// any side effects other than storing to the stack slot.
50 int &FrameIndex) const override;
51
55 bool AllowModify) const override;
56
59 const DebugLoc &DL,
60 int *BytesAdded = nullptr) const override;
61
63 int *BytesRemoved = nullptr) const override;
64
66 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
67 bool KillSrc) const override;
68
71 bool isKill, int FrameIndex,
72 const TargetRegisterClass *RC,
74 Register VReg) const override;
75
78 int FrameIndex, const TargetRegisterClass *RC,
80 Register VReg) const override;
81
84
85 // Emit code before MBBI to load immediate value into physical register Reg.
86 // Returns an iterator to the new instruction.
89 unsigned Reg, uint64_t Value) const;
90};
91
92}
93
94#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:69
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition: Value.h:74
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
analyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
const TargetRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18