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30 #define GET_INSTRINFO_CTOR_DTOR
31 #include "XCoreGenInstrInfo.inc"
46 void XCoreInstrInfo::anchor() {}
54 return op.isImm() &&
op.getImm() == 0;
64 int Opcode =
MI.getOpcode();
65 if (Opcode == XCore::LDWFI)
67 if ((
MI.getOperand(1).isFI()) &&
68 (
MI.getOperand(2).isImm()) &&
71 return MI.getOperand(0).getReg();
84 int Opcode =
MI.getOpcode();
85 if (Opcode == XCore::STWFI)
87 if ((
MI.getOperand(1).isFI()) &&
88 (
MI.getOperand(2).isImm()) &&
91 return MI.getOperand(0).getReg();
101 static inline bool IsBRU(
unsigned BrOpc) {
102 return BrOpc == XCore::BRFU_u6
103 || BrOpc == XCore::BRFU_lu6
104 || BrOpc == XCore::BRBU_u6
105 || BrOpc == XCore::BRBU_lu6;
108 static inline bool IsBRT(
unsigned BrOpc) {
109 return BrOpc == XCore::BRFT_ru6
110 || BrOpc == XCore::BRFT_lru6
111 || BrOpc == XCore::BRBT_ru6
112 || BrOpc == XCore::BRBT_lru6;
115 static inline bool IsBRF(
unsigned BrOpc) {
116 return BrOpc == XCore::BRFF_ru6
117 || BrOpc == XCore::BRFF_lru6
118 || BrOpc == XCore::BRBF_ru6
119 || BrOpc == XCore::BRBF_lru6;
137 }
else if (
IsBRF(BrOpc)) {
193 bool AllowModify)
const {
199 if (!isUnpredicatedTerminator(*
I))
206 if (
I ==
MBB.
begin() || !isUnpredicatedTerminator(*--
I)) {
229 if (SecondLastInst &&
I !=
MBB.
begin() && isUnpredicatedTerminator(*--
I))
232 unsigned SecondLastOpc = SecondLastInst->
getOpcode();
255 I->eraseFromParent();
263 I->eraseFromParent();
276 int *BytesAdded)
const {
278 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
280 "Unexpected number of components!");
281 assert(!BytesAdded &&
"code size not handled");
297 assert(
Cond.size() == 2 &&
"Unexpected number of components!");
307 assert(!BytesRemoved &&
"code size not handled");
317 I->eraseFromParent();
327 I->eraseFromParent();
335 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
336 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
338 if (GRDest && GRSrc) {
345 if (GRDest && SrcReg == XCore::SP) {
350 if (DestReg == XCore::SP && GRSrc) {
366 if (
I !=
MBB.
end() && !
I->isDebugInstr())
367 DL =
I->getDebugLoc();
388 if (
I !=
MBB.
end() && !
I->isDebugInstr())
389 DL =
I->getDebugLoc();
405 "Invalid XCore branch condition!");
411 return val < (1 << 6);
415 return val < (1 << 16);
423 return (
N >= 1 &&
N <= 8) ||
N == 16 ||
N == 24 ||
N == 32;
429 unsigned Reg, uint64_t
Value)
const {
432 dl =
MI->getDebugLoc();
440 int Opcode =
isImmU6(
Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
static bool isImmMskBitp(unsigned val)
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
static XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified condition, e.g.
static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
GetCondFromBranchOpc - Return the XCore CC that matches the correspondent Branch instruction opcode.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static bool IsBRU(unsigned BrOpc)
@ BR_JT
BR_JT - Jumptable branch.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
analyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
static bool IsBRF(unsigned BrOpc)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
A description of a memory reference used in the backend.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned const TargetRegisterInfo * TRI
static IntegerType * getInt32Ty(LLVMContext &C)
static bool isImmU6(unsigned val)
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
static unsigned GetCondBranchFromCond(XCore::CondCode CC)
GetCondBranchFromCond - Return the Branch instruction opcode that matches the cc.
static MachineOperand CreateImm(int64_t Val)
(vector float) vec_cmpeq(*A, *B) C
const MachineOperand & getOperand(unsigned i) const
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
MachineOperand class - Representation of each machine instruction operand.
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const MachineInstrBuilder & addFrameIndex(int Idx) const
The initial backend is deliberately restricted to z10 We should add support for later architectures at some point If an asm ties an i32 r result to an i64 the input will be treated as an leaving the upper bits uninitialised For i64 store i32 val
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
This is an important base class in LLVM.
Representation of each machine instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static bool IsCondBranch(unsigned BrOpc)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
constexpr bool isMask_32(uint32_t Value)
Return true if the argument is a non-empty sequence of ones starting at the least significant bit wit...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
MachineBasicBlock * getMBB() const
SmallVector< MachineOperand, 4 > Cond
iterator getLastNonDebugInstr(bool SkipPseudoOp=false)
Returns an iterator to the last non-debug instruction in the basic block, or end().
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
@ MOLoad
The memory access reads data.
Wrapper class representing virtual and physical registers.
Function & getFunction()
Return the LLVM function that this machine code represents.
static bool isImmU16(unsigned val)
Should compile to something r4 addze r3 instead we get
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
@ MOStore
The memory access writes data.
unsigned getKillRegState(bool B)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
static bool IsBR_JT(unsigned BrOpc)
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static bool isZeroImm(const MachineOperand &op)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
static bool IsBRT(unsigned BrOpc)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
LLVM Value Representation.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Wrapper class representing physical registers. Should be passed by value.