LLVM  10.0.0svn
Mips16ISelLowering.cpp
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1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Subclass of MipsTargetLowering specialized for mips16.
10 //
11 //===----------------------------------------------------------------------===//
12 #include "Mips16ISelLowering.h"
14 #include "Mips16HardFloatInfo.h"
15 #include "MipsMachineFunction.h"
16 #include "MipsRegisterInfo.h"
17 #include "MipsTargetMachine.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "mips-lower"
25 
27  "mips16-dont-expand-cond-pseudo",
28  cl::init(false),
29  cl::desc("Don't expand conditional move related "
30  "pseudos for Mips 16"),
31  cl::Hidden);
32 
33 namespace {
34 struct Mips16Libcall {
36  const char *Name;
37 
38  bool operator<(const Mips16Libcall &RHS) const {
39  return std::strcmp(Name, RHS.Name) < 0;
40  }
41 };
42 
43 struct Mips16IntrinsicHelperType{
44  const char* Name;
45  const char* Helper;
46 
47  bool operator<(const Mips16IntrinsicHelperType &RHS) const {
48  return std::strcmp(Name, RHS.Name) < 0;
49  }
50  bool operator==(const Mips16IntrinsicHelperType &RHS) const {
51  return std::strcmp(Name, RHS.Name) == 0;
52  }
53 };
54 }
55 
56 // Libcalls for which no helper is generated. Sorted by name for binary search.
57 static const Mips16Libcall HardFloatLibCalls[] = {
58  { RTLIB::ADD_F64, "__mips16_adddf3" },
59  { RTLIB::ADD_F32, "__mips16_addsf3" },
60  { RTLIB::DIV_F64, "__mips16_divdf3" },
61  { RTLIB::DIV_F32, "__mips16_divsf3" },
62  { RTLIB::OEQ_F64, "__mips16_eqdf2" },
63  { RTLIB::OEQ_F32, "__mips16_eqsf2" },
64  { RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" },
65  { RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" },
66  { RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" },
67  { RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" },
68  { RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" },
69  { RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" },
70  { RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" },
71  { RTLIB::OGE_F64, "__mips16_gedf2" },
72  { RTLIB::OGE_F32, "__mips16_gesf2" },
73  { RTLIB::OGT_F64, "__mips16_gtdf2" },
74  { RTLIB::OGT_F32, "__mips16_gtsf2" },
75  { RTLIB::OLE_F64, "__mips16_ledf2" },
76  { RTLIB::OLE_F32, "__mips16_lesf2" },
77  { RTLIB::OLT_F64, "__mips16_ltdf2" },
78  { RTLIB::OLT_F32, "__mips16_ltsf2" },
79  { RTLIB::MUL_F64, "__mips16_muldf3" },
80  { RTLIB::MUL_F32, "__mips16_mulsf3" },
81  { RTLIB::UNE_F64, "__mips16_nedf2" },
82  { RTLIB::UNE_F32, "__mips16_nesf2" },
83  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall.
84  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall.
85  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall.
86  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall.
87  { RTLIB::SUB_F64, "__mips16_subdf3" },
88  { RTLIB::SUB_F32, "__mips16_subsf3" },
89  { RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" },
90  { RTLIB::UO_F64, "__mips16_unorddf2" },
91  { RTLIB::UO_F32, "__mips16_unordsf2" }
92 };
93 
94 static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
95  {"__fixunsdfsi", "__mips16_call_stub_2" },
96  {"ceil", "__mips16_call_stub_df_2"},
97  {"ceilf", "__mips16_call_stub_sf_1"},
98  {"copysign", "__mips16_call_stub_df_10"},
99  {"copysignf", "__mips16_call_stub_sf_5"},
100  {"cos", "__mips16_call_stub_df_2"},
101  {"cosf", "__mips16_call_stub_sf_1"},
102  {"exp2", "__mips16_call_stub_df_2"},
103  {"exp2f", "__mips16_call_stub_sf_1"},
104  {"floor", "__mips16_call_stub_df_2"},
105  {"floorf", "__mips16_call_stub_sf_1"},
106  {"log2", "__mips16_call_stub_df_2"},
107  {"log2f", "__mips16_call_stub_sf_1"},
108  {"nearbyint", "__mips16_call_stub_df_2"},
109  {"nearbyintf", "__mips16_call_stub_sf_1"},
110  {"rint", "__mips16_call_stub_df_2"},
111  {"rintf", "__mips16_call_stub_sf_1"},
112  {"sin", "__mips16_call_stub_df_2"},
113  {"sinf", "__mips16_call_stub_sf_1"},
114  {"sqrt", "__mips16_call_stub_df_2"},
115  {"sqrtf", "__mips16_call_stub_sf_1"},
116  {"trunc", "__mips16_call_stub_df_2"},
117  {"truncf", "__mips16_call_stub_sf_1"},
118 };
119 
121  const MipsSubtarget &STI)
122  : MipsTargetLowering(TM, STI) {
123 
124  // Set up the register classes
125  addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
126 
127  if (!Subtarget.useSoftFloat())
128  setMips16HardFloatLibCalls();
129 
143 
148 
150 }
151 
152 const MipsTargetLowering *
154  const MipsSubtarget &STI) {
155  return new Mips16TargetLowering(TM, STI);
156 }
157 
159  EVT VT, unsigned, unsigned, MachineMemOperand::Flags, bool *Fast) const {
160  return false;
161 }
162 
165  MachineBasicBlock *BB) const {
166  switch (MI.getOpcode()) {
167  default:
169  case Mips::SelBeqZ:
170  return emitSel16(Mips::BeqzRxImm16, MI, BB);
171  case Mips::SelBneZ:
172  return emitSel16(Mips::BnezRxImm16, MI, BB);
173  case Mips::SelTBteqZCmpi:
174  return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB);
175  case Mips::SelTBteqZSlti:
176  return emitSeliT16(Mips::Bteqz16, Mips::SltiRxImmX16, MI, BB);
177  case Mips::SelTBteqZSltiu:
178  return emitSeliT16(Mips::Bteqz16, Mips::SltiuRxImmX16, MI, BB);
179  case Mips::SelTBtneZCmpi:
180  return emitSeliT16(Mips::Btnez16, Mips::CmpiRxImmX16, MI, BB);
181  case Mips::SelTBtneZSlti:
182  return emitSeliT16(Mips::Btnez16, Mips::SltiRxImmX16, MI, BB);
183  case Mips::SelTBtneZSltiu:
184  return emitSeliT16(Mips::Btnez16, Mips::SltiuRxImmX16, MI, BB);
185  case Mips::SelTBteqZCmp:
186  return emitSelT16(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
187  case Mips::SelTBteqZSlt:
188  return emitSelT16(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
189  case Mips::SelTBteqZSltu:
190  return emitSelT16(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
191  case Mips::SelTBtneZCmp:
192  return emitSelT16(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
193  case Mips::SelTBtneZSlt:
194  return emitSelT16(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
195  case Mips::SelTBtneZSltu:
196  return emitSelT16(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
197  case Mips::BteqzT8CmpX16:
198  return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
199  case Mips::BteqzT8SltX16:
200  return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
201  case Mips::BteqzT8SltuX16:
202  // TBD: figure out a way to get this or remove the instruction
203  // altogether.
204  return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
205  case Mips::BtnezT8CmpX16:
206  return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
207  case Mips::BtnezT8SltX16:
208  return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
209  case Mips::BtnezT8SltuX16:
210  // TBD: figure out a way to get this or remove the instruction
211  // altogether.
212  return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
213  case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
214  Mips::Bteqz16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
215  case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
216  Mips::Bteqz16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
217  case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
218  Mips::Bteqz16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
219  case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
220  Mips::Btnez16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
221  case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
222  Mips::Btnez16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
223  case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
224  Mips::Btnez16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
225  break;
226  case Mips::SltCCRxRy16:
227  return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
228  break;
229  case Mips::SltiCCRxImmX16:
230  return emitFEXT_CCRXI16_ins
231  (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
232  case Mips::SltiuCCRxImmX16:
233  return emitFEXT_CCRXI16_ins
234  (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
235  case Mips::SltuCCRxRy16:
236  return emitFEXT_CCRX16_ins
237  (Mips::SltuRxRy16, MI, BB);
238  }
239 }
240 
241 bool Mips16TargetLowering::isEligibleForTailCallOptimization(
242  const CCState &CCInfo, unsigned NextStackOffset,
243  const MipsFunctionInfo &FI) const {
244  // No tail call optimization for mips16.
245  return false;
246 }
247 
248 void Mips16TargetLowering::setMips16HardFloatLibCalls() {
249  for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) {
250  assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) &&
251  "Array not sorted!");
252  if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL)
253  setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name);
254  }
255 
256  setLibcallName(RTLIB::O_F64, "__mips16_unorddf2");
257  setLibcallName(RTLIB::O_F32, "__mips16_unordsf2");
258 }
259 
260 //
261 // The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
262 // cleaner way to do all of this but it will have to wait until the traditional
263 // gcc mechanism is completed.
264 //
265 // For Pic, in order for Mips16 code to call Mips32 code which according the abi
266 // have either arguments or returned values placed in floating point registers,
267 // we use a set of helper functions. (This includes functions which return type
268 // complex which on Mips are returned in a pair of floating point registers).
269 //
270 // This is an encoding that we inherited from gcc.
271 // In Mips traditional O32, N32 ABI, floating point numbers are passed in
272 // floating point argument registers 1,2 only when the first and optionally
273 // the second arguments are float (sf) or double (df).
274 // For Mips16 we are only concerned with the situations where floating point
275 // arguments are being passed in floating point registers by the ABI, because
276 // Mips16 mode code cannot execute floating point instructions to load those
277 // values and hence helper functions are needed.
278 // The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
279 // the helper function suffixs for these are:
280 // 0, 1, 5, 9, 2, 6, 10
281 // this suffix can then be calculated as follows:
282 // for a given argument Arg:
283 // Arg1x, Arg2x = 1 : Arg is sf
284 // 2 : Arg is df
285 // 0: Arg is neither sf or df
286 // So this stub is the string for number Arg1x + Arg2x*4.
287 // However not all numbers between 0 and 10 are possible, we check anyway and
288 // assert if the impossible exists.
289 //
290 
291 unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
292  (ArgListTy &Args) const {
293  unsigned int resultNum = 0;
294  if (Args.size() >= 1) {
295  Type *t = Args[0].Ty;
296  if (t->isFloatTy()) {
297  resultNum = 1;
298  }
299  else if (t->isDoubleTy()) {
300  resultNum = 2;
301  }
302  }
303  if (resultNum) {
304  if (Args.size() >=2) {
305  Type *t = Args[1].Ty;
306  if (t->isFloatTy()) {
307  resultNum += 4;
308  }
309  else if (t->isDoubleTy()) {
310  resultNum += 8;
311  }
312  }
313  }
314  return resultNum;
315 }
316 
317 //
318 // Prefixes are attached to stub numbers depending on the return type.
319 // return type: float sf_
320 // double df_
321 // single complex sc_
322 // double complext dc_
323 // others NO PREFIX
324 //
325 //
326 // The full name of a helper function is__mips16_call_stub +
327 // return type dependent prefix + stub number
328 //
329 // FIXME: This is something that probably should be in a different source file
330 // and perhaps done differently but my main purpose is to not waste runtime
331 // on something that we can enumerate in the source. Another possibility is
332 // to have a python script to generate these mapping tables. This will do
333 // for now. There are a whole series of helper function mapping arrays, one
334 // for each return type class as outlined above. There there are 11 possible
335 // entries. Ones with 0 are ones which should never be selected.
336 //
337 // All the arrays are similar except for ones which return neither
338 // sf, df, sc, dc, in which we only care about ones which have sf or df as a
339 // first parameter.
340 //
341 #define P_ "__mips16_call_stub_"
342 #define MAX_STUB_NUMBER 10
343 #define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
344 #define T P "0" , T1
345 #define P P_
346 static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
347  {nullptr, T1 };
348 #undef P
349 #define P P_ "sf_"
350 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
351  { T };
352 #undef P
353 #define P P_ "df_"
354 static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
355  { T };
356 #undef P
357 #define P P_ "sc_"
358 static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
359  { T };
360 #undef P
361 #define P P_ "dc_"
362 static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
363  { T };
364 #undef P
365 #undef P_
366 
367 
368 const char* Mips16TargetLowering::
369  getMips16HelperFunction
370  (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
371  const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
372 #ifndef NDEBUG
373  const unsigned int maxStubNum = 10;
374  assert(stubNum <= maxStubNum);
375  const bool validStubNum[maxStubNum+1] =
376  {true, true, true, false, false, true, true, false, false, true, true};
377  assert(validStubNum[stubNum]);
378 #endif
379  const char *result;
380  if (RetTy->isFloatTy()) {
381  result = sfMips16Helper[stubNum];
382  }
383  else if (RetTy ->isDoubleTy()) {
384  result = dfMips16Helper[stubNum];
385  } else if (StructType *SRetTy = dyn_cast<StructType>(RetTy)) {
386  // check if it's complex
387  if (SRetTy->getNumElements() == 2) {
388  if ((SRetTy->getElementType(0)->isFloatTy()) &&
389  (SRetTy->getElementType(1)->isFloatTy())) {
390  result = scMips16Helper[stubNum];
391  } else if ((SRetTy->getElementType(0)->isDoubleTy()) &&
392  (SRetTy->getElementType(1)->isDoubleTy())) {
393  result = dcMips16Helper[stubNum];
394  } else {
395  llvm_unreachable("Uncovered condition");
396  }
397  } else {
398  llvm_unreachable("Uncovered condition");
399  }
400  } else {
401  if (stubNum == 0) {
402  needHelper = false;
403  return "";
404  }
405  result = vMips16Helper[stubNum];
406  }
407  needHelper = true;
408  return result;
409 }
410 
411 void Mips16TargetLowering::
412 getOpndList(SmallVectorImpl<SDValue> &Ops,
413  std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
414  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
415  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
416  SDValue Chain) const {
417  SelectionDAG &DAG = CLI.DAG;
419  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
420  const char* Mips16HelperFunction = nullptr;
421  bool NeedMips16Helper = false;
422 
424  //
425  // currently we don't have symbols tagged with the mips16 or mips32
426  // qualifier so we will assume that we don't know what kind it is.
427  // and generate the helper
428  //
429  bool LookupHelper = true;
430  if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
431  Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() };
432 
433  if (std::binary_search(std::begin(HardFloatLibCalls),
434  std::end(HardFloatLibCalls), Find))
435  LookupHelper = false;
436  else {
437  const char *Symbol = S->getSymbol();
438  Mips16IntrinsicHelperType IntrinsicFind = { Symbol, "" };
439  const Mips16HardFloatInfo::FuncSignature *Signature =
441  if (!IsPICCall && (Signature && (FuncInfo->StubsNeeded.find(Symbol) ==
442  FuncInfo->StubsNeeded.end()))) {
443  FuncInfo->StubsNeeded[Symbol] = Signature;
444  //
445  // S2 is normally saved if the stub is for a function which
446  // returns a float or double value and is not otherwise. This is
447  // because more work is required after the function the stub
448  // is calling completes, and so the stub cannot directly return
449  // and the stub has no stack space to store the return address so
450  // S2 is used for that purpose.
451  // In order to take advantage of not saving S2, we need to also
452  // optimize the call in the stub and this requires some further
453  // functionality in MipsAsmPrinter which we don't have yet.
454  // So for now we always save S2. The optimization will be done
455  // in a follow-on patch.
456  //
457  if (1 || (Signature->RetSig != Mips16HardFloatInfo::NoFPRet))
458  FuncInfo->setSaveS2();
459  }
460  // one more look at list of intrinsics
461  const Mips16IntrinsicHelperType *Helper =
462  llvm::lower_bound(Mips16IntrinsicHelper, IntrinsicFind);
463  if (Helper != std::end(Mips16IntrinsicHelper) &&
464  *Helper == IntrinsicFind) {
465  Mips16HelperFunction = Helper->Helper;
466  NeedMips16Helper = true;
467  LookupHelper = false;
468  }
469 
470  }
471  } else if (GlobalAddressSDNode *G =
472  dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
473  Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL,
474  G->getGlobal()->getName().data() };
475 
476  if (std::binary_search(std::begin(HardFloatLibCalls),
477  std::end(HardFloatLibCalls), Find))
478  LookupHelper = false;
479  }
480  if (LookupHelper)
481  Mips16HelperFunction =
482  getMips16HelperFunction(CLI.RetTy, CLI.getArgs(), NeedMips16Helper);
483  }
484 
485  SDValue JumpTarget = Callee;
486 
487  // T9 should contain the address of the callee function if
488  // -relocation-model=pic or it is an indirect call.
489  if (IsPICCall || !GlobalOrExternal) {
490  unsigned V0Reg = Mips::V0;
491  if (NeedMips16Helper) {
492  RegsToPass.push_front(std::make_pair(V0Reg, Callee));
493  JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction,
494  getPointerTy(DAG.getDataLayout()));
495  ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(JumpTarget);
496  JumpTarget = getAddrGlobal(S, CLI.DL, JumpTarget.getValueType(), DAG,
497  MipsII::MO_GOT, Chain,
498  FuncInfo->callPtrInfo(S->getSymbol()));
499  } else
500  RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
501  }
502 
503  Ops.push_back(JumpTarget);
504 
505  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
506  InternalLinkage, IsCallReloc, CLI, Callee,
507  Chain);
508 }
509 
511 Mips16TargetLowering::emitSel16(unsigned Opc, MachineInstr &MI,
512  MachineBasicBlock *BB) const {
514  return BB;
516  DebugLoc DL = MI.getDebugLoc();
517  // To "insert" a SELECT_CC instruction, we actually have to insert the
518  // diamond control-flow pattern. The incoming instruction knows the
519  // destination vreg to set, the condition code register to branch on, the
520  // true/false values to select between, and a branch opcode to use.
521  const BasicBlock *LLVM_BB = BB->getBasicBlock();
523 
524  // thisMBB:
525  // ...
526  // TrueVal = ...
527  // setcc r1, r2, r3
528  // bNE r1, r0, copy1MBB
529  // fallthrough --> copy0MBB
530  MachineBasicBlock *thisMBB = BB;
531  MachineFunction *F = BB->getParent();
532  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
533  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
534  F->insert(It, copy0MBB);
535  F->insert(It, sinkMBB);
536 
537  // Transfer the remainder of BB and its successor edges to sinkMBB.
538  sinkMBB->splice(sinkMBB->begin(), BB,
539  std::next(MachineBasicBlock::iterator(MI)), BB->end());
540  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
541 
542  // Next, add the true and fallthrough blocks as its successors.
543  BB->addSuccessor(copy0MBB);
544  BB->addSuccessor(sinkMBB);
545 
546  BuildMI(BB, DL, TII->get(Opc))
547  .addReg(MI.getOperand(3).getReg())
548  .addMBB(sinkMBB);
549 
550  // copy0MBB:
551  // %FalseValue = ...
552  // # fallthrough to sinkMBB
553  BB = copy0MBB;
554 
555  // Update machine-CFG edges
556  BB->addSuccessor(sinkMBB);
557 
558  // sinkMBB:
559  // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
560  // ...
561  BB = sinkMBB;
562 
563  BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
564  .addReg(MI.getOperand(1).getReg())
565  .addMBB(thisMBB)
566  .addReg(MI.getOperand(2).getReg())
567  .addMBB(copy0MBB);
568 
569  MI.eraseFromParent(); // The pseudo instruction is gone now.
570  return BB;
571 }
572 
574 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI,
575  MachineBasicBlock *BB) const {
577  return BB;
579  DebugLoc DL = MI.getDebugLoc();
580  // To "insert" a SELECT_CC instruction, we actually have to insert the
581  // diamond control-flow pattern. The incoming instruction knows the
582  // destination vreg to set, the condition code register to branch on, the
583  // true/false values to select between, and a branch opcode to use.
584  const BasicBlock *LLVM_BB = BB->getBasicBlock();
586 
587  // thisMBB:
588  // ...
589  // TrueVal = ...
590  // setcc r1, r2, r3
591  // bNE r1, r0, copy1MBB
592  // fallthrough --> copy0MBB
593  MachineBasicBlock *thisMBB = BB;
594  MachineFunction *F = BB->getParent();
595  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
596  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
597  F->insert(It, copy0MBB);
598  F->insert(It, sinkMBB);
599 
600  // Transfer the remainder of BB and its successor edges to sinkMBB.
601  sinkMBB->splice(sinkMBB->begin(), BB,
602  std::next(MachineBasicBlock::iterator(MI)), BB->end());
603  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
604 
605  // Next, add the true and fallthrough blocks as its successors.
606  BB->addSuccessor(copy0MBB);
607  BB->addSuccessor(sinkMBB);
608 
609  BuildMI(BB, DL, TII->get(Opc2))
610  .addReg(MI.getOperand(3).getReg())
611  .addReg(MI.getOperand(4).getReg());
612  BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
613 
614  // copy0MBB:
615  // %FalseValue = ...
616  // # fallthrough to sinkMBB
617  BB = copy0MBB;
618 
619  // Update machine-CFG edges
620  BB->addSuccessor(sinkMBB);
621 
622  // sinkMBB:
623  // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
624  // ...
625  BB = sinkMBB;
626 
627  BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
628  .addReg(MI.getOperand(1).getReg())
629  .addMBB(thisMBB)
630  .addReg(MI.getOperand(2).getReg())
631  .addMBB(copy0MBB);
632 
633  MI.eraseFromParent(); // The pseudo instruction is gone now.
634  return BB;
635 
636 }
637 
639 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2,
640  MachineInstr &MI,
641  MachineBasicBlock *BB) const {
643  return BB;
645  DebugLoc DL = MI.getDebugLoc();
646  // To "insert" a SELECT_CC instruction, we actually have to insert the
647  // diamond control-flow pattern. The incoming instruction knows the
648  // destination vreg to set, the condition code register to branch on, the
649  // true/false values to select between, and a branch opcode to use.
650  const BasicBlock *LLVM_BB = BB->getBasicBlock();
652 
653  // thisMBB:
654  // ...
655  // TrueVal = ...
656  // setcc r1, r2, r3
657  // bNE r1, r0, copy1MBB
658  // fallthrough --> copy0MBB
659  MachineBasicBlock *thisMBB = BB;
660  MachineFunction *F = BB->getParent();
661  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
662  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
663  F->insert(It, copy0MBB);
664  F->insert(It, sinkMBB);
665 
666  // Transfer the remainder of BB and its successor edges to sinkMBB.
667  sinkMBB->splice(sinkMBB->begin(), BB,
668  std::next(MachineBasicBlock::iterator(MI)), BB->end());
669  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
670 
671  // Next, add the true and fallthrough blocks as its successors.
672  BB->addSuccessor(copy0MBB);
673  BB->addSuccessor(sinkMBB);
674 
675  BuildMI(BB, DL, TII->get(Opc2))
676  .addReg(MI.getOperand(3).getReg())
677  .addImm(MI.getOperand(4).getImm());
678  BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
679 
680  // copy0MBB:
681  // %FalseValue = ...
682  // # fallthrough to sinkMBB
683  BB = copy0MBB;
684 
685  // Update machine-CFG edges
686  BB->addSuccessor(sinkMBB);
687 
688  // sinkMBB:
689  // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
690  // ...
691  BB = sinkMBB;
692 
693  BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
694  .addReg(MI.getOperand(1).getReg())
695  .addMBB(thisMBB)
696  .addReg(MI.getOperand(2).getReg())
697  .addMBB(copy0MBB);
698 
699  MI.eraseFromParent(); // The pseudo instruction is gone now.
700  return BB;
701 
702 }
703 
705 Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
706  MachineInstr &MI,
707  MachineBasicBlock *BB) const {
709  return BB;
711  Register regX = MI.getOperand(0).getReg();
712  Register regY = MI.getOperand(1).getReg();
713  MachineBasicBlock *target = MI.getOperand(2).getMBB();
714  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc))
715  .addReg(regX)
716  .addReg(regY);
717  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
718  MI.eraseFromParent(); // The pseudo instruction is gone now.
719  return BB;
720 }
721 
722 MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
723  unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned,
724  MachineInstr &MI, MachineBasicBlock *BB) const {
726  return BB;
728  Register regX = MI.getOperand(0).getReg();
729  int64_t imm = MI.getOperand(1).getImm();
730  MachineBasicBlock *target = MI.getOperand(2).getMBB();
731  unsigned CmpOpc;
732  if (isUInt<8>(imm))
733  CmpOpc = CmpiOpc;
734  else if ((!ImmSigned && isUInt<16>(imm)) ||
735  (ImmSigned && isInt<16>(imm)))
736  CmpOpc = CmpiXOpc;
737  else
738  llvm_unreachable("immediate field not usable");
739  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
740  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
741  MI.eraseFromParent(); // The pseudo instruction is gone now.
742  return BB;
743 }
744 
745 static unsigned Mips16WhichOp8uOr16simm
746  (unsigned shortOp, unsigned longOp, int64_t Imm) {
747  if (isUInt<8>(Imm))
748  return shortOp;
749  else if (isInt<16>(Imm))
750  return longOp;
751  else
752  llvm_unreachable("immediate field not usable");
753 }
754 
756 Mips16TargetLowering::emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI,
757  MachineBasicBlock *BB) const {
759  return BB;
761  Register CC = MI.getOperand(0).getReg();
762  Register regX = MI.getOperand(1).getReg();
763  Register regY = MI.getOperand(2).getReg();
764  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc))
765  .addReg(regX)
766  .addReg(regY);
767  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
768  .addReg(Mips::T8);
769  MI.eraseFromParent(); // The pseudo instruction is gone now.
770  return BB;
771 }
772 
774 Mips16TargetLowering::emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc,
775  MachineInstr &MI,
776  MachineBasicBlock *BB) const {
778  return BB;
780  Register CC = MI.getOperand(0).getReg();
781  Register regX = MI.getOperand(1).getReg();
782  int64_t Imm = MI.getOperand(2).getImm();
783  unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
784  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc)).addReg(regX).addImm(Imm);
785  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
786  .addReg(Mips::T8);
787  MI.eraseFromParent(); // The pseudo instruction is gone now.
788  return BB;
789 
790 }
auto lower_bound(R &&Range, T &&Value) -> decltype(adl_begin(Range))
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1261
bool inMips16HardFloat() const
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align, MachineMemOperand::Flags Flags, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
MachineBasicBlock * getMBB() const
static char const * vMips16Helper[MAX_STUB_NUMBER+1]
const MipsSubtarget & Subtarget
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
Mips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
static char const * scMips16Helper[MAX_STUB_NUMBER+1]
const MipsInstrInfo * getInstrInfo() const override
std::map< const char *, const Mips16HardFloatInfo::FuncSignature * > StubsNeeded
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:342
A debug info location.
Definition: DebugLoc.h:33
F(f)
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
static unsigned Mips16WhichOp8uOr16simm(unsigned shortOp, unsigned longOp, int64_t Imm)
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:813
SDValue getExternalSymbol(const char *Sym, EVT VT)
MachinePointerInfo callPtrInfo(const char *ES)
Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue object representing a GOT ent...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
const HexagonInstrInfo * TII
Class to represent struct types.
Definition: DerivedTypes.h:238
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:842
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:417
static char const * dfMips16Helper[MAX_STUB_NUMBER+1]
static const T * Find(StringRef S, ArrayRef< T > A)
Find KV in array using binary search.
static char const * dcMips16Helper[MAX_STUB_NUMBER+1]
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:414
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const char * getSymbol() const
static const Mips16Libcall HardFloatLibCalls[]
TargetInstrInfo - Interface to description of machine instruction set.
static cl::opt< bool > DontExpandCondPseudos16("mips16-dont-expand-cond-pseudo", cl::init(false), cl::desc("Don't expand conditional move related " "pseudos for Mips 16"), cl::Hidden)
bool isFloatTy() const
Return true if this is &#39;float&#39;, a 32-bit IEEE fp type.
Definition: Type.h:147
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue >> &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:379
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
self_iterator getIterator()
Definition: ilist_node.h:81
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:828
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:33
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
FuncSignature const * findFuncSignature(const char *name)
static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[]
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:37
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MipsRegisterInfo * getRegisterInfo() const override
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1023
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:445
int64_t getImm() const
amdgpu Simplify well known AMD library false FunctionCallee Callee
Flags
Flags values. These may be or&#39;d together.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static char const * sfMips16Helper[MAX_STUB_NUMBER+1]
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
#define I(x, y, z)
Definition: MD5.cpp:58
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:382
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
bool operator<(int64_t V1, const APSInt &V2)
Definition: APSInt.h:343
bool useSoftFloat() const
IRTranslator LLVM IR MI
#define MAX_STUB_NUMBER
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1975
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool isDoubleTy() const
Return true if this is &#39;double&#39;, a 64-bit IEEE fp type.
Definition: Type.h:150
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
#define T1
Wrapper class representing virtual and physical registers.
Definition: Register.h:19