LLVM  16.0.0git
AMDGPUArgumentUsageInfo.cpp
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1 //===----------------------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "AMDGPU.h"
11 #include "AMDGPUTargetMachine.h"
13 #include "SIRegisterInfo.h"
15 #include "llvm/IR/Function.h"
18 
19 using namespace llvm;
20 
21 #define DEBUG_TYPE "amdgpu-argument-reg-usage-info"
22 
24  "Argument Register Usage Information Storage", false, true)
25 
27  const TargetRegisterInfo *TRI) const {
28  if (!isSet()) {
29  OS << "<not set>\n";
30  return;
31  }
32 
33  if (isRegister())
34  OS << "Reg " << printReg(getRegister(), TRI);
35  else
36  OS << "Stack offset " << getStackOffset();
37 
38  if (isMasked()) {
39  OS << " & ";
41  }
42 
43  OS << '\n';
44 }
45 
47 
49 
50 // Hardcoded registers from fixed function ABI
53 
55  return false;
56 }
57 
59  ArgInfoMap.clear();
60  return false;
61 }
62 
64  for (const auto &FI : ArgInfoMap) {
65  OS << "Arguments for " << FI.first->getName() << '\n'
66  << " PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
67  << " DispatchPtr: " << FI.second.DispatchPtr
68  << " QueuePtr: " << FI.second.QueuePtr
69  << " KernargSegmentPtr: " << FI.second.KernargSegmentPtr
70  << " DispatchID: " << FI.second.DispatchID
71  << " FlatScratchInit: " << FI.second.FlatScratchInit
72  << " PrivateSegmentSize: " << FI.second.PrivateSegmentSize
73  << " WorkGroupIDX: " << FI.second.WorkGroupIDX
74  << " WorkGroupIDY: " << FI.second.WorkGroupIDY
75  << " WorkGroupIDZ: " << FI.second.WorkGroupIDZ
76  << " WorkGroupInfo: " << FI.second.WorkGroupInfo
77  << " LDSKernelId: " << FI.second.LDSKernelId
78  << " PrivateSegmentWaveByteOffset: "
79  << FI.second.PrivateSegmentWaveByteOffset
80  << " ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr
81  << " ImplicitArgPtr: " << FI.second.ImplicitArgPtr
82  << " WorkItemIDX " << FI.second.WorkItemIDX
83  << " WorkItemIDY " << FI.second.WorkItemIDY
84  << " WorkItemIDZ " << FI.second.WorkItemIDZ
85  << '\n';
86  }
87 }
88 
89 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
92  switch (Value) {
94  return std::make_tuple(PrivateSegmentBuffer ? &PrivateSegmentBuffer
95  : nullptr,
96  &AMDGPU::SGPR_128RegClass, LLT::fixed_vector(4, 32));
97  }
99  return std::make_tuple(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
100  &AMDGPU::SGPR_64RegClass,
103  return std::make_tuple(WorkGroupIDX ? &WorkGroupIDX : nullptr,
104  &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
106  return std::make_tuple(WorkGroupIDY ? &WorkGroupIDY : nullptr,
107  &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
109  return std::make_tuple(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
110  &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
112  return std::make_tuple(LDSKernelId ? &LDSKernelId : nullptr,
113  &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
115  return std::make_tuple(
117  &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
119  return std::make_tuple(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
120  &AMDGPU::SGPR_64RegClass,
123  return std::make_tuple(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
124  &AMDGPU::SGPR_64RegClass,
127  return std::make_tuple(DispatchID ? &DispatchID : nullptr,
128  &AMDGPU::SGPR_64RegClass, LLT::scalar(64));
130  return std::make_tuple(FlatScratchInit ? &FlatScratchInit : nullptr,
131  &AMDGPU::SGPR_64RegClass, LLT::scalar(64));
133  return std::make_tuple(DispatchPtr ? &DispatchPtr : nullptr,
134  &AMDGPU::SGPR_64RegClass,
137  return std::make_tuple(QueuePtr ? &QueuePtr : nullptr,
138  &AMDGPU::SGPR_64RegClass,
141  return std::make_tuple(WorkItemIDX ? &WorkItemIDX : nullptr,
142  &AMDGPU::VGPR_32RegClass, LLT::scalar(32));
144  return std::make_tuple(WorkItemIDY ? &WorkItemIDY : nullptr,
145  &AMDGPU::VGPR_32RegClass, LLT::scalar(32));
147  return std::make_tuple(WorkItemIDZ ? &WorkItemIDZ : nullptr,
148  &AMDGPU::VGPR_32RegClass, LLT::scalar(32));
149  }
150  llvm_unreachable("unexpected preloaded value type");
151 }
152 
156  = ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3);
157  AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5);
158  AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7);
159 
160  // Do not pass kernarg segment pointer, only pass increment version in its
161  // place.
162  AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::SGPR8_SGPR9);
163  AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11);
164 
165  // Skip FlatScratchInit/PrivateSegmentSize
166  AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12);
167  AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13);
168  AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14);
169  AI.LDSKernelId = ArgDescriptor::createRegister(AMDGPU::SGPR15);
170 
171  const unsigned Mask = 0x3ff;
172  AI.WorkItemIDX = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask);
173  AI.WorkItemIDY = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 10);
174  AI.WorkItemIDZ = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 20);
175  return AI;
176 }
177 
178 const AMDGPUFunctionArgInfo &
180  auto I = ArgInfoMap.find(&F);
181  if (I == ArgInfoMap.end())
182  return FixedABIFunctionInfo;
183  return I->second;
184 }
llvm::AMDGPUFunctionArgInfo::PreloadedValue
PreloadedValue
Definition: AMDGPUArgumentUsageInfo.h:98
llvm::AMDGPUFunctionArgInfo::QUEUE_PTR
@ QUEUE_PTR
Definition: AMDGPUArgumentUsageInfo.h:102
llvm::AMDGPUFunctionArgInfo::QueuePtr
ArgDescriptor QueuePtr
Definition: AMDGPUArgumentUsageInfo.h:127
llvm::AMDGPUFunctionArgInfo::FLAT_SCRATCH_INIT
@ FLAT_SCRATCH_INIT
Definition: AMDGPUArgumentUsageInfo.h:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::Function
Definition: Function.h:60
llvm::AMDGPUFunctionArgInfo::LDSKernelId
ArgDescriptor LDSKernelId
Definition: AMDGPUArgumentUsageInfo.h:132
NativeFormatting.h
llvm::AMDGPUArgumentUsageInfo::FixedABIFunctionInfo
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
Definition: AMDGPUArgumentUsageInfo.h:168
llvm::AMDGPUFunctionArgInfo::FlatScratchInit
ArgDescriptor FlatScratchInit
Definition: AMDGPUArgumentUsageInfo.h:130
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::AMDGPUFunctionArgInfo::DispatchPtr
ArgDescriptor DispatchPtr
Definition: AMDGPUArgumentUsageInfo.h:126
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_X
@ WORKGROUP_ID_X
Definition: AMDGPUArgumentUsageInfo.h:107
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AMDGPUFunctionArgInfo::DispatchID
ArgDescriptor DispatchID
Definition: AMDGPUArgumentUsageInfo.h:129
llvm::AMDGPUFunctionArgInfo::ImplicitArgPtr
ArgDescriptor ImplicitArgPtr
Definition: AMDGPUArgumentUsageInfo.h:143
llvm::LLT::fixed_vector
static LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:74
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::AMDGPUFunctionArgInfo::WorkGroupIDX
ArgDescriptor WorkGroupIDX
Definition: AMDGPUArgumentUsageInfo.h:135
llvm::AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR
@ KERNARG_SEGMENT_PTR
Definition: AMDGPUArgumentUsageInfo.h:103
llvm::AMDGPUFunctionArgInfo
Definition: AMDGPUArgumentUsageInfo.h:97
llvm::AMDGPUArgumentUsageInfo::lookupFuncArgInfo
const AMDGPUFunctionArgInfo & lookupFuncArgInfo(const Function &F) const
Definition: AMDGPUArgumentUsageInfo.cpp:179
llvm::AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR
@ IMPLICIT_ARG_PTR
Definition: AMDGPUArgumentUsageInfo.h:112
llvm::AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR
@ IMPLICIT_BUFFER_PTR
Definition: AMDGPUArgumentUsageInfo.h:111
llvm::AMDGPUFunctionArgInfo::WorkItemIDX
ArgDescriptor WorkItemIDX
Definition: AMDGPUArgumentUsageInfo.h:150
getStackOffset
static StackOffset getStackOffset(const MachineFunction &MF, int64_t ObjectOffset)
Definition: AArch64FrameLowering.cpp:2273
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::AMDGPUArgumentUsageInfo::doInitialization
bool doInitialization(Module &M) override
doInitialization - Virtual method overridden by subclasses to do any necessary initialization before ...
Definition: AMDGPUArgumentUsageInfo.cpp:54
llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_Y
@ WORKITEM_ID_Y
Definition: AMDGPUArgumentUsageInfo.h:116
llvm::AMDGPUArgumentUsageInfo::ID
static char ID
Definition: AMDGPUArgumentUsageInfo.h:165
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:49
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:375
llvm::AMDGPUFunctionArgInfo::getPreloadedValue
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(PreloadedValue Value) const
Definition: AMDGPUArgumentUsageInfo.cpp:90
AMDGPUMCTargetDesc.h
llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Z
@ WORKGROUP_ID_Z
Definition: AMDGPUArgumentUsageInfo.h:109
llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_Z
@ WORKITEM_ID_Z
Definition: AMDGPUArgumentUsageInfo.h:117
llvm::AMDGPUFunctionArgInfo::WorkGroupIDZ
ArgDescriptor WorkGroupIDZ
Definition: AMDGPUArgumentUsageInfo.h:137
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
llvm::AMDGPUFunctionArgInfo::PrivateSegmentBuffer
ArgDescriptor PrivateSegmentBuffer
Definition: AMDGPUArgumentUsageInfo.h:125
llvm::AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET
@ PRIVATE_SEGMENT_WAVE_BYTE_OFFSET
Definition: AMDGPUArgumentUsageInfo.h:110
llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_X
@ WORKITEM_ID_X
Definition: AMDGPUArgumentUsageInfo.h:115
llvm::HexPrintStyle::PrefixLower
@ PrefixLower
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::AMDGPUFunctionArgInfo::PrivateSegmentWaveByteOffset
ArgDescriptor PrivateSegmentWaveByteOffset
Definition: AMDGPUArgumentUsageInfo.h:139
llvm::AMDGPUArgumentUsageInfo
Definition: AMDGPUArgumentUsageInfo.h:160
llvm::AMDGPUFunctionArgInfo::WorkGroupIDY
ArgDescriptor WorkGroupIDY
Definition: AMDGPUArgumentUsageInfo.h:136
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:66
llvm::AMDGPUFunctionArgInfo::WorkItemIDZ
ArgDescriptor WorkItemIDZ
Definition: AMDGPUArgumentUsageInfo.h:152
llvm::print
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
Definition: GCNRegPressure.cpp:138
llvm::AMDGPUFunctionArgInfo::DISPATCH_ID
@ DISPATCH_ID
Definition: AMDGPUArgumentUsageInfo.h:104
llvm::AMDGPUFunctionArgInfo::LDS_KERNEL_ID
@ LDS_KERNEL_ID
Definition: AMDGPUArgumentUsageInfo.h:106
AMDGPU.h
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::AMDGPUFunctionArgInfo::ImplicitBufferPtr
ArgDescriptor ImplicitBufferPtr
Definition: AMDGPUArgumentUsageInfo.h:146
llvm::AMDGPUArgumentUsageInfo::print
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
Definition: AMDGPUArgumentUsageInfo.cpp:63
llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Y
@ WORKGROUP_ID_Y
Definition: AMDGPUArgumentUsageInfo.h:108
Function.h
llvm::ArgDescriptor::createRegister
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:44
DEBUG_TYPE
#define DEBUG_TYPE
Definition: AMDGPUArgumentUsageInfo.cpp:21
llvm::AMDGPUFunctionArgInfo::KernargSegmentPtr
ArgDescriptor KernargSegmentPtr
Definition: AMDGPUArgumentUsageInfo.h:128
llvm::AMDGPUFunctionArgInfo::DISPATCH_PTR
@ DISPATCH_PTR
Definition: AMDGPUArgumentUsageInfo.h:101
llvm::AMDGPUFunctionArgInfo::WorkItemIDY
ArgDescriptor WorkItemIDY
Definition: AMDGPUArgumentUsageInfo.h:151
llvm::AMDGPUArgumentUsageInfo::doFinalization
bool doFinalization(Module &M) override
doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes...
Definition: AMDGPUArgumentUsageInfo.cpp:58
llvm::AMDGPUArgumentUsageInfo::ExternFunctionInfo
static const AMDGPUFunctionArgInfo ExternFunctionInfo
Definition: AMDGPUArgumentUsageInfo.h:167
llvm::AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER
@ PRIVATE_SEGMENT_BUFFER
Definition: AMDGPUArgumentUsageInfo.h:100
llvm::AMDGPUFunctionArgInfo::fixedABILayout
static constexpr AMDGPUFunctionArgInfo fixedABILayout()
Definition: AMDGPUArgumentUsageInfo.cpp:153
raw_ostream.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
AMDGPUArgumentUsageInfo.h
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
TargetRegisterInfo.h
SIRegisterInfo.h
AMDGPUTargetMachine.h
llvm::write_hex
void write_hex(raw_ostream &S, uint64_t N, HexPrintStyle Style, Optional< size_t > Width=std::nullopt)
Definition: NativeFormatting.cpp:138