LLVM 17.0.0git
AMDGPUArgumentUsageInfo.cpp
Go to the documentation of this file.
1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10#include "AMDGPU.h"
11#include "AMDGPUTargetMachine.h"
13#include "SIRegisterInfo.h"
15#include "llvm/IR/Function.h"
18
19using namespace llvm;
20
21#define DEBUG_TYPE "amdgpu-argument-reg-usage-info"
22
24 "Argument Register Usage Information Storage", false, true)
25
28 if (!isSet()) {
29 OS << "<not set>\n";
30 return;
31 }
32
33 if (isRegister())
34 OS << "Reg " << printReg(getRegister(), TRI);
35 else
36 OS << "Stack offset " << getStackOffset();
37
38 if (isMasked()) {
39 OS << " & ";
41 }
42
43 OS << '\n';
44}
45
47
49
50// Hardcoded registers from fixed function ABI
53
55 return false;
56}
57
59 ArgInfoMap.clear();
60 return false;
61}
62
64 for (const auto &FI : ArgInfoMap) {
65 OS << "Arguments for " << FI.first->getName() << '\n'
66 << " PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
67 << " DispatchPtr: " << FI.second.DispatchPtr
68 << " QueuePtr: " << FI.second.QueuePtr
69 << " KernargSegmentPtr: " << FI.second.KernargSegmentPtr
70 << " DispatchID: " << FI.second.DispatchID
71 << " FlatScratchInit: " << FI.second.FlatScratchInit
72 << " PrivateSegmentSize: " << FI.second.PrivateSegmentSize
73 << " WorkGroupIDX: " << FI.second.WorkGroupIDX
74 << " WorkGroupIDY: " << FI.second.WorkGroupIDY
75 << " WorkGroupIDZ: " << FI.second.WorkGroupIDZ
76 << " WorkGroupInfo: " << FI.second.WorkGroupInfo
77 << " LDSKernelId: " << FI.second.LDSKernelId
78 << " PrivateSegmentWaveByteOffset: "
79 << FI.second.PrivateSegmentWaveByteOffset
80 << " ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr
81 << " ImplicitArgPtr: " << FI.second.ImplicitArgPtr
82 << " WorkItemIDX " << FI.second.WorkItemIDX
83 << " WorkItemIDY " << FI.second.WorkItemIDY
84 << " WorkItemIDZ " << FI.second.WorkItemIDZ
85 << '\n';
86 }
87}
88
89std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
92 switch (Value) {
94 return std::tuple(PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr,
95 &AMDGPU::SGPR_128RegClass, LLT::fixed_vector(4, 32));
96 }
98 return std::tuple(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
99 &AMDGPU::SGPR_64RegClass,
102 return std::tuple(WorkGroupIDX ? &WorkGroupIDX : nullptr,
103 &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
105 return std::tuple(WorkGroupIDY ? &WorkGroupIDY : nullptr,
106 &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
108 return std::tuple(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
109 &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
111 return std::tuple(LDSKernelId ? &LDSKernelId : nullptr,
112 &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
114 return std::tuple(
116 &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
118 return std::tuple(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
119 &AMDGPU::SGPR_64RegClass,
122 return std::tuple(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
123 &AMDGPU::SGPR_64RegClass,
126 return std::tuple(DispatchID ? &DispatchID : nullptr,
127 &AMDGPU::SGPR_64RegClass, LLT::scalar(64));
129 return std::tuple(FlatScratchInit ? &FlatScratchInit : nullptr,
130 &AMDGPU::SGPR_64RegClass, LLT::scalar(64));
132 return std::tuple(DispatchPtr ? &DispatchPtr : nullptr,
133 &AMDGPU::SGPR_64RegClass,
136 return std::tuple(QueuePtr ? &QueuePtr : nullptr, &AMDGPU::SGPR_64RegClass,
139 return std::tuple(WorkItemIDX ? &WorkItemIDX : nullptr,
140 &AMDGPU::VGPR_32RegClass, LLT::scalar(32));
142 return std::tuple(WorkItemIDY ? &WorkItemIDY : nullptr,
143 &AMDGPU::VGPR_32RegClass, LLT::scalar(32));
145 return std::tuple(WorkItemIDZ ? &WorkItemIDZ : nullptr,
146 &AMDGPU::VGPR_32RegClass, LLT::scalar(32));
147 }
148 llvm_unreachable("unexpected preloaded value type");
149}
150
154 = ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3);
155 AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5);
156 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7);
157
158 // Do not pass kernarg segment pointer, only pass increment version in its
159 // place.
160 AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::SGPR8_SGPR9);
161 AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11);
162
163 // Skip FlatScratchInit/PrivateSegmentSize
164 AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12);
165 AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13);
166 AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14);
167 AI.LDSKernelId = ArgDescriptor::createRegister(AMDGPU::SGPR15);
168
169 const unsigned Mask = 0x3ff;
170 AI.WorkItemIDX = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask);
171 AI.WorkItemIDY = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 10);
172 AI.WorkItemIDZ = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 20);
173 return AI;
174}
175
178 auto I = ArgInfoMap.find(&F);
179 if (I == ArgInfoMap.end())
181 return I->second;
182}
static StackOffset getStackOffset(const MachineFunction &MF, int64_t ObjectOffset)
aarch64 promote const
#define DEBUG_TYPE
Provides AMDGPU specific target descriptions.
The AMDGPU TargetMachine interface definition for hw codegen targets.
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
Interface definition for SIRegisterInfo.
raw_pwrite_stream & OS
static const AMDGPUFunctionArgInfo ExternFunctionInfo
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
const AMDGPUFunctionArgInfo & lookupFuncArgInfo(const Function &F) const
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
bool doInitialization(Module &M) override
doInitialization - Virtual method overridden by subclasses to do any necessary initialization before ...
bool doFinalization(Module &M) override
doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes...
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:380
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void write_hex(raw_ostream &S, uint64_t N, HexPrintStyle Style, std::optional< size_t > Width=std::nullopt)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
static constexpr AMDGPUFunctionArgInfo fixedABILayout()
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(PreloadedValue Value) const
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)