15#ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
16#define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
26class MCObjectTargetWriter;
39 const MCSubtargetInfo &STI,
40 const MCRegisterInfo &
MRI,
41 const MCTargetOptions &
Options);
43std::unique_ptr<MCObjectTargetWriter>
45 bool HasRelocationAddend, uint8_t ABIVersion);
48#define GET_REGINFO_ENUM
49#include "AMDGPUGenRegisterInfo.inc"
51#define GET_INSTRINFO_ENUM
52#define GET_INSTRINFO_OPERAND_ENUM
53#define GET_INSTRINFO_MC_HELPER_DECLS
54#include "AMDGPUGenInstrInfo.inc"
56#define GET_SUBTARGETINFO_ENUM
57#include "AMDGPUGenSubtargetInfo.inc"
unsigned const MachineRegisterInfo * MRI
This is an optimization pass for GlobalISel generic memory operations.
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend, uint8_t ABIVersion)
MCRegisterInfo * createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour)
MCCodeEmitter * createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)