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38 #define GET_INSTRINFO_MC_DESC
39 #include "AMDGPUGenInstrInfo.inc"
41 #define GET_SUBTARGETINFO_MC_DESC
42 #include "AMDGPUGenSubtargetInfo.inc"
44 #define NoSchedModel NoSchedModelR600
45 #define GET_SUBTARGETINFO_MC_DESC
46 #include "R600GenSubtargetInfo.inc"
47 #undef NoSchedModelR600
49 #define GET_REGINFO_MC_DESC
50 #include "AMDGPUGenRegisterInfo.inc"
52 #define GET_REGINFO_MC_DESC
53 #include "R600GenRegisterInfo.inc"
57 InitAMDGPUMCInstrInfo(
X);
64 InitR600MCRegisterInfo(
X, 0);
66 InitAMDGPUMCRegisterInfo(
X, AMDGPU::PC_REG);
72 InitAMDGPUMCRegisterInfo(
X, AMDGPU::PC_REG, DwarfFlavour);
79 return createR600MCSubtargetInfoImpl(TT, CPU, CPU,
FS);
80 return createAMDGPUMCSubtargetInfoImpl(TT, CPU, CPU,
FS);
84 unsigned SyntaxVariant,
108 std::unique_ptr<MCAsmBackend> &&MAB,
109 std::unique_ptr<MCObjectWriter> &&OW,
110 std::unique_ptr<MCCodeEmitter> &&Emitter,
133 APInt SignedOffset(18, Imm * 4,
true);
142 return new AMDGPUMCInstrAnalysis(
Info);
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
This is an optimization pass for GlobalISel generic memory operations.
Context object for machine code objects.
Target - Wrapper for Target specific information.
This class is intended to be used as a base class for asm properties and features specific to the tar...
static MCTargetStreamer * createAMDGPUAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
MCELFStreamer * createAMDGPUELFStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll)
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Triple - Helper class for working with autoconf configuration names.
static MCTargetStreamer * createAMDGPUObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Instances of this class represent a single low-level machine instruction.
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
unsigned getNumOperands() const
Streaming machine code generation interface.
MCInstrInfo * createR600MCInstrInfo()
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
static MCStreamer * createMCStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll)
static MCInstrAnalysis * createAMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
Target specific streamer interface.
Analysis containing CSE Info
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
#define LLVM_EXTERNAL_VISIBILITY
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Target & getTheGCNTarget()
The target for GCN GPUs.
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Class for arbitrary precision integers.
MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTargetMC()
StringRef - Represent a constant reference to a string, i.e.
RegisterMCAsmInfo - Helper template for registering a target assembly info implementation.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Interface to description of machine instruction set.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static MCRegisterInfo * createAMDGPUMCRegisterInfo(const Triple &TT)
unsigned getOpcode() const
const MCOperand & getOperand(unsigned i) const
static MCInstPrinter * createAMDGPUMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static MCSubtargetInfo * createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Generic base class for all target subtargets.
MCRegisterInfo * createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour)
static MCInstrInfo * createAMDGPUMCInstrInfo()
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)