LLVM  16.0.0git
AMDGPUMCTargetDesc.cpp
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1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file provides AMDGPU specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPUMCTargetDesc.h"
15 #include "AMDGPUELFStreamer.h"
16 #include "AMDGPUInstPrinter.h"
17 #include "AMDGPUMCAsmInfo.h"
18 #include "AMDGPUTargetStreamer.h"
19 #include "R600InstPrinter.h"
20 #include "R600MCTargetDesc.h"
22 #include "llvm/MC/LaneBitmask.h"
23 #include "llvm/MC/MCAsmBackend.h"
24 #include "llvm/MC/MCCodeEmitter.h"
25 #include "llvm/MC/MCELFStreamer.h"
26 #include "llvm/MC/MCInstPrinter.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCObjectWriter.h"
31 #include "llvm/MC/MCRegisterInfo.h"
32 #include "llvm/MC/MCStreamer.h"
34 #include "llvm/MC/TargetRegistry.h"
35 
36 using namespace llvm;
37 
38 #define GET_INSTRINFO_MC_DESC
39 #define ENABLE_INSTR_PREDICATE_VERIFIER
40 #include "AMDGPUGenInstrInfo.inc"
41 
42 #define GET_SUBTARGETINFO_MC_DESC
43 #include "AMDGPUGenSubtargetInfo.inc"
44 
45 #define NoSchedModel NoSchedModelR600
46 #define GET_SUBTARGETINFO_MC_DESC
47 #include "R600GenSubtargetInfo.inc"
48 #undef NoSchedModelR600
49 
50 #define GET_REGINFO_MC_DESC
51 #include "AMDGPUGenRegisterInfo.inc"
52 
53 #define GET_REGINFO_MC_DESC
54 #include "R600GenRegisterInfo.inc"
55 
57  MCInstrInfo *X = new MCInstrInfo();
58  InitAMDGPUMCInstrInfo(X);
59  return X;
60 }
61 
64  if (TT.getArch() == Triple::r600)
65  InitR600MCRegisterInfo(X, 0);
66  else
67  InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG);
68  return X;
69 }
70 
73  InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG, DwarfFlavour);
74  return X;
75 }
76 
77 static MCSubtargetInfo *
79  if (TT.getArch() == Triple::r600)
80  return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
81  return createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
82 }
83 
85  unsigned SyntaxVariant,
86  const MCAsmInfo &MAI,
87  const MCInstrInfo &MII,
88  const MCRegisterInfo &MRI) {
89  if (T.getArch() == Triple::r600)
90  return new R600InstPrinter(MAI, MII, MRI);
91  else
92  return new AMDGPUInstPrinter(MAI, MII, MRI);
93 }
94 
97  MCInstPrinter *InstPrint,
98  bool isVerboseAsm) {
99  return new AMDGPUTargetAsmStreamer(S, OS);
100 }
101 
103  MCStreamer &S,
104  const MCSubtargetInfo &STI) {
105  return new AMDGPUTargetELFStreamer(S, STI);
106 }
107 
109  return new AMDGPUTargetStreamer(S);
110 }
111 
113  std::unique_ptr<MCAsmBackend> &&MAB,
114  std::unique_ptr<MCObjectWriter> &&OW,
115  std::unique_ptr<MCCodeEmitter> &&Emitter,
116  bool RelaxAll) {
118  std::move(Emitter), RelaxAll);
119 }
120 
121 namespace {
122 
123 class AMDGPUMCInstrAnalysis : public MCInstrAnalysis {
124 public:
125  explicit AMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
126  : MCInstrAnalysis(Info) {}
127 
128  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
129  uint64_t &Target) const override {
130  if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() ||
131  Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=
133  return false;
134 
135  int64_t Imm = Inst.getOperand(0).getImm();
136  // Our branches take a simm16, but we need two extra bits to account for
137  // the factor of 4.
138  APInt SignedOffset(18, Imm * 4, true);
139  Target = (SignedOffset.sext(64) + Addr + Size).getZExtValue();
140  return true;
141  }
142 };
143 
144 } // end anonymous namespace
145 
147  return new AMDGPUMCInstrAnalysis(Info);
148 }
149 
151 
154  for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
156 
163  }
164 
165  // R600 specific registration
170 
171  // GCN specific registration
174 
181 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:77
llvm::createSIMCCodeEmitter
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: SIMCCodeEmitter.cpp:90
AMDGPUELFStreamer.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCInstrDesc.h
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
MCCodeEmitter.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
createAMDGPUAsmTargetStreamer
static MCTargetStreamer * createAMDGPUAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Definition: AMDGPUMCTargetDesc.cpp:95
llvm::createAMDGPUELFStreamer
MCELFStreamer * createAMDGPUELFStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll)
Definition: AMDGPUELFStreamer.cpp:31
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1038
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition: TargetRegistry.h:881
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::X86AS::FS
@ FS
Definition: X86.h:200
createAMDGPUObjectTargetStreamer
static MCTargetStreamer * createAMDGPUObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition: AMDGPUMCTargetDesc.cpp:102
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:988
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:208
MCELFStreamer.h
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:212
llvm::createR600MCInstrInfo
MCInstrInfo * createR600MCInstrInfo()
Definition: R600MCTargetDesc.cpp:24
llvm::AMDGPUInstPrinter
Definition: AMDGPUInstPrinter.h:20
Emitter
dxil DXContainer Global Emitter
Definition: DXContainerGlobals.cpp:67
MCAsmBackend.h
llvm::getTheAMDGPUTarget
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
Definition: AMDGPUTargetInfo.cpp:20
AMDGPUTargetInfo.h
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:30
MCSubtargetInfo.h
createMCStreamer
static MCStreamer * createMCStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll)
Definition: AMDGPUMCTargetDesc.cpp:112
llvm::Triple::r600
@ r600
Definition: Triple.h:73
createAMDGPUMCInstrAnalysis
static MCInstrAnalysis * createAMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
Definition: AMDGPUMCTargetDesc.cpp:146
llvm::MCTargetStreamer
Target specific streamer interface.
Definition: MCStreamer.h:93
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:62
R600InstPrinter.h
MCInstPrinter.h
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
R600MCTargetDesc.h
llvm::AMDGPUDwarfFlavour
AMDGPUDwarfFlavour
Definition: AMDGPUMCTargetDesc.h:31
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
AMDGPUMCTargetDesc.h
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:935
AMDGPUTargetStreamer.h
uint64_t
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1044
MCRegisterInfo.h
AMDGPUInstPrinter.h
llvm::formatted_raw_ostream
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Definition: FormattedStream.h:30
llvm::getTheGCNTarget
Target & getTheGCNTarget()
The target for GCN GPUs.
Definition: AMDGPUTargetInfo.cpp:25
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:908
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::createR600MCCodeEmitter
MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: R600MCCodeEmitter.cpp:82
LLVMInitializeAMDGPUTargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTargetMC()
Definition: AMDGPUMCTargetDesc.cpp:150
MCInstrAnalysis.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::RegisterMCAsmInfo
RegisterMCAsmInfo - Helper template for registering a target assembly info implementation.
Definition: TargetRegistry.h:1158
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::AMDGPUTargetStreamer
Definition: AMDGPUTargetStreamer.h:34
AMDGPUMCAsmInfo.h
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPUTargetAsmStreamer
Definition: AMDGPUTargetStreamer.h:119
MCObjectWriter.h
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:875
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:1001
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:895
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition: TargetRegistry.h:1013
createAMDGPUMCRegisterInfo
static MCRegisterInfo * createAMDGPUMCRegisterInfo(const Triple &TT)
Definition: AMDGPUMCTargetDesc.cpp:62
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
createAMDGPUNullTargetStreamer
static MCTargetStreamer * createAMDGPUNullTargetStreamer(MCStreamer &S)
Definition: AMDGPUMCTargetDesc.cpp:108
llvm::R600InstPrinter
Definition: R600InstPrinter.h:16
llvm::TargetRegistry::RegisterNullTargetStreamer
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1033
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
MCStreamer.h
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::AMDGPUTargetELFStreamer
Definition: AMDGPUTargetStreamer.h:159
createAMDGPUMCInstPrinter
static MCInstPrinter * createAMDGPUMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: AMDGPUMCTargetDesc.cpp:84
LaneBitmask.h
createAMDGPUMCSubtargetInfo
static MCSubtargetInfo * createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Definition: AMDGPUMCTargetDesc.cpp:78
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::createGCNMCRegisterInfo
MCRegisterInfo * createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour)
Definition: AMDGPUMCTargetDesc.cpp:71
createAMDGPUMCInstrInfo
static MCInstrInfo * createAMDGPUMCInstrInfo()
Definition: AMDGPUMCTargetDesc.cpp:56
llvm::createAMDGPUAsmBackend
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: AMDGPUAsmBackend.cpp:261