LLVM  13.0.0git
AMDGPUAsmBackend.cpp
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1 //===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
12 #include "Utils/AMDGPUBaseInfo.h"
13 #include "llvm/MC/MCAsmBackend.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCObjectWriter.h"
20 
21 using namespace llvm;
22 using namespace llvm::AMDGPU;
23 
24 namespace {
25 
26 class AMDGPUAsmBackend : public MCAsmBackend {
27 public:
28  AMDGPUAsmBackend(const Target &T) : MCAsmBackend(support::little) {}
29 
30  unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
31 
32  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
34  uint64_t Value, bool IsResolved,
35  const MCSubtargetInfo *STI) const override;
36  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
37  const MCRelaxableFragment *DF,
38  const MCAsmLayout &Layout) const override;
39 
40  void relaxInstruction(MCInst &Inst,
41  const MCSubtargetInfo &STI) const override;
42 
43  bool mayNeedRelaxation(const MCInst &Inst,
44  const MCSubtargetInfo &STI) const override;
45 
46  unsigned getMinimumNopSize() const override;
47  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
48 
49  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
50 };
51 
52 } //End anonymous namespace
53 
54 void AMDGPUAsmBackend::relaxInstruction(MCInst &Inst,
55  const MCSubtargetInfo &STI) const {
56  MCInst Res;
57  unsigned RelaxedOpcode = AMDGPU::getSOPPWithRelaxation(Inst.getOpcode());
58  Res.setOpcode(RelaxedOpcode);
59  Res.addOperand(Inst.getOperand(0));
60  Inst = std::move(Res);
61 }
62 
63 bool AMDGPUAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
64  uint64_t Value,
65  const MCRelaxableFragment *DF,
66  const MCAsmLayout &Layout) const {
67  // if the branch target has an offset of x3f this needs to be relaxed to
68  // add a s_nop 0 immediately after branch to effectively increment offset
69  // for hardware workaround in gfx1010
70  return (((int64_t(Value)/4)-1) == 0x3f);
71 }
72 
73 bool AMDGPUAsmBackend::mayNeedRelaxation(const MCInst &Inst,
74  const MCSubtargetInfo &STI) const {
75  if (!STI.getFeatureBits()[AMDGPU::FeatureOffset3fBug])
76  return false;
77 
79  return true;
80 
81  return false;
82 }
83 
84 static unsigned getFixupKindNumBytes(unsigned Kind) {
85  switch (Kind) {
87  return 2;
88  case FK_SecRel_1:
89  case FK_Data_1:
90  return 1;
91  case FK_SecRel_2:
92  case FK_Data_2:
93  return 2;
94  case FK_SecRel_4:
95  case FK_Data_4:
96  case FK_PCRel_4:
97  return 4;
98  case FK_SecRel_8:
99  case FK_Data_8:
100  return 8;
101  default:
102  llvm_unreachable("Unknown fixup kind!");
103  }
104 }
105 
106 static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
107  MCContext *Ctx) {
108  int64_t SignedValue = static_cast<int64_t>(Value);
109 
110  switch (Fixup.getTargetKind()) {
112  int64_t BrImm = (SignedValue - 4) / 4;
113 
114  if (Ctx && !isInt<16>(BrImm))
115  Ctx->reportError(Fixup.getLoc(), "branch size exceeds simm16");
116 
117  return BrImm;
118  }
119  case FK_Data_1:
120  case FK_Data_2:
121  case FK_Data_4:
122  case FK_Data_8:
123  case FK_PCRel_4:
124  case FK_SecRel_4:
125  return Value;
126  default:
127  llvm_unreachable("unhandled fixup kind");
128  }
129 }
130 
131 void AMDGPUAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
132  const MCValue &Target,
133  MutableArrayRef<char> Data, uint64_t Value,
134  bool IsResolved,
135  const MCSubtargetInfo *STI) const {
136  Value = adjustFixupValue(Fixup, Value, &Asm.getContext());
137  if (!Value)
138  return; // Doesn't change encoding.
139 
140  MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
141 
142  // Shift the value into position.
143  Value <<= Info.TargetOffset;
144 
145  unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
146  uint32_t Offset = Fixup.getOffset();
147  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
148 
149  // For each byte of the fragment that the fixup touches, mask in the bits from
150  // the fixup value.
151  for (unsigned i = 0; i != NumBytes; ++i)
152  Data[Offset + i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);
153 }
154 
155 const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
156  MCFixupKind Kind) const {
157  const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
158  // name offset bits flags
159  { "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
160  };
161 
164 
165  return Infos[Kind - FirstTargetFixupKind];
166 }
167 
168 unsigned AMDGPUAsmBackend::getMinimumNopSize() const {
169  return 4;
170 }
171 
172 bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
173  // If the count is not 4-byte aligned, we must be writing data into the text
174  // section (otherwise we have unaligned instructions, and thus have far
175  // bigger problems), so just write zeros instead.
176  OS.write_zeros(Count % 4);
177 
178  // We are properly aligned, so write NOPs as requested.
179  Count /= 4;
180 
181  // FIXME: R600 support.
182  // s_nop 0
183  const uint32_t Encoded_S_NOP_0 = 0xbf800000;
184 
185  for (uint64_t I = 0; I != Count; ++I)
186  support::endian::write<uint32_t>(OS, Encoded_S_NOP_0, Endian);
187 
188  return true;
189 }
190 
191 //===----------------------------------------------------------------------===//
192 // ELFAMDGPUAsmBackend class
193 //===----------------------------------------------------------------------===//
194 
195 namespace {
196 
197 class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
198  bool Is64Bit;
199  bool HasRelocationAddend;
200  uint8_t OSABI = ELF::ELFOSABI_NONE;
201  uint8_t ABIVersion = 0;
202 
203 public:
204  ELFAMDGPUAsmBackend(const Target &T, const Triple &TT, uint8_t ABIVersion) :
205  AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn),
206  HasRelocationAddend(TT.getOS() == Triple::AMDHSA),
207  ABIVersion(ABIVersion) {
208  switch (TT.getOS()) {
209  case Triple::AMDHSA:
210  OSABI = ELF::ELFOSABI_AMDGPU_HSA;
211  break;
212  case Triple::AMDPAL:
213  OSABI = ELF::ELFOSABI_AMDGPU_PAL;
214  break;
215  case Triple::Mesa3D:
217  break;
218  default:
219  break;
220  }
221  }
222 
223  std::unique_ptr<MCObjectTargetWriter>
224  createObjectTargetWriter() const override {
225  return createAMDGPUELFObjectWriter(Is64Bit, OSABI, HasRelocationAddend,
226  ABIVersion);
227  }
228 };
229 
230 } // end anonymous namespace
231 
233  const MCSubtargetInfo &STI,
234  const MCRegisterInfo &MRI,
235  const MCTargetOptions &Options) {
236  return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple(),
237  getHsaAbiVersion(&STI).getValueOr(0));
238 }
i
i
Definition: README.txt:29
llvm
Definition: AllocatorList.h:23
llvm::MCRelaxableFragment
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:271
AMDGPUFixupKinds.h
llvm::ARM::PredBlockMask::TT
@ TT
llvm::MCAsmBackend::getFixupKindInfo
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Definition: MCAsmBackend.cpp:74
llvm::raw_ostream::write_zeros
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
Definition: raw_ostream.cpp:502
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:71
llvm::AMDGPU::fixup_si_sopp_br
@ fixup_si_sopp_br
16-bit PC relative fixup for SOPP branch instructions.
Definition: AMDGPUFixupKinds.h:18
llvm::ELF::ELFOSABI_AMDGPU_MESA3D
@ ELFOSABI_AMDGPU_MESA3D
Definition: ELF.h:360
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:125
llvm::FirstTargetFixupKind
@ FirstTargetFixupKind
Definition: MCFixup.h:55
llvm::AMDGPU::getHsaAbiVersion
Optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:91
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
MCAssembler.h
llvm::ELF::ELFOSABI_AMDGPU_PAL
@ ELFOSABI_AMDGPU_PAL
Definition: ELF.h:359
MCFixupKindInfo.h
T
#define T
Definition: Mips16ISelLowering.cpp:341
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
adjustFixupValue
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext *Ctx)
Definition: AMDGPUAsmBackend.cpp:106
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::Data
@ Data
Definition: SIMachineScheduler.h:56
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
llvm::AMDGPU::getSOPPWithRelaxation
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::MCAsmBackend
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:36
MCAsmBackend.h
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
llvm::FK_SecRel_4
@ FK_SecRel_4
A four-byte section relative fixup.
Definition: MCFixup.h:42
llvm::support::little
@ little
Definition: Endian.h:27
llvm::Triple::Mesa3D
@ Mesa3D
Definition: Triple.h:195
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
getFixupKindNumBytes
static unsigned getFixupKindNumBytes(unsigned Kind)
Definition: AMDGPUAsmBackend.cpp:84
MCContext.h
llvm::FK_SecRel_2
@ FK_SecRel_2
A two-byte section relative fixup.
Definition: MCFixup.h:41
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::AMDGPU
Definition: AMDGPUMetadataVerifier.h:22
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
DF
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::Triple::AMDHSA
@ AMDHSA
Definition: Triple.h:190
llvm::MCAssembler
Definition: MCAssembler.h:60
AMDGPUMCTargetDesc.h
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCFixupKindInfo::FKF_IsPCRel
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
Definition: MCFixupKindInfo.h:19
I
#define I(x, y, z)
Definition: MD5.cpp:59
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCFixupKindInfo
Target independent information on a fixup kind.
Definition: MCFixupKindInfo.h:15
llvm::ELF::ELFOSABI_NONE
@ ELFOSABI_NONE
Definition: ELF.h:339
llvm::MCContext::reportError
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:948
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
llvm::FK_PCRel_4
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:235
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
uint32_t
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::FK_SecRel_1
@ FK_SecRel_1
A one-byte section relative fixup.
Definition: MCFixup.h:40
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::isInt< 16 >
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:370
MCObjectWriter.h
llvm::AMDGPU::NumTargetFixupKinds
@ NumTargetFixupKinds
Definition: AMDGPUFixupKinds.h:22
EndianStream.h
llvm::MCAsmLayout
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
llvm::FK_SecRel_8
@ FK_SecRel_8
A eight-byte section relative fixup.
Definition: MCFixup.h:43
llvm::Triple::AMDPAL
@ AMDPAL
Definition: Triple.h:197
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::ELF::ELFOSABI_AMDGPU_HSA
@ ELFOSABI_AMDGPU_HSA
Definition: ELF.h:358
llvm::FK_Data_8
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
support
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
Definition: README.txt:10
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:34
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:37
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:81
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
AMDGPUBaseInfo.h
llvm::createAMDGPUELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend, uint8_t ABIVersion)
Definition: AMDGPUELFObjectWriter.cpp:92
llvm::createAMDGPUAsmBackend
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: AMDGPUAsmBackend.cpp:232