Go to the documentation of this file.
14 #ifndef LLVM_MC_MCINSTRANALYSIS_H
15 #define LLVM_MC_MCINSTRANALYSIS_H
112 unsigned CPUID)
const {
137 unsigned CPUID)
const {
148 unsigned CPUID)
const {
170 virtual std::vector<std::pair<uint64_t, uint64_t>>
179 #endif // LLVM_MC_MCINSTRANALYSIS_H
virtual bool isBranch(const MCInst &Inst) const
This is an optimization pass for GlobalISel generic memory operations.
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
virtual bool isDependencyBreaking(const MCInst &MI, APInt &Mask, unsigned CPUID) const
Returns true if MI is a dependency breaking instruction for the subtarget associated with CPUID .
Target - Wrapper for Target specific information.
virtual Optional< uint64_t > getMemoryOperandRelocationOffset(const MCInst &Inst, uint64_t Size) const
Given an instruction with a memory operand that could require relocation, returns the offset within t...
virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, APInt &Writes) const
Returns true if at least one of the register writes performed by.
Triple - Helper class for working with autoconf configuration names.
MCInstrAnalysis(const MCInstrInfo *Info)
Instances of this class represent a single low-level machine instruction.
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
virtual bool isZeroIdiom(const MCInst &MI, APInt &Mask, unsigned CPUID) const
Returns true if MI is a dependency breaking zero-idiom for the given subtarget.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
virtual std::vector< std::pair< uint64_t, uint64_t > > findPltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, uint64_t GotPltSectionVA, const Triple &TargetTriple) const
Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
virtual bool isCall(const MCInst &Inst) const
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
virtual Optional< uint64_t > evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, uint64_t Size) const
Given an instruction tries to get the address of a memory operand.
virtual bool isUnconditionalBranch(const MCInst &Inst) const
virtual bool isReturn(const MCInst &Inst) const
virtual ~MCInstrAnalysis()=default
virtual bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const
Given a branch instruction try to get the address the branch targets.
virtual bool isConditionalBranch(const MCInst &Inst) const
bool isCall() const
Return true if the instruction is a call.
Class for arbitrary precision integers.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
Interface to description of machine instruction set.
unsigned getOpcode() const
virtual bool isOptimizableRegisterMove(const MCInst &MI, unsigned CPUID) const
Returns true if MI is a candidate for move elimination.
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block.
bool isReturn() const
Return true if the instruction is a return.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
virtual bool isIndirectBranch(const MCInst &Inst) const
Generic base class for all target subtargets.
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
virtual bool isTerminator(const MCInst &Inst) const