LLVM 17.0.0git
MCInstrAnalysis.h
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1//===- llvm/MC/MCInstrAnalysis.h - InstrDesc target hooks -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the MCInstrAnalysis class which the MCTargetDescs can
10// derive from to give additional information to MC.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_MC_MCINSTRANALYSIS_H
15#define LLVM_MC_MCINSTRANALYSIS_H
16
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCInstrDesc.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include <cstdint>
22#include <vector>
23
24namespace llvm {
25
26class MCRegisterInfo;
27class Triple;
28
30protected:
31 friend class Target;
32
34
35public:
37 virtual ~MCInstrAnalysis() = default;
38
39 virtual bool isBranch(const MCInst &Inst) const {
40 return Info->get(Inst.getOpcode()).isBranch();
41 }
42
43 virtual bool isConditionalBranch(const MCInst &Inst) const {
44 return Info->get(Inst.getOpcode()).isConditionalBranch();
45 }
46
47 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
48 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
49 }
50
51 virtual bool isIndirectBranch(const MCInst &Inst) const {
52 return Info->get(Inst.getOpcode()).isIndirectBranch();
53 }
54
55 virtual bool isCall(const MCInst &Inst) const {
56 return Info->get(Inst.getOpcode()).isCall();
57 }
58
59 virtual bool isReturn(const MCInst &Inst) const {
60 return Info->get(Inst.getOpcode()).isReturn();
61 }
62
63 virtual bool isTerminator(const MCInst &Inst) const {
64 return Info->get(Inst.getOpcode()).isTerminator();
65 }
66
67 /// Returns true if at least one of the register writes performed by
68 /// \param Inst implicitly clears the upper portion of all super-registers.
69 ///
70 /// Example: on X86-64, a write to EAX implicitly clears the upper half of
71 /// RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit
72 /// instruction implicitly clears the upper portion of the correspondent
73 /// YMM register.
74 ///
75 /// This method also updates an APInt which is used as mask of register
76 /// writes. There is one bit for every explicit/implicit write performed by
77 /// the instruction. If a write implicitly clears its super-registers, then
78 /// the corresponding bit is set (vic. the corresponding bit is cleared).
79 ///
80 /// The first bits in the APint are related to explicit writes. The remaining
81 /// bits are related to implicit writes. The sequence of writes follows the
82 /// machine operand sequence. For implicit writes, the sequence is defined by
83 /// the MCInstrDesc.
84 ///
85 /// The assumption is that the bit-width of the APInt is correctly set by
86 /// the caller. The default implementation conservatively assumes that none of
87 /// the writes clears the upper portion of a super-register.
88 virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI,
89 const MCInst &Inst,
90 APInt &Writes) const;
91
92 /// Returns true if MI is a dependency breaking zero-idiom for the given
93 /// subtarget.
94 ///
95 /// Mask is used to identify input operands that have their dependency
96 /// broken. Each bit of the mask is associated with a specific input operand.
97 /// Bits associated with explicit input operands are laid out first in the
98 /// mask; implicit operands come after explicit operands.
99 ///
100 /// Dependencies are broken only for operands that have their corresponding bit
101 /// set. Operands that have their bit cleared, or that don't have a
102 /// corresponding bit in the mask don't have their dependency broken. Note
103 /// that Mask may not be big enough to describe all operands. The assumption
104 /// for operands that don't have a correspondent bit in the mask is that those
105 /// are still data dependent.
106 ///
107 /// The only exception to the rule is for when Mask has all zeroes.
108 /// A zero mask means: dependencies are broken for all explicit register
109 /// operands.
110 virtual bool isZeroIdiom(const MCInst &MI, APInt &Mask,
111 unsigned CPUID) const {
112 return false;
113 }
114
115 /// Returns true if MI is a dependency breaking instruction for the
116 /// subtarget associated with CPUID .
117 ///
118 /// The value computed by a dependency breaking instruction is not dependent
119 /// on the inputs. An example of dependency breaking instruction on X86 is
120 /// `XOR %eax, %eax`.
121 ///
122 /// If MI is a dependency breaking instruction for subtarget CPUID, then Mask
123 /// can be inspected to identify independent operands.
124 ///
125 /// Essentially, each bit of the mask corresponds to an input operand.
126 /// Explicit operands are laid out first in the mask; implicit operands follow
127 /// explicit operands. Bits are set for operands that are independent.
128 ///
129 /// Note that the number of bits in Mask may not be equivalent to the sum of
130 /// explicit and implicit operands in MI. Operands that don't have a
131 /// corresponding bit in Mask are assumed "not independente".
132 ///
133 /// The only exception is for when Mask is all zeroes. That means: explicit
134 /// input operands of MI are independent.
135 virtual bool isDependencyBreaking(const MCInst &MI, APInt &Mask,
136 unsigned CPUID) const {
137 return isZeroIdiom(MI, Mask, CPUID);
138 }
139
140 /// Returns true if MI is a candidate for move elimination.
141 ///
142 /// Different subtargets may apply different constraints to optimizable
143 /// register moves. For example, on most X86 subtargets, a candidate for move
144 /// elimination cannot specify the same register for both source and
145 /// destination.
147 unsigned CPUID) const {
148 return false;
149 }
150
151 /// Given a branch instruction try to get the address the branch
152 /// targets. Return true on success, and the address in Target.
153 virtual bool
155 uint64_t &Target) const;
156
157 /// Given an instruction tries to get the address of a memory operand. Returns
158 /// the address on success.
159 virtual std::optional<uint64_t>
161 uint64_t Addr, uint64_t Size) const;
162
163 /// Given an instruction with a memory operand that could require relocation,
164 /// returns the offset within the instruction of that relocation.
165 virtual std::optional<uint64_t>
167
168 /// Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
169 virtual std::vector<std::pair<uint64_t, uint64_t>>
170 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
171 uint64_t GotPltSectionVA, const Triple &TargetTriple) const {
172 return {};
173 }
174};
175
176} // end namespace llvm
177
178#endif // LLVM_MC_MCINSTRANALYSIS_H
unsigned const MachineRegisterInfo * MRI
uint64_t Addr
uint64_t Size
IRTranslator LLVM IR MI
Class for arbitrary precision integers.
Definition: APInt.h:75
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
virtual bool isCall(const MCInst &Inst) const
virtual bool isBranch(const MCInst &Inst) const
virtual bool isOptimizableRegisterMove(const MCInst &MI, unsigned CPUID) const
Returns true if MI is a candidate for move elimination.
virtual bool isDependencyBreaking(const MCInst &MI, APInt &Mask, unsigned CPUID) const
Returns true if MI is a dependency breaking instruction for the subtarget associated with CPUID .
virtual bool isUnconditionalBranch(const MCInst &Inst) const
virtual bool isZeroIdiom(const MCInst &MI, APInt &Mask, unsigned CPUID) const
Returns true if MI is a dependency breaking zero-idiom for the given subtarget.
virtual std::optional< uint64_t > getMemoryOperandRelocationOffset(const MCInst &Inst, uint64_t Size) const
Given an instruction with a memory operand that could require relocation, returns the offset within t...
virtual bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const
Given a branch instruction try to get the address the branch targets.
virtual bool isTerminator(const MCInst &Inst) const
virtual bool isConditionalBranch(const MCInst &Inst) const
virtual bool isReturn(const MCInst &Inst) const
virtual std::optional< uint64_t > evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, uint64_t Size) const
Given an instruction tries to get the address of a memory operand.
virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, APInt &Writes) const
Returns true if at least one of the register writes performed by.
virtual std::vector< std::pair< uint64_t, uint64_t > > findPltEntries(uint64_t PltSectionVA, ArrayRef< uint8_t > PltContents, uint64_t GotPltSectionVA, const Triple &TargetTriple) const
Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
const MCInstrInfo * Info
MCInstrAnalysis(const MCInstrInfo *Info)
virtual ~MCInstrAnalysis()=default
virtual bool isIndirectBranch(const MCInst &Inst) const
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MCInstrDesc.h:310
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:306
bool isUnconditionalBranch() const
Return true if this is a branch which always transfers control flow to some other block.
Definition: MCInstrDesc.h:324
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:287
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:300
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:275
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:316
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18