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28 #define DEBUG_TYPE "avr-disassembler"
39 virtual ~AVRDisassembler() =
default;
50 return new AVRDisassembler(STI, Ctx);
61 AVR::R7, AVR::R8, AVR::R9, AVR::R10, AVR::R11, AVR::R12, AVR::R13,
62 AVR::R14, AVR::R15, AVR::R16, AVR::R17, AVR::R18, AVR::R19, AVR::R20,
63 AVR::R21, AVR::R22, AVR::R23, AVR::R24, AVR::R25, AVR::R26, AVR::R27,
64 AVR::R28, AVR::R29, AVR::R30, AVR::R31,
130 #include "AVRGenDisassemblerTables.inc"
135 addr |= fieldFromInstruction(
Insn, 0, 4);
136 addr |= fieldFromInstruction(
Insn, 9, 2) << 4;
137 unsigned reg = fieldFromInstruction(
Insn, 4, 5);
148 addr |= fieldFromInstruction(
Insn, 0, 4);
149 addr |= fieldFromInstruction(
Insn, 9, 2) << 4;
150 unsigned reg = fieldFromInstruction(
Insn, 4, 5);
160 unsigned addr = fieldFromInstruction(
Insn, 3, 5);
161 unsigned b = fieldFromInstruction(
Insn, 0, 3);
178 unsigned d = fieldFromInstruction(
Insn, 4, 5);
196 unsigned d = fieldFromInstruction(
Insn, 4, 3) + 16;
197 unsigned r = fieldFromInstruction(
Insn, 0, 3) + 16;
210 unsigned r = fieldFromInstruction(
Insn, 4, 4) * 2;
211 unsigned d = fieldFromInstruction(
Insn, 0, 4) * 2;
223 unsigned d = fieldFromInstruction(
Insn, 4, 2) * 2 + 24;
225 k |= fieldFromInstruction(
Insn, 0, 4);
226 k |= fieldFromInstruction(
Insn, 6, 2) << 4;
240 unsigned rd = fieldFromInstruction(
Insn, 4, 4) + 16;
241 unsigned rr = fieldFromInstruction(
Insn, 0, 4) + 16;
275 if ((
Insn & 0xf000) == 0x8000) {
276 unsigned RegBase = (
Insn & 0x8) ? AVR::R29R28 : AVR::R31R30;
277 unsigned Offset =
Insn & 7;
278 if ((
Insn & 0x200) == 0) {
310 if ((
Insn & 0xfc00) != 0x9000 || (
Insn & 0xf) == 0)
315 switch (
Insn & 0xc) {
317 RegBase = AVR::R27R26;
320 RegBase = AVR::R29R28;
323 RegBase = AVR::R31R30;
330 switch (
Insn & 0x203) {
358 if ((
Insn & 0x200) == 0) {
375 if (Bytes.
size() < 2) {
381 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
389 if (Bytes.
size() < 4) {
396 (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) | (Bytes[3] << 8);
405 return DecoderTable16;
407 return DecoderTable32;
static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
This is an optimization pass for GlobalISel generic memory operations.
static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static MCOperand createImm(int64_t Val)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRDisassembler()
Context object for machine code objects.
static DecodeStatus decodeLoadStore(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
DecodeStatus(* DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Target - Wrapper for Target specific information.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Instances of this class represent a single low-level machine instruction.
void setOpcode(unsigned Op)
static const uint8_t * getDecoderTable(uint64_t Size)
static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
Target & getTheAVRTarget()
static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream.
DecodeStatus
Ternary decode status.
static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
void addOperand(const MCOperand Op)
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)
#define LLVM_EXTERNAL_VISIBILITY
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)
Superclass for all disassemblers.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static MCOperand createReg(unsigned Reg)
static DecodeStatus decodeMemri(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createAVRDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Wrapper class representing virtual and physical registers.
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
static const uint16_t GPRDecoderTable[]
static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
size_t size() const
size - Get the array size.
static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int int int d
Generic base class for all target subtargets.
static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)