LLVM  16.0.0git
Macros | Functions | Variables
GCNSchedStrategy.cpp File Reference
#include "GCNSchedStrategy.h"
#include "AMDGPUIGroupLP.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
Include dependency graph for GCNSchedStrategy.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "machine-scheduler"
 Generally, the reason for having multiple scheduling stages is to account for the kernel-wide effect of register usage on occupancy. More...
 

Functions

static bool hasIGLPInstrs (ScheduleDAGInstrs *DAG)
 

Variables

static cl::opt< bool > DisableUnclusterHighRP ("amdgpu-disable-unclustred-high-rp-reschedule", cl::Hidden, cl::desc("Disable unclustred high register pressure " "reduction scheduling stage."), cl::init(false))
 

Detailed Description

This contains a MachineSchedStrategy implementation for maximizing wave occupancy on GCN hardware.

This pass will apply multiple scheduling stages to the same function. Regions are first recorded in GCNScheduleDAGMILive::schedule. The actual entry point for the scheduling of those regions is GCNScheduleDAGMILive::runSchedStages.

Definition in file GCNSchedStrategy.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "machine-scheduler"

Generally, the reason for having multiple scheduling stages is to account for the kernel-wide effect of register usage on occupancy.

Usually, only a few scheduling regions will have register pressure high enough to limit occupancy for the kernel, so constraints can be relaxed to improve ILP in other regions.

Definition at line 31 of file GCNSchedStrategy.cpp.

Function Documentation

◆ hasIGLPInstrs()

static bool hasIGLPInstrs ( ScheduleDAGInstrs DAG)
static

Variable Documentation

◆ DisableUnclusterHighRP

cl::opt<bool> DisableUnclusterHighRP("amdgpu-disable-unclustred-high-rp-reschedule", cl::Hidden, cl::desc("Disable unclustred high register pressure " "reduction scheduling stage."), cl::init(false))
static