LLVM  16.0.0git
GCNSchedStrategy.h
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1 //===-- GCNSchedStrategy.h - GCN Scheduler Strategy -*- C++ -*-------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_GCNSCHEDSTRATEGY_H
14 #define LLVM_LIB_TARGET_AMDGPU_GCNSCHEDSTRATEGY_H
15 
16 #include "GCNRegPressure.h"
17 #include "llvm/ADT/MapVector.h"
19 
20 namespace llvm {
21 
22 class SIMachineFunctionInfo;
23 class SIRegisterInfo;
24 class GCNSubtarget;
25 class GCNSchedStage;
26 
27 enum class GCNSchedStageID : unsigned {
33 };
34 
35 #ifndef NDEBUG
36 raw_ostream &operator<<(raw_ostream &OS, const GCNSchedStageID &StageID);
37 #endif
38 
39 /// This is a minimal scheduler strategy. The main difference between this
40 /// and the GenericScheduler is that GCNSchedStrategy uses different
41 /// heuristics to determine excess/critical pressure sets.
43 protected:
44  SUnit *pickNodeBidirectional(bool &IsTopNode);
45 
46  void pickNodeFromQueue(SchedBoundary &Zone, const CandPolicy &ZonePolicy,
47  const RegPressureTracker &RPTracker,
48  SchedCandidate &Cand);
49 
50  void initCandidate(SchedCandidate &Cand, SUnit *SU,
51  bool AtTop, const RegPressureTracker &RPTracker,
52  const SIRegisterInfo *SRI,
53  unsigned SGPRPressure, unsigned VGPRPressure);
54 
55  std::vector<unsigned> Pressure;
56 
57  std::vector<unsigned> MaxPressure;
58 
59  unsigned SGPRExcessLimit;
60 
61  unsigned VGPRExcessLimit;
62 
63  unsigned TargetOccupancy;
64 
66 
67  // Scheduling stages for this strategy.
69 
70  // Pointer to the current SchedStageID.
72 
73 public:
74  // schedule() have seen register pressure over the critical limits and had to
75  // track register pressure for actual scheduling heuristics.
77 
78  // An error margin is necessary because of poor performance of the generic RP
79  // tracker and can be adjusted up for tuning heuristics to try and more
80  // aggressively reduce register pressure.
81  const unsigned DefaultErrorMargin = 3;
82 
83  const unsigned HighRPErrorMargin = 10;
84 
86 
88 
90 
92 
93  SUnit *pickNode(bool &IsTopNode) override;
94 
95  void initialize(ScheduleDAGMI *DAG) override;
96 
97  unsigned getTargetOccupancy() { return TargetOccupancy; }
98 
99  void setTargetOccupancy(unsigned Occ) { TargetOccupancy = Occ; }
100 
102 
103  // Advances stage. Returns true if there are remaining stages.
104  bool advanceStage();
105 
106  bool hasNextStage() const;
107 
109 };
110 
111 /// The goal of this scheduling strategy is to maximize kernel occupancy (i.e.
112 /// maximum number of waves per simd).
114 public:
116 };
117 
118 /// The goal of this scheduling strategy is to maximize ILP for a single wave
119 /// (i.e. latency hiding).
121 protected:
122  bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand,
123  SchedBoundary *Zone) const override;
124 
125 public:
127 };
128 
130  friend class GCNSchedStage;
133  friend class ClusteredLowOccStage;
134  friend class PreRARematStage;
136 
137  const GCNSubtarget &ST;
138 
140 
141  // Occupancy target at the beginning of function scheduling cycle.
142  unsigned StartingOccupancy;
143 
144  // Minimal real occupancy recorder for the function.
145  unsigned MinOccupancy;
146 
147  // Vector of regions recorder for later rescheduling
149  MachineBasicBlock::iterator>, 32> Regions;
150 
151  // Records if a region is not yet scheduled, or schedule has been reverted,
152  // or we generally desire to reschedule it.
153  BitVector RescheduleRegions;
154 
155  // Record regions with high register pressure.
156  BitVector RegionsWithHighRP;
157 
158  // Record regions with excess register pressure over the physical register
159  // limit. Register pressure in these regions usually will result in spilling.
160  BitVector RegionsWithExcessRP;
161 
162  // Regions that has the same occupancy as the latest MinOccupancy
163  BitVector RegionsWithMinOcc;
164 
165  // Regions that have IGLP instructions (SCHED_GROUP_BARRIER or IGLP_OPT).
166  BitVector RegionsWithIGLPInstrs;
167 
168  // Region live-in cache.
170 
171  // Region pressure cache.
173 
174  // Temporary basic block live-in cache.
176 
178 
180 
181  // Return current region pressure.
182  GCNRegPressure getRealRegPressure(unsigned RegionIdx) const;
183 
184  // Compute and cache live-ins and pressure for all regions in block.
185  void computeBlockPressure(unsigned RegionIdx, const MachineBasicBlock *MBB);
186 
187  // Update region boundaries when removing MI or inserting NewMI before MI.
188  void updateRegionBoundaries(
190  MachineBasicBlock::iterator>> &RegionBoundaries,
192  bool Removing = false);
193 
194  void runSchedStages();
195 
196  std::unique_ptr<GCNSchedStage> createSchedStage(GCNSchedStageID SchedStageID);
197 
198 public:
200  std::unique_ptr<MachineSchedStrategy> S);
201 
202  void schedule() override;
203 
204  void finalizeSchedule() override;
205 };
206 
207 // GCNSchedStrategy applies multiple scheduling stages to a function.
209 protected:
211 
213 
215 
217 
218  const GCNSubtarget &ST;
219 
221 
222  // The current block being scheduled.
224 
225  // Current region index.
226  unsigned RegionIdx = 0;
227 
228  // Record the original order of instructions before scheduling.
229  std::vector<MachineInstr *> Unsched;
230 
231  // RP before scheduling the current region.
233 
234  // RP after scheduling the current region.
236 
237  std::vector<std::unique_ptr<ScheduleDAGMutation>> SavedMutations;
238 
240 
241 public:
242  // Initialize state for a scheduling stage. Returns false if the current stage
243  // should be skipped.
244  virtual bool initGCNSchedStage();
245 
246  // Finalize state after finishing a scheduling pass on the function.
247  virtual void finalizeGCNSchedStage();
248 
249  // Setup for scheduling a region. Returns false if the current region should
250  // be skipped.
251  virtual bool initGCNRegion();
252 
253  // Track whether a new region is also a new MBB.
254  void setupNewBlock();
255 
256  // Finalize state after scheudling a region.
257  void finalizeGCNRegion();
258 
259  // Check result of scheduling.
260  void checkScheduling();
261 
262  // Returns true if scheduling should be reverted.
263  virtual bool shouldRevertScheduling(unsigned WavesAfter);
264 
265  // Returns true if the new schedule may result in more spilling.
266  bool mayCauseSpilling(unsigned WavesAfter);
267 
268  // Attempt to revert scheduling for this region.
269  void revertScheduling();
270 
271  void advanceRegion() { RegionIdx++; }
272 
273  virtual ~GCNSchedStage() = default;
274 };
275 
277 public:
278  bool shouldRevertScheduling(unsigned WavesAfter) override;
279 
281  : GCNSchedStage(StageID, DAG) {}
282 };
283 
285 private:
286  // Save the initial occupancy before starting this stage.
287  unsigned InitialOccupancy;
288 
289 public:
290  bool initGCNSchedStage() override;
291 
292  void finalizeGCNSchedStage() override;
293 
294  bool initGCNRegion() override;
295 
296  bool shouldRevertScheduling(unsigned WavesAfter) override;
297 
299  : GCNSchedStage(StageID, DAG) {}
300 };
301 
302 // Retry function scheduling if we found resulting occupancy and it is
303 // lower than used for other scheduling passes. This will give more freedom
304 // to schedule low register pressure blocks.
306 public:
307  bool initGCNSchedStage() override;
308 
309  bool initGCNRegion() override;
310 
311  bool shouldRevertScheduling(unsigned WavesAfter) override;
312 
314  : GCNSchedStage(StageID, DAG) {}
315 };
316 
318 private:
319  // Each region at MinOccupancy will have their own list of trivially
320  // rematerializable instructions we can remat to reduce RP. The list maps an
321  // instruction to the position we should remat before, usually the MI using
322  // the rematerializable instruction.
324  RematerializableInsts;
325 
326  // Map a trivially remateriazable def to a list of regions at MinOccupancy
327  // that has the defined reg as a live-in.
328  DenseMap<MachineInstr *, SmallVector<unsigned, 4>> RematDefToLiveInRegions;
329 
330  // Collect all trivially rematerializable VGPR instructions with a single def
331  // and single use outside the defining block into RematerializableInsts.
332  void collectRematerializableInstructions();
333 
334  bool isTriviallyReMaterializable(const MachineInstr &MI);
335 
336  // TODO: Should also attempt to reduce RP of SGPRs and AGPRs
337  // Attempt to reduce RP of VGPR by sinking trivially rematerializable
338  // instructions. Returns true if we were able to sink instruction(s).
339  bool sinkTriviallyRematInsts(const GCNSubtarget &ST,
340  const TargetInstrInfo *TII);
341 
342 public:
343  bool initGCNSchedStage() override;
344 
345  bool initGCNRegion() override;
346 
347  bool shouldRevertScheduling(unsigned WavesAfter) override;
348 
350  : GCNSchedStage(StageID, DAG) {}
351 };
352 
354 public:
355  bool shouldRevertScheduling(unsigned WavesAfter) override;
356 
358  : GCNSchedStage(StageID, DAG) {}
359 };
360 
362 private:
363  std::vector<std::unique_ptr<ScheduleDAGMutation>> SavedMutations;
364 
365  bool HasIGLPInstrs = false;
366 
367 public:
368  void schedule() override;
369 
370  void finalizeSchedule() override;
371 
373  std::unique_ptr<MachineSchedStrategy> S,
374  bool RemoveKillFlags);
375 };
376 
377 } // End namespace llvm
378 
379 #endif // LLVM_LIB_TARGET_AMDGPU_GCNSCHEDSTRATEGY_H
llvm::GCNSchedStageID::OccInitialSchedule
@ OccInitialSchedule
llvm::ClusteredLowOccStage
Definition: GCNSchedStrategy.h:305
llvm::ClusteredLowOccStage::initGCNSchedStage
bool initGCNSchedStage() override
Definition: GCNSchedStrategy.cpp:678
llvm::GCNSchedStage
Definition: GCNSchedStrategy.h:208
llvm::GCNSchedStrategy::TargetOccupancy
unsigned TargetOccupancy
Definition: GCNSchedStrategy.h:63
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::GCNRegPressure
Definition: GCNRegPressure.h:30
llvm::ClusteredLowOccStage::initGCNRegion
bool initGCNRegion() override
Definition: GCNSchedStrategy.cpp:812
llvm::GCNSchedStrategy::pickNodeBidirectional
SUnit * pickNodeBidirectional(bool &IsTopNode)
Definition: GCNSchedStrategy.cpp:198
llvm::UnclusteredHighRPStage
Definition: GCNSchedStrategy.h:284
llvm::GCNSchedStage::~GCNSchedStage
virtual ~GCNSchedStage()=default
llvm::GCNSchedStage::MF
MachineFunction & MF
Definition: GCNSchedStrategy.h:214
llvm::GCNSchedStrategy::CurrentStage
SmallVectorImpl< GCNSchedStageID >::iterator CurrentStage
Definition: GCNSchedStrategy.h:71
llvm::PreRARematStage::shouldRevertScheduling
bool shouldRevertScheduling(unsigned WavesAfter) override
Definition: GCNSchedStrategy.cpp:968
llvm::GCNMaxILPSchedStrategy::GCNMaxILPSchedStrategy
GCNMaxILPSchedStrategy(const MachineSchedContext *C)
Definition: GCNSchedStrategy.cpp:352
llvm::ClusteredLowOccStage::ClusteredLowOccStage
ClusteredLowOccStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
Definition: GCNSchedStrategy.h:313
llvm::OccInitialScheduleStage::OccInitialScheduleStage
OccInitialScheduleStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
Definition: GCNSchedStrategy.h:280
llvm::SmallVector< GCNSchedStageID, 4 >
llvm::GCNSchedStageID
GCNSchedStageID
Definition: GCNSchedStrategy.h:27
llvm::GCNMaxILPSchedStrategy::tryCandidate
bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, SchedBoundary *Zone) const override
Apply a set of heuristics to a new candidate.
Definition: GCNSchedStrategy.cpp:357
MapVector.h
llvm::GCNSchedStageID::UnclusteredHighRPReschedule
@ UnclusteredHighRPReschedule
llvm::GCNSchedStage::advanceRegion
void advanceRegion()
Definition: GCNSchedStrategy.h:271
llvm::GCNSchedStrategy::SGPRExcessLimit
unsigned SGPRExcessLimit
Definition: GCNSchedStrategy.h:59
llvm::RegPressureTracker
Track the current register pressure at some position in the instruction stream, and remember the high...
Definition: RegisterPressure.h:357
llvm::GCNScheduleDAGMILive
Definition: GCNSchedStrategy.h:129
llvm::MapVector
This class implements a map that also provides access to all stored values in a deterministic order.
Definition: MapVector.h:37
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::UnclusteredHighRPStage::UnclusteredHighRPStage
UnclusteredHighRPStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
Definition: GCNSchedStrategy.h:298
llvm::GCNScheduleDAGMILive::finalizeSchedule
void finalizeSchedule() override
Allow targets to perform final scheduling actions at the level of the whole MachineFunction.
Definition: GCNSchedStrategy.cpp:563
llvm::GCNSchedStrategy::ErrorMargin
unsigned ErrorMargin
Definition: GCNSchedStrategy.h:85
llvm::PreRARematStage::initGCNRegion
bool initGCNRegion() override
Definition: GCNSchedStrategy.cpp:824
llvm::GCNSchedStage::MFI
SIMachineFunctionInfo & MFI
Definition: GCNSchedStrategy.h:216
llvm::UnclusteredHighRPStage::initGCNSchedStage
bool initGCNSchedStage() override
Definition: GCNSchedStrategy.cpp:649
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::UnclusteredHighRPStage::initGCNRegion
bool initGCNRegion() override
Definition: GCNSchedStrategy.cpp:801
llvm::GCNSchedStrategy::MF
MachineFunction * MF
Definition: GCNSchedStrategy.h:65
llvm::GCNMaxOccupancySchedStrategy
The goal of this scheduling strategy is to maximize kernel occupancy (i.e.
Definition: GCNSchedStrategy.h:113
llvm::GCNSchedStrategy::HighRPErrorMargin
const unsigned HighRPErrorMargin
Definition: GCNSchedStrategy.h:83
llvm::GCNSchedStage::S
GCNSchedStrategy & S
Definition: GCNSchedStrategy.h:212
llvm::GCNMaxILPSchedStrategy
The goal of this scheduling strategy is to maximize ILP for a single wave (i.e.
Definition: GCNSchedStrategy.h:120
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::PreRARematStage::PreRARematStage
PreRARematStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
Definition: GCNSchedStrategy.h:349
llvm::GenericSchedulerBase::CandPolicy
Policy for scheduling the next instruction in the candidate's zone.
Definition: MachineScheduler.h:825
llvm::UnclusteredHighRPStage::shouldRevertScheduling
bool shouldRevertScheduling(unsigned WavesAfter) override
Definition: GCNSchedStrategy.cpp:945
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:291
llvm::GCNSchedStageID::PreRARematerialize
@ PreRARematerialize
llvm::GCNSchedStage::finalizeGCNSchedStage
virtual void finalizeGCNSchedStage()
Definition: GCNSchedStrategy.cpp:723
llvm::ILPInitialScheduleStage
Definition: GCNSchedStrategy.h:353
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::BitVector
Definition: BitVector.h:75
llvm::GCNSchedStrategy::MaxPressure
std::vector< unsigned > MaxPressure
Definition: GCNSchedStrategy.h:57
llvm::GCNSchedStrategy::initialize
void initialize(ScheduleDAGMI *DAG) override
Initialize the strategy after building the DAG for a new region.
Definition: GCNSchedStrategy.cpp:46
llvm::GCNSchedStrategy::getNextStage
GCNSchedStageID getNextStage() const
Definition: GCNSchedStrategy.cpp:338
llvm::OccInitialScheduleStage
Definition: GCNSchedStrategy.h:276
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::GCNSchedStrategy::getTargetOccupancy
unsigned getTargetOccupancy()
Definition: GCNSchedStrategy.h:97
llvm::GenericSchedulerBase::SchedCandidate
Store the state used by GenericScheduler heuristics, required for the lifetime of one invocation of p...
Definition: MachineScheduler.h:863
llvm::GCNSchedStage::Unsched
std::vector< MachineInstr * > Unsched
Definition: GCNSchedStrategy.h:229
llvm::GCNSchedStage::initGCNSchedStage
virtual bool initGCNSchedStage()
Definition: GCNSchedStrategy.cpp:641
llvm::GCNSchedStage::setupNewBlock
void setupNewBlock()
Definition: GCNSchedStrategy.cpp:831
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::GCNSchedStrategy::initCandidate
void initCandidate(SchedCandidate &Cand, SUnit *SU, bool AtTop, const RegPressureTracker &RPTracker, const SIRegisterInfo *SRI, unsigned SGPRPressure, unsigned VGPRPressure)
Definition: GCNSchedStrategy.cpp:77
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::GCNSchedStage::mayCauseSpilling
bool mayCauseSpilling(unsigned WavesAfter)
Definition: GCNSchedStrategy.cpp:985
llvm::DenseMap
Definition: DenseMap.h:714
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:127
llvm::GCNSchedStage::revertScheduling
void revertScheduling()
Definition: GCNSchedStrategy.cpp:996
llvm::GCNSchedStage::DAG
GCNScheduleDAGMILive & DAG
Definition: GCNSchedStrategy.h:210
llvm::GCNSchedStrategy
This is a minimal scheduler strategy.
Definition: GCNSchedStrategy.h:42
llvm::GCNSchedStage::StageID
const GCNSchedStageID StageID
Definition: GCNSchedStrategy.h:220
llvm::ClusteredLowOccStage::shouldRevertScheduling
bool shouldRevertScheduling(unsigned WavesAfter) override
Definition: GCNSchedStrategy.cpp:958
llvm::GCNSchedStage::RegionIdx
unsigned RegionIdx
Definition: GCNSchedStrategy.h:226
llvm::ILPInitialScheduleStage::ILPInitialScheduleStage
ILPInitialScheduleStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
Definition: GCNSchedStrategy.h:357
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:273
llvm::GCNPostScheduleDAGMILive::finalizeSchedule
void finalizeSchedule() override
Allow targets to perform final scheduling actions at the level of the whole MachineFunction.
Definition: GCNSchedStrategy.cpp:1368
llvm::GCNSchedStage::initGCNRegion
virtual bool initGCNRegion()
Definition: GCNSchedStrategy.cpp:744
llvm::GCNSchedStageID::ILPInitialSchedule
@ ILPInitialSchedule
llvm::GCNSchedStrategy::setTargetOccupancy
void setTargetOccupancy(unsigned Occ)
Definition: GCNSchedStrategy.h:99
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::GCNPostScheduleDAGMILive::GCNPostScheduleDAGMILive
GCNPostScheduleDAGMILive(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S, bool RemoveKillFlags)
Definition: GCNSchedStrategy.cpp:1352
llvm::GCNSchedStage::CurrentMBB
MachineBasicBlock * CurrentMBB
Definition: GCNSchedStrategy.h:223
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:269
llvm::UnclusteredHighRPStage::finalizeGCNSchedStage
void finalizeGCNSchedStage() override
Definition: GCNSchedStrategy.cpp:728
llvm::GenericScheduler::DAG
ScheduleDAGMILive * DAG
Definition: MachineScheduler.h:999
llvm::GCNScheduleDAGMILive::schedule
void schedule() override
Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.
Definition: GCNSchedStrategy.cpp:468
llvm::GCNSchedStrategy::SchedStages
SmallVector< GCNSchedStageID, 4 > SchedStages
Definition: GCNSchedStrategy.h:68
llvm::PreRARematStage::initGCNSchedStage
bool initGCNSchedStage() override
Definition: GCNSchedStrategy.cpp:694
llvm::OccInitialScheduleStage::shouldRevertScheduling
bool shouldRevertScheduling(unsigned WavesAfter) override
Definition: GCNSchedStrategy.cpp:935
llvm::GCNSchedStage::finalizeGCNRegion
void finalizeGCNRegion()
Definition: GCNSchedStrategy.cpp:843
llvm::GCNSchedStrategy::advanceStage
bool advanceStage()
Definition: GCNSchedStrategy.cpp:323
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::GCNSchedStrategy::HasHighPressure
bool HasHighPressure
Definition: GCNSchedStrategy.h:76
llvm::GCNSchedStrategy::DefaultErrorMargin
const unsigned DefaultErrorMargin
Definition: GCNSchedStrategy.h:81
llvm::GCNSchedStage::checkScheduling
void checkScheduling()
Definition: GCNSchedStrategy.cpp:861
llvm::GCNMaxOccupancySchedStrategy::GCNMaxOccupancySchedStrategy
GCNMaxOccupancySchedStrategy(const MachineSchedContext *C)
Definition: GCNSchedStrategy.cpp:343
llvm::GCNSchedStrategy::SGPRCriticalLimit
unsigned SGPRCriticalLimit
Definition: GCNSchedStrategy.h:87
llvm::ScheduleDAGInstrs::RemoveKillFlags
bool RemoveKillFlags
True if the DAG builder should remove kill flags (in preparation for rescheduling).
Definition: ScheduleDAGInstrs.h:130
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::GCNSchedStage::PressureAfter
GCNRegPressure PressureAfter
Definition: GCNSchedStrategy.h:235
llvm::GCNSchedStrategy::VGPRExcessLimit
unsigned VGPRExcessLimit
Definition: GCNSchedStrategy.h:61
llvm::GCNSchedStage::GCNSchedStage
GCNSchedStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
Definition: GCNSchedStrategy.cpp:637
GCNRegPressure.h
llvm::GCNSchedStage::SavedMutations
std::vector< std::unique_ptr< ScheduleDAGMutation > > SavedMutations
Definition: GCNSchedStrategy.h:237
llvm::ILPInitialScheduleStage::shouldRevertScheduling
bool shouldRevertScheduling(unsigned WavesAfter) override
Definition: GCNSchedStrategy.cpp:978
llvm::SchedBoundary
Each Scheduling boundary is associated with ready queues.
Definition: MachineScheduler.h:611
llvm::GCNSchedStrategy::hasNextStage
bool hasNextStage() const
Definition: GCNSchedStrategy.cpp:333
llvm::GCNSchedStrategy::pickNode
SUnit * pickNode(bool &IsTopNode) override
Pick the best node to balance the schedule. Implements MachineSchedStrategy.
Definition: GCNSchedStrategy.cpp:275
llvm::GCNSchedStageID::ClusteredLowOccupancyReschedule
@ ClusteredLowOccupancyReschedule
llvm::GCNSchedStrategy::pickNodeFromQueue
void pickNodeFromQueue(SchedBoundary &Zone, const CandPolicy &ZonePolicy, const RegPressureTracker &RPTracker, SchedCandidate &Cand)
Definition: GCNSchedStrategy.cpp:165
MachineScheduler.h
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:351
llvm::GCNSchedStage::ST
const GCNSubtarget & ST
Definition: GCNSchedStrategy.h:218
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::PreRARematStage
Definition: GCNSchedStrategy.h:317
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::GCNSchedStrategy::GCNSchedStrategy
GCNSchedStrategy(const MachineSchedContext *C)
Definition: GCNSchedStrategy.cpp:42
llvm::GCNSchedStrategy::Pressure
std::vector< unsigned > Pressure
Definition: GCNSchedStrategy.h:55
llvm::GCNSchedStrategy::VGPRCriticalLimit
unsigned VGPRCriticalLimit
Definition: GCNSchedStrategy.h:89
llvm::GCNSchedStrategy::getCurrentStage
GCNSchedStageID getCurrentStage()
Definition: GCNSchedStrategy.cpp:318
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:392
llvm::GenericScheduler
GenericScheduler shrinks the unscheduled zone using heuristics to balance the schedule.
Definition: MachineScheduler.h:954
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::GCNPostScheduleDAGMILive::schedule
void schedule() override
Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.
Definition: GCNSchedStrategy.cpp:1357
llvm::GCNSchedStage::PressureBefore
GCNRegPressure PressureBefore
Definition: GCNSchedStrategy.h:232
llvm::GCNPostScheduleDAGMILive
Definition: GCNSchedStrategy.h:361
llvm::GCNScheduleDAGMILive::GCNScheduleDAGMILive
GCNScheduleDAGMILive(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)
Definition: GCNSchedStrategy.cpp:441
llvm::GCNSchedStage::shouldRevertScheduling
virtual bool shouldRevertScheduling(unsigned WavesAfter)
Definition: GCNSchedStrategy.cpp:928