LLVM  16.0.0git
SIMachineFunctionInfo.h
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1 //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 
17 #include "AMDGPUMachineFunction.h"
18 #include "AMDGPUTargetMachine.h"
20 #include "SIInstrInfo.h"
21 #include "llvm/ADT/SetVector.h"
25 
26 namespace llvm {
27 
28 class MachineFrameInfo;
29 class MachineFunction;
30 class SIMachineFunctionInfo;
31 class SIRegisterInfo;
32 class TargetRegisterClass;
33 
35 public:
36  enum AMDGPUPSVKind : unsigned {
40  };
41 
42 protected:
44  : PseudoSourceValue(Kind, TM) {}
45 
46 public:
47  bool isConstant(const MachineFrameInfo *) const override {
48  // This should probably be true for most images, but we will start by being
49  // conservative.
50  return false;
51  }
52 
53  bool isAliased(const MachineFrameInfo *) const override {
54  return true;
55  }
56 
57  bool mayAlias(const MachineFrameInfo *) const override {
58  return true;
59  }
60 };
61 
63 public:
66 
67  static bool classof(const PseudoSourceValue *V) {
68  return V->kind() == PSVBuffer;
69  }
70 
71  void printCustom(raw_ostream &OS) const override { OS << "BufferResource"; }
72 };
73 
75 public:
76  // TODO: Is the img rsrc useful?
79 
80  static bool classof(const PseudoSourceValue *V) {
81  return V->kind() == PSVImage;
82  }
83 
84  void printCustom(raw_ostream &OS) const override { OS << "ImageResource"; }
85 };
86 
88 public:
91 
92  static bool classof(const PseudoSourceValue *V) {
93  return V->kind() == GWSResource;
94  }
95 
96  // These are inaccessible memory from IR.
97  bool isAliased(const MachineFrameInfo *) const override {
98  return false;
99  }
100 
101  // These are inaccessible memory from IR.
102  bool mayAlias(const MachineFrameInfo *) const override {
103  return false;
104  }
105 
106  void printCustom(raw_ostream &OS) const override {
107  OS << "GWSResource";
108  }
109 };
110 
111 namespace yaml {
112 
113 struct SIArgument {
115  union {
117  unsigned StackOffset;
118  };
120 
121  // Default constructor, which creates a stack argument.
123  SIArgument(const SIArgument &Other) {
124  IsRegister = Other.IsRegister;
125  if (IsRegister) {
126  ::new ((void *)std::addressof(RegisterName))
127  StringValue(Other.RegisterName);
128  } else
129  StackOffset = Other.StackOffset;
130  Mask = Other.Mask;
131  }
132  SIArgument &operator=(const SIArgument &Other) {
133  IsRegister = Other.IsRegister;
134  if (IsRegister) {
135  ::new ((void *)std::addressof(RegisterName))
136  StringValue(Other.RegisterName);
137  } else
138  StackOffset = Other.StackOffset;
139  Mask = Other.Mask;
140  return *this;
141  }
143  if (IsRegister)
144  RegisterName.~StringValue();
145  }
146 
147  // Helper to create a register or stack argument.
148  static inline SIArgument createArgument(bool IsReg) {
149  if (IsReg)
150  return SIArgument(IsReg);
151  return SIArgument();
152  }
153 
154 private:
155  // Construct a register argument.
156  SIArgument(bool) : IsRegister(true), RegisterName() {}
157 };
158 
159 template <> struct MappingTraits<SIArgument> {
160  static void mapping(IO &YamlIO, SIArgument &A) {
161  if (YamlIO.outputting()) {
162  if (A.IsRegister)
163  YamlIO.mapRequired("reg", A.RegisterName);
164  else
165  YamlIO.mapRequired("offset", A.StackOffset);
166  } else {
167  auto Keys = YamlIO.keys();
168  if (is_contained(Keys, "reg")) {
169  A = SIArgument::createArgument(true);
170  YamlIO.mapRequired("reg", A.RegisterName);
171  } else if (is_contained(Keys, "offset"))
172  YamlIO.mapRequired("offset", A.StackOffset);
173  else
174  YamlIO.setError("missing required key 'reg' or 'offset'");
175  }
176  YamlIO.mapOptional("mask", A.Mask);
177  }
178  static const bool flow = true;
179 };
180 
189 
196 
199 
203 };
204 
205 template <> struct MappingTraits<SIArgumentInfo> {
206  static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
207  YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
208  YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
209  YamlIO.mapOptional("queuePtr", AI.QueuePtr);
210  YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
211  YamlIO.mapOptional("dispatchID", AI.DispatchID);
212  YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
213  YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
214 
215  YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
216  YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
217  YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
218  YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
219  YamlIO.mapOptional("LDSKernelId", AI.LDSKernelId);
220  YamlIO.mapOptional("privateSegmentWaveByteOffset",
222 
223  YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
224  YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
225 
226  YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
227  YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
228  YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
229  }
230 };
231 
232 // Default to default mode for default calling convention.
233 struct SIMode {
234  bool IEEE = true;
235  bool DX10Clamp = true;
236  bool FP32InputDenormals = true;
237  bool FP32OutputDenormals = true;
240 
241  SIMode() = default;
242 
244  IEEE = Mode.IEEE;
245  DX10Clamp = Mode.DX10Clamp;
246  FP32InputDenormals = Mode.FP32InputDenormals;
247  FP32OutputDenormals = Mode.FP32OutputDenormals;
248  FP64FP16InputDenormals = Mode.FP64FP16InputDenormals;
249  FP64FP16OutputDenormals = Mode.FP64FP16OutputDenormals;
250  }
251 
252  bool operator ==(const SIMode Other) const {
253  return IEEE == Other.IEEE &&
254  DX10Clamp == Other.DX10Clamp &&
255  FP32InputDenormals == Other.FP32InputDenormals &&
256  FP32OutputDenormals == Other.FP32OutputDenormals &&
257  FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
258  FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
259  }
260 };
261 
262 template <> struct MappingTraits<SIMode> {
263  static void mapping(IO &YamlIO, SIMode &Mode) {
264  YamlIO.mapOptional("ieee", Mode.IEEE, true);
265  YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
266  YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
267  YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
268  YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
269  YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
270  }
271 };
272 
279  bool IsEntryFunction = false;
280  bool NoSignedZerosFPMath = false;
281  bool MemoryBound = false;
282  bool WaveLimiter = false;
283  bool HasSpilledSGPRs = false;
284  bool HasSpilledVGPRs = false;
286 
287  // TODO: 10 may be a better default since it's the maximum.
288  unsigned Occupancy = 0;
289 
291 
292  StringValue ScratchRSrcReg = "$private_rsrc_reg";
295 
296  unsigned BytesInStackArgArea = 0;
297  bool ReturnsVoid = true;
298 
303 
304  SIMachineFunctionInfo() = default;
306  const TargetRegisterInfo &TRI,
307  const llvm::MachineFunction &MF);
308 
309  void mappingImpl(yaml::IO &YamlIO) override;
310  ~SIMachineFunctionInfo() = default;
311 };
312 
314  static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
315  YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
316  UINT64_C(0));
317  YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign);
318  YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
319  YamlIO.mapOptional("gdsSize", MFI.GDSSize, 0u);
320  YamlIO.mapOptional("dynLDSAlign", MFI.DynLDSAlign, Align());
321  YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
322  YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
323  YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
324  YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
325  YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
326  YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false);
327  YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
328  StringValue("$private_rsrc_reg"));
329  YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
330  StringValue("$fp_reg"));
331  YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
332  StringValue("$sp_reg"));
333  YamlIO.mapOptional("bytesInStackArgArea", MFI.BytesInStackArgArea, 0u);
334  YamlIO.mapOptional("returnsVoid", MFI.ReturnsVoid, true);
335  YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
336  YamlIO.mapOptional("mode", MFI.Mode, SIMode());
337  YamlIO.mapOptional("highBitsOf32BitAddress",
338  MFI.HighBitsOf32BitAddress, 0u);
339  YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
340  YamlIO.mapOptional("wwmReservedRegs", MFI.WWMReservedRegs);
341  YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
342  YamlIO.mapOptional("vgprForAGPRCopy", MFI.VGPRForAGPRCopy,
343  StringValue()); // Don't print out when it's empty.
344  }
345 };
346 
347 } // end namespace yaml
348 
349 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
350 /// tells the hardware which interpolation parameters to load.
352  friend class GCNTargetMachine;
353 
354  // State of MODE register, assumed FP mode.
356 
357  // Registers that may be reserved for spilling purposes. These may be the same
358  // as the input registers.
359  Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
360 
361  // This is the unswizzled offset from the current dispatch's scratch wave
362  // base to the beginning of the current function's frame.
363  Register FrameOffsetReg = AMDGPU::FP_REG;
364 
365  // This is an ABI register used in the non-entry calling convention to
366  // communicate the unswizzled offset from the current dispatch's scratch wave
367  // base to the beginning of the new function's frame.
368  Register StackPtrOffsetReg = AMDGPU::SP_REG;
369 
371 
372  // Graphics info.
373  unsigned PSInputAddr = 0;
374  unsigned PSInputEnable = 0;
375 
376  /// Number of bytes of arguments this function has on the stack. If the callee
377  /// is expected to restore the argument stack this should be a multiple of 16,
378  /// all usable during a tail call.
379  ///
380  /// The alternative would forbid tail call optimisation in some cases: if we
381  /// want to transfer control from a function with 8-bytes of stack-argument
382  /// space to a function with 16-bytes then misalignment of this value would
383  /// make a stack adjustment necessary, which could not be undone by the
384  /// callee.
385  unsigned BytesInStackArgArea = 0;
386 
387  bool ReturnsVoid = true;
388 
389  // A pair of default/requested minimum/maximum flat work group sizes.
390  // Minimum - first, maximum - second.
391  std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
392 
393  // A pair of default/requested minimum/maximum number of waves per execution
394  // unit. Minimum - first, maximum - second.
395  std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
396 
397  const AMDGPUBufferPseudoSourceValue BufferPSV;
398  const AMDGPUImagePseudoSourceValue ImagePSV;
399  const AMDGPUGWSResourcePseudoSourceValue GWSResourcePSV;
400 
401 private:
402  unsigned NumUserSGPRs = 0;
403  unsigned NumSystemSGPRs = 0;
404 
405  bool HasSpilledSGPRs = false;
406  bool HasSpilledVGPRs = false;
407  bool HasNonSpillStackObjects = false;
408  bool IsStackRealigned = false;
409 
410  unsigned NumSpilledSGPRs = 0;
411  unsigned NumSpilledVGPRs = 0;
412 
413  // Feature bits required for inputs passed in user SGPRs.
414  bool PrivateSegmentBuffer : 1;
415  bool DispatchPtr : 1;
416  bool QueuePtr : 1;
417  bool KernargSegmentPtr : 1;
418  bool DispatchID : 1;
419  bool FlatScratchInit : 1;
420 
421  // Feature bits required for inputs passed in system SGPRs.
422  bool WorkGroupIDX : 1; // Always initialized.
423  bool WorkGroupIDY : 1;
424  bool WorkGroupIDZ : 1;
425  bool WorkGroupInfo : 1;
426  bool LDSKernelId : 1;
427  bool PrivateSegmentWaveByteOffset : 1;
428 
429  bool WorkItemIDX : 1; // Always initialized.
430  bool WorkItemIDY : 1;
431  bool WorkItemIDZ : 1;
432 
433  // Private memory buffer
434  // Compute directly in sgpr[0:1]
435  // Other shaders indirect 64-bits at sgpr[0:1]
436  bool ImplicitBufferPtr : 1;
437 
438  // Pointer to where the ABI inserts special kernel arguments separate from the
439  // user arguments. This is an offset from the KernargSegmentPtr.
440  bool ImplicitArgPtr : 1;
441 
442  bool MayNeedAGPRs : 1;
443 
444  // The hard-wired high half of the address of the global information table
445  // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
446  // current hardware only allows a 16 bit value.
447  unsigned GITPtrHigh;
448 
449  unsigned HighBitsOf32BitAddress;
450 
451  // Current recorded maximum possible occupancy.
452  unsigned Occupancy;
453 
454  mutable Optional<bool> UsesAGPRs;
455 
456  MCPhysReg getNextUserSGPR() const;
457 
458  MCPhysReg getNextSystemSGPR() const;
459 
460 public:
461  struct SGPRSpillVGPR {
462  // VGPR used for SGPR spills
464 
465  // If the VGPR is used for SGPR spills in a non-entrypoint function, the
466  // stack slot used to save/restore it in the prolog/epilog.
468 
470  };
471 
474  bool FullyAllocated = false;
475  bool IsDead = false;
476  };
477 
478  // Track VGPRs reserved for WWM.
480 
481  /// Track stack slots used for save/restore of reserved WWM VGPRs in the
482  /// prolog/epilog.
483 
484  /// FIXME: This is temporary state only needed in PrologEpilogInserter, and
485  /// doesn't really belong here. It does not require serialization
487 
489  const SIRegisterInfo &TRI);
490 
491  auto wwmAllocation() const {
494  }
495 
496 private:
497  // Track VGPR + wave index for each subregister of the SGPR spilled to
498  // frameindex key.
500  unsigned NumVGPRSpillLanes = 0;
502 
503  DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
504 
505  // AGPRs used for VGPR spills.
506  SmallVector<MCPhysReg, 32> SpillAGPR;
507 
508  // VGPRs used for AGPR spills.
509  SmallVector<MCPhysReg, 32> SpillVGPR;
510 
511  // Emergency stack slot. Sometimes, we create this before finalizing the stack
512  // frame, so save it here and add it to the RegScavenger later.
513  Optional<int> ScavengeFI;
514 
515 private:
516  Register VGPRForAGPRCopy;
517 
518 public:
520  return VGPRForAGPRCopy;
521  }
522 
523  void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy) {
524  VGPRForAGPRCopy = NewVGPRForAGPRCopy;
525  }
526 
527 public: // FIXME
528  /// If this is set, an SGPR used for save/restore of the register used for the
529  /// frame pointer.
532 
533  /// If this is set, an SGPR used for save/restore of the register used for the
534  /// base pointer.
537 
538  bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg);
539 
540 public:
542  SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI) = default;
543 
547  const override;
548 
550  const MachineFunction &MF,
552  SMDiagnostic &Error, SMRange &SourceRange);
553 
555  WWMReservedRegs.insert(Reg);
556  }
557 
559  return Mode;
560  }
561 
564  auto I = SGPRToVGPRSpills.find(FrameIndex);
565  return (I == SGPRToVGPRSpills.end())
567  : makeArrayRef(I->second);
568  }
569 
570  ArrayRef<SGPRSpillVGPR> getSGPRSpillVGPRs() const { return SpillVGPRs; }
571 
573  return SpillAGPR;
574  }
575 
577  return SpillVGPR;
578  }
579 
580  MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
581  auto I = VGPRToAGPRSpills.find(FrameIndex);
582  return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
583  : I->second.Lanes[Lane];
584  }
585 
587  auto I = VGPRToAGPRSpills.find(FrameIndex);
588  if (I != VGPRToAGPRSpills.end())
589  I->second.IsDead = true;
590  }
591 
593  unsigned NumLane) const;
594  bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
595  bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
596 
597  /// If \p ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill
598  /// to the default stack.
600  bool ResetSGPRSpillStackIDs);
601 
603  Optional<int> getOptionalScavengeFI() const { return ScavengeFI; }
604 
605  unsigned getBytesInStackArgArea() const {
606  return BytesInStackArgArea;
607  }
608 
609  void setBytesInStackArgArea(unsigned Bytes) {
610  BytesInStackArgArea = Bytes;
611  }
612 
613  // Add user SGPRs.
622 
623  /// Increment user SGPRs used for padding the argument list only.
625  Register Next = getNextUserSGPR();
626  ++NumUserSGPRs;
627  return Next;
628  }
629 
630  // Add system SGPRs.
632  ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
633  NumSystemSGPRs += 1;
634  return ArgInfo.WorkGroupIDX.getRegister();
635  }
636 
638  ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
639  NumSystemSGPRs += 1;
640  return ArgInfo.WorkGroupIDY.getRegister();
641  }
642 
644  ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
645  NumSystemSGPRs += 1;
646  return ArgInfo.WorkGroupIDZ.getRegister();
647  }
648 
650  ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
651  NumSystemSGPRs += 1;
652  return ArgInfo.WorkGroupInfo.getRegister();
653  }
654 
655  // Add special VGPR inputs
657  ArgInfo.WorkItemIDX = Arg;
658  }
659 
661  ArgInfo.WorkItemIDY = Arg;
662  }
663 
665  ArgInfo.WorkItemIDZ = Arg;
666  }
667 
669  ArgInfo.PrivateSegmentWaveByteOffset
670  = ArgDescriptor::createRegister(getNextSystemSGPR());
671  NumSystemSGPRs += 1;
672  return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
673  }
674 
676  ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
677  }
678 
679  bool hasPrivateSegmentBuffer() const {
680  return PrivateSegmentBuffer;
681  }
682 
683  bool hasDispatchPtr() const {
684  return DispatchPtr;
685  }
686 
687  bool hasQueuePtr() const {
688  return QueuePtr;
689  }
690 
691  bool hasKernargSegmentPtr() const {
692  return KernargSegmentPtr;
693  }
694 
695  bool hasDispatchID() const {
696  return DispatchID;
697  }
698 
699  bool hasFlatScratchInit() const {
700  return FlatScratchInit;
701  }
702 
703  bool hasWorkGroupIDX() const {
704  return WorkGroupIDX;
705  }
706 
707  bool hasWorkGroupIDY() const {
708  return WorkGroupIDY;
709  }
710 
711  bool hasWorkGroupIDZ() const {
712  return WorkGroupIDZ;
713  }
714 
715  bool hasWorkGroupInfo() const {
716  return WorkGroupInfo;
717  }
718 
719  bool hasLDSKernelId() const { return LDSKernelId; }
720 
722  return PrivateSegmentWaveByteOffset;
723  }
724 
725  bool hasWorkItemIDX() const {
726  return WorkItemIDX;
727  }
728 
729  bool hasWorkItemIDY() const {
730  return WorkItemIDY;
731  }
732 
733  bool hasWorkItemIDZ() const {
734  return WorkItemIDZ;
735  }
736 
737  bool hasImplicitArgPtr() const {
738  return ImplicitArgPtr;
739  }
740 
741  bool hasImplicitBufferPtr() const {
742  return ImplicitBufferPtr;
743  }
744 
746  return ArgInfo;
747  }
748 
750  return ArgInfo;
751  }
752 
753  std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
755  return ArgInfo.getPreloadedValue(Value);
756  }
757 
759  auto Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));
760  return Arg ? Arg->getRegister() : MCRegister();
761  }
762 
763  unsigned getGITPtrHigh() const {
764  return GITPtrHigh;
765  }
766 
767  Register getGITPtrLoReg(const MachineFunction &MF) const;
768 
770  return HighBitsOf32BitAddress;
771  }
772 
773  unsigned getNumUserSGPRs() const {
774  return NumUserSGPRs;
775  }
776 
777  unsigned getNumPreloadedSGPRs() const {
778  return NumUserSGPRs + NumSystemSGPRs;
779  }
780 
782  return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
783  }
784 
785  /// Returns the physical register reserved for use as the resource
786  /// descriptor for scratch accesses.
788  return ScratchRSrcReg;
789  }
790 
792  assert(Reg != 0 && "Should never be unset");
793  ScratchRSrcReg = Reg;
794  }
795 
797  return FrameOffsetReg;
798  }
799 
801  assert(Reg != 0 && "Should never be unset");
802  FrameOffsetReg = Reg;
803  }
804 
806  assert(Reg != 0 && "Should never be unset");
807  StackPtrOffsetReg = Reg;
808  }
809 
810  // Note the unset value for this is AMDGPU::SP_REG rather than
811  // NoRegister. This is mostly a workaround for MIR tests where state that
812  // can't be directly computed from the function is not preserved in serialized
813  // MIR.
815  return StackPtrOffsetReg;
816  }
817 
819  return ArgInfo.QueuePtr.getRegister();
820  }
821 
823  return ArgInfo.ImplicitBufferPtr.getRegister();
824  }
825 
826  bool hasSpilledSGPRs() const {
827  return HasSpilledSGPRs;
828  }
829 
830  void setHasSpilledSGPRs(bool Spill = true) {
831  HasSpilledSGPRs = Spill;
832  }
833 
834  bool hasSpilledVGPRs() const {
835  return HasSpilledVGPRs;
836  }
837 
838  void setHasSpilledVGPRs(bool Spill = true) {
839  HasSpilledVGPRs = Spill;
840  }
841 
842  bool hasNonSpillStackObjects() const {
843  return HasNonSpillStackObjects;
844  }
845 
846  void setHasNonSpillStackObjects(bool StackObject = true) {
847  HasNonSpillStackObjects = StackObject;
848  }
849 
850  bool isStackRealigned() const {
851  return IsStackRealigned;
852  }
853 
854  void setIsStackRealigned(bool Realigned = true) {
855  IsStackRealigned = Realigned;
856  }
857 
858  unsigned getNumSpilledSGPRs() const {
859  return NumSpilledSGPRs;
860  }
861 
862  unsigned getNumSpilledVGPRs() const {
863  return NumSpilledVGPRs;
864  }
865 
866  void addToSpilledSGPRs(unsigned num) {
867  NumSpilledSGPRs += num;
868  }
869 
870  void addToSpilledVGPRs(unsigned num) {
871  NumSpilledVGPRs += num;
872  }
873 
874  unsigned getPSInputAddr() const {
875  return PSInputAddr;
876  }
877 
878  unsigned getPSInputEnable() const {
879  return PSInputEnable;
880  }
881 
882  bool isPSInputAllocated(unsigned Index) const {
883  return PSInputAddr & (1 << Index);
884  }
885 
886  void markPSInputAllocated(unsigned Index) {
887  PSInputAddr |= 1 << Index;
888  }
889 
890  void markPSInputEnabled(unsigned Index) {
891  PSInputEnable |= 1 << Index;
892  }
893 
894  bool returnsVoid() const {
895  return ReturnsVoid;
896  }
897 
898  void setIfReturnsVoid(bool Value) {
899  ReturnsVoid = Value;
900  }
901 
902  /// \returns A pair of default/requested minimum/maximum flat work group sizes
903  /// for this function.
904  std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
905  return FlatWorkGroupSizes;
906  }
907 
908  /// \returns Default/requested minimum flat work group size for this function.
909  unsigned getMinFlatWorkGroupSize() const {
910  return FlatWorkGroupSizes.first;
911  }
912 
913  /// \returns Default/requested maximum flat work group size for this function.
914  unsigned getMaxFlatWorkGroupSize() const {
915  return FlatWorkGroupSizes.second;
916  }
917 
918  /// \returns A pair of default/requested minimum/maximum number of waves per
919  /// execution unit.
920  std::pair<unsigned, unsigned> getWavesPerEU() const {
921  return WavesPerEU;
922  }
923 
924  /// \returns Default/requested minimum number of waves per execution unit.
925  unsigned getMinWavesPerEU() const {
926  return WavesPerEU.first;
927  }
928 
929  /// \returns Default/requested maximum number of waves per execution unit.
930  unsigned getMaxWavesPerEU() const {
931  return WavesPerEU.second;
932  }
933 
934  /// \returns SGPR used for \p Dim's work group ID.
935  Register getWorkGroupIDSGPR(unsigned Dim) const {
936  switch (Dim) {
937  case 0:
939  return ArgInfo.WorkGroupIDX.getRegister();
940  case 1:
942  return ArgInfo.WorkGroupIDY.getRegister();
943  case 2:
945  return ArgInfo.WorkGroupIDZ.getRegister();
946  }
947  llvm_unreachable("unexpected dimension");
948  }
949 
952  return &BufferPSV;
953  }
954 
957  return &ImagePSV;
958  }
959 
962  return &GWSResourcePSV;
963  }
964 
965  unsigned getOccupancy() const {
966  return Occupancy;
967  }
968 
969  unsigned getMinAllowedOccupancy() const {
970  if (!isMemoryBound() && !needsWaveLimiter())
971  return Occupancy;
972  return (Occupancy < 4) ? Occupancy : 4;
973  }
974 
975  void limitOccupancy(const MachineFunction &MF);
976 
977  void limitOccupancy(unsigned Limit) {
978  if (Occupancy > Limit)
979  Occupancy = Limit;
980  }
981 
982  void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
983  if (Occupancy < Limit)
984  Occupancy = Limit;
985  limitOccupancy(MF);
986  }
987 
988  bool mayNeedAGPRs() const {
989  return MayNeedAGPRs;
990  }
991 
992  // \returns true if a function has a use of AGPRs via inline asm or
993  // has a call which may use it.
994  bool mayUseAGPRs(const Function &F) const;
995 
996  // \returns true if a function needs or may need AGPRs.
997  bool usesAGPRs(const MachineFunction &MF) const;
998 };
999 
1000 } // end namespace llvm
1001 
1002 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
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Definition: Allocator.h:63
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Definition: SIMachineFunctionInfo.h:479
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Definition: SIMachineFunctionInfo.h:925
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Definition: DenseMap.h:150
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Definition: AMDGPUMachineFunction.h:90
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Definition: MIRYamlMapping.h:34
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Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
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Returns the physical register reserved for use as the resource descriptor for scratch accesses.
Definition: SIMachineFunctionInfo.h:787
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Definition: Register.h:19
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Definition: SIMachineFunctionInfo.h:721
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Definition: ISDOpcodes.h:80
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If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
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Definition: MIParser.h:162
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Definition: DenseMap.h:84
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Definition: Error.h:155
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Definition: SIMachineFunctionInfo.h:675
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Definition: AMDGPUArgumentUsageInfo.h:44
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Definition: SIMachineFunctionInfo.h:920
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Definition: SIMachineFunctionInfo.h:572
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Definition: SIMachineFunctionInfo.h:791
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Definition: SIMachineFunctionInfo.h:277
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Definition: SIMachineFunctionInfo.h:800
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Definition: SIMachineFunctionInfo.h:182
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Definition: SIMachineFunctionInfo.h:605
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Definition: SIMachineFunctionInfo.cpp:667
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Definition: SIMachineFunctionInfo.h:37
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Definition: ArrayRef.h:475
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Definition: SIMachineFunctionInfo.h:846
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Definition: SIMachineFunctionInfo.h:206
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Definition: MachineFrameInfo.h:106
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Definition: RegAllocBasic.cpp:143
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Represents a range in source code.
Definition: SMLoc.h:48
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const AMDGPUBufferPseudoSourceValue * getBufferPSV(const AMDGPUTargetMachine &TM)
Definition: SIMachineFunctionInfo.h:951
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Definition: SIMachineFunctionInfo.h:351
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Definition: SIMachineFunctionInfo.h:687
llvm::SIMachineFunctionInfo::hasWorkGroupIDY
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Definition: SIMachineFunctionInfo.h:707
llvm::SIMachineFunctionInfo::addWorkGroupIDX
Register addWorkGroupIDX()
Definition: SIMachineFunctionInfo.h:631
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Align DynLDSAlign
Definition: SIMachineFunctionInfo.h:278
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Definition: SIMachineFunctionInfo.h:691
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Definition: SIMachineFunctionInfo.h:874
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Definition: SIMachineFunctionInfo.h:882
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Definition: SIMachineFunctionInfo.h:649
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Definition: SIMachineFunctionInfo.h:234
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Implement printing for PseudoSourceValue.
Definition: SIMachineFunctionInfo.h:71
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Definition: SetVector.h:307
TM
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Definition: PassBuilderBindings.cpp:47
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Definition: SIMachineFunctionInfo.h:830
llvm::SIMachineFunctionInfo::addToSpilledVGPRs
void addToSpilledVGPRs(unsigned num)
Definition: SIMachineFunctionInfo.h:870
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constexpr char NumSpilledSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSpilledSGPRs.
Definition: AMDGPUMetadata.h:268
llvm::yaml::SIMachineFunctionInfo::~SIMachineFunctionInfo
~SIMachineFunctionInfo()=default
raw_ostream.h
llvm::AMDGPUPseudoSourceValue::isConstant
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Test whether the memory pointed to by this PseudoSourceValue has a constant value.
Definition: SIMachineFunctionInfo.h:47
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Definition: SIMachineFunctionInfo.h:117
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Definition: SIMachineFunctionInfo.h:461
AMDGPUArgumentUsageInfo.h
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Definition: AMDGPUMachineFunction.h:23
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Definition: MachineFunction.h:95
llvm::yaml::SIMachineFunctionInfo::MaxKernArgAlign
Align MaxKernArgAlign
Definition: SIMachineFunctionInfo.h:275
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Definition: SIMachineFunctionInfo.h:725
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Definition: SIMachineFunctionInfo.h:239
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Definition: SIMachineFunctionInfo.h:119
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LLVM Value Representation.
Definition: Value.h:74
llvm::SIMachineFunctionInfo::hasImplicitBufferPtr
bool hasImplicitBufferPtr() const
Definition: SIMachineFunctionInfo.h:741
llvm::SIMachineFunctionInfo::hasFlatScratchInit
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Definition: SIMachineFunctionInfo.h:699
llvm::yaml::SIArgumentInfo::FlatScratchInit
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Definition: SIMachineFunctionInfo.h:187
llvm::SIMachineFunctionInfo::getQueuePtrUserSGPR
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Definition: SIMachineFunctionInfo.h:818
AMDGPUTargetMachine.h
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Definition: SIMachineFunctionInfo.h:796
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llvm::SIMachineFunctionInfo::allocateWWMReservedSpillSlots
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Definition: SIMachineFunctionInfo.cpp:474
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1251
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Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::yaml::SIArgumentInfo::QueuePtr
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Definition: SIMachineFunctionInfo.h:184