LLVM 18.0.0git
SIMachineFunctionInfo.h
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1//==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15
18#include "AMDGPUTargetMachine.h"
19#include "GCNSubtarget.h"
21#include "SIInstrInfo.h"
23#include "llvm/ADT/SetVector.h"
28#include <optional>
29
30namespace llvm {
31
32class MachineFrameInfo;
33class MachineFunction;
34class SIMachineFunctionInfo;
35class SIRegisterInfo;
36class TargetRegisterClass;
37
39public:
40 enum AMDGPUPSVKind : unsigned {
43 };
44
45protected:
47 : PseudoSourceValue(Kind, TM) {}
48
49public:
50 bool isConstant(const MachineFrameInfo *) const override {
51 // This should probably be true for most images, but we will start by being
52 // conservative.
53 return false;
54 }
55
56 bool isAliased(const MachineFrameInfo *) const override {
57 return true;
58 }
59
60 bool mayAlias(const MachineFrameInfo *) const override {
61 return true;
62 }
63};
64
66public:
69
70 static bool classof(const PseudoSourceValue *V) {
71 return V->kind() == GWSResource;
72 }
73
74 // These are inaccessible memory from IR.
75 bool isAliased(const MachineFrameInfo *) const override {
76 return false;
77 }
78
79 // These are inaccessible memory from IR.
80 bool mayAlias(const MachineFrameInfo *) const override {
81 return false;
82 }
83
84 void printCustom(raw_ostream &OS) const override {
85 OS << "GWSResource";
86 }
87};
88
89namespace yaml {
90
91struct SIArgument {
93 union {
95 unsigned StackOffset;
96 };
97 std::optional<unsigned> Mask;
98
99 // Default constructor, which creates a stack argument.
102 IsRegister = Other.IsRegister;
103 if (IsRegister) {
104 ::new ((void *)std::addressof(RegisterName))
105 StringValue(Other.RegisterName);
106 } else
107 StackOffset = Other.StackOffset;
108 Mask = Other.Mask;
109 }
111 IsRegister = Other.IsRegister;
112 if (IsRegister) {
113 ::new ((void *)std::addressof(RegisterName))
114 StringValue(Other.RegisterName);
115 } else
116 StackOffset = Other.StackOffset;
117 Mask = Other.Mask;
118 return *this;
119 }
121 if (IsRegister)
122 RegisterName.~StringValue();
123 }
124
125 // Helper to create a register or stack argument.
126 static inline SIArgument createArgument(bool IsReg) {
127 if (IsReg)
128 return SIArgument(IsReg);
129 return SIArgument();
130 }
131
132private:
133 // Construct a register argument.
135};
136
137template <> struct MappingTraits<SIArgument> {
138 static void mapping(IO &YamlIO, SIArgument &A) {
139 if (YamlIO.outputting()) {
140 if (A.IsRegister)
141 YamlIO.mapRequired("reg", A.RegisterName);
142 else
143 YamlIO.mapRequired("offset", A.StackOffset);
144 } else {
145 auto Keys = YamlIO.keys();
146 if (is_contained(Keys, "reg")) {
148 YamlIO.mapRequired("reg", A.RegisterName);
149 } else if (is_contained(Keys, "offset"))
150 YamlIO.mapRequired("offset", A.StackOffset);
151 else
152 YamlIO.setError("missing required key 'reg' or 'offset'");
153 }
154 YamlIO.mapOptional("mask", A.Mask);
155 }
156 static const bool flow = true;
157};
158
160 std::optional<SIArgument> PrivateSegmentBuffer;
161 std::optional<SIArgument> DispatchPtr;
162 std::optional<SIArgument> QueuePtr;
163 std::optional<SIArgument> KernargSegmentPtr;
164 std::optional<SIArgument> DispatchID;
165 std::optional<SIArgument> FlatScratchInit;
166 std::optional<SIArgument> PrivateSegmentSize;
167
168 std::optional<SIArgument> WorkGroupIDX;
169 std::optional<SIArgument> WorkGroupIDY;
170 std::optional<SIArgument> WorkGroupIDZ;
171 std::optional<SIArgument> WorkGroupInfo;
172 std::optional<SIArgument> LDSKernelId;
173 std::optional<SIArgument> PrivateSegmentWaveByteOffset;
174
175 std::optional<SIArgument> ImplicitArgPtr;
176 std::optional<SIArgument> ImplicitBufferPtr;
177
178 std::optional<SIArgument> WorkItemIDX;
179 std::optional<SIArgument> WorkItemIDY;
180 std::optional<SIArgument> WorkItemIDZ;
181};
182
183template <> struct MappingTraits<SIArgumentInfo> {
184 static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
185 YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
186 YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
187 YamlIO.mapOptional("queuePtr", AI.QueuePtr);
188 YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
189 YamlIO.mapOptional("dispatchID", AI.DispatchID);
190 YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
191 YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
192
193 YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
194 YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
195 YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
196 YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
197 YamlIO.mapOptional("LDSKernelId", AI.LDSKernelId);
198 YamlIO.mapOptional("privateSegmentWaveByteOffset",
200
201 YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
202 YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
203
204 YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
205 YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
206 YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
207 }
208};
209
210// Default to default mode for default calling convention.
211struct SIMode {
212 bool IEEE = true;
213 bool DX10Clamp = true;
218
219 SIMode() = default;
220
222 IEEE = Mode.IEEE;
223 DX10Clamp = Mode.DX10Clamp;
224 FP32InputDenormals = Mode.FP32Denormals.Input != DenormalMode::PreserveSign;
226 Mode.FP32Denormals.Output != DenormalMode::PreserveSign;
228 Mode.FP64FP16Denormals.Input != DenormalMode::PreserveSign;
230 Mode.FP64FP16Denormals.Output != DenormalMode::PreserveSign;
231 }
232
233 bool operator ==(const SIMode Other) const {
234 return IEEE == Other.IEEE &&
235 DX10Clamp == Other.DX10Clamp &&
236 FP32InputDenormals == Other.FP32InputDenormals &&
237 FP32OutputDenormals == Other.FP32OutputDenormals &&
238 FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
239 FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
240 }
241};
242
243template <> struct MappingTraits<SIMode> {
244 static void mapping(IO &YamlIO, SIMode &Mode) {
245 YamlIO.mapOptional("ieee", Mode.IEEE, true);
246 YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
247 YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
248 YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
249 YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
250 YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
251 }
252};
253
260 bool IsEntryFunction = false;
261 bool IsChainFunction = false;
263 bool MemoryBound = false;
264 bool WaveLimiter = false;
265 bool HasSpilledSGPRs = false;
266 bool HasSpilledVGPRs = false;
268
269 // TODO: 10 may be a better default since it's the maximum.
270 unsigned Occupancy = 0;
271
273
274 StringValue ScratchRSrcReg = "$private_rsrc_reg";
277
279 bool ReturnsVoid = true;
280
281 std::optional<SIArgumentInfo> ArgInfo;
282
283 unsigned PSInputAddr = 0;
284 unsigned PSInputEnable = 0;
285
287 std::optional<FrameIndex> ScavengeFI;
291
294 const TargetRegisterInfo &TRI,
295 const llvm::MachineFunction &MF);
296
297 void mappingImpl(yaml::IO &YamlIO) override;
299};
300
302 static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
303 YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
304 UINT64_C(0));
305 YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign);
306 YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
307 YamlIO.mapOptional("gdsSize", MFI.GDSSize, 0u);
308 YamlIO.mapOptional("dynLDSAlign", MFI.DynLDSAlign, Align());
309 YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
310 YamlIO.mapOptional("isChainFunction", MFI.IsChainFunction, false);
311 YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
312 YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
313 YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
314 YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
315 YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false);
316 YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
317 StringValue("$private_rsrc_reg"));
318 YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
319 StringValue("$fp_reg"));
320 YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
321 StringValue("$sp_reg"));
322 YamlIO.mapOptional("bytesInStackArgArea", MFI.BytesInStackArgArea, 0u);
323 YamlIO.mapOptional("returnsVoid", MFI.ReturnsVoid, true);
324 YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
325 YamlIO.mapOptional("psInputAddr", MFI.PSInputAddr, 0u);
326 YamlIO.mapOptional("psInputEnable", MFI.PSInputEnable, 0u);
327 YamlIO.mapOptional("mode", MFI.Mode, SIMode());
328 YamlIO.mapOptional("highBitsOf32BitAddress",
329 MFI.HighBitsOf32BitAddress, 0u);
330 YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
331 YamlIO.mapOptional("wwmReservedRegs", MFI.WWMReservedRegs);
332 YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
333 YamlIO.mapOptional("vgprForAGPRCopy", MFI.VGPRForAGPRCopy,
334 StringValue()); // Don't print out when it's empty.
335 YamlIO.mapOptional("sgprForEXECCopy", MFI.SGPRForEXECCopy,
336 StringValue()); // Don't print out when it's empty.
337 YamlIO.mapOptional("longBranchReservedReg", MFI.LongBranchReservedReg,
338 StringValue());
339 }
340};
341
342} // end namespace yaml
343
344// A CSR SGPR value can be preserved inside a callee using one of the following
345// methods.
346// 1. Copy to an unused scratch SGPR.
347// 2. Spill to a VGPR lane.
348// 3. Spill to memory via. a scratch VGPR.
349// class PrologEpilogSGPRSaveRestoreInfo represents the save/restore method used
350// for an SGPR at function prolog/epilog.
351enum class SGPRSaveKind : uint8_t {
355};
356
358 SGPRSaveKind Kind;
359 union {
360 int Index;
362 };
363
364public:
367 : Kind(K), Reg(R) {}
368 Register getReg() const { return Reg; }
369 int getIndex() const { return Index; }
370 SGPRSaveKind getKind() const { return Kind; }
371};
372
373/// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
374/// tells the hardware which interpolation parameters to load.
377 friend class GCNTargetMachine;
378
379 // State of MODE register, assumed FP mode.
381
382 // Registers that may be reserved for spilling purposes. These may be the same
383 // as the input registers.
384 Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
385
386 // This is the unswizzled offset from the current dispatch's scratch wave
387 // base to the beginning of the current function's frame.
388 Register FrameOffsetReg = AMDGPU::FP_REG;
389
390 // This is an ABI register used in the non-entry calling convention to
391 // communicate the unswizzled offset from the current dispatch's scratch wave
392 // base to the beginning of the new function's frame.
393 Register StackPtrOffsetReg = AMDGPU::SP_REG;
394
395 // Registers that may be reserved when RA doesn't allocate enough
396 // registers to plan for the case where an indirect branch ends up
397 // being needed during branch relaxation.
398 Register LongBranchReservedReg;
399
401
402 // Graphics info.
403 unsigned PSInputAddr = 0;
404 unsigned PSInputEnable = 0;
405
406 /// Number of bytes of arguments this function has on the stack. If the callee
407 /// is expected to restore the argument stack this should be a multiple of 16,
408 /// all usable during a tail call.
409 ///
410 /// The alternative would forbid tail call optimisation in some cases: if we
411 /// want to transfer control from a function with 8-bytes of stack-argument
412 /// space to a function with 16-bytes then misalignment of this value would
413 /// make a stack adjustment necessary, which could not be undone by the
414 /// callee.
415 unsigned BytesInStackArgArea = 0;
416
417 bool ReturnsVoid = true;
418
419 // A pair of default/requested minimum/maximum flat work group sizes.
420 // Minimum - first, maximum - second.
421 std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
422
423 // A pair of default/requested minimum/maximum number of waves per execution
424 // unit. Minimum - first, maximum - second.
425 std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
426
427 const AMDGPUGWSResourcePseudoSourceValue GWSResourcePSV;
428
429private:
430 unsigned NumUserSGPRs = 0;
431 unsigned NumSystemSGPRs = 0;
432
433 bool HasSpilledSGPRs = false;
434 bool HasSpilledVGPRs = false;
435 bool HasNonSpillStackObjects = false;
436 bool IsStackRealigned = false;
437
438 unsigned NumSpilledSGPRs = 0;
439 unsigned NumSpilledVGPRs = 0;
440
441 // Tracks information about user SGPRs that will be setup by hardware which
442 // will apply to all wavefronts of the grid.
443 GCNUserSGPRUsageInfo UserSGPRInfo;
444
445 // Feature bits required for inputs passed in system SGPRs.
446 bool WorkGroupIDX : 1; // Always initialized.
447 bool WorkGroupIDY : 1;
448 bool WorkGroupIDZ : 1;
449 bool WorkGroupInfo : 1;
450 bool LDSKernelId : 1;
451 bool PrivateSegmentWaveByteOffset : 1;
452
453 bool WorkItemIDX : 1; // Always initialized.
454 bool WorkItemIDY : 1;
455 bool WorkItemIDZ : 1;
456
457 // Pointer to where the ABI inserts special kernel arguments separate from the
458 // user arguments. This is an offset from the KernargSegmentPtr.
459 bool ImplicitArgPtr : 1;
460
461 bool MayNeedAGPRs : 1;
462
463 // The hard-wired high half of the address of the global information table
464 // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
465 // current hardware only allows a 16 bit value.
466 unsigned GITPtrHigh;
467
468 unsigned HighBitsOf32BitAddress;
469
470 // Flags associated with the virtual registers.
471 IndexedMap<uint8_t, VirtReg2IndexFunctor> VRegFlags;
472
473 // Current recorded maximum possible occupancy.
474 unsigned Occupancy;
475
476 mutable std::optional<bool> UsesAGPRs;
477
478 MCPhysReg getNextUserSGPR() const;
479
480 MCPhysReg getNextSystemSGPR() const;
481
482 // MachineRegisterInfo callback functions to notify events.
483 void MRI_NoteNewVirtualRegister(Register Reg) override;
484 void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg) override;
485
486public:
489 bool FullyAllocated = false;
490 bool IsDead = false;
491 };
492
493private:
494 // To track virtual VGPR + lane index for each subregister of the SGPR spilled
495 // to frameindex key during SILowerSGPRSpills pass.
497 SGPRSpillsToVirtualVGPRLanes;
498 // To track physical VGPR + lane index for CSR SGPR spills and special SGPRs
499 // like Frame Pointer identified during PrologEpilogInserter.
501 SGPRSpillsToPhysicalVGPRLanes;
502 unsigned NumVirtualVGPRSpillLanes = 0;
503 unsigned NumPhysicalVGPRSpillLanes = 0;
504 SmallVector<Register, 2> SpillVGPRs;
506 // To track the registers used in instructions that can potentially modify the
507 // inactive lanes. The WWM instructions and the writelane instructions for
508 // spilling SGPRs to VGPRs fall under such category of operations. The VGPRs
509 // modified by them should be spilled/restored at function prolog/epilog to
510 // avoid any undesired outcome. Each entry in this map holds a pair of values,
511 // the VGPR and its stack slot index.
512 WWMSpillsMap WWMSpills;
513
515 // To track the VGPRs reserved for WWM instructions. They get stack slots
516 // later during PrologEpilogInserter and get added into the superset WWMSpills
517 // for actual spilling. A separate set makes the register reserved part and
518 // the serialization easier.
519 ReservedRegSet WWMReservedRegs;
520
523 // To track the SGPR spill method used for a CSR SGPR register during
524 // frame lowering. Even though the SGPR spills are handled during
525 // SILowerSGPRSpills pass, some special handling needed later during the
526 // PrologEpilogInserter.
527 PrologEpilogSGPRSpillsMap PrologEpilogSGPRSpills;
528
529 // To save/restore EXEC MASK around WWM spills and copies.
530 Register SGPRForEXECCopy;
531
532 DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
533
534 // AGPRs used for VGPR spills.
536
537 // VGPRs used for AGPR spills.
539
540 // Emergency stack slot. Sometimes, we create this before finalizing the stack
541 // frame, so save it here and add it to the RegScavenger later.
542 std::optional<int> ScavengeFI;
543
544private:
545 Register VGPRForAGPRCopy;
546
547 bool allocateVirtualVGPRForSGPRSpills(MachineFunction &MF, int FI,
548 unsigned LaneIndex);
549 bool allocatePhysicalVGPRForSGPRSpills(MachineFunction &MF, int FI,
550 unsigned LaneIndex);
551
552public:
554 return VGPRForAGPRCopy;
555 }
556
557 void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy) {
558 VGPRForAGPRCopy = NewVGPRForAGPRCopy;
559 }
560
561 bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const;
562
563public:
565 SIMachineFunctionInfo(const Function &F, const GCNSubtarget *STI);
566
570 const override;
571
573 const MachineFunction &MF,
575 SMDiagnostic &Error, SMRange &SourceRange);
576
577 void reserveWWMRegister(Register Reg) { WWMReservedRegs.insert(Reg); }
578
579 SIModeRegisterDefaults getMode() const { return Mode; }
580
582 getSGPRSpillToVirtualVGPRLanes(int FrameIndex) const {
583 auto I = SGPRSpillsToVirtualVGPRLanes.find(FrameIndex);
584 return (I == SGPRSpillsToVirtualVGPRLanes.end())
586 : ArrayRef(I->second);
587 }
588
589 ArrayRef<Register> getSGPRSpillVGPRs() const { return SpillVGPRs; }
590 const WWMSpillsMap &getWWMSpills() const { return WWMSpills; }
591 const ReservedRegSet &getWWMReservedRegs() const { return WWMReservedRegs; }
592
594 return PrologEpilogSGPRSpills;
595 }
596
597 GCNUserSGPRUsageInfo &getUserSGPRInfo() { return UserSGPRInfo; }
598
599 const GCNUserSGPRUsageInfo &getUserSGPRInfo() const { return UserSGPRInfo; }
600
603 PrologEpilogSGPRSpills.insert(std::make_pair(Reg, SI));
604 }
605
606 // Check if an entry created for \p Reg in PrologEpilogSGPRSpills. Return true
607 // on success and false otherwise.
609 return PrologEpilogSGPRSpills.contains(Reg);
610 }
611
612 // Get the scratch SGPR if allocated to save/restore \p Reg.
614 auto I = PrologEpilogSGPRSpills.find(Reg);
615 if (I != PrologEpilogSGPRSpills.end() &&
616 I->second.getKind() == SGPRSaveKind::COPY_TO_SCRATCH_SGPR)
617 return I->second.getReg();
618
619 return AMDGPU::NoRegister;
620 }
621
622 // Get all scratch SGPRs allocated to copy/restore the SGPR spills.
624 for (const auto &SI : PrologEpilogSGPRSpills) {
625 if (SI.second.getKind() == SGPRSaveKind::COPY_TO_SCRATCH_SGPR)
626 Regs.push_back(SI.second.getReg());
627 }
628 }
629
630 // Check if \p FI is allocated for any SGPR spill to a VGPR lane during PEI.
632 return find_if(PrologEpilogSGPRSpills,
633 [FI](const std::pair<Register,
635 return SI.second.getKind() ==
637 SI.second.getIndex() == FI;
638 }) != PrologEpilogSGPRSpills.end();
639 }
640
643 auto I = PrologEpilogSGPRSpills.find(Reg);
644 assert(I != PrologEpilogSGPRSpills.end());
645
646 return I->second;
647 }
648
650 getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) const {
651 auto I = SGPRSpillsToPhysicalVGPRLanes.find(FrameIndex);
652 return (I == SGPRSpillsToPhysicalVGPRLanes.end())
654 : ArrayRef(I->second);
655 }
656
657 void setFlag(Register Reg, uint8_t Flag) {
658 assert(Reg.isVirtual());
659 if (VRegFlags.inBounds(Reg))
660 VRegFlags[Reg] |= Flag;
661 }
662
663 bool checkFlag(Register Reg, uint8_t Flag) const {
664 if (Reg.isPhysical())
665 return false;
666
667 return VRegFlags.inBounds(Reg) && VRegFlags[Reg] & Flag;
668 }
669
670 bool hasVRegFlags() { return VRegFlags.size(); }
671
673 Align Alignment = Align(4));
674
676 MachineFunction &MF,
677 SmallVectorImpl<std::pair<Register, int>> &CalleeSavedRegs,
678 SmallVectorImpl<std::pair<Register, int>> &ScratchRegs) const;
679
681 return SpillAGPR;
682 }
683
684 Register getSGPRForEXECCopy() const { return SGPRForEXECCopy; }
685
686 void setSGPRForEXECCopy(Register Reg) { SGPRForEXECCopy = Reg; }
687
689 return SpillVGPR;
690 }
691
692 MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
693 auto I = VGPRToAGPRSpills.find(FrameIndex);
694 return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
695 : I->second.Lanes[Lane];
696 }
697
698 void setVGPRToAGPRSpillDead(int FrameIndex) {
699 auto I = VGPRToAGPRSpills.find(FrameIndex);
700 if (I != VGPRToAGPRSpills.end())
701 I->second.IsDead = true;
702 }
703
705 bool IsPrologEpilog = false);
706 bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
707
708 /// If \p ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill
709 /// to the default stack.
711 bool ResetSGPRSpillStackIDs);
712
714 std::optional<int> getOptionalScavengeFI() const { return ScavengeFI; }
715
716 unsigned getBytesInStackArgArea() const {
717 return BytesInStackArgArea;
718 }
719
720 void setBytesInStackArgArea(unsigned Bytes) {
721 BytesInStackArgArea = Bytes;
722 }
723
724 // Add user SGPRs.
735 unsigned AllocSizeDWord, int KernArgIdx,
736 int PaddingSGPRs);
737
738 /// Increment user SGPRs used for padding the argument list only.
740 Register Next = getNextUserSGPR();
741 ++NumUserSGPRs;
742 return Next;
743 }
744
745 // Add system SGPRs.
746 Register addWorkGroupIDX(bool HasArchitectedSGPRs) {
747 Register Reg =
748 HasArchitectedSGPRs ? (MCPhysReg)AMDGPU::TTMP9 : getNextSystemSGPR();
750 if (!HasArchitectedSGPRs)
751 NumSystemSGPRs += 1;
752
753 return ArgInfo.WorkGroupIDX.getRegister();
754 }
755
756 Register addWorkGroupIDY(bool HasArchitectedSGPRs) {
757 Register Reg =
758 HasArchitectedSGPRs ? (MCPhysReg)AMDGPU::TTMP7 : getNextSystemSGPR();
759 unsigned Mask = HasArchitectedSGPRs && hasWorkGroupIDZ() ? 0xffff : ~0u;
760 ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(Reg, Mask);
761 if (!HasArchitectedSGPRs)
762 NumSystemSGPRs += 1;
763
764 return ArgInfo.WorkGroupIDY.getRegister();
765 }
766
767 Register addWorkGroupIDZ(bool HasArchitectedSGPRs) {
768 Register Reg =
769 HasArchitectedSGPRs ? (MCPhysReg)AMDGPU::TTMP7 : getNextSystemSGPR();
770 unsigned Mask = HasArchitectedSGPRs ? 0xffff << 16 : ~0u;
771 ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(Reg, Mask);
772 if (!HasArchitectedSGPRs)
773 NumSystemSGPRs += 1;
774
775 return ArgInfo.WorkGroupIDZ.getRegister();
776 }
777
779 ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
780 NumSystemSGPRs += 1;
781 return ArgInfo.WorkGroupInfo.getRegister();
782 }
783
784 bool hasLDSKernelId() const { return LDSKernelId; }
785
786 // Add special VGPR inputs
788 ArgInfo.WorkItemIDX = Arg;
789 }
790
792 ArgInfo.WorkItemIDY = Arg;
793 }
794
796 ArgInfo.WorkItemIDZ = Arg;
797 }
798
800 ArgInfo.PrivateSegmentWaveByteOffset
801 = ArgDescriptor::createRegister(getNextSystemSGPR());
802 NumSystemSGPRs += 1;
803 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
804 }
805
807 ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
808 }
809
810 bool hasWorkGroupIDX() const {
811 return WorkGroupIDX;
812 }
813
814 bool hasWorkGroupIDY() const {
815 return WorkGroupIDY;
816 }
817
818 bool hasWorkGroupIDZ() const {
819 return WorkGroupIDZ;
820 }
821
822 bool hasWorkGroupInfo() const {
823 return WorkGroupInfo;
824 }
825
827 return PrivateSegmentWaveByteOffset;
828 }
829
830 bool hasWorkItemIDX() const {
831 return WorkItemIDX;
832 }
833
834 bool hasWorkItemIDY() const {
835 return WorkItemIDY;
836 }
837
838 bool hasWorkItemIDZ() const {
839 return WorkItemIDZ;
840 }
841
842 bool hasImplicitArgPtr() const {
843 return ImplicitArgPtr;
844 }
845
847 return ArgInfo;
848 }
849
851 return ArgInfo;
852 }
853
854 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
856 return ArgInfo.getPreloadedValue(Value);
857 }
858
860 auto Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));
861 return Arg ? Arg->getRegister() : MCRegister();
862 }
863
864 unsigned getGITPtrHigh() const {
865 return GITPtrHigh;
866 }
867
868 Register getGITPtrLoReg(const MachineFunction &MF) const;
869
871 return HighBitsOf32BitAddress;
872 }
873
874 unsigned getNumUserSGPRs() const {
875 return NumUserSGPRs;
876 }
877
878 unsigned getNumPreloadedSGPRs() const {
879 return NumUserSGPRs + NumSystemSGPRs;
880 }
881
883 return UserSGPRInfo.getNumKernargPreloadSGPRs();
884 }
885
887 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
888 }
889
890 /// Returns the physical register reserved for use as the resource
891 /// descriptor for scratch accesses.
893 return ScratchRSrcReg;
894 }
895
897 assert(Reg != 0 && "Should never be unset");
898 ScratchRSrcReg = Reg;
899 }
900
902 return FrameOffsetReg;
903 }
904
906 assert(Reg != 0 && "Should never be unset");
907 FrameOffsetReg = Reg;
908 }
909
911 assert(Reg != 0 && "Should never be unset");
912 StackPtrOffsetReg = Reg;
913 }
914
915 void setLongBranchReservedReg(Register Reg) { LongBranchReservedReg = Reg; }
916
917 // Note the unset value for this is AMDGPU::SP_REG rather than
918 // NoRegister. This is mostly a workaround for MIR tests where state that
919 // can't be directly computed from the function is not preserved in serialized
920 // MIR.
922 return StackPtrOffsetReg;
923 }
924
925 Register getLongBranchReservedReg() const { return LongBranchReservedReg; }
926
928 return ArgInfo.QueuePtr.getRegister();
929 }
930
932 return ArgInfo.ImplicitBufferPtr.getRegister();
933 }
934
935 bool hasSpilledSGPRs() const {
936 return HasSpilledSGPRs;
937 }
938
939 void setHasSpilledSGPRs(bool Spill = true) {
940 HasSpilledSGPRs = Spill;
941 }
942
943 bool hasSpilledVGPRs() const {
944 return HasSpilledVGPRs;
945 }
946
947 void setHasSpilledVGPRs(bool Spill = true) {
948 HasSpilledVGPRs = Spill;
949 }
950
952 return HasNonSpillStackObjects;
953 }
954
955 void setHasNonSpillStackObjects(bool StackObject = true) {
956 HasNonSpillStackObjects = StackObject;
957 }
958
959 bool isStackRealigned() const {
960 return IsStackRealigned;
961 }
962
963 void setIsStackRealigned(bool Realigned = true) {
964 IsStackRealigned = Realigned;
965 }
966
967 unsigned getNumSpilledSGPRs() const {
968 return NumSpilledSGPRs;
969 }
970
971 unsigned getNumSpilledVGPRs() const {
972 return NumSpilledVGPRs;
973 }
974
975 void addToSpilledSGPRs(unsigned num) {
976 NumSpilledSGPRs += num;
977 }
978
979 void addToSpilledVGPRs(unsigned num) {
980 NumSpilledVGPRs += num;
981 }
982
983 unsigned getPSInputAddr() const {
984 return PSInputAddr;
985 }
986
987 unsigned getPSInputEnable() const {
988 return PSInputEnable;
989 }
990
991 bool isPSInputAllocated(unsigned Index) const {
992 return PSInputAddr & (1 << Index);
993 }
994
996 PSInputAddr |= 1 << Index;
997 }
998
999 void markPSInputEnabled(unsigned Index) {
1000 PSInputEnable |= 1 << Index;
1001 }
1002
1003 bool returnsVoid() const {
1004 return ReturnsVoid;
1005 }
1006
1008 ReturnsVoid = Value;
1009 }
1010
1011 /// \returns A pair of default/requested minimum/maximum flat work group sizes
1012 /// for this function.
1013 std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
1014 return FlatWorkGroupSizes;
1015 }
1016
1017 /// \returns Default/requested minimum flat work group size for this function.
1018 unsigned getMinFlatWorkGroupSize() const {
1019 return FlatWorkGroupSizes.first;
1020 }
1021
1022 /// \returns Default/requested maximum flat work group size for this function.
1023 unsigned getMaxFlatWorkGroupSize() const {
1024 return FlatWorkGroupSizes.second;
1025 }
1026
1027 /// \returns A pair of default/requested minimum/maximum number of waves per
1028 /// execution unit.
1029 std::pair<unsigned, unsigned> getWavesPerEU() const {
1030 return WavesPerEU;
1031 }
1032
1033 /// \returns Default/requested minimum number of waves per execution unit.
1034 unsigned getMinWavesPerEU() const {
1035 return WavesPerEU.first;
1036 }
1037
1038 /// \returns Default/requested maximum number of waves per execution unit.
1039 unsigned getMaxWavesPerEU() const {
1040 return WavesPerEU.second;
1041 }
1042
1043 /// \returns SGPR used for \p Dim's work group ID.
1044 Register getWorkGroupIDSGPR(unsigned Dim) const {
1045 switch (Dim) {
1046 case 0:
1048 return ArgInfo.WorkGroupIDX.getRegister();
1049 case 1:
1051 return ArgInfo.WorkGroupIDY.getRegister();
1052 case 2:
1054 return ArgInfo.WorkGroupIDZ.getRegister();
1055 }
1056 llvm_unreachable("unexpected dimension");
1057 }
1058
1061 return &GWSResourcePSV;
1062 }
1063
1064 unsigned getOccupancy() const {
1065 return Occupancy;
1066 }
1067
1068 unsigned getMinAllowedOccupancy() const {
1069 if (!isMemoryBound() && !needsWaveLimiter())
1070 return Occupancy;
1071 return (Occupancy < 4) ? Occupancy : 4;
1072 }
1073
1074 void limitOccupancy(const MachineFunction &MF);
1075
1076 void limitOccupancy(unsigned Limit) {
1077 if (Occupancy > Limit)
1078 Occupancy = Limit;
1079 }
1080
1081 void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
1082 if (Occupancy < Limit)
1083 Occupancy = Limit;
1084 limitOccupancy(MF);
1085 }
1086
1087 bool mayNeedAGPRs() const {
1088 return MayNeedAGPRs;
1089 }
1090
1091 // \returns true if a function has a use of AGPRs via inline asm or
1092 // has a call which may use it.
1093 bool mayUseAGPRs(const Function &F) const;
1094
1095 // \returns true if a function needs or may need AGPRs.
1096 bool usesAGPRs(const MachineFunction &MF) const;
1097};
1098
1099} // end namespace llvm
1100
1101#endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
Provides AMDGPU specific target descriptions.
The AMDGPU TargetMachine interface definition for hw codegen targets.
basic Basic Alias true
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
uint64_t Size
IO & YamlIO
Definition: ELFYAML.cpp:1274
AMD GCN specific subclass of TargetSubtarget.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Promote Memory to Register
Definition: Mem2Reg.cpp:114
const char LLVMTargetMachineRef TM
Basic Register Allocator
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
Interface definition for SIInstrInfo.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file implements a set that has insertion order iteration characteristics.
This file defines the SmallVector class.
void printCustom(raw_ostream &OS) const override
Implement printing for PseudoSourceValue.
static bool classof(const PseudoSourceValue *V)
AMDGPUGWSResourcePseudoSourceValue(const AMDGPUTargetMachine &TM)
bool mayAlias(const MachineFrameInfo *) const override
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
bool isAliased(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...
bool isConstant(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue has a constant value.
AMDGPUPseudoSourceValue(unsigned Kind, const AMDGPUTargetMachine &TM)
bool mayAlias(const MachineFrameInfo *) const override
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
bool isAliased(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:155
iterator end()
Definition: DenseMap.h:84
bool contains(const_arg_type_t< KeyT > Val) const
Return true if the specified key is in the map, false otherwise.
Definition: DenseMap.h:145
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:220
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, Register R)
PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, int I)
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
const WWMSpillsMap & getWWMSpills() const
bool usesAGPRs(const MachineFunction &MF) const
bool isPSInputAllocated(unsigned Index) const
void getAllScratchSGPRCopyDstRegs(SmallVectorImpl< Register > &Regs) const
ArrayRef< MCPhysReg > getAGPRSpillVGPRs() const
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
void setWorkItemIDY(ArgDescriptor Arg)
const PrologEpilogSGPRSpillsMap & getPrologEpilogSGPRSpills() const
void increaseOccupancy(const MachineFunction &MF, unsigned Limit)
void setWorkItemIDZ(ArgDescriptor Arg)
std::pair< unsigned, unsigned > getWavesPerEU() const
MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const
GCNUserSGPRUsageInfo & getUserSGPRInfo()
void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size=4, Align Alignment=Align(4))
Register addDispatchPtr(const SIRegisterInfo &TRI)
void setFlag(Register Reg, uint8_t Flag)
void setVGPRToAGPRSpillDead(int FrameIndex)
std::pair< unsigned, unsigned > getFlatWorkGroupSizes() const
Register addFlatScratchInit(const SIRegisterInfo &TRI)
Register getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses.
void setStackPtrOffsetReg(Register Reg)
Register addReservedUserSGPR()
Increment user SGPRs used for padding the argument list only.
ArrayRef< MCPhysReg > getVGPRSpillAGPRs() const
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Register addQueuePtr(const SIRegisterInfo &TRI)
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToVirtualVGPRLanes(int FrameIndex) const
bool allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI, bool IsPrologEpilog=false)
SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI)=default
bool hasPrologEpilogSGPRSpillEntry(Register Reg) const
Register getGITPtrLoReg(const MachineFunction &MF) const
void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy)
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
void splitWWMSpillRegisters(MachineFunction &MF, SmallVectorImpl< std::pair< Register, int > > &CalleeSavedRegs, SmallVectorImpl< std::pair< Register, int > > &ScratchRegs) const
void setBytesInStackArgArea(unsigned Bytes)
SIModeRegisterDefaults getMode() const
Register addWorkGroupIDX(bool HasArchitectedSGPRs)
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) const
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const
bool mayUseAGPRs(const Function &F) const
bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const
Register addWorkGroupIDY(bool HasArchitectedSGPRs)
const GCNUserSGPRUsageInfo & getUserSGPRInfo() const
void setPrivateSegmentWaveByteOffset(Register Reg)
void setLongBranchReservedReg(Register Reg)
const AMDGPUFunctionArgInfo & getArgInfo() const
Register addKernargSegmentPtr(const SIRegisterInfo &TRI)
Register addDispatchID(const SIRegisterInfo &TRI)
void setHasSpilledVGPRs(bool Spill=true)
bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)
If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
void markPSInputAllocated(unsigned Index)
void setWorkItemIDX(ArgDescriptor Arg)
MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
bool checkFlag(Register Reg, uint8_t Flag) const
void markPSInputEnabled(unsigned Index)
MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const
void setHasSpilledSGPRs(bool Spill=true)
Register getWorkGroupIDSGPR(unsigned Dim) const
bool checkIndexInPrologEpilogSGPRSpills(int FI) const
unsigned getNumKernargPreloadedSGPRs() const
Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
Register addWorkGroupIDZ(bool HasArchitectedSGPRs)
const ReservedRegSet & getWWMReservedRegs() const
Register getImplicitBufferPtrUserSGPR() const
std::optional< int > getOptionalScavengeFI() const
Register addImplicitBufferPtr(const SIRegisterInfo &TRI)
AMDGPUFunctionArgInfo & getArgInfo()
const PrologEpilogSGPRSaveRestoreInfo & getPrologEpilogSGPRSaveRestoreInfo(Register Reg) const
void setHasNonSpillStackObjects(bool StackObject=true)
void setIsStackRealigned(bool Realigned=true)
void limitOccupancy(const MachineFunction &MF)
ArrayRef< Register > getSGPRSpillVGPRs() const
SmallVectorImpl< MCRegister > * addPreloadedKernArg(const SIRegisterInfo &TRI, const TargetRegisterClass *RC, unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs)
void addToPrologEpilogSGPRSpills(Register Reg, PrologEpilogSGPRSaveRestoreInfo SI)
Register getScratchSGPRCopyDstReg(Register Reg) const
Register getPrivateSegmentWaveByteOffsetSystemSGPR() const
const AMDGPUGWSResourcePseudoSourceValue * getGWSPSV(const AMDGPUTargetMachine &TM)
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
Represents a range in source code.
Definition: SMLoc.h:48
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:162
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
@ Other
Any other memory.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1753
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1883
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
static ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Helper struct shared between Function Specialization and SCCP Solver.
Definition: SCCPSolver.h:41
@ PreserveSign
The sign of a flushed-to-zero number is preserved in the sign of 0.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
static void mapping(IO &YamlIO, SIArgumentInfo &AI)
static void mapping(IO &YamlIO, SIArgument &A)
static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI)
static void mapping(IO &YamlIO, SIMode &Mode)
std::optional< SIArgument > PrivateSegmentWaveByteOffset
std::optional< SIArgument > WorkGroupIDY
std::optional< SIArgument > FlatScratchInit
std::optional< SIArgument > DispatchPtr
std::optional< SIArgument > DispatchID
std::optional< SIArgument > WorkItemIDY
std::optional< SIArgument > WorkGroupIDX
std::optional< SIArgument > ImplicitArgPtr
std::optional< SIArgument > QueuePtr
std::optional< SIArgument > WorkGroupInfo
std::optional< SIArgument > LDSKernelId
std::optional< SIArgument > ImplicitBufferPtr
std::optional< SIArgument > WorkItemIDX
std::optional< SIArgument > KernargSegmentPtr
std::optional< SIArgument > WorkItemIDZ
std::optional< SIArgument > PrivateSegmentSize
std::optional< SIArgument > PrivateSegmentBuffer
std::optional< SIArgument > WorkGroupIDZ
std::optional< unsigned > Mask
SIArgument(const SIArgument &Other)
SIArgument & operator=(const SIArgument &Other)
static SIArgument createArgument(bool IsReg)
SmallVector< StringValue > WWMReservedRegs
void mappingImpl(yaml::IO &YamlIO) override
std::optional< SIArgumentInfo > ArgInfo
std::optional< FrameIndex > ScavengeFI
SIMode(const SIModeRegisterDefaults &Mode)
bool operator==(const SIMode Other) const
A wrapper around std::string which contains a source range that's being set during parsing.