LLVM  15.0.0git
SIMachineFunctionInfo.h
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1 //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 
17 #include "AMDGPUMachineFunction.h"
18 #include "AMDGPUTargetMachine.h"
20 #include "SIInstrInfo.h"
21 #include "llvm/ADT/SetVector.h"
25 
26 namespace llvm {
27 
28 class MachineFrameInfo;
29 class MachineFunction;
30 class SIMachineFunctionInfo;
31 class SIRegisterInfo;
32 class TargetRegisterClass;
33 
35 public:
36  enum AMDGPUPSVKind : unsigned {
40  };
41 
42 protected:
44  : PseudoSourceValue(Kind, TM) {}
45 
46 public:
47  bool isConstant(const MachineFrameInfo *) const override {
48  // This should probably be true for most images, but we will start by being
49  // conservative.
50  return false;
51  }
52 
53  bool isAliased(const MachineFrameInfo *) const override {
54  return true;
55  }
56 
57  bool mayAlias(const MachineFrameInfo *) const override {
58  return true;
59  }
60 };
61 
63 public:
66 
67  static bool classof(const PseudoSourceValue *V) {
68  return V->kind() == PSVBuffer;
69  }
70 
71  void printCustom(raw_ostream &OS) const override { OS << "BufferResource"; }
72 };
73 
75 public:
76  // TODO: Is the img rsrc useful?
79 
80  static bool classof(const PseudoSourceValue *V) {
81  return V->kind() == PSVImage;
82  }
83 
84  void printCustom(raw_ostream &OS) const override { OS << "ImageResource"; }
85 };
86 
88 public:
91 
92  static bool classof(const PseudoSourceValue *V) {
93  return V->kind() == GWSResource;
94  }
95 
96  // These are inaccessible memory from IR.
97  bool isAliased(const MachineFrameInfo *) const override {
98  return false;
99  }
100 
101  // These are inaccessible memory from IR.
102  bool mayAlias(const MachineFrameInfo *) const override {
103  return false;
104  }
105 
106  void printCustom(raw_ostream &OS) const override {
107  OS << "GWSResource";
108  }
109 };
110 
111 namespace yaml {
112 
113 struct SIArgument {
115  union {
117  unsigned StackOffset;
118  };
120 
121  // Default constructor, which creates a stack argument.
123  SIArgument(const SIArgument &Other) {
124  IsRegister = Other.IsRegister;
125  if (IsRegister) {
126  ::new ((void *)std::addressof(RegisterName))
127  StringValue(Other.RegisterName);
128  } else
129  StackOffset = Other.StackOffset;
130  Mask = Other.Mask;
131  }
132  SIArgument &operator=(const SIArgument &Other) {
133  IsRegister = Other.IsRegister;
134  if (IsRegister) {
135  ::new ((void *)std::addressof(RegisterName))
136  StringValue(Other.RegisterName);
137  } else
138  StackOffset = Other.StackOffset;
139  Mask = Other.Mask;
140  return *this;
141  }
143  if (IsRegister)
144  RegisterName.~StringValue();
145  }
146 
147  // Helper to create a register or stack argument.
148  static inline SIArgument createArgument(bool IsReg) {
149  if (IsReg)
150  return SIArgument(IsReg);
151  return SIArgument();
152  }
153 
154 private:
155  // Construct a register argument.
156  SIArgument(bool) : IsRegister(true), RegisterName() {}
157 };
158 
159 template <> struct MappingTraits<SIArgument> {
160  static void mapping(IO &YamlIO, SIArgument &A) {
161  if (YamlIO.outputting()) {
162  if (A.IsRegister)
163  YamlIO.mapRequired("reg", A.RegisterName);
164  else
165  YamlIO.mapRequired("offset", A.StackOffset);
166  } else {
167  auto Keys = YamlIO.keys();
168  if (is_contained(Keys, "reg")) {
169  A = SIArgument::createArgument(true);
170  YamlIO.mapRequired("reg", A.RegisterName);
171  } else if (is_contained(Keys, "offset"))
172  YamlIO.mapRequired("offset", A.StackOffset);
173  else
174  YamlIO.setError("missing required key 'reg' or 'offset'");
175  }
176  YamlIO.mapOptional("mask", A.Mask);
177  }
178  static const bool flow = true;
179 };
180 
189 
195 
198 
202 };
203 
204 template <> struct MappingTraits<SIArgumentInfo> {
205  static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
206  YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
207  YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
208  YamlIO.mapOptional("queuePtr", AI.QueuePtr);
209  YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
210  YamlIO.mapOptional("dispatchID", AI.DispatchID);
211  YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
212  YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
213 
214  YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
215  YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
216  YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
217  YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
218  YamlIO.mapOptional("privateSegmentWaveByteOffset",
220 
221  YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
222  YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
223 
224  YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
225  YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
226  YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
227  }
228 };
229 
230 // Default to default mode for default calling convention.
231 struct SIMode {
232  bool IEEE = true;
233  bool DX10Clamp = true;
234  bool FP32InputDenormals = true;
235  bool FP32OutputDenormals = true;
238 
239  SIMode() = default;
240 
242  IEEE = Mode.IEEE;
243  DX10Clamp = Mode.DX10Clamp;
244  FP32InputDenormals = Mode.FP32InputDenormals;
245  FP32OutputDenormals = Mode.FP32OutputDenormals;
246  FP64FP16InputDenormals = Mode.FP64FP16InputDenormals;
247  FP64FP16OutputDenormals = Mode.FP64FP16OutputDenormals;
248  }
249 
250  bool operator ==(const SIMode Other) const {
251  return IEEE == Other.IEEE &&
252  DX10Clamp == Other.DX10Clamp &&
253  FP32InputDenormals == Other.FP32InputDenormals &&
254  FP32OutputDenormals == Other.FP32OutputDenormals &&
255  FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
256  FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
257  }
258 };
259 
260 template <> struct MappingTraits<SIMode> {
261  static void mapping(IO &YamlIO, SIMode &Mode) {
262  YamlIO.mapOptional("ieee", Mode.IEEE, true);
263  YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
264  YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
265  YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
266  YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
267  YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
268  }
269 };
270 
277  bool IsEntryFunction = false;
278  bool NoSignedZerosFPMath = false;
279  bool MemoryBound = false;
280  bool WaveLimiter = false;
281  bool HasSpilledSGPRs = false;
282  bool HasSpilledVGPRs = false;
284 
285  // TODO: 10 may be a better default since it's the maximum.
286  unsigned Occupancy = 0;
287 
289 
290  StringValue ScratchRSrcReg = "$private_rsrc_reg";
293 
294  unsigned BytesInStackArgArea = 0;
295  bool ReturnsVoid = true;
296 
301 
302  SIMachineFunctionInfo() = default;
304  const TargetRegisterInfo &TRI,
305  const llvm::MachineFunction &MF);
306 
307  void mappingImpl(yaml::IO &YamlIO) override;
308  ~SIMachineFunctionInfo() = default;
309 };
310 
312  static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
313  YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
314  UINT64_C(0));
315  YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign);
316  YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
317  YamlIO.mapOptional("gdsSize", MFI.GDSSize, 0u);
318  YamlIO.mapOptional("dynLDSAlign", MFI.DynLDSAlign, Align());
319  YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
320  YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
321  YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
322  YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
323  YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
324  YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false);
325  YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
326  StringValue("$private_rsrc_reg"));
327  YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
328  StringValue("$fp_reg"));
329  YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
330  StringValue("$sp_reg"));
331  YamlIO.mapOptional("bytesInStackArgArea", MFI.BytesInStackArgArea, 0u);
332  YamlIO.mapOptional("returnsVoid", MFI.ReturnsVoid, true);
333  YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
334  YamlIO.mapOptional("mode", MFI.Mode, SIMode());
335  YamlIO.mapOptional("highBitsOf32BitAddress",
336  MFI.HighBitsOf32BitAddress, 0u);
337  YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
338  YamlIO.mapOptional("wwmReservedRegs", MFI.WWMReservedRegs);
339  YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
340  YamlIO.mapOptional("vgprForAGPRCopy", MFI.VGPRForAGPRCopy,
341  StringValue()); // Don't print out when it's empty.
342  }
343 };
344 
345 } // end namespace yaml
346 
347 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
348 /// tells the hardware which interpolation parameters to load.
350  friend class GCNTargetMachine;
351 
352  // Registers that may be reserved for spilling purposes. These may be the same
353  // as the input registers.
354  Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
355 
356  // This is the the unswizzled offset from the current dispatch's scratch wave
357  // base to the beginning of the current function's frame.
358  Register FrameOffsetReg = AMDGPU::FP_REG;
359 
360  // This is an ABI register used in the non-entry calling convention to
361  // communicate the unswizzled offset from the current dispatch's scratch wave
362  // base to the beginning of the new function's frame.
363  Register StackPtrOffsetReg = AMDGPU::SP_REG;
364 
366 
367  // Graphics info.
368  unsigned PSInputAddr = 0;
369  unsigned PSInputEnable = 0;
370 
371  /// Number of bytes of arguments this function has on the stack. If the callee
372  /// is expected to restore the argument stack this should be a multiple of 16,
373  /// all usable during a tail call.
374  ///
375  /// The alternative would forbid tail call optimisation in some cases: if we
376  /// want to transfer control from a function with 8-bytes of stack-argument
377  /// space to a function with 16-bytes then misalignment of this value would
378  /// make a stack adjustment necessary, which could not be undone by the
379  /// callee.
380  unsigned BytesInStackArgArea = 0;
381 
382  bool ReturnsVoid = true;
383 
384  // A pair of default/requested minimum/maximum flat work group sizes.
385  // Minimum - first, maximum - second.
386  std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
387 
388  // A pair of default/requested minimum/maximum number of waves per execution
389  // unit. Minimum - first, maximum - second.
390  std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
391 
392  const AMDGPUBufferPseudoSourceValue BufferPSV;
393  const AMDGPUImagePseudoSourceValue ImagePSV;
394  const AMDGPUGWSResourcePseudoSourceValue GWSResourcePSV;
395 
396 private:
397  unsigned NumUserSGPRs = 0;
398  unsigned NumSystemSGPRs = 0;
399 
400  bool HasSpilledSGPRs = false;
401  bool HasSpilledVGPRs = false;
402  bool HasNonSpillStackObjects = false;
403  bool IsStackRealigned = false;
404 
405  unsigned NumSpilledSGPRs = 0;
406  unsigned NumSpilledVGPRs = 0;
407 
408  // Feature bits required for inputs passed in user SGPRs.
409  bool PrivateSegmentBuffer : 1;
410  bool DispatchPtr : 1;
411  bool QueuePtr : 1;
412  bool KernargSegmentPtr : 1;
413  bool DispatchID : 1;
414  bool FlatScratchInit : 1;
415 
416  // Feature bits required for inputs passed in system SGPRs.
417  bool WorkGroupIDX : 1; // Always initialized.
418  bool WorkGroupIDY : 1;
419  bool WorkGroupIDZ : 1;
420  bool WorkGroupInfo : 1;
421  bool PrivateSegmentWaveByteOffset : 1;
422 
423  bool WorkItemIDX : 1; // Always initialized.
424  bool WorkItemIDY : 1;
425  bool WorkItemIDZ : 1;
426 
427  // Private memory buffer
428  // Compute directly in sgpr[0:1]
429  // Other shaders indirect 64-bits at sgpr[0:1]
430  bool ImplicitBufferPtr : 1;
431 
432  // Pointer to where the ABI inserts special kernel arguments separate from the
433  // user arguments. This is an offset from the KernargSegmentPtr.
434  bool ImplicitArgPtr : 1;
435 
436  bool MayNeedAGPRs : 1;
437 
438  // The hard-wired high half of the address of the global information table
439  // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
440  // current hardware only allows a 16 bit value.
441  unsigned GITPtrHigh;
442 
443  unsigned HighBitsOf32BitAddress;
444 
445  // Current recorded maximum possible occupancy.
446  unsigned Occupancy;
447 
448  mutable Optional<bool> UsesAGPRs;
449 
450  MCPhysReg getNextUserSGPR() const;
451 
452  MCPhysReg getNextSystemSGPR() const;
453 
454 public:
455  struct SGPRSpillVGPR {
456  // VGPR used for SGPR spills
458 
459  // If the VGPR is is used for SGPR spills in a non-entrypoint function, the
460  // stack slot used to save/restore it in the prolog/epilog.
462 
464  };
465 
468  bool FullyAllocated = false;
469  bool IsDead = false;
470  };
471 
472  // Track VGPRs reserved for WWM.
474 
475  /// Track stack slots used for save/restore of reserved WWM VGPRs in the
476  /// prolog/epilog.
477 
478  /// FIXME: This is temporary state only needed in PrologEpilogInserter, and
479  /// doesn't really belong here. It does not require serialization
481 
483  const SIRegisterInfo &TRI);
484 
485  auto wwmAllocation() const {
488  }
489 
490 private:
491  // Track VGPR + wave index for each subregister of the SGPR spilled to
492  // frameindex key.
494  unsigned NumVGPRSpillLanes = 0;
496 
497  DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
498 
499  // AGPRs used for VGPR spills.
500  SmallVector<MCPhysReg, 32> SpillAGPR;
501 
502  // VGPRs used for AGPR spills.
503  SmallVector<MCPhysReg, 32> SpillVGPR;
504 
505  // Emergency stack slot. Sometimes, we create this before finalizing the stack
506  // frame, so save it here and add it to the RegScavenger later.
507  Optional<int> ScavengeFI;
508 
509 private:
510  Register VGPRForAGPRCopy;
511 
512 public:
514  return VGPRForAGPRCopy;
515  }
516 
517  void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy) {
518  VGPRForAGPRCopy = NewVGPRForAGPRCopy;
519  }
520 
521 public: // FIXME
522  /// If this is set, an SGPR used for save/restore of the register used for the
523  /// frame pointer.
526 
527  /// If this is set, an SGPR used for save/restore of the register used for the
528  /// base pointer.
531 
532  bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg);
533 
534 public:
536  SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI) = default;
537 
541  const override;
542 
544  const MachineFunction &MF,
546  SMDiagnostic &Error, SMRange &SourceRange);
547 
549  WWMReservedRegs.insert(Reg);
550  }
551 
554  auto I = SGPRToVGPRSpills.find(FrameIndex);
555  return (I == SGPRToVGPRSpills.end())
557  : makeArrayRef(I->second);
558  }
559 
560  ArrayRef<SGPRSpillVGPR> getSGPRSpillVGPRs() const { return SpillVGPRs; }
561 
563  return SpillAGPR;
564  }
565 
567  return SpillVGPR;
568  }
569 
570  MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
571  auto I = VGPRToAGPRSpills.find(FrameIndex);
572  return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
573  : I->second.Lanes[Lane];
574  }
575 
577  auto I = VGPRToAGPRSpills.find(FrameIndex);
578  if (I != VGPRToAGPRSpills.end())
579  I->second.IsDead = true;
580  }
581 
583  unsigned NumLane) const;
584  bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
585  bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
586 
587  /// If \p ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill
588  /// to the default stack.
590  bool ResetSGPRSpillStackIDs);
591 
593  Optional<int> getOptionalScavengeFI() const { return ScavengeFI; }
594 
595  unsigned getBytesInStackArgArea() const {
596  return BytesInStackArgArea;
597  }
598 
599  void setBytesInStackArgArea(unsigned Bytes) {
600  BytesInStackArgArea = Bytes;
601  }
602 
603  // Add user SGPRs.
611 
612  // Add system SGPRs.
614  ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
615  NumSystemSGPRs += 1;
616  return ArgInfo.WorkGroupIDX.getRegister();
617  }
618 
620  ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
621  NumSystemSGPRs += 1;
622  return ArgInfo.WorkGroupIDY.getRegister();
623  }
624 
626  ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
627  NumSystemSGPRs += 1;
628  return ArgInfo.WorkGroupIDZ.getRegister();
629  }
630 
632  ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
633  NumSystemSGPRs += 1;
634  return ArgInfo.WorkGroupInfo.getRegister();
635  }
636 
637  // Add special VGPR inputs
639  ArgInfo.WorkItemIDX = Arg;
640  }
641 
643  ArgInfo.WorkItemIDY = Arg;
644  }
645 
647  ArgInfo.WorkItemIDZ = Arg;
648  }
649 
651  ArgInfo.PrivateSegmentWaveByteOffset
652  = ArgDescriptor::createRegister(getNextSystemSGPR());
653  NumSystemSGPRs += 1;
654  return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
655  }
656 
658  ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
659  }
660 
661  bool hasPrivateSegmentBuffer() const {
662  return PrivateSegmentBuffer;
663  }
664 
665  bool hasDispatchPtr() const {
666  return DispatchPtr;
667  }
668 
669  bool hasQueuePtr() const {
670  return QueuePtr;
671  }
672 
673  bool hasKernargSegmentPtr() const {
674  return KernargSegmentPtr;
675  }
676 
677  bool hasDispatchID() const {
678  return DispatchID;
679  }
680 
681  bool hasFlatScratchInit() const {
682  return FlatScratchInit;
683  }
684 
685  bool hasWorkGroupIDX() const {
686  return WorkGroupIDX;
687  }
688 
689  bool hasWorkGroupIDY() const {
690  return WorkGroupIDY;
691  }
692 
693  bool hasWorkGroupIDZ() const {
694  return WorkGroupIDZ;
695  }
696 
697  bool hasWorkGroupInfo() const {
698  return WorkGroupInfo;
699  }
700 
702  return PrivateSegmentWaveByteOffset;
703  }
704 
705  bool hasWorkItemIDX() const {
706  return WorkItemIDX;
707  }
708 
709  bool hasWorkItemIDY() const {
710  return WorkItemIDY;
711  }
712 
713  bool hasWorkItemIDZ() const {
714  return WorkItemIDZ;
715  }
716 
717  bool hasImplicitArgPtr() const {
718  return ImplicitArgPtr;
719  }
720 
721  bool hasImplicitBufferPtr() const {
722  return ImplicitBufferPtr;
723  }
724 
726  return ArgInfo;
727  }
728 
730  return ArgInfo;
731  }
732 
733  std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
735  return ArgInfo.getPreloadedValue(Value);
736  }
737 
739  auto Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));
740  return Arg ? Arg->getRegister() : MCRegister();
741  }
742 
743  unsigned getGITPtrHigh() const {
744  return GITPtrHigh;
745  }
746 
747  Register getGITPtrLoReg(const MachineFunction &MF) const;
748 
750  return HighBitsOf32BitAddress;
751  }
752 
753  unsigned getNumUserSGPRs() const {
754  return NumUserSGPRs;
755  }
756 
757  unsigned getNumPreloadedSGPRs() const {
758  return NumUserSGPRs + NumSystemSGPRs;
759  }
760 
762  return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
763  }
764 
765  /// Returns the physical register reserved for use as the resource
766  /// descriptor for scratch accesses.
768  return ScratchRSrcReg;
769  }
770 
772  assert(Reg != 0 && "Should never be unset");
773  ScratchRSrcReg = Reg;
774  }
775 
777  return FrameOffsetReg;
778  }
779 
781  assert(Reg != 0 && "Should never be unset");
782  FrameOffsetReg = Reg;
783  }
784 
786  assert(Reg != 0 && "Should never be unset");
787  StackPtrOffsetReg = Reg;
788  }
789 
790  // Note the unset value for this is AMDGPU::SP_REG rather than
791  // NoRegister. This is mostly a workaround for MIR tests where state that
792  // can't be directly computed from the function is not preserved in serialized
793  // MIR.
795  return StackPtrOffsetReg;
796  }
797 
799  return ArgInfo.QueuePtr.getRegister();
800  }
801 
803  return ArgInfo.ImplicitBufferPtr.getRegister();
804  }
805 
806  bool hasSpilledSGPRs() const {
807  return HasSpilledSGPRs;
808  }
809 
810  void setHasSpilledSGPRs(bool Spill = true) {
811  HasSpilledSGPRs = Spill;
812  }
813 
814  bool hasSpilledVGPRs() const {
815  return HasSpilledVGPRs;
816  }
817 
818  void setHasSpilledVGPRs(bool Spill = true) {
819  HasSpilledVGPRs = Spill;
820  }
821 
822  bool hasNonSpillStackObjects() const {
823  return HasNonSpillStackObjects;
824  }
825 
826  void setHasNonSpillStackObjects(bool StackObject = true) {
827  HasNonSpillStackObjects = StackObject;
828  }
829 
830  bool isStackRealigned() const {
831  return IsStackRealigned;
832  }
833 
834  void setIsStackRealigned(bool Realigned = true) {
835  IsStackRealigned = Realigned;
836  }
837 
838  unsigned getNumSpilledSGPRs() const {
839  return NumSpilledSGPRs;
840  }
841 
842  unsigned getNumSpilledVGPRs() const {
843  return NumSpilledVGPRs;
844  }
845 
846  void addToSpilledSGPRs(unsigned num) {
847  NumSpilledSGPRs += num;
848  }
849 
850  void addToSpilledVGPRs(unsigned num) {
851  NumSpilledVGPRs += num;
852  }
853 
854  unsigned getPSInputAddr() const {
855  return PSInputAddr;
856  }
857 
858  unsigned getPSInputEnable() const {
859  return PSInputEnable;
860  }
861 
862  bool isPSInputAllocated(unsigned Index) const {
863  return PSInputAddr & (1 << Index);
864  }
865 
866  void markPSInputAllocated(unsigned Index) {
867  PSInputAddr |= 1 << Index;
868  }
869 
870  void markPSInputEnabled(unsigned Index) {
871  PSInputEnable |= 1 << Index;
872  }
873 
874  bool returnsVoid() const {
875  return ReturnsVoid;
876  }
877 
878  void setIfReturnsVoid(bool Value) {
879  ReturnsVoid = Value;
880  }
881 
882  /// \returns A pair of default/requested minimum/maximum flat work group sizes
883  /// for this function.
884  std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
885  return FlatWorkGroupSizes;
886  }
887 
888  /// \returns Default/requested minimum flat work group size for this function.
889  unsigned getMinFlatWorkGroupSize() const {
890  return FlatWorkGroupSizes.first;
891  }
892 
893  /// \returns Default/requested maximum flat work group size for this function.
894  unsigned getMaxFlatWorkGroupSize() const {
895  return FlatWorkGroupSizes.second;
896  }
897 
898  /// \returns A pair of default/requested minimum/maximum number of waves per
899  /// execution unit.
900  std::pair<unsigned, unsigned> getWavesPerEU() const {
901  return WavesPerEU;
902  }
903 
904  /// \returns Default/requested minimum number of waves per execution unit.
905  unsigned getMinWavesPerEU() const {
906  return WavesPerEU.first;
907  }
908 
909  /// \returns Default/requested maximum number of waves per execution unit.
910  unsigned getMaxWavesPerEU() const {
911  return WavesPerEU.second;
912  }
913 
914  /// \returns SGPR used for \p Dim's work group ID.
915  Register getWorkGroupIDSGPR(unsigned Dim) const {
916  switch (Dim) {
917  case 0:
919  return ArgInfo.WorkGroupIDX.getRegister();
920  case 1:
922  return ArgInfo.WorkGroupIDY.getRegister();
923  case 2:
925  return ArgInfo.WorkGroupIDZ.getRegister();
926  }
927  llvm_unreachable("unexpected dimension");
928  }
929 
932  return &BufferPSV;
933  }
934 
937  return &ImagePSV;
938  }
939 
942  return &GWSResourcePSV;
943  }
944 
945  unsigned getOccupancy() const {
946  return Occupancy;
947  }
948 
949  unsigned getMinAllowedOccupancy() const {
950  if (!isMemoryBound() && !needsWaveLimiter())
951  return Occupancy;
952  return (Occupancy < 4) ? Occupancy : 4;
953  }
954 
955  void limitOccupancy(const MachineFunction &MF);
956 
957  void limitOccupancy(unsigned Limit) {
958  if (Occupancy > Limit)
959  Occupancy = Limit;
960  }
961 
962  void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
963  if (Occupancy < Limit)
964  Occupancy = Limit;
965  limitOccupancy(MF);
966  }
967 
968  bool mayNeedAGPRs() const {
969  return MayNeedAGPRs;
970  }
971 
972  // \returns true if a function has a use of AGPRs via inline asm or
973  // has a call which may use it.
974  bool mayUseAGPRs(const MachineFunction &MF) const;
975 
976  // \returns true if a function needs or may need AGPRs.
977  bool usesAGPRs(const MachineFunction &MF) const;
978 };
979 
980 } // end namespace llvm
981 
982 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
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Definition: Allocator.h:63
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Definition: SIMachineFunctionInfo.h:905
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Definition: AMDGPUMachineFunction.h:96
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Returns the physical register reserved for use as the resource descriptor for scratch accesses.
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Definition: Register.h:19
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If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
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Definition: DenseMap.h:84
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Definition: Error.h:155
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Definition: TargetFrameLowering.h:27
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Definition: SIMachineFunctionInfo.h:657
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Definition: SIMachineFunctionInfo.h:900
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Definition: SIMachineFunctionInfo.h:562
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Definition: SIMachineFunctionInfo.h:771
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Definition: SIMachineFunctionInfo.h:275
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Definition: SIMachineFunctionInfo.h:780
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Definition: SIMachineFunctionInfo.h:182
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Definition: SIMachineFunctionInfo.h:595
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@ PSVBuffer
Definition: SIMachineFunctionInfo.h:37
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SIMode()=default
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Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
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Definition: SIMachineFunctionInfo.h:826
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Definition: SIMachineFunctionInfo.h:870
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Definition: SIMachineFunctionInfo.h:281
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Definition: SIMachineFunctionInfo.h:205
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The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:142
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Represents a range in source code.
Definition: SMLoc.h:48
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const AMDGPUBufferPseudoSourceValue * getBufferPSV(const AMDGPUTargetMachine &TM)
Definition: SIMachineFunctionInfo.h:931
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This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:349
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Definition: SIMachineFunctionInfo.h:669
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Definition: SIMachineFunctionInfo.h:689
llvm::SIMachineFunctionInfo::addWorkGroupIDX
Register addWorkGroupIDX()
Definition: SIMachineFunctionInfo.h:613
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Align DynLDSAlign
Definition: SIMachineFunctionInfo.h:276
llvm::SIMachineFunctionInfo::hasKernargSegmentPtr
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Definition: SIMachineFunctionInfo.h:673
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unsigned getPSInputAddr() const
Definition: SIMachineFunctionInfo.h:854
llvm::SIMachineFunctionInfo::isPSInputAllocated
bool isPSInputAllocated(unsigned Index) const
Definition: SIMachineFunctionInfo.h:862
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Definition: SIMachineFunctionInfo.h:631
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Definition: SIMachineFunctionInfo.h:232
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void printCustom(raw_ostream &OS) const override
Implement printing for PseudoSourceValue.
Definition: SIMachineFunctionInfo.h:71
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A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:307
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SIMachineFunctionInfo::setHasSpilledSGPRs
void setHasSpilledSGPRs(bool Spill=true)
Definition: SIMachineFunctionInfo.h:810
llvm::SIMachineFunctionInfo::addToSpilledVGPRs
void addToSpilledVGPRs(unsigned num)
Definition: SIMachineFunctionInfo.h:850
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constexpr char NumSpilledSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSpilledSGPRs.
Definition: AMDGPUMetadata.h:268
llvm::yaml::SIMachineFunctionInfo::~SIMachineFunctionInfo
~SIMachineFunctionInfo()=default
raw_ostream.h
llvm::AMDGPUPseudoSourceValue::isConstant
bool isConstant(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue has a constant value.
Definition: SIMachineFunctionInfo.h:47
llvm::yaml::SIArgument::StackOffset
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Definition: SIMachineFunctionInfo.h:117
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Definition: SIMachineFunctionInfo.h:455
AMDGPUArgumentUsageInfo.h
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:22
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MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Definition: MachineFunction.h:95
llvm::yaml::SIMachineFunctionInfo::MaxKernArgAlign
Align MaxKernArgAlign
Definition: SIMachineFunctionInfo.h:273
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bool hasWorkItemIDX() const
Definition: SIMachineFunctionInfo.h:705
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Definition: SIMachineFunctionInfo.h:237
llvm::yaml::SIArgument::Mask
Optional< unsigned > Mask
Definition: SIMachineFunctionInfo.h:119
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::SIMachineFunctionInfo::hasImplicitBufferPtr
bool hasImplicitBufferPtr() const
Definition: SIMachineFunctionInfo.h:721
llvm::SIMachineFunctionInfo::hasFlatScratchInit
bool hasFlatScratchInit() const
Definition: SIMachineFunctionInfo.h:681
llvm::yaml::SIArgumentInfo::FlatScratchInit
Optional< SIArgument > FlatScratchInit
Definition: SIMachineFunctionInfo.h:187
llvm::SIMachineFunctionInfo::getQueuePtrUserSGPR
Register getQueuePtrUserSGPR() const
Definition: SIMachineFunctionInfo.h:798
AMDGPUTargetMachine.h
llvm::SIMachineFunctionInfo::getFrameOffsetReg
Register getFrameOffsetReg() const
Definition: SIMachineFunctionInfo.h:776
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llvm::SIMachineFunctionInfo::allocateWWMReservedSpillSlots
void allocateWWMReservedSpillSlots(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:463
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1236
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::yaml::SIArgumentInfo::QueuePtr
Optional< SIArgument > QueuePtr
Definition: SIMachineFunctionInfo.h:184