13#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
32class MachineFrameInfo;
34class SIMachineFunctionInfo;
36class TargetRegisterClass;
97 std::optional<unsigned>
Mask;
139 if (
YamlIO.outputting()) {
141 YamlIO.mapRequired(
"reg",
A.RegisterName);
143 YamlIO.mapRequired(
"offset",
A.StackOffset);
145 auto Keys =
YamlIO.keys();
148 YamlIO.mapRequired(
"reg",
A.RegisterName);
150 YamlIO.mapRequired(
"offset",
A.StackOffset);
152 YamlIO.setError(
"missing required key 'reg' or 'offset'");
154 YamlIO.mapOptional(
"mask",
A.Mask);
156 static const bool flow =
true;
198 YamlIO.mapOptional(
"privateSegmentWaveByteOffset",
246 YamlIO.mapOptional(
"dx10-clamp",
Mode.DX10Clamp,
true);
247 YamlIO.mapOptional(
"fp32-input-denormals",
Mode.FP32InputDenormals,
true);
248 YamlIO.mapOptional(
"fp32-output-denormals",
Mode.FP32OutputDenormals,
true);
249 YamlIO.mapOptional(
"fp64-fp16-input-denormals",
Mode.FP64FP16InputDenormals,
true);
250 YamlIO.mapOptional(
"fp64-fp16-output-denormals",
Mode.FP64FP16OutputDenormals,
true);
328 YamlIO.mapOptional(
"highBitsOf32BitAddress",
384 Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
388 Register FrameOffsetReg = AMDGPU::FP_REG;
393 Register StackPtrOffsetReg = AMDGPU::SP_REG;
403 unsigned PSInputAddr = 0;
404 unsigned PSInputEnable = 0;
415 unsigned BytesInStackArgArea = 0;
417 bool ReturnsVoid =
true;
421 std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
425 std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
427 const AMDGPUGWSResourcePseudoSourceValue GWSResourcePSV;
430 unsigned NumUserSGPRs = 0;
431 unsigned NumSystemSGPRs = 0;
433 bool HasSpilledSGPRs =
false;
434 bool HasSpilledVGPRs =
false;
435 bool HasNonSpillStackObjects =
false;
436 bool IsStackRealigned =
false;
438 unsigned NumSpilledSGPRs = 0;
439 unsigned NumSpilledVGPRs = 0;
443 GCNUserSGPRUsageInfo UserSGPRInfo;
446 bool WorkGroupIDX : 1;
447 bool WorkGroupIDY : 1;
448 bool WorkGroupIDZ : 1;
449 bool WorkGroupInfo : 1;
450 bool LDSKernelId : 1;
451 bool PrivateSegmentWaveByteOffset : 1;
453 bool WorkItemIDX : 1;
454 bool WorkItemIDY : 1;
455 bool WorkItemIDZ : 1;
459 bool ImplicitArgPtr : 1;
461 bool MayNeedAGPRs : 1;
468 unsigned HighBitsOf32BitAddress;
471 IndexedMap<uint8_t, VirtReg2IndexFunctor> VRegFlags;
476 mutable std::optional<bool> UsesAGPRs;
483 void MRI_NoteNewVirtualRegister(
Register Reg)
override;
484 void MRI_NoteCloneVirtualRegister(
Register NewReg,
Register SrcReg)
override;
497 SGPRSpillsToVirtualVGPRLanes;
501 SGPRSpillsToPhysicalVGPRLanes;
502 unsigned NumVirtualVGPRSpillLanes = 0;
503 unsigned NumPhysicalVGPRSpillLanes = 0;
542 std::optional<int> ScavengeFI;
554 return VGPRForAGPRCopy;
558 VGPRForAGPRCopy = NewVGPRForAGPRCopy;
583 auto I = SGPRSpillsToVirtualVGPRLanes.
find(FrameIndex);
584 return (
I == SGPRSpillsToVirtualVGPRLanes.
end())
594 return PrologEpilogSGPRSpills;
603 PrologEpilogSGPRSpills.
insert(std::make_pair(
Reg, SI));
614 auto I = PrologEpilogSGPRSpills.
find(
Reg);
615 if (
I != PrologEpilogSGPRSpills.
end() &&
617 return I->second.getReg();
619 return AMDGPU::NoRegister;
624 for (
const auto &SI : PrologEpilogSGPRSpills) {
632 return find_if(PrologEpilogSGPRSpills,
635 return SI.second.getKind() ==
637 SI.second.getIndex() == FI;
638 }) != PrologEpilogSGPRSpills.
end();
643 auto I = PrologEpilogSGPRSpills.
find(
Reg);
651 auto I = SGPRSpillsToPhysicalVGPRLanes.
find(FrameIndex);
652 return (
I == SGPRSpillsToPhysicalVGPRLanes.
end())
659 if (VRegFlags.inBounds(
Reg))
660 VRegFlags[
Reg] |= Flag;
664 if (
Reg.isPhysical())
667 return VRegFlags.inBounds(
Reg) && VRegFlags[
Reg] & Flag;
693 auto I = VGPRToAGPRSpills.
find(FrameIndex);
694 return (
I == VGPRToAGPRSpills.
end()) ? (
MCPhysReg)AMDGPU::NoRegister
695 :
I->second.Lanes[Lane];
699 auto I = VGPRToAGPRSpills.
find(FrameIndex);
700 if (
I != VGPRToAGPRSpills.
end())
701 I->second.IsDead =
true;
705 bool IsPrologEpilog =
false);
711 bool ResetSGPRSpillStackIDs);
717 return BytesInStackArgArea;
721 BytesInStackArgArea = Bytes;
735 unsigned AllocSizeDWord,
int KernArgIdx,
748 HasArchitectedSGPRs ? (
MCPhysReg)AMDGPU::TTMP9 : getNextSystemSGPR();
750 if (!HasArchitectedSGPRs)
753 return ArgInfo.WorkGroupIDX.getRegister();
758 HasArchitectedSGPRs ? (
MCPhysReg)AMDGPU::TTMP7 : getNextSystemSGPR();
759 unsigned Mask = HasArchitectedSGPRs &&
hasWorkGroupIDZ() ? 0xffff : ~0u;
761 if (!HasArchitectedSGPRs)
764 return ArgInfo.WorkGroupIDY.getRegister();
769 HasArchitectedSGPRs ? (
MCPhysReg)AMDGPU::TTMP7 : getNextSystemSGPR();
770 unsigned Mask = HasArchitectedSGPRs ? 0xffff << 16 : ~0u;
772 if (!HasArchitectedSGPRs)
775 return ArgInfo.WorkGroupIDZ.getRegister();
781 return ArgInfo.WorkGroupInfo.getRegister();
800 ArgInfo.PrivateSegmentWaveByteOffset
803 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
823 return WorkGroupInfo;
827 return PrivateSegmentWaveByteOffset;
843 return ImplicitArgPtr;
854 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
860 auto Arg = std::get<0>(
ArgInfo.getPreloadedValue(
Value));
861 return Arg ? Arg->getRegister() :
MCRegister();
871 return HighBitsOf32BitAddress;
879 return NumUserSGPRs + NumSystemSGPRs;
883 return UserSGPRInfo.getNumKernargPreloadSGPRs();
887 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
893 return ScratchRSrcReg;
897 assert(
Reg != 0 &&
"Should never be unset");
898 ScratchRSrcReg =
Reg;
902 return FrameOffsetReg;
906 assert(
Reg != 0 &&
"Should never be unset");
907 FrameOffsetReg =
Reg;
911 assert(
Reg != 0 &&
"Should never be unset");
912 StackPtrOffsetReg =
Reg;
922 return StackPtrOffsetReg;
928 return ArgInfo.QueuePtr.getRegister();
932 return ArgInfo.ImplicitBufferPtr.getRegister();
936 return HasSpilledSGPRs;
940 HasSpilledSGPRs = Spill;
944 return HasSpilledVGPRs;
948 HasSpilledVGPRs = Spill;
952 return HasNonSpillStackObjects;
956 HasNonSpillStackObjects = StackObject;
960 return IsStackRealigned;
964 IsStackRealigned = Realigned;
968 return NumSpilledSGPRs;
972 return NumSpilledVGPRs;
976 NumSpilledSGPRs += num;
980 NumSpilledVGPRs += num;
988 return PSInputEnable;
992 return PSInputAddr & (1 <<
Index);
996 PSInputAddr |= 1 <<
Index;
1000 PSInputEnable |= 1 <<
Index;
1008 ReturnsVoid =
Value;
1014 return FlatWorkGroupSizes;
1019 return FlatWorkGroupSizes.first;
1024 return FlatWorkGroupSizes.second;
1035 return WavesPerEU.first;
1040 return WavesPerEU.second;
1048 return ArgInfo.WorkGroupIDX.getRegister();
1051 return ArgInfo.WorkGroupIDY.getRegister();
1054 return ArgInfo.WorkGroupIDZ.getRegister();
1061 return &GWSResourcePSV;
1071 return (Occupancy < 4) ? Occupancy : 4;
1077 if (Occupancy > Limit)
1082 if (Occupancy < Limit)
1088 return MayNeedAGPRs;
Provides AMDGPU specific target descriptions.
The AMDGPU TargetMachine interface definition for hw codegen targets.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
AMD GCN specific subclass of TargetSubtarget.
unsigned const TargetRegisterInfo * TRI
Promote Memory to Register
const char LLVMTargetMachineRef TM
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
Interface definition for SIInstrInfo.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements a set that has insertion order iteration characteristics.
This file defines the SmallVector class.
void printCustom(raw_ostream &OS) const override
Implement printing for PseudoSourceValue.
static bool classof(const PseudoSourceValue *V)
AMDGPUGWSResourcePseudoSourceValue(const AMDGPUTargetMachine &TM)
bool mayAlias(const MachineFrameInfo *) const override
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
bool isAliased(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...
bool isMemoryBound() const
bool needsWaveLimiter() const
bool isConstant(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue has a constant value.
AMDGPUPseudoSourceValue(unsigned Kind, const AMDGPUTargetMachine &TM)
bool mayAlias(const MachineFrameInfo *) const override
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
bool isAliased(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Allocate memory in an ever growing pool, as if by bump-pointer.
iterator find(const_arg_type_t< KeyT > Val)
bool contains(const_arg_type_t< KeyT > Val) const
Return true if the specified key is in the map, false otherwise.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Lightweight error class with error context and mandatory checking.
Wrapper class representing physical registers. Should be passed by value.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, Register R)
PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, int I)
SGPRSaveKind getKind() const
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
bool hasNonSpillStackObjects() const
const WWMSpillsMap & getWWMSpills() const
bool usesAGPRs(const MachineFunction &MF) const
bool isPSInputAllocated(unsigned Index) const
void getAllScratchSGPRCopyDstRegs(SmallVectorImpl< Register > &Regs) const
ArrayRef< MCPhysReg > getAGPRSpillVGPRs() const
void setSGPRForEXECCopy(Register Reg)
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
unsigned getOccupancy() const
unsigned getNumPreloadedSGPRs() const
void setWorkItemIDY(ArgDescriptor Arg)
const PrologEpilogSGPRSpillsMap & getPrologEpilogSGPRSpills() const
unsigned getNumSpilledVGPRs() const
bool hasLDSKernelId() const
void increaseOccupancy(const MachineFunction &MF, unsigned Limit)
void setWorkItemIDZ(ArgDescriptor Arg)
std::pair< unsigned, unsigned > getWavesPerEU() const
MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const
unsigned getNumSpilledSGPRs() const
GCNUserSGPRUsageInfo & getUserSGPRInfo()
void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size=4, Align Alignment=Align(4))
Register addDispatchPtr(const SIRegisterInfo &TRI)
Register getLongBranchReservedReg() const
bool hasSpilledVGPRs() const
void setFlag(Register Reg, uint8_t Flag)
void setVGPRToAGPRSpillDead(int FrameIndex)
unsigned getMaxFlatWorkGroupSize() const
std::pair< unsigned, unsigned > getFlatWorkGroupSizes() const
Register getStackPtrOffsetReg() const
bool isStackRealigned() const
Register addFlatScratchInit(const SIRegisterInfo &TRI)
Register getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses.
unsigned getMaxWavesPerEU() const
void setStackPtrOffsetReg(Register Reg)
Register addReservedUserSGPR()
Increment user SGPRs used for padding the argument list only.
ArrayRef< MCPhysReg > getVGPRSpillAGPRs() const
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Register addQueuePtr(const SIRegisterInfo &TRI)
bool hasWorkGroupIDZ() const
Register getQueuePtrUserSGPR() const
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToVirtualVGPRLanes(int FrameIndex) const
bool allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI, bool IsPrologEpilog=false)
SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI)=default
bool hasPrologEpilogSGPRSpillEntry(Register Reg) const
Register getGITPtrLoReg(const MachineFunction &MF) const
bool hasWorkGroupIDY() const
void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy)
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
void splitWWMSpillRegisters(MachineFunction &MF, SmallVectorImpl< std::pair< Register, int > > &CalleeSavedRegs, SmallVectorImpl< std::pair< Register, int > > &ScratchRegs) const
void setBytesInStackArgArea(unsigned Bytes)
SIModeRegisterDefaults getMode() const
Register getSGPRForEXECCopy() const
void setFrameOffsetReg(Register Reg)
Register addWorkGroupIDX(bool HasArchitectedSGPRs)
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) const
Register addPrivateSegmentWaveByteOffset()
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const
bool hasWorkGroupInfo() const
bool mayUseAGPRs(const Function &F) const
bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const
Register addWorkGroupIDY(bool HasArchitectedSGPRs)
bool hasWorkItemIDY() const
unsigned getMinFlatWorkGroupSize() const
Register addLDSKernelId()
Register getVGPRForAGPRCopy() const
const GCNUserSGPRUsageInfo & getUserSGPRInfo() const
void setPrivateSegmentWaveByteOffset(Register Reg)
unsigned getMinWavesPerEU() const
Register getFrameOffsetReg() const
void setLongBranchReservedReg(Register Reg)
bool hasWorkGroupIDX() const
const AMDGPUFunctionArgInfo & getArgInfo() const
unsigned getBytesInStackArgArea() const
Register addKernargSegmentPtr(const SIRegisterInfo &TRI)
Register addDispatchID(const SIRegisterInfo &TRI)
void setHasSpilledVGPRs(bool Spill=true)
void setIfReturnsVoid(bool Value)
void limitOccupancy(unsigned Limit)
bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)
If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
void markPSInputAllocated(unsigned Index)
void setWorkItemIDX(ArgDescriptor Arg)
MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
bool checkFlag(Register Reg, uint8_t Flag) const
void markPSInputEnabled(unsigned Index)
void addToSpilledVGPRs(unsigned num)
MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const
uint32_t get32BitAddressHighBits() const
unsigned getMinAllowedOccupancy() const
void setHasSpilledSGPRs(bool Spill=true)
Register getWorkGroupIDSGPR(unsigned Dim) const
bool checkIndexInPrologEpilogSGPRSpills(int FI) const
unsigned getNumKernargPreloadedSGPRs() const
Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
bool hasWorkItemIDX() const
unsigned getNumUserSGPRs() const
Register addWorkGroupIDZ(bool HasArchitectedSGPRs)
const ReservedRegSet & getWWMReservedRegs() const
Register getImplicitBufferPtrUserSGPR() const
std::optional< int > getOptionalScavengeFI() const
Register addImplicitBufferPtr(const SIRegisterInfo &TRI)
AMDGPUFunctionArgInfo & getArgInfo()
const PrologEpilogSGPRSaveRestoreInfo & getPrologEpilogSGPRSaveRestoreInfo(Register Reg) const
void setHasNonSpillStackObjects(bool StackObject=true)
void setIsStackRealigned(bool Realigned=true)
unsigned getGITPtrHigh() const
void limitOccupancy(const MachineFunction &MF)
bool hasSpilledSGPRs() const
ArrayRef< Register > getSGPRSpillVGPRs() const
unsigned getPSInputAddr() const
SmallVectorImpl< MCRegister > * addPreloadedKernArg(const SIRegisterInfo &TRI, const TargetRegisterClass *RC, unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs)
void addToPrologEpilogSGPRSpills(Register Reg, PrologEpilogSGPRSaveRestoreInfo SI)
Register getScratchSGPRCopyDstReg(Register Reg) const
Register getPrivateSegmentWaveByteOffsetSystemSGPR() const
bool hasImplicitArgPtr() const
bool mayNeedAGPRs() const
Register addWorkGroupInfo()
bool hasWorkItemIDZ() const
unsigned getPSInputEnable() const
void setScratchRSrcReg(Register Reg)
void addToSpilledSGPRs(unsigned num)
const AMDGPUGWSResourcePseudoSourceValue * getGWSPSV(const AMDGPUTargetMachine &TM)
void reserveWWMRegister(Register Reg)
bool hasPrivateSegmentWaveByteOffset() const
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a range in source code.
bool insert(const value_type &X)
Insert a new element into the SetVector.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Helper struct shared between Function Specialization and SCCP Solver.
@ PreserveSign
The sign of a flushed-to-zero number is preserved in the sign of 0.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
SmallVector< MCPhysReg, 32 > Lanes
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
static void mapping(IO &YamlIO, SIArgumentInfo &AI)
static void mapping(IO &YamlIO, SIArgument &A)
static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI)
static void mapping(IO &YamlIO, SIMode &Mode)
std::optional< SIArgument > PrivateSegmentWaveByteOffset
std::optional< SIArgument > WorkGroupIDY
std::optional< SIArgument > FlatScratchInit
std::optional< SIArgument > DispatchPtr
std::optional< SIArgument > DispatchID
std::optional< SIArgument > WorkItemIDY
std::optional< SIArgument > WorkGroupIDX
std::optional< SIArgument > ImplicitArgPtr
std::optional< SIArgument > QueuePtr
std::optional< SIArgument > WorkGroupInfo
std::optional< SIArgument > LDSKernelId
std::optional< SIArgument > ImplicitBufferPtr
std::optional< SIArgument > WorkItemIDX
std::optional< SIArgument > KernargSegmentPtr
std::optional< SIArgument > WorkItemIDZ
std::optional< SIArgument > PrivateSegmentSize
std::optional< SIArgument > PrivateSegmentBuffer
std::optional< SIArgument > WorkGroupIDZ
std::optional< unsigned > Mask
SIArgument(const SIArgument &Other)
SIArgument & operator=(const SIArgument &Other)
static SIArgument createArgument(bool IsReg)
StringValue SGPRForEXECCopy
SmallVector< StringValue > WWMReservedRegs
uint32_t HighBitsOf32BitAddress
SIMachineFunctionInfo()=default
StringValue FrameOffsetReg
StringValue LongBranchReservedReg
uint64_t ExplicitKernArgSize
void mappingImpl(yaml::IO &YamlIO) override
~SIMachineFunctionInfo()=default
StringValue VGPRForAGPRCopy
std::optional< SIArgumentInfo > ArgInfo
std::optional< FrameIndex > ScavengeFI
unsigned BytesInStackArgArea
StringValue ScratchRSrcReg
StringValue StackPtrOffsetReg
SIMode(const SIModeRegisterDefaults &Mode)
bool FP64FP16OutputDenormals
bool operator==(const SIMode Other) const
bool FP64FP16InputDenormals
A wrapper around std::string which contains a source range that's being set during parsing.