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25 #define DEBUG_TYPE "post-RA-sched"
34 PrefVectorStoreNew =
nullptr;
41 if (!
MI || TII->isZeroCost(
MI->getOpcode()))
68 if (SU == UsesDotCur && DotCurPNum != (
int)PacketNum) {
69 LLVM_DEBUG(
dbgs() <<
"*** .cur Hazard in cycle " << PacketNum <<
", "
80 if (DotCurPNum != -1 && DotCurPNum != (
int)PacketNum) {
85 PrefVectorStoreNew =
nullptr;
101 if (PrefVectorStoreNew !=
nullptr && PrefVectorStoreNew != SU)
105 return UsesDotCur && ((SU == UsesDotCur) ^ (DotCurPNum == (
int)PacketNum));
116 if (MO.isReg() && MO.isDef() && !MO.isImplicit())
117 RegDefs.
insert(MO.getReg());
119 if (TII->isZeroCost(
MI->getOpcode()))
144 if (
S.isAssignedRegDep() &&
S.getLatency() == 0 &&
145 S.getSUnit()->NumPredsLeft == 1) {
146 UsesDotCur =
S.getSUnit();
147 DotCurPNum = PacketNum;
150 if (SU == UsesDotCur) {
151 UsesDotCur =
nullptr;
155 UsesLoad =
MI->mayLoad();
159 if (
S.isAssignedRegDep() &&
S.getLatency() == 0 &&
162 PrefVectorStoreNew =
S.getSUnit();
bool canReserveResources(const MCInstrDesc *MID)
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
HazardType getHazardType(SUnit *SU, int stalls) override
Return the hazard type of emitting this node.
SmallVector< SDep, 4 > Succs
All sunit successors.
bool ShouldPreferAnother(SUnit *) override
This callback may be invoked if getHazardType returns NoHazard.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool mayBeNewStore(const MachineInstr &MI) const
void EmitInstruction(SUnit *) override
This callback is invoked when an instruction is emitted to be scheduled, to advance the hazard state.
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
int getDotNewOp(const MachineInstr &MI) const
MachineOperand class - Representation of each machine instruction operand.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Register getReg() const
getReg - Returns the register number.
bool isHVXVec(const MachineInstr &MI) const
void Reset() override
This callback is invoked when a new block of instructions is about to be scheduled.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
bool isInstr() const
Returns true if this SUnit refers to a machine instruction as opposed to an SDNode.
Scheduling unit. This is a node in the scheduling DAG.
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
void AdvanceCycle() override
This callback is invoked whenever the next top-down instruction to be scheduled cannot issue in the c...
void reserveResources(const MCInstrDesc *MID)
bool mayBeCurLoad(const MachineInstr &MI) const