#include "Target/Hexagon/HexagonInstrInfo.h"
Detailed Description
Definition at line 40 of file HexagonInstrInfo.h.
Constructor & Destructor Documentation
◆ HexagonInstrInfo()
|
explicit |
Definition at line 120 of file HexagonInstrInfo.cpp.
Member Function Documentation
◆ addLatencyToSchedule()
| bool HexagonInstrInfo::addLatencyToSchedule | ( | const MachineInstr & | MI1, |
| const MachineInstr & | MI2 ) const |
Definition at line 3083 of file HexagonInstrInfo.cpp.
References isHVXVec(), and isVecUsableNextPacket().
◆ analyzeBranch()
|
override |
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.
This function can analyze one/two way branching only and should (mostly) be called by target independent side.
it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:
- If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null.
- If this block ends with only an unconditional branch, it sets TBB to be the destination block.
- If this block ends with a conditional branch and it falls through to a successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
- If this block ends with a conditional branch followed by an unconditional branch, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
Note that removeBranch and insertBranch must be implemented to support cases where this method returns success.
If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).
First entry is always the opcode of the branching instruction, except when the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a BB with only unconditional jump. Subsequent entries depend upon the opcode, e.g. Jump_c p will have Cond[0] = Jump_c Cond[1] = p HW-loop ENDLOOP: Cond[0] = ENDLOOP Cond[1] = MBB New value jump: Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 – specific opcode Cond[1] = R Cond[2] = Imm
Definition at line 435 of file HexagonInstrInfo.cpp.
References Cond, llvm::MachineOperand::CreateImm(), llvm::dbgs(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, isEndLoopN(), llvm::MachineOperand::isMBB(), isNewValueJump(), LLVM_DEBUG, MBB, PredOpcodeHasJMP_c(), llvm::printMBBReference(), and TBB.
Referenced by insertBranch().
◆ analyzeCompare()
|
override |
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 1898 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::isImm(), MI, and Opc.
◆ analyzeLoopForPipelining()
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override |
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.
Definition at line 809 of file HexagonInstrInfo.cpp.
References llvm::MachineBasicBlock::end(), findLoopInstr(), llvm::MachineBasicBlock::getFirstTerminator(), I, and isEndLoopN().
◆ areMemAccessesTriviallyDisjoint()
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override |
Definition at line 2004 of file HexagonInstrInfo.cpp.
References getBaseAndOffsetPosition(), llvm::MachineOperand::getImm(), getMemAccessSize(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineOperand::isImm(), isMemOp(), isPostIncrement(), and llvm::MachineInstr::mayLoad().
◆ canExecuteInBundle()
| bool HexagonInstrInfo::canExecuteInBundle | ( | const MachineInstr & | First, |
| const MachineInstr & | Second ) const |
Can these instructions execute at the same time in a bundle.
Definition at line 3105 of file HexagonInstrInfo.cpp.
References DisableNVSchedule, llvm::First, llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), mayBeNewStore(), and llvm::MachineInstr::mayStore().
Referenced by llvm::HexagonSubtarget::adjustSchedDependency().
◆ changeAddrMode_abs_io() [1/2]
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inline |
Definition at line 519 of file HexagonInstrInfo.h.
References changeAddrMode_abs_io(), and MI.
◆ changeAddrMode_abs_io() [2/2]
| short HexagonInstrInfo::changeAddrMode_abs_io | ( | short | Opc | ) | const |
Definition at line 4771 of file HexagonInstrInfo.cpp.
References Opc.
Referenced by changeAddrMode_abs_io().
◆ changeAddrMode_io_abs() [1/2]
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inline |
Definition at line 522 of file HexagonInstrInfo.h.
References changeAddrMode_io_abs(), and MI.
◆ changeAddrMode_io_abs() [2/2]
| short HexagonInstrInfo::changeAddrMode_io_abs | ( | short | Opc | ) | const |
Definition at line 4775 of file HexagonInstrInfo.cpp.
References Opc.
Referenced by changeAddrMode_io_abs().
◆ changeAddrMode_io_pi()
| short HexagonInstrInfo::changeAddrMode_io_pi | ( | short | Opc | ) | const |
Definition at line 4779 of file HexagonInstrInfo.cpp.
References Opc.
◆ changeAddrMode_io_rr() [1/2]
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inline |
Definition at line 525 of file HexagonInstrInfo.h.
References changeAddrMode_io_rr(), and MI.
◆ changeAddrMode_io_rr() [2/2]
| short HexagonInstrInfo::changeAddrMode_io_rr | ( | short | Opc | ) | const |
Definition at line 4783 of file HexagonInstrInfo.cpp.
References Opc.
Referenced by changeAddrMode_io_rr().
◆ changeAddrMode_pi_io()
| short HexagonInstrInfo::changeAddrMode_pi_io | ( | short | Opc | ) | const |
Definition at line 4787 of file HexagonInstrInfo.cpp.
References Opc.
◆ changeAddrMode_rr_io() [1/2]
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inline |
Definition at line 528 of file HexagonInstrInfo.h.
References changeAddrMode_rr_io(), and MI.
◆ changeAddrMode_rr_io() [2/2]
| short HexagonInstrInfo::changeAddrMode_rr_io | ( | short | Opc | ) | const |
Definition at line 4791 of file HexagonInstrInfo.cpp.
References Opc.
Referenced by changeAddrMode_rr_io().
◆ changeAddrMode_rr_ur() [1/2]
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inline |
Definition at line 531 of file HexagonInstrInfo.h.
References changeAddrMode_rr_ur(), and MI.
◆ changeAddrMode_rr_ur() [2/2]
| short HexagonInstrInfo::changeAddrMode_rr_ur | ( | short | Opc | ) | const |
Definition at line 4795 of file HexagonInstrInfo.cpp.
References Opc.
Referenced by changeAddrMode_rr_ur().
◆ changeAddrMode_ur_rr() [1/2]
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inline |
Definition at line 534 of file HexagonInstrInfo.h.
References changeAddrMode_ur_rr(), and MI.
◆ changeAddrMode_ur_rr() [2/2]
| short HexagonInstrInfo::changeAddrMode_ur_rr | ( | short | Opc | ) | const |
Definition at line 4799 of file HexagonInstrInfo.cpp.
References Opc.
Referenced by changeAddrMode_ur_rr().
◆ changeDuplexOpcode()
| void HexagonInstrInfo::changeDuplexOpcode | ( | MachineBasicBlock::instr_iterator | MII, |
| bool | ToBigInstrs ) const |
Definition at line 4471 of file HexagonInstrInfo.cpp.
References llvm::get(), getDuplexCandidateGroup(), and getDuplexOpcode().
Referenced by translateInstrsForDup(), and translateInstrsForDup().
◆ ClobbersPredicate()
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override |
If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference.
Definition at line 1748 of file HexagonInstrInfo.cpp.
References MI.
◆ copyPhysReg()
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override |
Emit instructions to copy a pair of physical registers.
This function should support copies within any legal register class as well as any cross-class copies created during instruction selection.
The source and destination registers may overlap, which may require a careful implementation when multiple copy instructions are required for large registers. See for example the ARM target.
Definition at line 860 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), llvm::LivePhysRegs::contains(), llvm::dbgs(), DL, llvm::get(), llvm::getKillRegState(), getLiveInRegsAt(), llvm::getUndefRegState(), I, llvm_unreachable, MBB, llvm::printMBBReference(), and llvm::printReg().
Referenced by expandPostRAPseudo().
◆ CreateTargetPostRAHazardRecognizer()
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override |
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation.
Definition at line 1887 of file HexagonInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer(), II, and UseDFAHazardRec.
◆ CreateTargetScheduleState()
|
override |
Create machine specific model for scheduling.
Definition at line 1994 of file HexagonInstrInfo.cpp.
References llvm::TargetSubtargetInfo::getInstrItineraryData(), and II.
◆ createVR()
| Register HexagonInstrInfo::createVR | ( | MachineFunction * | MF, |
| MVT | VT ) const |
HexagonInstrInfo specifics.
Definition at line 2119 of file HexagonInstrInfo.cpp.
References llvm::MachineFunction::getRegInfo(), llvm_unreachable, and MRI.
◆ decomposeMachineOperandsTargetFlags()
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override |
Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied.
Definition at line 2085 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::MO_Bitmasks.
◆ doesNotReturn()
| bool HexagonInstrInfo::doesNotReturn | ( | const MachineInstr & | CallMI | ) | const |
Definition at line 3130 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and Opc.
Referenced by isSchedulingBoundary().
◆ expandPostRAPseudo()
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override |
This function is called for all pseudo instructions that remain after register allocation.
expandPostRAPseudo - This function is called for all pseudo instructions that remain after register allocation.
Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed.
Definition at line 1057 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::all_of(), assert(), llvm::LivePhysRegs::available(), llvm::BuildMI(), llvm::cast(), llvm::MachineInstrBuilder::cloneMemRefs(), copyPhysReg(), llvm::MachineFunction::createExternalSymbolName(), DL, llvm::dyn_cast(), llvm::get(), llvm::HexagonRegisterInfo::getFrameRegister(), llvm::MachineOperand::getImm(), llvm::GlobalVariable::getInitializer(), llvm::getKillRegState(), getLiveInRegsAt(), getLiveOutRegsAt(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineOperand::getReg(), llvm::SrcOp::getReg(), llvm::MachineFunction::getRegInfo(), llvm::getRegState(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getTarget(), llvm::getUndefRegState(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::RegState::InternalRead, isConstant(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), llvm::RegState::Kill, mayAlias(), MBB, MBBI, MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOVolatile, MRI, llvm::Offset, Opc, T, and llvm::RegState::Undef.
◆ expandVGatherPseudo()
| MachineBasicBlock::instr_iterator HexagonInstrInfo::expandVGatherPseudo | ( | MachineInstr & | MI | ) | const |
Definition at line 1551 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::First, llvm::get(), MBB, MI, and Opc.
◆ findLoopInstr()
| MachineInstr * HexagonInstrInfo::findLoopInstr | ( | MachineBasicBlock * | BB, |
| unsigned | EndLoopOp, | ||
| MachineBasicBlock * | TargetBB, | ||
| SmallPtrSet< MachineBasicBlock *, 8 > & | Visited ) const |
Find the hardware loop instruction used to set-up the specified loop.
On Hexagon, we have two instructions used to set-up the hardware loop (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions to indicate the end of a loop.
Definition at line 198 of file HexagonInstrInfo.cpp.
References findLoopInstr(), I, llvm::SmallPtrSetImpl< PtrType >::insert(), Opc, PB(), llvm::MachineBasicBlock::predecessors(), and llvm::reverse().
Referenced by analyzeLoopForPipelining(), findLoopInstr(), and insertBranch().
◆ genAllInsnTimingClasses()
| void HexagonInstrInfo::genAllInsnTimingClasses | ( | MachineFunction & | MF | ) | const |
Definition at line 4696 of file HexagonInstrInfo.cpp.
References A(), B(), llvm::MachineFunction::begin(), llvm::BuildMI(), llvm::dbgs(), DL, llvm::MachineInstr::eraseFromParent(), llvm::get(), llvm::MachineInstr::getDesc(), getName(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::getSchedClass(), I, and LLVM_DEBUG.
◆ getAddrMode()
| unsigned HexagonInstrInfo::getAddrMode | ( | const MachineInstr & | MI | ) | const |
Definition at line 3301 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AddrModeMask, llvm::HexagonII::AddrModePos, F, and MI.
Referenced by llvm::HexagonSubtarget::BankConflictMutation::apply(), getBaseAndOffset(), getNonExtOpcode(), hasNonExtEquivalent(), isAbsoluteSet(), isBaseImmOffset(), and isPostIncrement().
◆ getBaseAndOffset()
| MachineOperand * HexagonInstrInfo::getBaseAndOffset | ( | const MachineInstr & | MI, |
| int64_t & | Offset, | ||
| LocationSize & | AccessSize ) const |
Definition at line 3311 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), getBaseAndOffsetPosition(), getMemAccessSize(), llvm::MachineOperand::getSubReg(), isMemOp(), isPostIncrement(), MI, llvm::Offset, and llvm::LocationSize::precise().
Referenced by llvm::HexagonSubtarget::BankConflictMutation::apply(), and getMemOperandsWithOffsetWidth().
◆ getBaseAndOffsetPosition()
|
override |
For instructions with a base and offset, return the position of the base register and offset operands.
Return the position of the base and offset operands for this instruction.
Definition at line 3343 of file HexagonInstrInfo.cpp.
References isAddrModeWithOffset(), isMemOp(), isPostIncrement(), isPredicated(), and MI.
Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), and getIncrementValue().
◆ getBranchingInstrs()
| SmallVector< MachineInstr *, 2 > HexagonInstrInfo::getBranchingInstrs | ( | MachineBasicBlock & | MBB | ) | const |
Definition at line 3380 of file HexagonInstrInfo.cpp.
References I, MBB, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
◆ getBundleNoShuf()
| bool HexagonInstrInfo::getBundleNoShuf | ( | const MachineInstr & | MIB | ) | const |
Definition at line 4751 of file HexagonInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::isBundle(), and llvm::MachineOperand::isImm().
◆ getCExtOpNum()
| unsigned HexagonInstrInfo::getCExtOpNum | ( | const MachineInstr & | MI | ) | const |
Definition at line 3438 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendableOpMask, llvm::HexagonII::ExtendableOpPos, F, and MI.
Referenced by immediateExtend(), and isConstExtended().
◆ getCompoundCandidateGroup()
| HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup | ( | const MachineInstr & | MI | ) | const |
Definition at line 3445 of file HexagonInstrInfo.cpp.
References contains(), llvm::HexagonII::HCG_A, llvm::HexagonII::HCG_B, llvm::HexagonII::HCG_C, llvm::HexagonII::HCG_None, isIntRegForSubInst(), llvm::isUInt(), and MI.
Referenced by getCompoundOpcode().
◆ getCompoundOpcode()
| unsigned HexagonInstrInfo::getCompoundOpcode | ( | const MachineInstr & | GA, |
| const MachineInstr & | GB ) const |
Definition at line 3533 of file HexagonInstrInfo.cpp.
References assert(), getCompoundCandidateGroup(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::HexagonII::HCG_A, llvm::HexagonII::HCG_B, llvm::MachineOperand::isImm(), llvm::isUInt(), and llvm::MachineInstr::readsRegister().
◆ getCondOpcode()
| int HexagonInstrInfo::getCondOpcode | ( | int | Opc, |
| bool | sense ) const |
Definition at line 3617 of file HexagonInstrInfo.cpp.
References llvm_unreachable, and Opc.
Referenced by PredicateInstruction().
◆ getDotCurOp()
| int HexagonInstrInfo::getDotCurOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 3629 of file HexagonInstrInfo.cpp.
References llvm_unreachable, and MI.
◆ getDotNewOp()
| int HexagonInstrInfo::getDotNewOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 3750 of file HexagonInstrInfo.cpp.
References MI, and llvm::report_fatal_error().
◆ getDotNewPredJumpOp()
| int HexagonInstrInfo::getDotNewPredJumpOp | ( | const MachineInstr & | MI, |
| const MachineBranchProbabilityInfo * | MBPI ) const |
Definition at line 3791 of file HexagonInstrInfo.cpp.
References assert(), B(), llvm::MachineBranchProbabilityInfo::getEdgeProbability(), llvm::MachineOperand::getMBB(), I, llvm::MachineOperand::isMBB(), llvm_unreachable, and MI.
Referenced by getDotNewPredOp().
◆ getDotNewPredOp()
| int HexagonInstrInfo::getDotNewPredOp | ( | const MachineInstr & | MI, |
| const MachineBranchProbabilityInfo * | MBPI ) const |
Definition at line 3877 of file HexagonInstrInfo.cpp.
References getDotNewPredJumpOp(), and MI.
◆ getDotOldOp()
| int HexagonInstrInfo::getDotOldOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 3892 of file HexagonInstrInfo.cpp.
References assert(), isNewValueStore(), isPredicated(), isPredicatedNew(), and MI.
◆ getDuplexCandidateGroup()
| HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup | ( | const MachineInstr & | MI | ) | const |
Definition at line 3943 of file HexagonInstrInfo.cpp.
References contains(), llvm::HexagonRegisterInfo::getStackRegister(), llvm::HexagonII::HSIG_A, llvm::HexagonII::HSIG_L1, llvm::HexagonII::HSIG_L2, llvm::HexagonII::HSIG_None, llvm::HexagonII::HSIG_S1, llvm::HexagonII::HSIG_S2, isDblRegForSubInst(), llvm::isInt(), isIntRegForSubInst(), llvm::isShiftedInt(), llvm::isShiftedUInt(), llvm::isUInt(), and MI.
Referenced by changeDuplexOpcode(), and isDuplexPair().
◆ getDuplexOpcode()
| int HexagonInstrInfo::getDuplexOpcode | ( | const MachineInstr & | MI, |
| bool | ForBigCore = true ) const |
Definition at line 3560 of file HexagonInstrInfo.cpp.
References MI.
Referenced by changeDuplexOpcode().
◆ getEquivalentHWInstr()
| short HexagonInstrInfo::getEquivalentHWInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 4323 of file HexagonInstrInfo.cpp.
References MI.
◆ getIncrementValue()
|
override |
If the instruction is an increment of a constant value, return the amount.
Definition at line 2062 of file HexagonInstrInfo.cpp.
References getBaseAndOffsetPosition(), isPostIncrement(), and MI.
◆ getInlineAsmLength()
|
override |
Measure the specified inline asm to determine an approximation of its length.
Comments (which run till the next SeparatorString or newline) do not count as an instruction. Any other non-whitespace text is considered an instruction, with multiple instructions separated by SeparatorString or newlines. Variable-length instructions are not handled here; this function may be overloaded in the target code to do that. Hexagon counts the number of ##'s and adjust for that many constant exenders.
Definition at line 1859 of file HexagonInstrInfo.cpp.
References llvm::StringRef::count(), llvm::StringRef::data(), llvm::MCAsmInfo::getCommentString(), llvm::MCAsmInfo::getMaxInstLength(), llvm::MCAsmInfo::getSeparatorString(), llvm::isSpace(), llvm::Length, and llvm::StringRef::size().
Referenced by getSize().
◆ getInstrLatency()
|
override |
Compute the instruction latency of a given instruction.
If the instruction has higher cost when predicated, it's returned via PredCost.
Definition at line 1988 of file HexagonInstrInfo.cpp.
References getInstrTimingClassLatency(), and MI.
Referenced by getInstrTimingClassLatency().
◆ getInstrTimingClassLatency()
| unsigned HexagonInstrInfo::getInstrTimingClassLatency | ( | const InstrItineraryData * | ItinData, |
| const MachineInstr & | MI ) const |
Definition at line 4327 of file HexagonInstrInfo.cpp.
References getInstrLatency(), llvm::InstrItineraryData::getStageLatency(), and MI.
Referenced by getInstrLatency().
◆ getInvertedPredicatedOpcode()
Definition at line 4400 of file HexagonInstrInfo.cpp.
References isPredicatedTrue(), llvm_unreachable, and Opc.
Referenced by getInvertedPredSense(), invertAndChangeJumpTarget(), reverseBranchCondition(), and reversePredSense().
◆ getInvertedPredSense()
| bool HexagonInstrInfo::getInvertedPredSense | ( | SmallVectorImpl< MachineOperand > & | Cond | ) | const |
Definition at line 4391 of file HexagonInstrInfo.cpp.
References Cond, llvm::getImm(), getInvertedPredicatedOpcode(), and Opc.
◆ getMaxValue()
| int HexagonInstrInfo::getMaxValue | ( | const MachineInstr & | MI | ) | const |
Definition at line 4411 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtentBitsMask, llvm::HexagonII::ExtentBitsPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F, isSigned(), and MI.
Referenced by isConstExtended().
◆ getMemAccessSize()
| unsigned HexagonInstrInfo::getMemAccessSize | ( | const MachineInstr & | MI | ) | const |
Definition at line 4508 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::DoubleWordAccess, F, llvm::HexagonII::HVXVectorAccess, llvm_unreachable, MI, and Size.
Referenced by areMemAccessesTriviallyDisjoint(), and getBaseAndOffset().
◆ getMemOperandsWithOffsetWidth()
|
override |
Get the base register and byte offset of a load/store instr.
Definition at line 3092 of file HexagonInstrInfo.cpp.
References getBaseAndOffset(), llvm::MachineOperand::isReg(), llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TRI.
◆ getMinValue()
| int HexagonInstrInfo::getMinValue | ( | const MachineInstr & | MI | ) | const |
Definition at line 4531 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtentBitsMask, llvm::HexagonII::ExtentBitsPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F, isSigned(), and MI.
Referenced by isConstExtended().
◆ getNonDotCurOp()
| int HexagonInstrInfo::getNonDotCurOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 3649 of file HexagonInstrInfo.cpp.
References llvm_unreachable, and MI.
◆ getNonExtOpcode()
| short HexagonInstrInfo::getNonExtOpcode | ( | const MachineInstr & | MI | ) | const |
Definition at line 4545 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::Absolute, llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), and MI.
◆ getNop()
|
override |
Definition at line 4803 of file HexagonInstrInfo.cpp.
References llvm::MCInstBuilder::addImm(), and llvm::MCInstBuilder::addInst().
◆ getOperandLatency()
|
override |
getOperandLatency - Compute and return the use operand latency of a given pair of def and use.
In most cases, the static scheduling itinerary was enough to determine the operand latency. But it may not be possible for instructions with variable number of defs / uses.
This is a raw interface to the itinerary that may be directly overridden by a target. Use computeOperandLatency to get the best estimate of latency.
Definition at line 4347 of file HexagonInstrInfo.cpp.
References DefMI, llvm::TargetInstrInfo::getOperandLatency(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImplicit(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), llvm::Latency, and UseMI.
◆ getPredReg()
| bool HexagonInstrInfo::getPredReg | ( | ArrayRef< MachineOperand > | Cond, |
| Register & | PredReg, | ||
| unsigned & | PredRegPos, | ||
| unsigned & | PredRegFlags ) const |
Definition at line 4569 of file HexagonInstrInfo.cpp.
References assert(), Cond, llvm::dbgs(), llvm::getImm(), llvm::RegState::Implicit, isNewValueJump(), isUndef(), LLVM_DEBUG, and llvm::RegState::Undef.
Referenced by PredicateInstruction().
◆ getPseudoInstrPair()
| short HexagonInstrInfo::getPseudoInstrPair | ( | const MachineInstr & | MI | ) | const |
Definition at line 4589 of file HexagonInstrInfo.cpp.
References MI.
◆ getRegForm()
| short HexagonInstrInfo::getRegForm | ( | const MachineInstr & | MI | ) | const |
Definition at line 4593 of file HexagonInstrInfo.cpp.
References MI.
◆ getRegisterInfo()
|
inline |
Definition at line 53 of file HexagonInstrInfo.h.
Referenced by llvm::HexagonDAGToDAGISel::runOnMachineFunction().
◆ getSerializableBitmaskMachineOperandTargetFlags()
|
override |
Return an array that contains the bitmask target flag values and their names.
MIR Serialization is able to serialize only the target flags that are defined by this method.
Definition at line 2110 of file HexagonInstrInfo.cpp.
References llvm::ArrayRef().
◆ getSerializableDirectMachineOperandTargetFlags()
|
override |
Return an array that contains the direct target flag values and their names.
MIR Serialization is able to serialize only the target flags that are defined by this method.
Definition at line 2091 of file HexagonInstrInfo.cpp.
References llvm::ArrayRef().
◆ getSize()
| unsigned HexagonInstrInfo::getSize | ( | const MachineInstr & | MI | ) | const |
Definition at line 4601 of file HexagonInstrInfo.cpp.
References assert(), BranchRelaxAsmLarge, getInlineAsmLength(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineFunction::getTarget(), HEXAGON_INSTR_SIZE, isConstExtended(), isExtended(), isReg(), MBB, MI, and Size.
◆ getType()
| uint64_t HexagonInstrInfo::getType | ( | const MachineInstr & | MI | ) | const |
Definition at line 4635 of file HexagonInstrInfo.cpp.
References F, MI, llvm::HexagonII::TypeMask, and llvm::HexagonII::TypePos.
Referenced by cannotCoexistAsymm(), isCompoundBranchInstr(), isHVXVec(), and isLateSourceInstr().
◆ getUnits()
| InstrStage::FuncUnits HexagonInstrInfo::getUnits | ( | const MachineInstr & | MI | ) | const |
Definition at line 4640 of file HexagonInstrInfo.cpp.
References llvm::InstrStage::getUnits(), II, and MI.
Referenced by isPureSlot0().
◆ hasEHLabel()
| bool HexagonInstrInfo::hasEHLabel | ( | const MachineBasicBlock * | B | ) | const |
Definition at line 3135 of file HexagonInstrInfo.cpp.
◆ hasLoadFromStackSlot()
|
override |
Check if the instruction or the bundle of instructions has load from stack slots.
This function checks if the instruction or bundle of instructions has load from stack slot and returns frameindex and machine memory operand of that instruction if true.
Return the frameindex and machine memory operand if true.
Definition at line 387 of file HexagonInstrInfo.cpp.
References Accesses, llvm::TargetInstrInfo::hasLoadFromStackSlot(), MBB, and MI.
◆ hasNonExtEquivalent()
| bool HexagonInstrInfo::hasNonExtEquivalent | ( | const MachineInstr & | MI | ) | const |
Definition at line 3144 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::Absolute, llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), and MI.
◆ hasPseudoInstrPair()
| bool HexagonInstrInfo::hasPseudoInstrPair | ( | const MachineInstr & | MI | ) | const |
Definition at line 3179 of file HexagonInstrInfo.cpp.
References MI.
◆ hasStoreToStackSlot()
|
override |
Check if the instruction or the bundle of instructions has store to stack slots.
This function checks if the instruction or bundle of instructions has store to stack slot and returns frameindex and machine memory operand of that instruction if true.
Return the frameindex and machine memory operand if true.
Definition at line 405 of file HexagonInstrInfo.cpp.
References Accesses, llvm::TargetInstrInfo::hasStoreToStackSlot(), MBB, and MI.
◆ hasUncondBranch()
| bool HexagonInstrInfo::hasUncondBranch | ( | const MachineBasicBlock * | B | ) | const |
Definition at line 3184 of file HexagonInstrInfo.cpp.
◆ immediateExtend()
| void HexagonInstrInfo::immediateExtend | ( | MachineInstr & | MI | ) | const |
immediateExtend - Changes the instruction in place to one using an immediate extender.
Definition at line 4662 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::addTargetFlag(), assert(), getCExtOpNum(), llvm::HexagonII::HMOTF_ConstExtended, isConstExtended(), isExtendable(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isMBB(), and MI.
◆ insertBranch()
|
override |
Insert branch code into the end of the specified MachineBasicBlock.
The operands to this method are the same as those returned by analyzeBranch. This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions inserted.
It is also invoked by tail merging to add unconditional branches in cases where analyzeBranch doesn't apply because there was no original branch to analyze. At least this much must be implemented, else tail merging needs to be disabled.
Definition at line 628 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), analyzeBranch(), assert(), llvm::BuildMI(), Cond, llvm::dbgs(), DL, findLoopInstr(), llvm::get(), llvm::getImm(), getReg(), llvm::MachineOperand::getReg(), llvm::getUndefRegState(), insertBranch(), isEndLoopN(), isNewValueJump(), isPredicated(), isReg(), isUndef(), llvm::MachineOperand::isUndef(), LLVM_DEBUG, llvm_unreachable, MBB, llvm::printMBBReference(), removeBranch(), reverseBranchCondition(), TBB, and validateBranchCond().
Referenced by insertBranch().
◆ insertNoop()
|
override |
Insert a noop into the instruction stream at the specified point.
Definition at line 1667 of file HexagonInstrInfo.cpp.
References llvm::BuildMI(), DL, llvm::get(), MBB, and MI.
◆ invertAndChangeJumpTarget()
| bool HexagonInstrInfo::invertAndChangeJumpTarget | ( | MachineInstr & | MI, |
| MachineBasicBlock * | NewTarget ) const |
Definition at line 4675 of file HexagonInstrInfo.cpp.
References assert(), llvm::dbgs(), EnableBranchPrediction, llvm::get(), getInvertedPredicatedOpcode(), isPredicatedNew(), LLVM_DEBUG, MI, llvm::printMBBReference(), and reversePrediction().
◆ isAbsoluteSet()
| bool HexagonInstrInfo::isAbsoluteSet | ( | const MachineInstr & | MI | ) | const |
Definition at line 2136 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AbsoluteSet, getAddrMode(), and MI.
◆ isAccumulator()
| bool HexagonInstrInfo::isAccumulator | ( | const MachineInstr & | MI | ) | const |
Definition at line 2140 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AccumulatorMask, llvm::HexagonII::AccumulatorPos, F, and MI.
Referenced by isVecAcc().
◆ isAddrModeWithOffset()
| bool HexagonInstrInfo::isAddrModeWithOffset | ( | const MachineInstr & | MI | ) | const |
Definition at line 4425 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AddrModeMask, llvm::HexagonII::AddrModePos, llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, llvm::HexagonII::BaseRegOffset, F, and MI.
Referenced by getBaseAndOffsetPosition().
◆ isAsCheapAsAMove()
|
override |
Definition at line 155 of file HexagonInstrInfo.cpp.
References llvm::isInt(), and MI.
◆ isBaseImmOffset()
| bool HexagonInstrInfo::isBaseImmOffset | ( | const MachineInstr & | MI | ) | const |
Definition at line 2145 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::BaseImmOffset, getAddrMode(), and MI.
◆ isComplex()
| bool HexagonInstrInfo::isComplex | ( | const MachineInstr & | MI | ) | const |
Definition at line 2149 of file HexagonInstrInfo.cpp.
References isMemOp(), isTC1(), isTC2Early(), and MI.
◆ isCompoundBranchInstr()
| bool HexagonInstrInfo::isCompoundBranchInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 2158 of file HexagonInstrInfo.cpp.
References getType(), MI, and llvm::HexagonII::TypeCJ.
◆ isConstExtended()
| bool HexagonInstrInfo::isConstExtended | ( | const MachineInstr & | MI | ) | const |
Definition at line 2164 of file HexagonInstrInfo.cpp.
References assert(), llvm::HexagonII::ExtendableMask, llvm::HexagonII::ExtendablePos, llvm::HexagonII::ExtendedMask, llvm::HexagonII::ExtendedPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F, getCExtOpNum(), llvm::MachineOperand::getImm(), getMaxValue(), getMinValue(), llvm::MachineOperand::getTargetFlags(), llvm::HexagonII::HMOTF_ConstExtended, llvm::MachineOperand::isBlockAddress(), llvm::MachineOperand::isCPI(), isExtendable(), isExtended(), llvm::MachineOperand::isFPImm(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isJTI(), llvm::MachineOperand::isMBB(), llvm::MachineOperand::isSymbol(), and MI.
Referenced by getSize(), and immediateExtend().
◆ isDeallocRet()
| bool HexagonInstrInfo::isDeallocRet | ( | const MachineInstr & | MI | ) | const |
Definition at line 2213 of file HexagonInstrInfo.cpp.
References MI.
◆ isDependent()
| bool HexagonInstrInfo::isDependent | ( | const MachineInstr & | ProdMI, |
| const MachineInstr & | ConsMI ) const |
Definition at line 2228 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), llvm::is_contained(), and parseOperands().
Referenced by producesStall().
◆ isDotCurInst()
| bool HexagonInstrInfo::isDotCurInst | ( | const MachineInstr & | MI | ) | const |
Definition at line 2259 of file HexagonInstrInfo.cpp.
References MI.
◆ isDotNewInst()
| bool HexagonInstrInfo::isDotNewInst | ( | const MachineInstr & | MI | ) | const |
Definition at line 2270 of file HexagonInstrInfo.cpp.
References isNewValueInst(), isPredicated(), isPredicatedNew(), and MI.
◆ isDuplexPair()
| bool HexagonInstrInfo::isDuplexPair | ( | const MachineInstr & | MIa, |
| const MachineInstr & | MIb ) const |
Symmetrical. See if these two instructions are fit for duplex pair.
Definition at line 2278 of file HexagonInstrInfo.cpp.
References getDuplexCandidateGroup(), and isDuplexPairMatch().
◆ isEndLoopN()
Definition at line 2285 of file HexagonInstrInfo.cpp.
Referenced by analyzeBranch(), analyzeLoopForPipelining(), insertBranch(), PredicateInstruction(), and reverseBranchCondition().
◆ isExpr()
Definition at line 2290 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::MO_BlockAddress, llvm::MachineOperand::MO_ConstantPoolIndex, llvm::MachineOperand::MO_ExternalSymbol, llvm::MachineOperand::MO_GlobalAddress, llvm::MachineOperand::MO_JumpTableIndex, and llvm::MachineOperand::MO_MachineBasicBlock.
◆ isExtendable()
| bool HexagonInstrInfo::isExtendable | ( | const MachineInstr & | MI | ) | const |
Definition at line 2304 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendableMask, llvm::HexagonII::ExtendablePos, F, MI, and llvm::MCInstrDesc::TSFlags.
Referenced by immediateExtend(), and isConstExtended().
◆ isExtended()
| bool HexagonInstrInfo::isExtended | ( | const MachineInstr & | MI | ) | const |
Definition at line 2326 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendedMask, llvm::HexagonII::ExtendedPos, F, llvm::HexagonII::HMOTF_ConstExtended, and MI.
Referenced by getSize(), and isConstExtended().
◆ isFloat()
| bool HexagonInstrInfo::isFloat | ( | const MachineInstr & | MI | ) | const |
Definition at line 2339 of file HexagonInstrInfo.cpp.
References F, llvm::HexagonII::FPMask, llvm::HexagonII::FPPos, llvm::get(), and MI.
Referenced by shouldSink().
◆ isHVXMemWithAIndirect()
| bool HexagonInstrInfo::isHVXMemWithAIndirect | ( | const MachineInstr & | I, |
| const MachineInstr & | J ) const |
Definition at line 2346 of file HexagonInstrInfo.cpp.
References I, isHVXVec(), llvm::MachineInstr::isIndirectBranch(), isIndirectCall(), and isIndirectL4Return().
Referenced by cannotCoexistAsymm().
◆ isHVXVec()
| bool HexagonInstrInfo::isHVXVec | ( | const MachineInstr & | MI | ) | const |
Definition at line 2723 of file HexagonInstrInfo.cpp.
References getType(), MI, llvm::HexagonII::TypeCVI_FIRST, and llvm::HexagonII::TypeCVI_LAST.
Referenced by addLatencyToSchedule(), isHVXMemWithAIndirect(), isVecAcc(), producesStall(), and producesStall().
◆ isIndirectCall()
| bool HexagonInstrInfo::isIndirectCall | ( | const MachineInstr & | MI | ) | const |
Definition at line 2355 of file HexagonInstrInfo.cpp.
References MI.
Referenced by isHVXMemWithAIndirect().
◆ isIndirectL4Return()
| bool HexagonInstrInfo::isIndirectL4Return | ( | const MachineInstr & | MI | ) | const |
Definition at line 2366 of file HexagonInstrInfo.cpp.
References MI.
Referenced by isHVXMemWithAIndirect().
◆ isJumpR()
| bool HexagonInstrInfo::isJumpR | ( | const MachineInstr & | MI | ) | const |
Definition at line 2380 of file HexagonInstrInfo.cpp.
References MI.
◆ isJumpWithinBranchRange()
| bool HexagonInstrInfo::isJumpWithinBranchRange | ( | const MachineInstr & | MI, |
| unsigned | offset ) const |
Definition at line 2398 of file HexagonInstrInfo.cpp.
References llvm::isInt(), isNewValueJump(), and MI.
◆ isLateSourceInstr()
| bool HexagonInstrInfo::isLateSourceInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 2440 of file HexagonInstrInfo.cpp.
References getType(), MI, and llvm::HexagonII::TypeCVI_VX_LATE.
Referenced by isVecUsableNextPacket().
◆ isLoadFromStackSlot()
|
override |
TargetInstrInfo overrides.
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.
If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
Definition at line 289 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and MI.
◆ isLoopN()
| bool HexagonInstrInfo::isLoopN | ( | const MachineInstr & | MI | ) | const |
Definition at line 2446 of file HexagonInstrInfo.cpp.
References MI.
◆ isMemOp()
| bool HexagonInstrInfo::isMemOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 2458 of file HexagonInstrInfo.cpp.
References MI.
Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), getBaseAndOffsetPosition(), and isComplex().
◆ isNewValue() [1/2]
| bool HexagonInstrInfo::isNewValue | ( | const MachineInstr & | MI | ) | const |
Definition at line 2490 of file HexagonInstrInfo.cpp.
References F, MI, llvm::HexagonII::NewValueMask, and llvm::HexagonII::NewValuePos.
Referenced by isNewValueJump(), isNewValueJump(), and isPredictedTaken().
◆ isNewValue() [2/2]
Definition at line 2495 of file HexagonInstrInfo.cpp.
References F, llvm::get(), llvm::HexagonII::NewValueMask, and llvm::HexagonII::NewValuePos.
◆ isNewValueInst()
| bool HexagonInstrInfo::isNewValueInst | ( | const MachineInstr & | MI | ) | const |
Definition at line 2500 of file HexagonInstrInfo.cpp.
References isNewValueJump(), isNewValueStore(), and MI.
Referenced by isDotNewInst().
◆ isNewValueJump() [1/2]
| bool HexagonInstrInfo::isNewValueJump | ( | const MachineInstr & | MI | ) | const |
Definition at line 2504 of file HexagonInstrInfo.cpp.
References isNewValue(), and MI.
Referenced by analyzeBranch(), getPredReg(), insertBranch(), isJumpWithinBranchRange(), isNewValueInst(), and PredicateInstruction().
◆ isNewValueJump() [2/2]
Definition at line 2508 of file HexagonInstrInfo.cpp.
References llvm::get(), isNewValue(), and isPredicated().
◆ isNewValueStore() [1/2]
| bool HexagonInstrInfo::isNewValueStore | ( | const MachineInstr & | MI | ) | const |
Definition at line 2512 of file HexagonInstrInfo.cpp.
References F, MI, llvm::HexagonII::NVStoreMask, and llvm::HexagonII::NVStorePos.
Referenced by cannotCoexistAsymm(), getDotOldOp(), and isNewValueInst().
◆ isNewValueStore() [2/2]
Definition at line 2517 of file HexagonInstrInfo.cpp.
References F, llvm::get(), llvm::HexagonII::NVStoreMask, and llvm::HexagonII::NVStorePos.
◆ isOperandExtended()
| bool HexagonInstrInfo::isOperandExtended | ( | const MachineInstr & | MI, |
| unsigned | OperandNum ) const |
Definition at line 2523 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendableOpMask, llvm::HexagonII::ExtendableOpPos, F, and MI.
◆ isPostIncrement()
|
override |
Return true for post-incremented instructions.
Definition at line 1673 of file HexagonInstrInfo.cpp.
References getAddrMode(), MI, and llvm::HexagonII::PostInc.
Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), getBaseAndOffsetPosition(), getIncrementValue(), and getPostIncrementOperand().
◆ isPredicable()
|
override |
Return true if the specified instruction can be predicated.
By default, this returns true for every instruction with a PredicateOperand.
Definition at line 1775 of file HexagonInstrInfo.cpp.
References isTailCall(), and MI.
Referenced by PredicateInstruction().
◆ isPredicated() [1/2]
|
override |
Returns true if the instruction is already predicated.
Definition at line 1685 of file HexagonInstrInfo.cpp.
References F, MI, llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.
Referenced by getBaseAndOffsetPosition(), getDotOldOp(), getPredicatedRegister(), getPredicateSense(), insertBranch(), isDotNewInst(), isNewValueJump(), isPredicatedNew(), isPredicatedNew(), and predOpcodeHasNot().
◆ isPredicated() [2/2]
Definition at line 2556 of file HexagonInstrInfo.cpp.
References F, llvm::get(), llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.
◆ isPredicatedNew() [1/2]
| bool HexagonInstrInfo::isPredicatedNew | ( | const MachineInstr & | MI | ) | const |
Definition at line 2530 of file HexagonInstrInfo.cpp.
References assert(), F, isPredicated(), MI, llvm::HexagonII::PredicatedNewMask, and llvm::HexagonII::PredicatedNewPos.
Referenced by getDotOldOp(), invertAndChangeJumpTarget(), isDotNewInst(), and isPredictedTaken().
◆ isPredicatedNew() [2/2]
Definition at line 2536 of file HexagonInstrInfo.cpp.
References assert(), F, llvm::get(), isPredicated(), llvm::HexagonII::PredicatedNewMask, and llvm::HexagonII::PredicatedNewPos.
◆ isPredicatedTrue() [1/2]
| bool HexagonInstrInfo::isPredicatedTrue | ( | const MachineInstr & | MI | ) | const |
Definition at line 2542 of file HexagonInstrInfo.cpp.
References F, MI, llvm::HexagonII::PredicatedFalseMask, and llvm::HexagonII::PredicatedFalsePos.
Referenced by getInvertedPredicatedOpcode(), getPredicateSense(), and predOpcodeHasNot().
◆ isPredicatedTrue() [2/2]
Definition at line 2548 of file HexagonInstrInfo.cpp.
References assert(), F, llvm::get(), llvm::HexagonII::PredicatedFalseMask, llvm::HexagonII::PredicatedFalsePos, llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.
◆ isPredicateLate()
Definition at line 2561 of file HexagonInstrInfo.cpp.
References F, llvm::get(), llvm::HexagonII::PredicateLateMask, and llvm::HexagonII::PredicateLatePos.
◆ isPredictedTaken()
Definition at line 2566 of file HexagonInstrInfo.cpp.
References assert(), F, llvm::get(), isBranch(), isNewValue(), isPredicatedNew(), llvm::HexagonII::TakenMask, and llvm::HexagonII::TakenPos.
Referenced by reversePrediction().
◆ isProfitableToDupForIfCvt()
|
override |
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion.
The probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 836 of file HexagonInstrInfo.cpp.
References MBB.
◆ isProfitableToIfCvt() [1/2]
|
override |
Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 823 of file HexagonInstrInfo.cpp.
References MBB, and nonDbgBBSize().
◆ isProfitableToIfCvt() [2/2]
|
override |
Second variant of isProfitableToIfCvt.
This one checks for the case where two basic blocks from true and false path of a if-then-else (diamond) are predicated on mutually exclusive predicates, where the probability of the true path being taken is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 829 of file HexagonInstrInfo.cpp.
References nonDbgBBSize().
◆ isPureSlot0()
| bool HexagonInstrInfo::isPureSlot0 | ( | const MachineInstr & | MI | ) | const |
Definition at line 4453 of file HexagonInstrInfo.cpp.
References getUnits(), llvm::HexagonFUnits::isSlot0Only(), and MI.
Referenced by cannotCoexistAsymm().
◆ isQFPMul()
| bool HexagonInstrInfo::isQFPMul | ( | const MachineInstr * | MF | ) | const |
Definition at line 4757 of file HexagonInstrInfo.cpp.
References MI.
◆ isRestrictNoSlot1Store()
| bool HexagonInstrInfo::isRestrictNoSlot1Store | ( | const MachineInstr & | MI | ) | const |
Definition at line 4465 of file HexagonInstrInfo.cpp.
References F, MI, llvm::HexagonII::RestrictNoSlot1StoreMask, and llvm::HexagonII::RestrictNoSlot1StorePos.
Referenced by cannotCoexistAsymm().
◆ isSaveCalleeSavedRegsCall()
| bool HexagonInstrInfo::isSaveCalleeSavedRegsCall | ( | const MachineInstr & | MI | ) | const |
Definition at line 2573 of file HexagonInstrInfo.cpp.
References MI.
◆ isSchedulingBoundary()
|
override |
Test if the given instruction should be considered a scheduling boundary.
This primarily includes labels and terminators.
Definition at line 1811 of file HexagonInstrInfo.cpp.
References doesNotReturn(), I, MBB, MI, and ScheduleInlineAsm.
◆ isSignExtendingLoad()
| bool HexagonInstrInfo::isSignExtendingLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 2580 of file HexagonInstrInfo.cpp.
References MI.
◆ isSolo()
| bool HexagonInstrInfo::isSolo | ( | const MachineInstr & | MI | ) | const |
Definition at line 2658 of file HexagonInstrInfo.cpp.
References F, MI, llvm::HexagonII::SoloMask, and llvm::HexagonII::SoloPos.
◆ isSpillPredRegOp()
| bool HexagonInstrInfo::isSpillPredRegOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 2663 of file HexagonInstrInfo.cpp.
References MI.
◆ isStoreToStackSlot()
|
override |
If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.
If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.
Definition at line 337 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and MI.
◆ isTailCall()
|
override |
◆ isTC1()
| bool HexagonInstrInfo::isTC1 | ( | const MachineInstr & | MI | ) | const |
Definition at line 2684 of file HexagonInstrInfo.cpp.
References llvm::is_TC1(), and MI.
Referenced by isComplex().
◆ isTC2()
| bool HexagonInstrInfo::isTC2 | ( | const MachineInstr & | MI | ) | const |
Definition at line 2689 of file HexagonInstrInfo.cpp.
References llvm::is_TC2(), and MI.
◆ isTC2Early()
| bool HexagonInstrInfo::isTC2Early | ( | const MachineInstr & | MI | ) | const |
Definition at line 2694 of file HexagonInstrInfo.cpp.
References llvm::is_TC2early(), and MI.
Referenced by isComplex().
◆ isTC4x()
| bool HexagonInstrInfo::isTC4x | ( | const MachineInstr & | MI | ) | const |
Definition at line 2699 of file HexagonInstrInfo.cpp.
References llvm::is_TC4x(), and MI.
◆ isToBeScheduledASAP()
| bool HexagonInstrInfo::isToBeScheduledASAP | ( | const MachineInstr & | MI1, |
| const MachineInstr & | MI2 ) const |
Definition at line 2705 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isReg(), mayBeCurLoad(), mayBeNewStore(), and N.
Referenced by llvm::HexagonSubtarget::adjustSchedDependency().
◆ isValidAutoIncImm()
Definition at line 2729 of file HexagonInstrInfo.cpp.
References llvm::Count, llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::isInt(), llvm_unreachable, llvm::Offset, llvm::MVT::SimpleTy, and Size.
◆ isValidOffset()
| bool HexagonInstrInfo::isValidOffset | ( | unsigned | Opcode, |
| int | Offset, | ||
| const TargetRegisterInfo * | TRI, | ||
| bool | Extend = true ) const |
Definition at line 2766 of file HexagonInstrInfo.cpp.
References assert(), llvm::dbgs(), getName(), Hexagon_ADDI_OFFSET_MAX, Hexagon_ADDI_OFFSET_MIN, Hexagon_MEMB_OFFSET_MAX, Hexagon_MEMB_OFFSET_MIN, Hexagon_MEMD_OFFSET_MAX, Hexagon_MEMD_OFFSET_MIN, Hexagon_MEMH_OFFSET_MAX, Hexagon_MEMH_OFFSET_MIN, Hexagon_MEMW_OFFSET_MAX, Hexagon_MEMW_OFFSET_MIN, llvm::isInt(), llvm::isPowerOf2_32(), llvm::isShiftedInt(), llvm::isShiftedUInt(), llvm::isUInt(), llvm_unreachable, llvm::Log2_32(), llvm::Offset, and TRI.
◆ isVecAcc()
| bool HexagonInstrInfo::isVecAcc | ( | const MachineInstr & | MI | ) | const |
Definition at line 2978 of file HexagonInstrInfo.cpp.
References isAccumulator(), isHVXVec(), and MI.
Referenced by isVecUsableNextPacket().
◆ isVecALU()
| bool HexagonInstrInfo::isVecALU | ( | const MachineInstr & | MI | ) | const |
Definition at line 2982 of file HexagonInstrInfo.cpp.
References F, llvm::get(), MI, llvm::HexagonII::TypeCVI_VA, llvm::HexagonII::TypeCVI_VA_DV, llvm::HexagonII::TypeMask, and llvm::HexagonII::TypePos.
Referenced by isVecUsableNextPacket().
◆ isVecUsableNextPacket()
| bool HexagonInstrInfo::isVecUsableNextPacket | ( | const MachineInstr & | ProdMI, |
| const MachineInstr & | ConsMI ) const |
Definition at line 2990 of file HexagonInstrInfo.cpp.
References EnableACCForwarding, EnableALUForwarding, isLateSourceInstr(), isVecAcc(), isVecALU(), and mayBeNewStore().
Referenced by addLatencyToSchedule(), and producesStall().
◆ isZeroExtendingLoad()
| bool HexagonInstrInfo::isZeroExtendingLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 3004 of file HexagonInstrInfo.cpp.
References MI.
◆ loadRegFromStackSlot()
|
override |
Load the specified register of the given register class from the specified stack frame index.
The load instruction is to be added to the given machine basic block before the specified machine instruction.
Definition at line 1011 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::BuildMI(), DL, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), I, llvm_unreachable, MBB, and llvm::MachineMemOperand::MOLoad.
◆ mayBeCurLoad()
| bool HexagonInstrInfo::mayBeCurLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 3196 of file HexagonInstrInfo.cpp.
References F, llvm::HexagonII::mayCVLoadMask, llvm::HexagonII::mayCVLoadPos, and MI.
Referenced by isToBeScheduledASAP().
◆ mayBeNewStore()
| bool HexagonInstrInfo::mayBeNewStore | ( | const MachineInstr & | MI | ) | const |
Definition at line 3203 of file HexagonInstrInfo.cpp.
References F, llvm::HexagonII::mayNVStoreMask, llvm::HexagonII::mayNVStorePos, and MI.
Referenced by canExecuteInBundle(), isToBeScheduledASAP(), and isVecUsableNextPacket().
◆ nonDbgBBSize()
| unsigned HexagonInstrInfo::nonDbgBBSize | ( | const MachineBasicBlock * | BB | ) | const |
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Class information, if available.
Definition at line 4648 of file HexagonInstrInfo.cpp.
References llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), and nonDbgMICount().
Referenced by isProfitableToIfCvt(), and isProfitableToIfCvt().
◆ nonDbgBundleSize()
| unsigned HexagonInstrInfo::nonDbgBundleSize | ( | MachineBasicBlock::const_iterator | BundleHead | ) | const |
Definition at line 4652 of file HexagonInstrInfo.cpp.
References assert(), llvm::getBundleEnd(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getInstrIterator(), and nonDbgMICount().
◆ predCanBeUsedAsDotNew()
| bool HexagonInstrInfo::predCanBeUsedAsDotNew | ( | const MachineInstr & | MI, |
| Register | PredReg ) const |
Definition at line 3249 of file HexagonInstrInfo.cpp.
References MI.
◆ PredicateInstruction()
|
override |
Convert the instruction into a predicated instruction.
It returns true if the operation was successful.
Definition at line 1690 of file HexagonInstrInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::NumOps, assert(), B(), llvm::BuildMI(), Cond, llvm::dbgs(), DL, llvm::get(), getCondOpcode(), llvm::getImm(), getPredReg(), isEndLoopN(), isNewValueJump(), isPredicable(), LLVM_DEBUG, MI, MRI, Opc, predOpcodeHasNot(), and T.
◆ PredOpcodeHasJMP_c()
Definition at line 3284 of file HexagonInstrInfo.cpp.
Referenced by analyzeBranch().
◆ predOpcodeHasNot()
| bool HexagonInstrInfo::predOpcodeHasNot | ( | ArrayRef< MachineOperand > | Cond | ) | const |
Definition at line 3295 of file HexagonInstrInfo.cpp.
References Cond, llvm::getImm(), isPredicated(), and isPredicatedTrue().
Referenced by PredicateInstruction().
◆ producesStall() [1/2]
| bool HexagonInstrInfo::producesStall | ( | const MachineInstr & | MI, |
| MachineBasicBlock::const_instr_iterator | MII ) const |
Definition at line 3229 of file HexagonInstrInfo.cpp.
References isHVXVec(), MI, and producesStall().
◆ producesStall() [2/2]
| bool HexagonInstrInfo::producesStall | ( | const MachineInstr & | ProdMI, |
| const MachineInstr & | ConsMI ) const |
Definition at line 3211 of file HexagonInstrInfo.cpp.
References isDependent(), isHVXVec(), and isVecUsableNextPacket().
Referenced by producesStall().
◆ removeBranch()
|
override |
Remove the branching code at the end of the specific MBB.
This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions that were removed.
Definition at line 605 of file HexagonInstrInfo.cpp.
References assert(), llvm::Count, llvm::dbgs(), I, LLVM_DEBUG, llvm_unreachable, MBB, and llvm::printMBBReference().
Referenced by insertBranch().
◆ reverseBranchCondition()
|
override |
Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.
Definition at line 1652 of file HexagonInstrInfo.cpp.
References assert(), Cond, llvm::get(), getInvertedPredicatedOpcode(), isBranch(), and isEndLoopN().
Referenced by insertBranch().
◆ reversePrediction()
Definition at line 4725 of file HexagonInstrInfo.cpp.
References assert(), and isPredictedTaken().
Referenced by invertAndChangeJumpTarget().
◆ reversePredSense()
| bool HexagonInstrInfo::reversePredSense | ( | MachineInstr & | MI | ) | const |
Definition at line 4718 of file HexagonInstrInfo.cpp.
References llvm::dbgs(), llvm::get(), getInvertedPredicatedOpcode(), LLVM_DEBUG, and MI.
◆ setBundleNoShuf()
| void HexagonInstrInfo::setBundleNoShuf | ( | MachineBasicBlock::instr_iterator | MIB | ) | const |
Definition at line 4741 of file HexagonInstrInfo.cpp.
References assert(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::getImm(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::setImm().
◆ shouldSink()
|
override |
Definition at line 186 of file HexagonInstrInfo.cpp.
◆ storeRegToStackSlot()
|
override |
Store the specified register of the given register class to the specified stack frame index.
The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.
Definition at line 963 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), I, llvm_unreachable, MBB, and llvm::MachineMemOperand::MOStore.
◆ SubsumesPredicate()
|
override |
Returns true if the first specified predicate subsumes the second, e.g.
GE subsumes GT.
Definition at line 1742 of file HexagonInstrInfo.cpp.
◆ translateInstrsForDup() [1/2]
| void HexagonInstrInfo::translateInstrsForDup | ( | MachineBasicBlock::instr_iterator | MII, |
| bool | ToBigInstrs ) const |
Definition at line 4499 of file HexagonInstrInfo.cpp.
References changeDuplexOpcode(), and MBB.
◆ translateInstrsForDup() [2/2]
| void HexagonInstrInfo::translateInstrsForDup | ( | MachineFunction & | MF, |
| bool | ToBigInstrs = true ) const |
Definition at line 4489 of file HexagonInstrInfo.cpp.
References changeDuplexOpcode().
◆ validateBranchCond()
| bool HexagonInstrInfo::validateBranchCond | ( | const ArrayRef< MachineOperand > & | Cond | ) | const |
Definition at line 4736 of file HexagonInstrInfo.cpp.
References Cond.
Referenced by insertBranch().
The documentation for this class was generated from the following files:
- lib/Target/Hexagon/HexagonInstrInfo.h
- lib/Target/Hexagon/HexagonInstrInfo.cpp
Generated on for LLVM by
1.14.0