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48 #define DEBUG_TYPE "packets"
51 cl::init(0),
cl::desc(
"If present, stops packetizing after N instructions"));
98 return RS[InstIdx] ^ RS[InstIdx - 1];
109 std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
138 for (
auto &
M : Mutations)
150 : MF(mf),
TII(mf.getSubtarget().getInstrInfo()),
AA(
aa) {
166 dbgs() <<
"Finalizing packet:\n";
168 for (MachineInstr *MI : CurrentPacketMIs) {
169 unsigned R = ResourceTracker->getUsedResources(Idx++);
170 dbgs() <<
" * [res:0x" << utohexstr(R) <<
"] " << *MI;
174 if (CurrentPacketMIs.size() > 1) {
178 CurrentPacketMIs.clear();
179 ResourceTracker->clearResources();
190 std::distance(BeginItr, EndItr));
194 dbgs() <<
"Scheduling DAG of the packetize region\n";
206 for (; BeginItr != EndItr; ++BeginItr) {
228 assert(SUI &&
"Missing SUnit Info!");
236 dbgs() <<
" Resources are available for adding MI to packet\n";
238 dbgs() <<
" Resources NOT available\n";
244 assert(SUJ &&
"Missing SUnit Info!");
254 <<
" Could not prune dependencies for adding MI\n");
263 <<
"Resources are available, but instruction should not be "
316 std::unique_ptr<ScheduleDAGMutation>
Mutation) {
DefaultVLIWScheduler * VLIWScheduler
This is an optimization pass for GlobalISel generic memory operations.
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
bool alias(const MachineInstr &MI1, const MachineInstr &MI2, bool UseTBAA=true) const
void buildSchedGraph(AAResults *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false)
Builds SUnits for the current region.
virtual bool ignorePseudoInstruction(const MachineInstr &I, const MachineBasicBlock *MBB)
virtual bool shouldAddToPacket(const MachineInstr &MI)
bool canReserveResources(const MCInstrDesc *MID)
unsigned getSchedClass() const
Return the scheduling class for this instruction.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
static unsigned InstrCount
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
A description of a memory reference used in the backend.
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
virtual void startBlock(MachineBasicBlock *BB)
Prepares to perform scheduling in the given block.
The possible results of an alias query.
static cl::opt< unsigned > InstrLimit("dfa-instr-limit", cl::Hidden, cl::init(0), cl::desc("If present, stops packetizing after N instructions"))
virtual void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI)
virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ)
VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, AAResults *AA)
DFAPacketizer * ResourceTracker
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
ArrayRef< NfaPath > getNfaPaths()
Obtain a set of possible paths through the input nondeterministic automaton that could be obtained fr...
bool empty() const
empty - Check if the array is empty.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
unsigned getUsedResources(unsigned InstIdx)
const Value * getValue() const
Return the base address of the memory access.
bool CanHandleTerminators
The standard DAG builder does not normally include terminators as DAG nodes because it does not creat...
virtual void exitRegion()
Called when the scheduler has finished scheduling the current region.
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
virtual MachineBasicBlock::iterator addToPacket(MachineInstr &MI)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
virtual bool isSoloInstruction(const MachineInstr &MI)
void setTrackResources(bool Track)
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
initializer< Ty > init(const Ty &Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual ~VLIWPacketizerList()
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
MachineFunction & MF
Machine function.
@ NoAlias
The two locations do not alias at all.
void postprocessDAG()
Apply each ScheduleDAGMutation step in order.
self_iterator getIterator()
bool canAdd(const ActionT &A)
Return true if the automaton can be transitioned based on input symbol A.
void dump() const override
void schedule() override
Orders nodes according to selected style.
const T & front() const
front - Get the first element.
virtual void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
Initialize the DAG and common scheduler state for a new scheduling region.
const MachineLoopInfo * MLI
std::vector< SUnit > SUnits
The scheduling units.
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
std::map< MachineInstr *, SUnit * > MIToSUnit
virtual void initPacketizerState()
virtual void finishBlock()
Cleans up after scheduling in the given block.
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
DefaultVLIWScheduler takes ownership of the Mutation object.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI, AAResults *AA)
Scheduling unit. This is a node in the scheduling DAG.
const TargetInstrInfo * TII
A ScheduleDAG for scheduling lists of MachineInstr.
virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ)
void reserveResources(const MCInstrDesc *MID)
bool add(const ActionT &A)
Transition the automaton based on input symbol A.
Representation for a specific memory location.
std::vector< MachineInstr * > CurrentPacketMIs