LLVM  16.0.0git
HexagonInstrInfo.cpp
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1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonInstrInfo.h"
14 #include "Hexagon.h"
15 #include "HexagonFrameLowering.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCInstBuilder.h"
44 #include "llvm/MC/MCInstrDesc.h"
46 #include "llvm/MC/MCRegisterInfo.h"
49 #include "llvm/Support/Debug.h"
55 #include <cassert>
56 #include <cctype>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <utility>
62 
63 using namespace llvm;
64 
65 #define DEBUG_TYPE "hexagon-instrinfo"
66 
67 #define GET_INSTRINFO_CTOR_DTOR
68 #define GET_INSTRMAP_INFO
70 #include "HexagonGenDFAPacketizer.inc"
71 #include "HexagonGenInstrInfo.inc"
72 
73 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
74  cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
75  "packetization boundary."));
76 
77 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
78  cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
79 
81  "disable-hexagon-nv-schedule", cl::Hidden,
82  cl::desc("Disable schedule adjustment for new value stores."));
83 
85  "enable-timing-class-latency", cl::Hidden, cl::init(false),
86  cl::desc("Enable timing class latency"));
87 
89  "enable-alu-forwarding", cl::Hidden, cl::init(true),
90  cl::desc("Enable vec alu forwarding"));
91 
93  "enable-acc-forwarding", cl::Hidden, cl::init(true),
94  cl::desc("Enable vec acc forwarding"));
95 
96 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
97  cl::init(true), cl::Hidden,
98  cl::desc("branch relax asm"));
99 
100 static cl::opt<bool>
101  UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden,
102  cl::desc("Use the DFA based hazard recognizer."));
103 
104 /// Constants for Hexagon instructions.
105 const int Hexagon_MEMW_OFFSET_MAX = 4095;
106 const int Hexagon_MEMW_OFFSET_MIN = -4096;
107 const int Hexagon_MEMD_OFFSET_MAX = 8191;
108 const int Hexagon_MEMD_OFFSET_MIN = -8192;
109 const int Hexagon_MEMH_OFFSET_MAX = 2047;
110 const int Hexagon_MEMH_OFFSET_MIN = -2048;
111 const int Hexagon_MEMB_OFFSET_MAX = 1023;
112 const int Hexagon_MEMB_OFFSET_MIN = -1024;
113 const int Hexagon_ADDI_OFFSET_MAX = 32767;
114 const int Hexagon_ADDI_OFFSET_MIN = -32768;
115 
116 // Pin the vtable to this file.
117 void HexagonInstrInfo::anchor() {}
118 
120  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
121  Subtarget(ST) {}
122 
123 namespace llvm {
124 namespace HexagonFUnits {
125  bool isSlot0Only(unsigned units);
126 }
127 }
128 
130  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
131  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
132 }
133 
135  return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
136  isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
137 }
138 
139 /// Calculate number of instructions excluding the debug instructions.
142  unsigned Count = 0;
143  for (; MIB != MIE; ++MIB) {
144  if (!MIB->isDebugInstr())
145  ++Count;
146  }
147  return Count;
148 }
149 
150 // Check if the A2_tfrsi instruction is cheap or not. If the operand has
151 // to be constant-extendend it is not cheap since it occupies two slots
152 // in a packet.
154  // Enable the following steps only at Os/Oz
155  if (!(MI.getMF()->getFunction().hasOptSize()))
156  return MI.isAsCheapAsAMove();
157 
158  if (MI.getOpcode() == Hexagon::A2_tfrsi) {
159  auto Op = MI.getOperand(1);
160  // If the instruction has a global address as operand, it is not cheap
161  // since the operand will be constant extended.
162  if (Op.isGlobal())
163  return false;
164  // If the instruction has an operand of size > 16bits, its will be
165  // const-extended and hence, it is not cheap.
166  if (Op.isImm()) {
167  int64_t Imm = Op.getImm();
168  if (!isInt<16>(Imm))
169  return false;
170  }
171  }
172  return MI.isAsCheapAsAMove();
173 }
174 
175 // Do not sink floating point instructions that updates USR register.
176 // Example:
177 // feclearexcept
178 // F2_conv_w2sf
179 // fetestexcept
180 // MachineSink sinks F2_conv_w2sf and we are not able to catch exceptions.
181 // TODO: On some of these floating point instructions, USR is marked as Use.
182 // In reality, these instructions also Def the USR. If USR is marked as Def,
183 // some of the assumptions in assembler packetization are broken.
185  // Assumption: A floating point instruction that reads the USR will write
186  // the USR as well.
187  if (isFloat(MI) && MI.hasRegisterImplicitUseOperand(Hexagon::USR))
188  return false;
189  return true;
190 }
191 
192 /// Find the hardware loop instruction used to set-up the specified loop.
193 /// On Hexagon, we have two instructions used to set-up the hardware loop
194 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
195 /// to indicate the end of a loop.
197  unsigned EndLoopOp, MachineBasicBlock *TargetBB,
198  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
199  unsigned LOOPi;
200  unsigned LOOPr;
201  if (EndLoopOp == Hexagon::ENDLOOP0) {
202  LOOPi = Hexagon::J2_loop0i;
203  LOOPr = Hexagon::J2_loop0r;
204  } else { // EndLoopOp == Hexagon::EndLOOP1
205  LOOPi = Hexagon::J2_loop1i;
206  LOOPr = Hexagon::J2_loop1r;
207  }
208 
209  // The loop set-up instruction will be in a predecessor block
210  for (MachineBasicBlock *PB : BB->predecessors()) {
211  // If this has been visited, already skip it.
212  if (!Visited.insert(PB).second)
213  continue;
214  if (PB == BB)
215  continue;
216  for (MachineInstr &I : llvm::reverse(PB->instrs())) {
217  unsigned Opc = I.getOpcode();
218  if (Opc == LOOPi || Opc == LOOPr)
219  return &I;
220  // We've reached a different loop, which means the loop01 has been
221  // removed.
222  if (Opc == EndLoopOp && I.getOperand(0).getMBB() != TargetBB)
223  return nullptr;
224  }
225  // Check the predecessors for the LOOP instruction.
226  if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
227  return Loop;
228  }
229  return nullptr;
230 }
231 
232 /// Gather register def/uses from MI.
233 /// This treats possible (predicated) defs as actually happening ones
234 /// (conservatively).
235 static inline void parseOperands(const MachineInstr &MI,
237  Defs.clear();
238  Uses.clear();
239 
240  for (const MachineOperand &MO : MI.operands()) {
241  if (!MO.isReg())
242  continue;
243 
244  Register Reg = MO.getReg();
245  if (!Reg)
246  continue;
247 
248  if (MO.isUse())
249  Uses.push_back(MO.getReg());
250 
251  if (MO.isDef())
252  Defs.push_back(MO.getReg());
253  }
254 }
255 
256 // Position dependent, so check twice for swap.
257 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
258  switch (Ga) {
260  default:
261  return false;
262  case HexagonII::HSIG_L1:
263  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
264  case HexagonII::HSIG_L2:
265  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
266  Gb == HexagonII::HSIG_A);
267  case HexagonII::HSIG_S1:
268  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
269  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
270  case HexagonII::HSIG_S2:
271  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
272  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
273  Gb == HexagonII::HSIG_A);
274  case HexagonII::HSIG_A:
275  return (Gb == HexagonII::HSIG_A);
277  return (Gb == HexagonII::HSIG_Compound);
278  }
279  return false;
280 }
281 
282 /// isLoadFromStackSlot - If the specified machine instruction is a direct
283 /// load from a stack slot, return the virtual or physical register number of
284 /// the destination along with the FrameIndex of the loaded stack slot. If
285 /// not, return 0. This predicate must return 0 if the instruction has
286 /// any side effects other than loading from the stack slot.
288  int &FrameIndex) const {
289  switch (MI.getOpcode()) {
290  default:
291  break;
292  case Hexagon::L2_loadri_io:
293  case Hexagon::L2_loadrd_io:
294  case Hexagon::V6_vL32b_ai:
295  case Hexagon::V6_vL32b_nt_ai:
296  case Hexagon::V6_vL32Ub_ai:
297  case Hexagon::LDriw_pred:
298  case Hexagon::LDriw_ctr:
299  case Hexagon::PS_vloadrq_ai:
300  case Hexagon::PS_vloadrw_ai:
301  case Hexagon::PS_vloadrw_nt_ai: {
302  const MachineOperand OpFI = MI.getOperand(1);
303  if (!OpFI.isFI())
304  return 0;
305  const MachineOperand OpOff = MI.getOperand(2);
306  if (!OpOff.isImm() || OpOff.getImm() != 0)
307  return 0;
308  FrameIndex = OpFI.getIndex();
309  return MI.getOperand(0).getReg();
310  }
311 
312  case Hexagon::L2_ploadrit_io:
313  case Hexagon::L2_ploadrif_io:
314  case Hexagon::L2_ploadrdt_io:
315  case Hexagon::L2_ploadrdf_io: {
316  const MachineOperand OpFI = MI.getOperand(2);
317  if (!OpFI.isFI())
318  return 0;
319  const MachineOperand OpOff = MI.getOperand(3);
320  if (!OpOff.isImm() || OpOff.getImm() != 0)
321  return 0;
322  FrameIndex = OpFI.getIndex();
323  return MI.getOperand(0).getReg();
324  }
325  }
326 
327  return 0;
328 }
329 
330 /// isStoreToStackSlot - If the specified machine instruction is a direct
331 /// store to a stack slot, return the virtual or physical register number of
332 /// the source reg along with the FrameIndex of the loaded stack slot. If
333 /// not, return 0. This predicate must return 0 if the instruction has
334 /// any side effects other than storing to the stack slot.
336  int &FrameIndex) const {
337  switch (MI.getOpcode()) {
338  default:
339  break;
340  case Hexagon::S2_storerb_io:
341  case Hexagon::S2_storerh_io:
342  case Hexagon::S2_storeri_io:
343  case Hexagon::S2_storerd_io:
344  case Hexagon::V6_vS32b_ai:
345  case Hexagon::V6_vS32Ub_ai:
346  case Hexagon::STriw_pred:
347  case Hexagon::STriw_ctr:
348  case Hexagon::PS_vstorerq_ai:
349  case Hexagon::PS_vstorerw_ai: {
350  const MachineOperand &OpFI = MI.getOperand(0);
351  if (!OpFI.isFI())
352  return 0;
353  const MachineOperand &OpOff = MI.getOperand(1);
354  if (!OpOff.isImm() || OpOff.getImm() != 0)
355  return 0;
356  FrameIndex = OpFI.getIndex();
357  return MI.getOperand(2).getReg();
358  }
359 
360  case Hexagon::S2_pstorerbt_io:
361  case Hexagon::S2_pstorerbf_io:
362  case Hexagon::S2_pstorerht_io:
363  case Hexagon::S2_pstorerhf_io:
364  case Hexagon::S2_pstorerit_io:
365  case Hexagon::S2_pstorerif_io:
366  case Hexagon::S2_pstorerdt_io:
367  case Hexagon::S2_pstorerdf_io: {
368  const MachineOperand &OpFI = MI.getOperand(1);
369  if (!OpFI.isFI())
370  return 0;
371  const MachineOperand &OpOff = MI.getOperand(2);
372  if (!OpOff.isImm() || OpOff.getImm() != 0)
373  return 0;
374  FrameIndex = OpFI.getIndex();
375  return MI.getOperand(3).getReg();
376  }
377  }
378 
379  return 0;
380 }
381 
382 /// This function checks if the instruction or bundle of instructions
383 /// has load from stack slot and returns frameindex and machine memory
384 /// operand of that instruction if true.
386  const MachineInstr &MI,
388  if (MI.isBundle()) {
389  const MachineBasicBlock *MBB = MI.getParent();
390  MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
391  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
392  if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
393  return true;
394  return false;
395  }
396 
397  return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
398 }
399 
400 /// This function checks if the instruction or bundle of instructions
401 /// has store to stack slot and returns frameindex and machine memory
402 /// operand of that instruction if true.
404  const MachineInstr &MI,
406  if (MI.isBundle()) {
407  const MachineBasicBlock *MBB = MI.getParent();
408  MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
409  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
410  if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
411  return true;
412  return false;
413  }
414 
415  return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
416 }
417 
418 /// This function can analyze one/two way branching only and should (mostly) be
419 /// called by target independent side.
420 /// First entry is always the opcode of the branching instruction, except when
421 /// the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a
422 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
423 /// e.g. Jump_c p will have
424 /// Cond[0] = Jump_c
425 /// Cond[1] = p
426 /// HW-loop ENDLOOP:
427 /// Cond[0] = ENDLOOP
428 /// Cond[1] = MBB
429 /// New value jump:
430 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
431 /// Cond[1] = R
432 /// Cond[2] = Imm
435  MachineBasicBlock *&FBB,
437  bool AllowModify) const {
438  TBB = nullptr;
439  FBB = nullptr;
440  Cond.clear();
441 
442  // If the block has no terminators, it just falls into the block after it.
444  if (I == MBB.instr_begin())
445  return false;
446 
447  // A basic block may looks like this:
448  //
449  // [ insn
450  // EH_LABEL
451  // insn
452  // insn
453  // insn
454  // EH_LABEL
455  // insn ]
456  //
457  // It has two succs but does not have a terminator
458  // Don't know how to handle it.
459  do {
460  --I;
461  if (I->isEHLabel())
462  // Don't analyze EH branches.
463  return true;
464  } while (I != MBB.instr_begin());
465 
466  I = MBB.instr_end();
467  --I;
468 
469  while (I->isDebugInstr()) {
470  if (I == MBB.instr_begin())
471  return false;
472  --I;
473  }
474 
475  bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
476  I->getOperand(0).isMBB();
477  // Delete the J2_jump if it's equivalent to a fall-through.
478  if (AllowModify && JumpToBlock &&
479  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
480  LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
481  I->eraseFromParent();
482  I = MBB.instr_end();
483  if (I == MBB.instr_begin())
484  return false;
485  --I;
486  }
487  if (!isUnpredicatedTerminator(*I))
488  return false;
489 
490  // Get the last instruction in the block.
491  MachineInstr *LastInst = &*I;
492  MachineInstr *SecondLastInst = nullptr;
493  // Find one more terminator if present.
494  while (true) {
495  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
496  if (!SecondLastInst)
497  SecondLastInst = &*I;
498  else
499  // This is a third branch.
500  return true;
501  }
502  if (I == MBB.instr_begin())
503  break;
504  --I;
505  }
506 
507  int LastOpcode = LastInst->getOpcode();
508  int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
509  // If the branch target is not a basic block, it could be a tail call.
510  // (It is, if the target is a function.)
511  if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
512  return true;
513  if (SecLastOpcode == Hexagon::J2_jump &&
514  !SecondLastInst->getOperand(0).isMBB())
515  return true;
516 
517  bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
518  bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
519 
520  if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
521  return true;
522 
523  // If there is only one terminator instruction, process it.
524  if (LastInst && !SecondLastInst) {
525  if (LastOpcode == Hexagon::J2_jump) {
526  TBB = LastInst->getOperand(0).getMBB();
527  return false;
528  }
529  if (isEndLoopN(LastOpcode)) {
530  TBB = LastInst->getOperand(0).getMBB();
531  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
532  Cond.push_back(LastInst->getOperand(0));
533  return false;
534  }
535  if (LastOpcodeHasJMP_c) {
536  TBB = LastInst->getOperand(1).getMBB();
537  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
538  Cond.push_back(LastInst->getOperand(0));
539  return false;
540  }
541  // Only supporting rr/ri versions of new-value jumps.
542  if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
543  TBB = LastInst->getOperand(2).getMBB();
544  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
545  Cond.push_back(LastInst->getOperand(0));
546  Cond.push_back(LastInst->getOperand(1));
547  return false;
548  }
549  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
550  << " with one jump\n";);
551  // Otherwise, don't know what this is.
552  return true;
553  }
554 
555  bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
556  bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
557  if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
558  if (!SecondLastInst->getOperand(1).isMBB())
559  return true;
560  TBB = SecondLastInst->getOperand(1).getMBB();
561  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
562  Cond.push_back(SecondLastInst->getOperand(0));
563  FBB = LastInst->getOperand(0).getMBB();
564  return false;
565  }
566 
567  // Only supporting rr/ri versions of new-value jumps.
568  if (SecLastOpcodeHasNVJump &&
569  (SecondLastInst->getNumExplicitOperands() == 3) &&
570  (LastOpcode == Hexagon::J2_jump)) {
571  TBB = SecondLastInst->getOperand(2).getMBB();
572  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
573  Cond.push_back(SecondLastInst->getOperand(0));
574  Cond.push_back(SecondLastInst->getOperand(1));
575  FBB = LastInst->getOperand(0).getMBB();
576  return false;
577  }
578 
579  // If the block ends with two Hexagon:JMPs, handle it. The second one is not
580  // executed, so remove it.
581  if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
582  TBB = SecondLastInst->getOperand(0).getMBB();
583  I = LastInst->getIterator();
584  if (AllowModify)
585  I->eraseFromParent();
586  return false;
587  }
588 
589  // If the block ends with an ENDLOOP, and J2_jump, handle it.
590  if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
591  TBB = SecondLastInst->getOperand(0).getMBB();
592  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
593  Cond.push_back(SecondLastInst->getOperand(0));
594  FBB = LastInst->getOperand(0).getMBB();
595  return false;
596  }
597  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
598  << " with two jumps";);
599  // Otherwise, can't handle this.
600  return true;
601 }
602 
604  int *BytesRemoved) const {
605  assert(!BytesRemoved && "code size not handled");
606 
607  LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
609  unsigned Count = 0;
610  while (I != MBB.begin()) {
611  --I;
612  if (I->isDebugInstr())
613  continue;
614  // Only removing branches from end of MBB.
615  if (!I->isBranch())
616  return Count;
617  if (Count && (I->getOpcode() == Hexagon::J2_jump))
618  llvm_unreachable("Malformed basic block: unconditional branch not last");
619  MBB.erase(&MBB.back());
620  I = MBB.end();
621  ++Count;
622  }
623  return Count;
624 }
625 
628  MachineBasicBlock *FBB,
630  const DebugLoc &DL,
631  int *BytesAdded) const {
632  unsigned BOpc = Hexagon::J2_jump;
633  unsigned BccOpc = Hexagon::J2_jumpt;
634  assert(validateBranchCond(Cond) && "Invalid branching condition");
635  assert(TBB && "insertBranch must not be told to insert a fallthrough");
636  assert(!BytesAdded && "code size not handled");
637 
638  // Check if reverseBranchCondition has asked to reverse this branch
639  // If we want to reverse the branch an odd number of times, we want
640  // J2_jumpf.
641  if (!Cond.empty() && Cond[0].isImm())
642  BccOpc = Cond[0].getImm();
643 
644  if (!FBB) {
645  if (Cond.empty()) {
646  // Due to a bug in TailMerging/CFG Optimization, we need to add a
647  // special case handling of a predicated jump followed by an
648  // unconditional jump. If not, Tail Merging and CFG Optimization go
649  // into an infinite loop.
650  MachineBasicBlock *NewTBB, *NewFBB;
652  auto Term = MBB.getFirstTerminator();
653  if (Term != MBB.end() && isPredicated(*Term) &&
654  !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
655  MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
657  removeBranch(MBB);
658  return insertBranch(MBB, TBB, nullptr, Cond, DL);
659  }
660  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
661  } else if (isEndLoopN(Cond[0].getImm())) {
662  int EndLoopOp = Cond[0].getImm();
663  assert(Cond[1].isMBB());
664  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
665  // Check for it, and change the BB target if needed.
667  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
668  VisitedBBs);
669  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
670  Loop->getOperand(0).setMBB(TBB);
671  // Add the ENDLOOP after the finding the LOOP0.
672  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
673  } else if (isNewValueJump(Cond[0].getImm())) {
674  assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
675  // New value jump
676  // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
677  // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
678  unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
679  LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
680  << printMBBReference(MBB););
681  if (Cond[2].isReg()) {
682  unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
683  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
684  addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
685  } else if(Cond[2].isImm()) {
686  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
687  addImm(Cond[2].getImm()).addMBB(TBB);
688  } else
689  llvm_unreachable("Invalid condition for branching");
690  } else {
691  assert((Cond.size() == 2) && "Malformed cond vector");
692  const MachineOperand &RO = Cond[1];
693  unsigned Flags = getUndefRegState(RO.isUndef());
694  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
695  }
696  return 1;
697  }
698  assert((!Cond.empty()) &&
699  "Cond. cannot be empty when multiple branchings are required");
700  assert((!isNewValueJump(Cond[0].getImm())) &&
701  "NV-jump cannot be inserted with another branch");
702  // Special case for hardware loops. The condition is a basic block.
703  if (isEndLoopN(Cond[0].getImm())) {
704  int EndLoopOp = Cond[0].getImm();
705  assert(Cond[1].isMBB());
706  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
707  // Check for it, and change the BB target if needed.
709  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
710  VisitedBBs);
711  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
712  Loop->getOperand(0).setMBB(TBB);
713  // Add the ENDLOOP after the finding the LOOP0.
714  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
715  } else {
716  const MachineOperand &RO = Cond[1];
717  unsigned Flags = getUndefRegState(RO.isUndef());
718  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
719  }
720  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
721 
722  return 2;
723 }
724 
725 namespace {
726 class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
727  MachineInstr *Loop, *EndLoop;
728  MachineFunction *MF;
729  const HexagonInstrInfo *TII;
730  int64_t TripCount;
731  Register LoopCount;
732  DebugLoc DL;
733 
734 public:
735  HexagonPipelinerLoopInfo(MachineInstr *Loop, MachineInstr *EndLoop)
736  : Loop(Loop), EndLoop(EndLoop), MF(Loop->getParent()->getParent()),
737  TII(MF->getSubtarget<HexagonSubtarget>().getInstrInfo()),
738  DL(Loop->getDebugLoc()) {
739  // Inspect the Loop instruction up-front, as it may be deleted when we call
740  // createTripCountGreaterCondition.
741  TripCount = Loop->getOpcode() == Hexagon::J2_loop0r
742  ? -1
743  : Loop->getOperand(1).getImm();
744  if (TripCount == -1)
745  LoopCount = Loop->getOperand(1).getReg();
746  }
747 
748  bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
749  // Only ignore the terminator.
750  return MI == EndLoop;
751  }
752 
754  createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
756  if (TripCount == -1) {
757  // Check if we're done with the loop.
758  Register Done = TII->createVR(MF, MVT::i1);
759  MachineInstr *NewCmp = BuildMI(&MBB, DL,
760  TII->get(Hexagon::C2_cmpgtui), Done)
761  .addReg(LoopCount)
762  .addImm(TC);
763  Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
764  Cond.push_back(NewCmp->getOperand(0));
765  return {};
766  }
767 
768  return TripCount > TC;
769  }
770 
771  void setPreheader(MachineBasicBlock *NewPreheader) override {
772  NewPreheader->splice(NewPreheader->getFirstTerminator(), Loop->getParent(),
773  Loop);
774  }
775 
776  void adjustTripCount(int TripCountAdjust) override {
777  // If the loop trip count is a compile-time value, then just change the
778  // value.
779  if (Loop->getOpcode() == Hexagon::J2_loop0i ||
780  Loop->getOpcode() == Hexagon::J2_loop1i) {
781  int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust;
782  assert(TripCount > 0 && "Can't create an empty or negative loop!");
783  Loop->getOperand(1).setImm(TripCount);
784  return;
785  }
786 
787  // The loop trip count is a run-time value. We generate code to subtract
788  // one from the trip count, and update the loop instruction.
789  Register LoopCount = Loop->getOperand(1).getReg();
790  Register NewLoopCount = TII->createVR(MF, MVT::i32);
791  BuildMI(*Loop->getParent(), Loop, Loop->getDebugLoc(),
792  TII->get(Hexagon::A2_addi), NewLoopCount)
793  .addReg(LoopCount)
794  .addImm(TripCountAdjust);
795  Loop->getOperand(1).setReg(NewLoopCount);
796  }
797 
798  void disposed() override { Loop->eraseFromParent(); }
799 };
800 } // namespace
801 
802 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
804  // We really "analyze" only hardware loops right now.
806 
807  if (I != LoopBB->end() && isEndLoopN(I->getOpcode())) {
809  MachineInstr *LoopInst = findLoopInstr(
810  LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
811  if (LoopInst)
812  return std::make_unique<HexagonPipelinerLoopInfo>(LoopInst, &*I);
813  }
814  return nullptr;
815 }
816 
818  unsigned NumCycles, unsigned ExtraPredCycles,
819  BranchProbability Probability) const {
820  return nonDbgBBSize(&MBB) <= 3;
821 }
822 
824  unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
825  unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
826  const {
827  return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
828 }
829 
831  unsigned NumInstrs, BranchProbability Probability) const {
832  return NumInstrs <= 4;
833 }
834 
835 static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
837  const MachineBasicBlock &B = *MI.getParent();
838  Regs.addLiveIns(B);
839  auto E = MachineBasicBlock::const_iterator(MI.getIterator());
840  for (auto I = B.begin(); I != E; ++I) {
841  Clobbers.clear();
842  Regs.stepForward(*I, Clobbers);
843  }
844 }
845 
846 static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
847  const MachineBasicBlock &B = *MI.getParent();
848  Regs.addLiveOuts(B);
849  auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
850  for (auto I = B.rbegin(); I != E; ++I)
851  Regs.stepBackward(*I);
852 }
853 
856  const DebugLoc &DL, MCRegister DestReg,
857  MCRegister SrcReg, bool KillSrc) const {
858  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
859  unsigned KillFlag = getKillRegState(KillSrc);
860 
861  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
862  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
863  .addReg(SrcReg, KillFlag);
864  return;
865  }
866  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
867  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
868  .addReg(SrcReg, KillFlag);
869  return;
870  }
871  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
872  // Map Pd = Ps to Pd = or(Ps, Ps).
873  BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
874  .addReg(SrcReg).addReg(SrcReg, KillFlag);
875  return;
876  }
877  if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
878  Hexagon::IntRegsRegClass.contains(SrcReg)) {
879  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
880  .addReg(SrcReg, KillFlag);
881  return;
882  }
883  if (Hexagon::IntRegsRegClass.contains(DestReg) &&
884  Hexagon::CtrRegsRegClass.contains(SrcReg)) {
885  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
886  .addReg(SrcReg, KillFlag);
887  return;
888  }
889  if (Hexagon::ModRegsRegClass.contains(DestReg) &&
890  Hexagon::IntRegsRegClass.contains(SrcReg)) {
891  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
892  .addReg(SrcReg, KillFlag);
893  return;
894  }
895  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
896  Hexagon::IntRegsRegClass.contains(DestReg)) {
897  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
898  .addReg(SrcReg, KillFlag);
899  return;
900  }
901  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
902  Hexagon::PredRegsRegClass.contains(DestReg)) {
903  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
904  .addReg(SrcReg, KillFlag);
905  return;
906  }
907  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
908  Hexagon::IntRegsRegClass.contains(DestReg)) {
909  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
910  .addReg(SrcReg, KillFlag);
911  return;
912  }
913  if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
914  BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
915  addReg(SrcReg, KillFlag);
916  return;
917  }
918  if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
919  LivePhysRegs LiveAtMI(HRI);
920  getLiveInRegsAt(LiveAtMI, *I);
921  Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
922  Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
923  unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo));
924  unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi));
925  BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
926  .addReg(SrcHi, KillFlag | UndefHi)
927  .addReg(SrcLo, KillFlag | UndefLo);
928  return;
929  }
930  if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
931  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
932  .addReg(SrcReg)
933  .addReg(SrcReg, KillFlag);
934  return;
935  }
936  if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
937  Hexagon::HvxVRRegClass.contains(DestReg)) {
938  llvm_unreachable("Unimplemented pred to vec");
939  return;
940  }
941  if (Hexagon::HvxQRRegClass.contains(DestReg) &&
942  Hexagon::HvxVRRegClass.contains(SrcReg)) {
943  llvm_unreachable("Unimplemented vec to pred");
944  return;
945  }
946 
947 #ifndef NDEBUG
948  // Show the invalid registers to ease debugging.
949  dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
950  << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
951 #endif
952  llvm_unreachable("Unimplemented");
953 }
954 
956  MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI,
957  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
959  MachineFunction &MF = *MBB.getParent();
960  MachineFrameInfo &MFI = MF.getFrameInfo();
961  unsigned KillFlag = getKillRegState(isKill);
962 
965  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
966 
967  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
968  BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
969  .addFrameIndex(FI).addImm(0)
970  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
971  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
972  BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
973  .addFrameIndex(FI).addImm(0)
974  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
975  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
976  BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
977  .addFrameIndex(FI).addImm(0)
978  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
979  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
980  BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
981  .addFrameIndex(FI).addImm(0)
982  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
983  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
984  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
985  .addFrameIndex(FI).addImm(0)
986  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
987  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
988  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerv_ai))
989  .addFrameIndex(FI).addImm(0)
990  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
991  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
992  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerw_ai))
993  .addFrameIndex(FI).addImm(0)
994  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
995  } else {
996  llvm_unreachable("Unimplemented");
997  }
998 }
999 
1002  int FI, const TargetRegisterClass *RC,
1003  const TargetRegisterInfo *TRI) const {
1005  MachineFunction &MF = *MBB.getParent();
1006  MachineFrameInfo &MFI = MF.getFrameInfo();
1007 
1010  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
1011 
1012  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
1013  BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
1014  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1015  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
1016  BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
1017  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1018  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
1019  BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
1020  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1021  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
1022  BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
1023  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1024  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
1025  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
1026  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1027  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
1028  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrv_ai), DestReg)
1029  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1030  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1031  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrw_ai), DestReg)
1032  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1033  } else {
1034  llvm_unreachable("Can't store this register to stack slot");
1035  }
1036 }
1037 
1038 /// expandPostRAPseudo - This function is called for all pseudo instructions
1039 /// that remain after register allocation. Many pseudo instructions are
1040 /// created to help register allocation. This is the place to convert them
1041 /// into real instructions. The target can edit MI in place, or it can insert
1042 /// new instructions and erase MI. The function should return true if
1043 /// anything was changed.
1045  MachineBasicBlock &MBB = *MI.getParent();
1046  MachineFunction &MF = *MBB.getParent();
1048  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1049  LivePhysRegs LiveIn(HRI), LiveOut(HRI);
1050  DebugLoc DL = MI.getDebugLoc();
1051  unsigned Opc = MI.getOpcode();
1052 
1053  auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1054  Register Mx = MI.getOperand(MxOp).getReg();
1055  Register CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1056  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1057  .add(MI.getOperand((HasImm ? 5 : 4)));
1058  auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1059  .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1060  if (HasImm)
1061  MIB.add(MI.getOperand(4));
1062  MIB.addReg(CSx, RegState::Implicit);
1063  MBB.erase(MI);
1064  return true;
1065  };
1066 
1067  auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) {
1068  if (MI.memoperands().empty())
1069  return false;
1070  return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) {
1071  return MMO->getAlign() >= NeedAlign;
1072  });
1073  };
1074 
1075  switch (Opc) {
1076  case Hexagon::PS_call_instrprof_custom: {
1077  auto Op0 = MI.getOperand(0);
1078  assert(Op0.isGlobal() &&
1079  "First operand must be a global containing handler name.");
1080  const GlobalValue *NameVar = Op0.getGlobal();
1081  const GlobalVariable *GV = dyn_cast<GlobalVariable>(NameVar);
1082  auto *Arr = cast<ConstantDataArray>(GV->getInitializer());
1083  StringRef NameStr = Arr->isCString() ? Arr->getAsCString() : Arr->getAsString();
1084 
1085  MachineOperand &Op1 = MI.getOperand(1);
1086  // Set R0 with the imm value to be passed to the custom profiling handler.
1087  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrsi), Hexagon::R0)
1088  .addImm(Op1.getImm());
1089  // The call to the custom handler is being treated as a special one as the
1090  // callee is responsible for saving and restoring all the registers
1091  // (including caller saved registers) it needs to modify. This is
1092  // done to reduce the impact of instrumentation on the code being
1093  // instrumented/profiled.
1094  // NOTE: R14, R15 and R28 are reserved for PLT handling. These registers
1095  // are in the Def list of the Hexagon::PS_call_instrprof_custom and
1096  // therefore will be handled appropriately duing register allocation.
1097 
1098  // TODO: It may be a good idea to add a separate pseudo instruction for
1099  // static relocation which doesn't need to reserve r14, r15 and r28.
1100 
1101  auto MIB = BuildMI(MBB, MI, DL, get(Hexagon::J2_call))
1103  .addDef(Hexagon::R29, RegState::ImplicitDefine)
1104  .addDef(Hexagon::R30, RegState::ImplicitDefine)
1105  .addDef(Hexagon::R14, RegState::ImplicitDefine)
1106  .addDef(Hexagon::R15, RegState::ImplicitDefine)
1107  .addDef(Hexagon::R28, RegState::ImplicitDefine);
1108  const char *cstr = MF.createExternalSymbolName(NameStr);
1109  MIB.addExternalSymbol(cstr);
1110  MBB.erase(MI);
1111  return true;
1112  }
1113  case TargetOpcode::COPY: {
1114  MachineOperand &MD = MI.getOperand(0);
1115  MachineOperand &MS = MI.getOperand(1);
1116  MachineBasicBlock::iterator MBBI = MI.getIterator();
1117  if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1118  copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1119  std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1120  }
1121  MBB.erase(MBBI);
1122  return true;
1123  }
1124  case Hexagon::PS_aligna:
1125  BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1126  .addReg(HRI.getFrameRegister())
1127  .addImm(-MI.getOperand(1).getImm());
1128  MBB.erase(MI);
1129  return true;
1130  case Hexagon::V6_vassignp: {
1131  Register SrcReg = MI.getOperand(1).getReg();
1132  Register DstReg = MI.getOperand(0).getReg();
1133  Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1134  Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1135  getLiveInRegsAt(LiveIn, MI);
1136  unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
1137  unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));
1138  unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1139  BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1140  .addReg(SrcHi, UndefHi)
1141  .addReg(SrcLo, Kill | UndefLo);
1142  MBB.erase(MI);
1143  return true;
1144  }
1145  case Hexagon::V6_lo: {
1146  Register SrcReg = MI.getOperand(1).getReg();
1147  Register DstReg = MI.getOperand(0).getReg();
1148  Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1149  copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1150  MBB.erase(MI);
1151  MRI.clearKillFlags(SrcSubLo);
1152  return true;
1153  }
1154  case Hexagon::V6_hi: {
1155  Register SrcReg = MI.getOperand(1).getReg();
1156  Register DstReg = MI.getOperand(0).getReg();
1157  Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1158  copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1159  MBB.erase(MI);
1160  MRI.clearKillFlags(SrcSubHi);
1161  return true;
1162  }
1163  case Hexagon::PS_vloadrv_ai: {
1164  Register DstReg = MI.getOperand(0).getReg();
1165  const MachineOperand &BaseOp = MI.getOperand(1);
1166  assert(BaseOp.getSubReg() == 0);
1167  int Offset = MI.getOperand(2).getImm();
1168  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1169  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1170  : Hexagon::V6_vL32Ub_ai;
1171  BuildMI(MBB, MI, DL, get(NewOpc), DstReg)
1172  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1173  .addImm(Offset)
1174  .cloneMemRefs(MI);
1175  MBB.erase(MI);
1176  return true;
1177  }
1178  case Hexagon::PS_vloadrw_ai: {
1179  Register DstReg = MI.getOperand(0).getReg();
1180  const MachineOperand &BaseOp = MI.getOperand(1);
1181  assert(BaseOp.getSubReg() == 0);
1182  int Offset = MI.getOperand(2).getImm();
1183  unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1184  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1185  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1186  : Hexagon::V6_vL32Ub_ai;
1187  BuildMI(MBB, MI, DL, get(NewOpc),
1188  HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1189  .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1190  .addImm(Offset)
1191  .cloneMemRefs(MI);
1192  BuildMI(MBB, MI, DL, get(NewOpc),
1193  HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1194  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1195  .addImm(Offset + VecOffset)
1196  .cloneMemRefs(MI);
1197  MBB.erase(MI);
1198  return true;
1199  }
1200  case Hexagon::PS_vstorerv_ai: {
1201  const MachineOperand &SrcOp = MI.getOperand(2);
1202  assert(SrcOp.getSubReg() == 0);
1203  const MachineOperand &BaseOp = MI.getOperand(0);
1204  assert(BaseOp.getSubReg() == 0);
1205  int Offset = MI.getOperand(1).getImm();
1206  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1207  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1208  : Hexagon::V6_vS32Ub_ai;
1209  BuildMI(MBB, MI, DL, get(NewOpc))
1210  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1211  .addImm(Offset)
1213  .cloneMemRefs(MI);
1214  MBB.erase(MI);
1215  return true;
1216  }
1217  case Hexagon::PS_vstorerw_ai: {
1218  Register SrcReg = MI.getOperand(2).getReg();
1219  const MachineOperand &BaseOp = MI.getOperand(0);
1220  assert(BaseOp.getSubReg() == 0);
1221  int Offset = MI.getOperand(1).getImm();
1222  unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1223  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1224  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1225  : Hexagon::V6_vS32Ub_ai;
1226  BuildMI(MBB, MI, DL, get(NewOpc))
1227  .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1228  .addImm(Offset)
1229  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo))
1230  .cloneMemRefs(MI);
1231  BuildMI(MBB, MI, DL, get(NewOpc))
1232  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1233  .addImm(Offset + VecOffset)
1234  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi))
1235  .cloneMemRefs(MI);
1236  MBB.erase(MI);
1237  return true;
1238  }
1239  case Hexagon::PS_true: {
1240  Register Reg = MI.getOperand(0).getReg();
1241  BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1244  MBB.erase(MI);
1245  return true;
1246  }
1247  case Hexagon::PS_false: {
1248  Register Reg = MI.getOperand(0).getReg();
1249  BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1252  MBB.erase(MI);
1253  return true;
1254  }
1255  case Hexagon::PS_qtrue: {
1256  BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1257  .addReg(Hexagon::V0, RegState::Undef)
1258  .addReg(Hexagon::V0, RegState::Undef);
1259  MBB.erase(MI);
1260  return true;
1261  }
1262  case Hexagon::PS_qfalse: {
1263  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1264  .addReg(Hexagon::V0, RegState::Undef)
1265  .addReg(Hexagon::V0, RegState::Undef);
1266  MBB.erase(MI);
1267  return true;
1268  }
1269  case Hexagon::PS_vdd0: {
1270  Register Vd = MI.getOperand(0).getReg();
1271  BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1272  .addReg(Vd, RegState::Undef)
1273  .addReg(Vd, RegState::Undef);
1274  MBB.erase(MI);
1275  return true;
1276  }
1277  case Hexagon::PS_vmulw: {
1278  // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1279  Register DstReg = MI.getOperand(0).getReg();
1280  Register Src1Reg = MI.getOperand(1).getReg();
1281  Register Src2Reg = MI.getOperand(2).getReg();
1282  Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1283  Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1284  Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1285  Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1286  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1287  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1288  .addReg(Src1SubHi)
1289  .addReg(Src2SubHi);
1290  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1291  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1292  .addReg(Src1SubLo)
1293  .addReg(Src2SubLo);
1294  MBB.erase(MI);
1295  MRI.clearKillFlags(Src1SubHi);
1296  MRI.clearKillFlags(Src1SubLo);
1297  MRI.clearKillFlags(Src2SubHi);
1298  MRI.clearKillFlags(Src2SubLo);
1299  return true;
1300  }
1301  case Hexagon::PS_vmulw_acc: {
1302  // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1303  Register DstReg = MI.getOperand(0).getReg();
1304  Register Src1Reg = MI.getOperand(1).getReg();
1305  Register Src2Reg = MI.getOperand(2).getReg();
1306  Register Src3Reg = MI.getOperand(3).getReg();
1307  Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1308  Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1309  Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1310  Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1311  Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1312  Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1313  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1314  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1315  .addReg(Src1SubHi)
1316  .addReg(Src2SubHi)
1317  .addReg(Src3SubHi);
1318  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1319  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1320  .addReg(Src1SubLo)
1321  .addReg(Src2SubLo)
1322  .addReg(Src3SubLo);
1323  MBB.erase(MI);
1324  MRI.clearKillFlags(Src1SubHi);
1325  MRI.clearKillFlags(Src1SubLo);
1326  MRI.clearKillFlags(Src2SubHi);
1327  MRI.clearKillFlags(Src2SubLo);
1328  MRI.clearKillFlags(Src3SubHi);
1329  MRI.clearKillFlags(Src3SubLo);
1330  return true;
1331  }
1332  case Hexagon::PS_pselect: {
1333  const MachineOperand &Op0 = MI.getOperand(0);
1334  const MachineOperand &Op1 = MI.getOperand(1);
1335  const MachineOperand &Op2 = MI.getOperand(2);
1336  const MachineOperand &Op3 = MI.getOperand(3);
1337  Register Rd = Op0.getReg();
1338  Register Pu = Op1.getReg();
1339  Register Rs = Op2.getReg();
1340  Register Rt = Op3.getReg();
1341  DebugLoc DL = MI.getDebugLoc();
1342  unsigned K1 = getKillRegState(Op1.isKill());
1343  unsigned K2 = getKillRegState(Op2.isKill());
1344  unsigned K3 = getKillRegState(Op3.isKill());
1345  if (Rd != Rs)
1346  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1347  .addReg(Pu, (Rd == Rt) ? K1 : 0)
1348  .addReg(Rs, K2);
1349  if (Rd != Rt)
1350  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1351  .addReg(Pu, K1)
1352  .addReg(Rt, K3);
1353  MBB.erase(MI);
1354  return true;
1355  }
1356  case Hexagon::PS_vselect: {
1357  const MachineOperand &Op0 = MI.getOperand(0);
1358  const MachineOperand &Op1 = MI.getOperand(1);
1359  const MachineOperand &Op2 = MI.getOperand(2);
1360  const MachineOperand &Op3 = MI.getOperand(3);
1361  getLiveOutRegsAt(LiveOut, MI);
1362  bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
1363  Register PReg = Op1.getReg();
1364  assert(Op1.getSubReg() == 0);
1365  unsigned PState = getRegState(Op1);
1366 
1367  if (Op0.getReg() != Op2.getReg()) {
1368  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1369  : PState;
1370  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1371  .add(Op0)
1372  .addReg(PReg, S)
1373  .add(Op2);
1374  if (IsDestLive)
1375  T.addReg(Op0.getReg(), RegState::Implicit);
1376  IsDestLive = true;
1377  }
1378  if (Op0.getReg() != Op3.getReg()) {
1379  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1380  .add(Op0)
1381  .addReg(PReg, PState)
1382  .add(Op3);
1383  if (IsDestLive)
1384  T.addReg(Op0.getReg(), RegState::Implicit);
1385  }
1386  MBB.erase(MI);
1387  return true;
1388  }
1389  case Hexagon::PS_wselect: {
1390  MachineOperand &Op0 = MI.getOperand(0);
1391  MachineOperand &Op1 = MI.getOperand(1);
1392  MachineOperand &Op2 = MI.getOperand(2);
1393  MachineOperand &Op3 = MI.getOperand(3);
1394  getLiveOutRegsAt(LiveOut, MI);
1395  bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
1396  Register PReg = Op1.getReg();
1397  assert(Op1.getSubReg() == 0);
1398  unsigned PState = getRegState(Op1);
1399 
1400  if (Op0.getReg() != Op2.getReg()) {
1401  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1402  : PState;
1403  Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1404  Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1405  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1406  .add(Op0)
1407  .addReg(PReg, S)
1408  .addReg(SrcHi)
1409  .addReg(SrcLo);
1410  if (IsDestLive)
1411  T.addReg(Op0.getReg(), RegState::Implicit);
1412  IsDestLive = true;
1413  }
1414  if (Op0.getReg() != Op3.getReg()) {
1415  Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1416  Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1417  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1418  .add(Op0)
1419  .addReg(PReg, PState)
1420  .addReg(SrcHi)
1421  .addReg(SrcLo);
1422  if (IsDestLive)
1423  T.addReg(Op0.getReg(), RegState::Implicit);
1424  }
1425  MBB.erase(MI);
1426  return true;
1427  }
1428 
1429  case Hexagon::PS_crash: {
1430  // Generate a misaligned load that is guaranteed to cause a crash.
1431  class CrashPseudoSourceValue : public PseudoSourceValue {
1432  public:
1433  CrashPseudoSourceValue(const TargetMachine &TM)
1434  : PseudoSourceValue(TargetCustom, TM) {}
1435 
1436  bool isConstant(const MachineFrameInfo *) const override {
1437  return false;
1438  }
1439  bool isAliased(const MachineFrameInfo *) const override {
1440  return false;
1441  }
1442  bool mayAlias(const MachineFrameInfo *) const override {
1443  return false;
1444  }
1445  void printCustom(raw_ostream &OS) const override {
1446  OS << "MisalignedCrash";
1447  }
1448  };
1449 
1450  static const CrashPseudoSourceValue CrashPSV(MF.getTarget());
1452  MachinePointerInfo(&CrashPSV),
1454  Align(1));
1455  BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
1456  .addImm(0xBADC0FEE) // Misaligned load.
1457  .addMemOperand(MMO);
1458  MBB.erase(MI);
1459  return true;
1460  }
1461 
1462  case Hexagon::PS_tailcall_i:
1463  MI.setDesc(get(Hexagon::J2_jump));
1464  return true;
1465  case Hexagon::PS_tailcall_r:
1466  case Hexagon::PS_jmpret:
1467  MI.setDesc(get(Hexagon::J2_jumpr));
1468  return true;
1469  case Hexagon::PS_jmprett:
1470  MI.setDesc(get(Hexagon::J2_jumprt));
1471  return true;
1472  case Hexagon::PS_jmpretf:
1473  MI.setDesc(get(Hexagon::J2_jumprf));
1474  return true;
1475  case Hexagon::PS_jmprettnewpt:
1476  MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1477  return true;
1478  case Hexagon::PS_jmpretfnewpt:
1479  MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1480  return true;
1481  case Hexagon::PS_jmprettnew:
1482  MI.setDesc(get(Hexagon::J2_jumprtnew));
1483  return true;
1484  case Hexagon::PS_jmpretfnew:
1485  MI.setDesc(get(Hexagon::J2_jumprfnew));
1486  return true;
1487 
1488  case Hexagon::PS_loadrub_pci:
1489  return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1490  case Hexagon::PS_loadrb_pci:
1491  return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1492  case Hexagon::PS_loadruh_pci:
1493  return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1494  case Hexagon::PS_loadrh_pci:
1495  return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1496  case Hexagon::PS_loadri_pci:
1497  return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1498  case Hexagon::PS_loadrd_pci:
1499  return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1500  case Hexagon::PS_loadrub_pcr:
1501  return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1502  case Hexagon::PS_loadrb_pcr:
1503  return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1504  case Hexagon::PS_loadruh_pcr:
1505  return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1506  case Hexagon::PS_loadrh_pcr:
1507  return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1508  case Hexagon::PS_loadri_pcr:
1509  return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1510  case Hexagon::PS_loadrd_pcr:
1511  return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1512  case Hexagon::PS_storerb_pci:
1513  return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1514  case Hexagon::PS_storerh_pci:
1515  return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1516  case Hexagon::PS_storerf_pci:
1517  return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1518  case Hexagon::PS_storeri_pci:
1519  return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1520  case Hexagon::PS_storerd_pci:
1521  return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1522  case Hexagon::PS_storerb_pcr:
1523  return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1524  case Hexagon::PS_storerh_pcr:
1525  return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1526  case Hexagon::PS_storerf_pcr:
1527  return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1528  case Hexagon::PS_storeri_pcr:
1529  return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1530  case Hexagon::PS_storerd_pcr:
1531  return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1532  }
1533 
1534  return false;
1535 }
1536 
1539  MachineBasicBlock &MBB = *MI.getParent();
1540  const DebugLoc &DL = MI.getDebugLoc();
1541  unsigned Opc = MI.getOpcode();
1543 
1544  switch (Opc) {
1545  case Hexagon::V6_vgathermh_pseudo:
1546  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1547  .add(MI.getOperand(2))
1548  .add(MI.getOperand(3))
1549  .add(MI.getOperand(4));
1550  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1551  .add(MI.getOperand(0))
1552  .addImm(MI.getOperand(1).getImm())
1553  .addReg(Hexagon::VTMP);
1554  MBB.erase(MI);
1555  return First.getInstrIterator();
1556 
1557  case Hexagon::V6_vgathermw_pseudo:
1558  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1559  .add(MI.getOperand(2))
1560  .add(MI.getOperand(3))
1561  .add(MI.getOperand(4));
1562  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1563  .add(MI.getOperand(0))
1564  .addImm(MI.getOperand(1).getImm())
1565  .addReg(Hexagon::VTMP);
1566  MBB.erase(MI);
1567  return First.getInstrIterator();
1568 
1569  case Hexagon::V6_vgathermhw_pseudo:
1570  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1571  .add(MI.getOperand(2))
1572  .add(MI.getOperand(3))
1573  .add(MI.getOperand(4));
1574  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1575  .add(MI.getOperand(0))
1576  .addImm(MI.getOperand(1).getImm())
1577  .addReg(Hexagon::VTMP);
1578  MBB.erase(MI);
1579  return First.getInstrIterator();
1580 
1581  case Hexagon::V6_vgathermhq_pseudo:
1582  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1583  .add(MI.getOperand(2))
1584  .add(MI.getOperand(3))
1585  .add(MI.getOperand(4))
1586  .add(MI.getOperand(5));
1587  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1588  .add(MI.getOperand(0))
1589  .addImm(MI.getOperand(1).getImm())
1590  .addReg(Hexagon::VTMP);
1591  MBB.erase(MI);
1592  return First.getInstrIterator();
1593 
1594  case Hexagon::V6_vgathermwq_pseudo:
1595  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1596  .add(MI.getOperand(2))
1597  .add(MI.getOperand(3))
1598  .add(MI.getOperand(4))
1599  .add(MI.getOperand(5));
1600  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1601  .add(MI.getOperand(0))
1602  .addImm(MI.getOperand(1).getImm())
1603  .addReg(Hexagon::VTMP);
1604  MBB.erase(MI);
1605  return First.getInstrIterator();
1606 
1607  case Hexagon::V6_vgathermhwq_pseudo:
1608  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1609  .add(MI.getOperand(2))
1610  .add(MI.getOperand(3))
1611  .add(MI.getOperand(4))
1612  .add(MI.getOperand(5));
1613  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1614  .add(MI.getOperand(0))
1615  .addImm(MI.getOperand(1).getImm())
1616  .addReg(Hexagon::VTMP);
1617  MBB.erase(MI);
1618  return First.getInstrIterator();
1619  }
1620 
1621  return MI.getIterator();
1622 }
1623 
1624 // We indicate that we want to reverse the branch by
1625 // inserting the reversed branching opcode.
1628  if (Cond.empty())
1629  return true;
1630  assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1631  unsigned opcode = Cond[0].getImm();
1632  //unsigned temp;
1633  assert(get(opcode).isBranch() && "Should be a branching condition.");
1634  if (isEndLoopN(opcode))
1635  return true;
1636  unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1637  Cond[0].setImm(NewOpcode);
1638  return false;
1639 }
1640 
1643  DebugLoc DL;
1644  BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1645 }
1646 
1648  return getAddrMode(MI) == HexagonII::PostInc;
1649 }
1650 
1651 // Returns true if an instruction is predicated irrespective of the predicate
1652 // sense. For example, all of the following will return true.
1653 // if (p0) R1 = add(R2, R3)
1654 // if (!p0) R1 = add(R2, R3)
1655 // if (p0.new) R1 = add(R2, R3)
1656 // if (!p0.new) R1 = add(R2, R3)
1657 // Note: New-value stores are not included here as in the current
1658 // implementation, we don't need to check their predicate sense.
1660  const uint64_t F = MI.getDesc().TSFlags;
1662 }
1663 
1666  if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1667  isEndLoopN(Cond[0].getImm())) {
1668  LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1669  return false;
1670  }
1671  int Opc = MI.getOpcode();
1672  assert (isPredicable(MI) && "Expected predicable instruction");
1673  bool invertJump = predOpcodeHasNot(Cond);
1674 
1675  // We have to predicate MI "in place", i.e. after this function returns,
1676  // MI will need to be transformed into a predicated form. To avoid com-
1677  // plicated manipulations with the operands (handling tied operands,
1678  // etc.), build a new temporary instruction, then overwrite MI with it.
1679 
1680  MachineBasicBlock &B = *MI.getParent();
1681  DebugLoc DL = MI.getDebugLoc();
1682  unsigned PredOpc = getCondOpcode(Opc, invertJump);
1683  MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1684  unsigned NOp = 0, NumOps = MI.getNumOperands();
1685  while (NOp < NumOps) {
1686  MachineOperand &Op = MI.getOperand(NOp);
1687  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1688  break;
1689  T.add(Op);
1690  NOp++;
1691  }
1692 
1693  Register PredReg;
1694  unsigned PredRegPos, PredRegFlags;
1695  bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1696  (void)GotPredReg;
1697  assert(GotPredReg);
1698  T.addReg(PredReg, PredRegFlags);
1699  while (NOp < NumOps)
1700  T.add(MI.getOperand(NOp++));
1701 
1702  MI.setDesc(get(PredOpc));
1703  while (unsigned n = MI.getNumOperands())
1704  MI.removeOperand(n-1);
1705  for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1706  MI.addOperand(T->getOperand(i));
1707 
1708  MachineBasicBlock::instr_iterator TI = T->getIterator();
1709  B.erase(TI);
1710 
1711  MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1712  MRI.clearKillFlags(PredReg);
1713  return true;
1714 }
1715 
1717  ArrayRef<MachineOperand> Pred2) const {
1718  // TODO: Fix this
1719  return false;
1720 }
1721 
1723  std::vector<MachineOperand> &Pred,
1724  bool SkipDead) const {
1725  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1726 
1727  for (const MachineOperand &MO : MI.operands()) {
1728  if (MO.isReg()) {
1729  if (!MO.isDef())
1730  continue;
1731  const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1732  if (RC == &Hexagon::PredRegsRegClass) {
1733  Pred.push_back(MO);
1734  return true;
1735  }
1736  continue;
1737  } else if (MO.isRegMask()) {
1738  for (Register PR : Hexagon::PredRegsRegClass) {
1739  if (!MI.modifiesRegister(PR, &HRI))
1740  continue;
1741  Pred.push_back(MO);
1742  return true;
1743  }
1744  }
1745  }
1746  return false;
1747 }
1748 
1750  if (!MI.getDesc().isPredicable())
1751  return false;
1752 
1753  if (MI.isCall() || isTailCall(MI)) {
1754  if (!Subtarget.usePredicatedCalls())
1755  return false;
1756  }
1757 
1758  // HVX loads are not predicable on v60, but are on v62.
1759  if (!Subtarget.hasV62Ops()) {
1760  switch (MI.getOpcode()) {
1761  case Hexagon::V6_vL32b_ai:
1762  case Hexagon::V6_vL32b_pi:
1763  case Hexagon::V6_vL32b_ppu:
1764  case Hexagon::V6_vL32b_cur_ai:
1765  case Hexagon::V6_vL32b_cur_pi:
1766  case Hexagon::V6_vL32b_cur_ppu:
1767  case Hexagon::V6_vL32b_nt_ai:
1768  case Hexagon::V6_vL32b_nt_pi:
1769  case Hexagon::V6_vL32b_nt_ppu:
1770  case Hexagon::V6_vL32b_tmp_ai:
1771  case Hexagon::V6_vL32b_tmp_pi:
1772  case Hexagon::V6_vL32b_tmp_ppu:
1773  case Hexagon::V6_vL32b_nt_cur_ai:
1774  case Hexagon::V6_vL32b_nt_cur_pi:
1775  case Hexagon::V6_vL32b_nt_cur_ppu:
1776  case Hexagon::V6_vL32b_nt_tmp_ai:
1777  case Hexagon::V6_vL32b_nt_tmp_pi:
1778  case Hexagon::V6_vL32b_nt_tmp_ppu:
1779  return false;
1780  }
1781  }
1782  return true;
1783 }
1784 
1786  const MachineBasicBlock *MBB,
1787  const MachineFunction &MF) const {
1788  // Debug info is never a scheduling boundary. It's necessary to be explicit
1789  // due to the special treatment of IT instructions below, otherwise a
1790  // dbg_value followed by an IT will result in the IT instruction being
1791  // considered a scheduling hazard, which is wrong. It should be the actual
1792  // instruction preceding the dbg_value instruction(s), just like it is
1793  // when debug info is not present.
1794  if (MI.isDebugInstr())
1795  return false;
1796 
1797  // Throwing call is a boundary.
1798  if (MI.isCall()) {
1799  // Don't mess around with no return calls.
1800  if (doesNotReturn(MI))
1801  return true;
1802  // If any of the block's successors is a landing pad, this could be a
1803  // throwing call.
1804  for (auto *I : MBB->successors())
1805  if (I->isEHPad())
1806  return true;
1807  }
1808 
1809  // Terminators and labels can't be scheduled around.
1810  if (MI.getDesc().isTerminator() || MI.isPosition())
1811  return true;
1812 
1813  // INLINEASM_BR can jump to another block
1814  if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1815  return true;
1816 
1817  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1818  return true;
1819 
1820  return false;
1821 }
1822 
1823 /// Measure the specified inline asm to determine an approximation of its
1824 /// length.
1825 /// Comments (which run till the next SeparatorString or newline) do not
1826 /// count as an instruction.
1827 /// Any other non-whitespace text is considered an instruction, with
1828 /// multiple instructions separated by SeparatorString or newlines.
1829 /// Variable-length instructions are not handled here; this function
1830 /// may be overloaded in the target code to do that.
1831 /// Hexagon counts the number of ##'s and adjust for that many
1832 /// constant exenders.
1833 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1834  const MCAsmInfo &MAI,
1835  const TargetSubtargetInfo *STI) const {
1836  StringRef AStr(Str);
1837  // Count the number of instructions in the asm.
1838  bool atInsnStart = true;
1839  unsigned Length = 0;
1840  const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
1841  for (; *Str; ++Str) {
1842  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1843  strlen(MAI.getSeparatorString())) == 0)
1844  atInsnStart = true;
1845  if (atInsnStart && !isSpace(static_cast<unsigned char>(*Str))) {
1846  Length += MaxInstLength;
1847  atInsnStart = false;
1848  }
1849  if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1850  MAI.getCommentString().size()) == 0)
1851  atInsnStart = false;
1852  }
1853 
1854  // Add to size number of constant extenders seen * 4.
1855  StringRef Occ("##");
1856  Length += AStr.count(Occ)*4;
1857  return Length;
1858 }
1859 
1862  const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1863  if (UseDFAHazardRec)
1864  return new HexagonHazardRecognizer(II, this, Subtarget);
1866 }
1867 
1868 /// For a comparison instruction, return the source registers in
1869 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1870 /// compares against in CmpValue. Return true if the comparison instruction
1871 /// can be analyzed.
1873  Register &SrcReg2, int64_t &Mask,
1874  int64_t &Value) const {
1875  unsigned Opc = MI.getOpcode();
1876 
1877  // Set mask and the first source register.
1878  switch (Opc) {
1879  case Hexagon::C2_cmpeq:
1880  case Hexagon::C2_cmpeqp:
1881  case Hexagon::C2_cmpgt:
1882  case Hexagon::C2_cmpgtp:
1883  case Hexagon::C2_cmpgtu:
1884  case Hexagon::C2_cmpgtup:
1885  case Hexagon::C4_cmpneq:
1886  case Hexagon::C4_cmplte:
1887  case Hexagon::C4_cmplteu:
1888  case Hexagon::C2_cmpeqi:
1889  case Hexagon::C2_cmpgti:
1890  case Hexagon::C2_cmpgtui:
1891  case Hexagon::C4_cmpneqi:
1892  case Hexagon::C4_cmplteui:
1893  case Hexagon::C4_cmpltei:
1894  SrcReg = MI.getOperand(1).getReg();
1895  Mask = ~0;
1896  break;
1897  case Hexagon::A4_cmpbeq:
1898  case Hexagon::A4_cmpbgt:
1899  case Hexagon::A4_cmpbgtu:
1900  case Hexagon::A4_cmpbeqi:
1901  case Hexagon::A4_cmpbgti:
1902  case Hexagon::A4_cmpbgtui:
1903  SrcReg = MI.getOperand(1).getReg();
1904  Mask = 0xFF;
1905  break;
1906  case Hexagon::A4_cmpheq:
1907  case Hexagon::A4_cmphgt:
1908  case Hexagon::A4_cmphgtu:
1909  case Hexagon::A4_cmpheqi:
1910  case Hexagon::A4_cmphgti:
1911  case Hexagon::A4_cmphgtui:
1912  SrcReg = MI.getOperand(1).getReg();
1913  Mask = 0xFFFF;
1914  break;
1915  }
1916 
1917  // Set the value/second source register.
1918  switch (Opc) {
1919  case Hexagon::C2_cmpeq:
1920  case Hexagon::C2_cmpeqp:
1921  case Hexagon::C2_cmpgt:
1922  case Hexagon::C2_cmpgtp:
1923  case Hexagon::C2_cmpgtu:
1924  case Hexagon::C2_cmpgtup:
1925  case Hexagon::A4_cmpbeq:
1926  case Hexagon::A4_cmpbgt:
1927  case Hexagon::A4_cmpbgtu:
1928  case Hexagon::A4_cmpheq:
1929  case Hexagon::A4_cmphgt:
1930  case Hexagon::A4_cmphgtu:
1931  case Hexagon::C4_cmpneq:
1932  case Hexagon::C4_cmplte:
1933  case Hexagon::C4_cmplteu:
1934  SrcReg2 = MI.getOperand(2).getReg();
1935  Value = 0;
1936  return true;
1937 
1938  case Hexagon::C2_cmpeqi:
1939  case Hexagon::C2_cmpgtui:
1940  case Hexagon::C2_cmpgti:
1941  case Hexagon::C4_cmpneqi:
1942  case Hexagon::C4_cmplteui:
1943  case Hexagon::C4_cmpltei:
1944  case Hexagon::A4_cmpbeqi:
1945  case Hexagon::A4_cmpbgti:
1946  case Hexagon::A4_cmpbgtui:
1947  case Hexagon::A4_cmpheqi:
1948  case Hexagon::A4_cmphgti:
1949  case Hexagon::A4_cmphgtui: {
1950  SrcReg2 = 0;
1951  const MachineOperand &Op2 = MI.getOperand(2);
1952  if (!Op2.isImm())
1953  return false;
1954  Value = MI.getOperand(2).getImm();
1955  return true;
1956  }
1957  }
1958 
1959  return false;
1960 }
1961 
1963  const MachineInstr &MI,
1964  unsigned *PredCost) const {
1965  return getInstrTimingClassLatency(ItinData, MI);
1966 }
1967 
1969  const TargetSubtargetInfo &STI) const {
1970  const InstrItineraryData *II = STI.getInstrItineraryData();
1971  return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1972 }
1973 
1974 // Inspired by this pair:
1975 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1976 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1977 // Currently AA considers the addresses in these instructions to be aliasing.
1979  const MachineInstr &MIa, const MachineInstr &MIb) const {
1980  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1982  return false;
1983 
1984  // Instructions that are pure loads, not loads and stores like memops are not
1985  // dependent.
1986  if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1987  return true;
1988 
1989  // Get the base register in MIa.
1990  unsigned BasePosA, OffsetPosA;
1991  if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1992  return false;
1993  const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1994  Register BaseRegA = BaseA.getReg();
1995  unsigned BaseSubA = BaseA.getSubReg();
1996 
1997  // Get the base register in MIb.
1998  unsigned BasePosB, OffsetPosB;
1999  if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
2000  return false;
2001  const MachineOperand &BaseB = MIb.getOperand(BasePosB);
2002  Register BaseRegB = BaseB.getReg();
2003  unsigned BaseSubB = BaseB.getSubReg();
2004 
2005  if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
2006  return false;
2007 
2008  // Get the access sizes.
2009  unsigned SizeA = getMemAccessSize(MIa);
2010  unsigned SizeB = getMemAccessSize(MIb);
2011 
2012  // Get the offsets. Handle immediates only for now.
2013  const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
2014  const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
2015  if (!MIa.getOperand(OffsetPosA).isImm() ||
2016  !MIb.getOperand(OffsetPosB).isImm())
2017  return false;
2018  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
2019  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
2020 
2021  // This is a mem access with the same base register and known offsets from it.
2022  // Reason about it.
2023  if (OffsetA > OffsetB) {
2024  uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
2025  return SizeB <= OffDiff;
2026  }
2027  if (OffsetA < OffsetB) {
2028  uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
2029  return SizeA <= OffDiff;
2030  }
2031 
2032  return false;
2033 }
2034 
2035 /// If the instruction is an increment of a constant value, return the amount.
2037  int &Value) const {
2038  if (isPostIncrement(MI)) {
2039  unsigned BasePos = 0, OffsetPos = 0;
2040  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
2041  return false;
2042  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
2043  if (OffsetOp.isImm()) {
2044  Value = OffsetOp.getImm();
2045  return true;
2046  }
2047  } else if (MI.getOpcode() == Hexagon::A2_addi) {
2048  const MachineOperand &AddOp = MI.getOperand(2);
2049  if (AddOp.isImm()) {
2050  Value = AddOp.getImm();
2051  return true;
2052  }
2053  }
2054 
2055  return false;
2056 }
2057 
2058 std::pair<unsigned, unsigned>
2060  return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
2061  TF & HexagonII::MO_Bitmasks);
2062 }
2063 
2066  using namespace HexagonII;
2067 
2068  static const std::pair<unsigned, const char*> Flags[] = {
2069  {MO_PCREL, "hexagon-pcrel"},
2070  {MO_GOT, "hexagon-got"},
2071  {MO_LO16, "hexagon-lo16"},
2072  {MO_HI16, "hexagon-hi16"},
2073  {MO_GPREL, "hexagon-gprel"},
2074  {MO_GDGOT, "hexagon-gdgot"},
2075  {MO_GDPLT, "hexagon-gdplt"},
2076  {MO_IE, "hexagon-ie"},
2077  {MO_IEGOT, "hexagon-iegot"},
2078  {MO_TPREL, "hexagon-tprel"}
2079  };
2080  return makeArrayRef(Flags);
2081 }
2082 
2085  using namespace HexagonII;
2086 
2087  static const std::pair<unsigned, const char*> Flags[] = {
2088  {HMOTF_ConstExtended, "hexagon-ext"}
2089  };
2090  return makeArrayRef(Flags);
2091 }
2092 
2095  const TargetRegisterClass *TRC;
2096  if (VT == MVT::i1) {
2097  TRC = &Hexagon::PredRegsRegClass;
2098  } else if (VT == MVT::i32 || VT == MVT::f32) {
2099  TRC = &Hexagon::IntRegsRegClass;
2100  } else if (VT == MVT::i64 || VT == MVT::f64) {
2101  TRC = &Hexagon::DoubleRegsRegClass;
2102  } else {
2103  llvm_unreachable("Cannot handle this register class");
2104  }
2105 
2106  Register NewReg = MRI.createVirtualRegister(TRC);
2107  return NewReg;
2108 }
2109 
2111  return (getAddrMode(MI) == HexagonII::AbsoluteSet);
2112 }
2113 
2115  const uint64_t F = MI.getDesc().TSFlags;
2117 }
2118 
2121 }
2122 
2124  return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
2125  !MI.getDesc().mayStore() &&
2126  MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2127  MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2128  !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
2129 }
2130 
2131 // Return true if the instruction is a compound branch instruction.
2133  return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
2134 }
2135 
2136 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
2137 // isFPImm and later getFPImm as well.
2139  const uint64_t F = MI.getDesc().TSFlags;
2141  if (isExtended) // Instruction must be extended.
2142  return true;
2143 
2144  unsigned isExtendable =
2146  if (!isExtendable)
2147  return false;
2148 
2149  if (MI.isCall())
2150  return false;
2151 
2152  short ExtOpNum = getCExtOpNum(MI);
2153  const MachineOperand &MO = MI.getOperand(ExtOpNum);
2154  // Use MO operand flags to determine if MO
2155  // has the HMOTF_ConstExtended flag set.
2157  return true;
2158  // If this is a Machine BB address we are talking about, and it is
2159  // not marked as extended, say so.
2160  if (MO.isMBB())
2161  return false;
2162 
2163  // We could be using an instruction with an extendable immediate and shoehorn
2164  // a global address into it. If it is a global address it will be constant
2165  // extended. We do this for COMBINE.
2166  if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2167  MO.isJTI() || MO.isCPI() || MO.isFPImm())
2168  return true;
2169 
2170  // If the extendable operand is not 'Immediate' type, the instruction should
2171  // have 'isExtended' flag set.
2172  assert(MO.isImm() && "Extendable operand must be Immediate type");
2173 
2174  int MinValue = getMinValue(MI);
2175  int MaxValue = getMaxValue(MI);
2176  int ImmValue = MO.getImm();
2177 
2178  return (ImmValue < MinValue || ImmValue > MaxValue);
2179 }
2180 
2182  switch (MI.getOpcode()) {
2183  case Hexagon::L4_return:
2184  case Hexagon::L4_return_t:
2185  case Hexagon::L4_return_f:
2186  case Hexagon::L4_return_tnew_pnt:
2187  case Hexagon::L4_return_fnew_pnt:
2188  case Hexagon::L4_return_tnew_pt:
2189  case Hexagon::L4_return_fnew_pt:
2190  return true;
2191  }
2192  return false;
2193 }
2194 
2195 // Return true when ConsMI uses a register defined by ProdMI.
2197  const MachineInstr &ConsMI) const {
2198  if (!ProdMI.getDesc().getNumDefs())
2199  return false;
2200  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2201 
2206 
2207  parseOperands(ProdMI, DefsA, UsesA);
2208  parseOperands(ConsMI, DefsB, UsesB);
2209 
2210  for (auto &RegA : DefsA)
2211  for (auto &RegB : UsesB) {
2212  // True data dependency.
2213  if (RegA == RegB)
2214  return true;
2215 
2216  if (Register::isPhysicalRegister(RegA))
2217  for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
2218  if (RegB == *SubRegs)
2219  return true;
2220 
2221  if (Register::isPhysicalRegister(RegB))
2222  for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
2223  if (RegA == *SubRegs)
2224  return true;
2225  }
2226 
2227  return false;
2228 }
2229 
2230 // Returns true if the instruction is alread a .cur.
2232  switch (MI.getOpcode()) {
2233  case Hexagon::V6_vL32b_cur_pi:
2234  case Hexagon::V6_vL32b_cur_ai:
2235  return true;
2236  }
2237  return false;
2238 }
2239 
2240 // Returns true, if any one of the operands is a dot new
2241 // insn, whether it is predicated dot new or register dot new.
2244  return true;
2245 
2246  return false;
2247 }
2248 
2249 /// Symmetrical. See if these two instructions are fit for duplex pair.
2251  const MachineInstr &MIb) const {
2254  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2255 }
2256 
2257 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2258  return (Opcode == Hexagon::ENDLOOP0 ||
2259  Opcode == Hexagon::ENDLOOP1);
2260 }
2261 
2262 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2263  switch(OpType) {
2270  return true;
2271  default:
2272  return false;
2273  }
2274 }
2275 
2277  const MCInstrDesc &MID = MI.getDesc();
2278  const uint64_t F = MID.TSFlags;
2280  return true;
2281 
2282  // TODO: This is largely obsolete now. Will need to be removed
2283  // in consecutive patches.
2284  switch (MI.getOpcode()) {
2285  // PS_fi and PS_fia remain special cases.
2286  case Hexagon::PS_fi:
2287  case Hexagon::PS_fia:
2288  return true;
2289  default:
2290  return false;
2291  }
2292  return false;
2293 }
2294 
2295 // This returns true in two cases:
2296 // - The OP code itself indicates that this is an extended instruction.
2297 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2299  // First check if this is permanently extended op code.
2300  const uint64_t F = MI.getDesc().TSFlags;
2302  return true;
2303  // Use MO operand flags to determine if one of MI's operands
2304  // has HMOTF_ConstExtended flag set.
2305  for (const MachineOperand &MO : MI.operands())
2306  if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2307  return true;
2308  return false;
2309 }
2310 
2312  unsigned Opcode = MI.getOpcode();
2313  const uint64_t F = get(Opcode).TSFlags;
2314  return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2315 }
2316 
2317 // No V60 HVX VMEM with A_INDIRECT.
2319  const MachineInstr &J) const {
2320  if (!isHVXVec(I))
2321  return false;
2322  if (!I.mayLoad() && !I.mayStore())
2323  return false;
2324  return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2325 }
2326 
2328  switch (MI.getOpcode()) {
2329  case Hexagon::J2_callr:
2330  case Hexagon::J2_callrf:
2331  case Hexagon::J2_callrt:
2332  case Hexagon::PS_call_nr:
2333  return true;
2334  }
2335  return false;
2336 }
2337 
2339  switch (MI.getOpcode()) {
2340  case Hexagon::L4_return:
2341  case Hexagon::L4_return_t:
2342  case Hexagon::L4_return_f:
2343  case Hexagon::L4_return_fnew_pnt:
2344  case Hexagon::L4_return_fnew_pt:
2345  case Hexagon::L4_return_tnew_pnt:
2346  case Hexagon::L4_return_tnew_pt:
2347  return true;
2348  }
2349  return false;
2350 }
2351 
2353  switch (MI.getOpcode()) {
2354  case Hexagon::J2_jumpr:
2355  case Hexagon::J2_jumprt:
2356  case Hexagon::J2_jumprf:
2357  case Hexagon::J2_jumprtnewpt:
2358  case Hexagon::J2_jumprfnewpt:
2359  case Hexagon::J2_jumprtnew:
2360  case Hexagon::J2_jumprfnew:
2361  return true;
2362  }
2363  return false;
2364 }
2365 
2366 // Return true if a given MI can accommodate given offset.
2367 // Use abs estimate as oppose to the exact number.
2368 // TODO: This will need to be changed to use MC level
2369 // definition of instruction extendable field size.
2371  unsigned offset) const {
2372  // This selection of jump instructions matches to that what
2373  // analyzeBranch can parse, plus NVJ.
2374  if (isNewValueJump(MI)) // r9:2
2375  return isInt<11>(offset);
2376 
2377  switch (MI.getOpcode()) {
2378  // Still missing Jump to address condition on register value.
2379  default:
2380  return false;
2381  case Hexagon::J2_jump: // bits<24> dst; // r22:2
2382  case Hexagon::J2_call:
2383  case Hexagon::PS_call_nr:
2384  return isInt<24>(offset);
2385  case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2386  case Hexagon::J2_jumpf:
2387  case Hexagon::J2_jumptnew:
2388  case Hexagon::J2_jumptnewpt:
2389  case Hexagon::J2_jumpfnew:
2390  case Hexagon::J2_jumpfnewpt:
2391  case Hexagon::J2_callt:
2392  case Hexagon::J2_callf:
2393  return isInt<17>(offset);
2394  case Hexagon::J2_loop0i:
2395  case Hexagon::J2_loop0iext:
2396  case Hexagon::J2_loop0r:
2397  case Hexagon::J2_loop0rext:
2398  case Hexagon::J2_loop1i:
2399  case Hexagon::J2_loop1iext:
2400  case Hexagon::J2_loop1r:
2401  case Hexagon::J2_loop1rext:
2402  return isInt<9>(offset);
2403  // TODO: Add all the compound branches here. Can we do this in Relation model?
2404  case Hexagon::J4_cmpeqi_tp0_jump_nt:
2405  case Hexagon::J4_cmpeqi_tp1_jump_nt:
2406  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2407  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2408  return isInt<11>(offset);
2409  }
2410 }
2411 
2413  // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2414  // resource, but all operands can be received late like an ALU instruction.
2416 }
2417 
2419  unsigned Opcode = MI.getOpcode();
2420  return Opcode == Hexagon::J2_loop0i ||
2421  Opcode == Hexagon::J2_loop0r ||
2422  Opcode == Hexagon::J2_loop0iext ||
2423  Opcode == Hexagon::J2_loop0rext ||
2424  Opcode == Hexagon::J2_loop1i ||
2425  Opcode == Hexagon::J2_loop1r ||
2426  Opcode == Hexagon::J2_loop1iext ||
2427  Opcode == Hexagon::J2_loop1rext;
2428 }
2429 
2431  switch (MI.getOpcode()) {
2432  default: return false;
2433  case Hexagon::L4_iadd_memopw_io:
2434  case Hexagon::L4_isub_memopw_io:
2435  case Hexagon::L4_add_memopw_io:
2436  case Hexagon::L4_sub_memopw_io:
2437  case Hexagon::L4_and_memopw_io:
2438  case Hexagon::L4_or_memopw_io:
2439  case Hexagon::L4_iadd_memoph_io:
2440  case Hexagon::L4_isub_memoph_io:
2441  case Hexagon::L4_add_memoph_io:
2442  case Hexagon::L4_sub_memoph_io:
2443  case Hexagon::L4_and_memoph_io:
2444  case Hexagon::L4_or_memoph_io:
2445  case Hexagon::L4_iadd_memopb_io:
2446  case Hexagon::L4_isub_memopb_io:
2447  case Hexagon::L4_add_memopb_io:
2448  case Hexagon::L4_sub_memopb_io:
2449  case Hexagon::L4_and_memopb_io:
2450  case Hexagon::L4_or_memopb_io:
2451  case Hexagon::L4_ior_memopb_io:
2452  case Hexagon::L4_ior_memoph_io:
2453  case Hexagon::L4_ior_memopw_io:
2454  case Hexagon::L4_iand_memopb_io:
2455  case Hexagon::L4_iand_memoph_io:
2456  case Hexagon::L4_iand_memopw_io:
2457  return true;
2458  }
2459  return false;
2460 }
2461 
2463  const uint64_t F = MI.getDesc().TSFlags;
2465 }
2466 
2467 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2468  const uint64_t F = get(Opcode).TSFlags;
2470 }
2471 
2473  return isNewValueJump(MI) || isNewValueStore(MI);
2474 }
2475 
2477  return isNewValue(MI) && MI.isBranch();
2478 }
2479 
2480 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2481  return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2482 }
2483 
2485  const uint64_t F = MI.getDesc().TSFlags;
2487 }
2488 
2489 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2490  const uint64_t F = get(Opcode).TSFlags;
2492 }
2493 
2494 // Returns true if a particular operand is extendable for an instruction.
2496  unsigned OperandNum) const {
2497  const uint64_t F = MI.getDesc().TSFlags;
2499  == OperandNum;
2500 }
2501 
2503  const uint64_t F = MI.getDesc().TSFlags;
2506 }
2507 
2508 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2509  const uint64_t F = get(Opcode).TSFlags;
2510  assert(isPredicated(Opcode));
2512 }
2513 
2515  const uint64_t F = MI.getDesc().TSFlags;
2516  return !((F >> HexagonII::PredicatedFalsePos) &
2518 }
2519 
2520 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2521  const uint64_t F = get(Opcode).TSFlags;
2522  // Make sure that the instruction is predicated.
2524  return !((F >> HexagonII::PredicatedFalsePos) &
2526 }
2527 
2528 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2529  const uint64_t F = get(Opcode).TSFlags;
2531 }
2532 
2533 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2534  const uint64_t F = get(Opcode).TSFlags;
2536 }
2537 
2538 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2539  const uint64_t F = get(Opcode).TSFlags;
2540  assert(get(Opcode).isBranch() &&
2541  (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2543 }
2544 
2546  return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2547  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2548  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2549  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2550 }
2551 
2553  switch (MI.getOpcode()) {
2554  // Byte
2555  case Hexagon::L2_loadrb_io:
2556  case Hexagon::L4_loadrb_ur:
2557  case Hexagon::L4_loadrb_ap:
2558  case Hexagon::L2_loadrb_pr:
2559  case Hexagon::L2_loadrb_pbr:
2560  case Hexagon::L2_loadrb_pi:
2561  case Hexagon::L2_loadrb_pci:
2562  case Hexagon::L2_loadrb_pcr:
2563  case Hexagon::L2_loadbsw2_io:
2564  case Hexagon::L4_loadbsw2_ur:
2565  case Hexagon::L4_loadbsw2_ap:
2566  case Hexagon::L2_loadbsw2_pr:
2567  case Hexagon::L2_loadbsw2_pbr:
2568  case Hexagon::L2_loadbsw2_pi:
2569  case Hexagon::L2_loadbsw2_pci:
2570  case Hexagon::L2_loadbsw2_pcr:
2571  case Hexagon::L2_loadbsw4_io:
2572  case Hexagon::L4_loadbsw4_ur:
2573  case Hexagon::L4_loadbsw4_ap:
2574  case Hexagon::L2_loadbsw4_pr:
2575  case Hexagon::L2_loadbsw4_pbr:
2576  case Hexagon::L2_loadbsw4_pi:
2577  case Hexagon::L2_loadbsw4_pci:
2578  case Hexagon::L2_loadbsw4_pcr:
2579  case Hexagon::L4_loadrb_rr:
2580  case Hexagon::L2_ploadrbt_io:
2581  case Hexagon::L2_ploadrbt_pi:
2582  case Hexagon::L2_ploadrbf_io:
2583  case Hexagon::L2_ploadrbf_pi:
2584  case Hexagon::L2_ploadrbtnew_io:
2585  case Hexagon::L2_ploadrbfnew_io:
2586  case Hexagon::L4_ploadrbt_rr:
2587  case Hexagon::L4_ploadrbf_rr:
2588  case Hexagon::L4_ploadrbtnew_rr:
2589  case Hexagon::L4_ploadrbfnew_rr:
2590  case Hexagon::L2_ploadrbtnew_pi:
2591  case Hexagon::L2_ploadrbfnew_pi:
2592  case Hexagon::L4_ploadrbt_abs:
2593  case Hexagon::L4_ploadrbf_abs:
2594  case Hexagon::L4_ploadrbtnew_abs:
2595  case Hexagon::L4_ploadrbfnew_abs:
2596  case Hexagon::L2_loadrbgp:
2597  // Half
2598  case Hexagon::L2_loadrh_io:
2599  case Hexagon::L4_loadrh_ur:
2600  case Hexagon::L4_loadrh_ap:
2601  case Hexagon::L2_loadrh_pr:
2602  case Hexagon::L2_loadrh_pbr:
2603  case Hexagon::L2_loadrh_pi:
2604  case Hexagon::L2_loadrh_pci:
2605  case Hexagon::L2_loadrh_pcr:
2606  case Hexagon::L4_loadrh_rr:
2607  case Hexagon::L2_ploadrht_io:
2608  case Hexagon::L2_ploadrht_pi:
2609  case Hexagon::L2_ploadrhf_io:
2610  case Hexagon::L2_ploadrhf_pi:
2611  case Hexagon::L2_ploadrhtnew_io:
2612  case Hexagon::L2_ploadrhfnew_io:
2613  case Hexagon::L4_ploadrht_rr:
2614  case Hexagon::L4_ploadrhf_rr:
2615  case Hexagon::L4_ploadrhtnew_rr:
2616  case Hexagon::L4_ploadrhfnew_rr:
2617  case Hexagon::L2_ploadrhtnew_pi:
2618  case Hexagon::L2_ploadrhfnew_pi:
2619  case Hexagon::L4_ploadrht_abs:
2620  case Hexagon::L4_ploadrhf_abs:
2621  case Hexagon::L4_ploadrhtnew_abs:
2622  case Hexagon::L4_ploadrhfnew_abs:
2623  case Hexagon::L2_loadrhgp:
2624  return true;
2625  default:
2626  return false;
2627  }
2628 }
2629 
2631  const uint64_t F = MI.getDesc().TSFlags;
2633 }
2634 
2636  switch (MI.getOpcode()) {
2637  case Hexagon::STriw_pred:
2638  case Hexagon::LDriw_pred:
2639  return true;
2640  default:
2641  return false;
2642  }
2643 }
2644 
2646  if (!MI.isBranch())
2647  return false;
2648 
2649  for (auto &Op : MI.operands())
2650  if (Op.isGlobal() || Op.isSymbol())
2651  return true;
2652  return false;
2653 }
2654 
2655 // Returns true when SU has a timing class TC1.
2657  unsigned SchedClass = MI.getDesc().getSchedClass();
2658  return is_TC1(SchedClass);
2659 }
2660 
2662  unsigned SchedClass = MI.getDesc().getSchedClass();
2663  return is_TC2(SchedClass);
2664 }
2665 
2667  unsigned SchedClass = MI.getDesc().getSchedClass();
2668  return is_TC2early(SchedClass);
2669 }
2670 
2672  unsigned SchedClass = MI.getDesc().getSchedClass();
2673  return is_TC4x(SchedClass);
2674 }
2675 
2676 // Schedule this ASAP.
2678  const MachineInstr &MI2) const {
2679  if (mayBeCurLoad(MI1)) {
2680  // if (result of SU is used in Next) return true;
2681  Register DstReg = MI1.getOperand(0).getReg();
2682  int N = MI2.getNumOperands();
2683  for (int I = 0; I < N; I++)
2684  if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2685  return true;
2686  }
2687  if (mayBeNewStore(MI2))
2688  if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2689  if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2690  MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2691  return true;
2692  return false;
2693 }
2694 
2696  const uint64_t V = getType(MI);
2698 }
2699 
2700 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2701 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const {
2702  int Size = VT.getSizeInBits() / 8;
2703  if (Offset % Size != 0)
2704  return false;
2705  int Count = Offset / Size;
2706 
2707  switch (VT.getSimpleVT().SimpleTy) {
2708  // For scalars the auto-inc is s4
2709  case MVT::i8:
2710  case MVT::i16:
2711  case MVT::i32:
2712  case MVT::i64:
2713  case MVT::f32:
2714  case MVT::f64:
2715  case MVT::v2i16:
2716  case MVT::v2i32:
2717  case MVT::v4i8:
2718  case MVT::v4i16:
2719  case MVT::v8i8:
2720  return isInt<4>(Count);
2721  // For HVX vectors the auto-inc is s3
2722  case MVT::v64i8:
2723  case MVT::v32i16:
2724  case MVT::v16i32:
2725  case MVT::v8i64:
2726  case MVT::v128i8:
2727  case MVT::v64i16:
2728  case MVT::v32i32:
2729  case MVT::v16i64:
2730  return isInt<3>(Count);
2731  default:
2732  break;
2733  }
2734 
2735  llvm_unreachable("Not an valid type!");
2736 }
2737 
2738 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2739  const TargetRegisterInfo *TRI, bool Extend) const {
2740  // This function is to check whether the "Offset" is in the correct range of
2741  // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2742  // inserted to calculate the final address. Due to this reason, the function
2743  // assumes that the "Offset" has correct alignment.
2744  // We used to assert if the offset was not properly aligned, however,
2745  // there are cases where a misaligned pointer recast can cause this
2746  // problem, and we need to allow for it. The front end warns of such
2747  // misaligns with respect to load size.
2748  switch (Opcode) {
2749  case Hexagon::PS_vstorerq_ai:
2750  case Hexagon::PS_vstorerv_ai:
2751  case Hexagon::PS_vstorerw_ai:
2752  case Hexagon::PS_vstorerw_nt_ai:
2753  case Hexagon::PS_vloadrq_ai:
2754  case Hexagon::PS_vloadrv_ai:
2755  case Hexagon::PS_vloadrw_ai:
2756  case Hexagon::PS_vloadrw_nt_ai:
2757  case Hexagon::V6_vL32b_ai:
2758  case Hexagon::V6_vS32b_ai:
2759  case Hexagon::V6_vS32b_qpred_ai:
2760  case Hexagon::V6_vS32b_nqpred_ai:
2761  case Hexagon::V6_vL32b_nt_ai:
2762  case Hexagon::V6_vS32b_nt_ai:
2763  case Hexagon::V6_vL32Ub_ai:
2764  case Hexagon::V6_vS32Ub_ai:
2765  case Hexagon::V6_vgathermh_pseudo:
2766  case Hexagon::V6_vgathermw_pseudo:
2767  case Hexagon::V6_vgathermhw_pseudo:
2768  case Hexagon::V6_vgathermhq_pseudo:
2769  case Hexagon::V6_vgathermwq_pseudo:
2770  case Hexagon::V6_vgathermhwq_pseudo: {
2771  unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2772  assert(isPowerOf2_32(VectorSize));
2773  if (Offset & (VectorSize-1))
2774  return false;
2775  return isInt<4>(Offset >> Log2_32(VectorSize));
2776  }
2777 
2778  case Hexagon::J2_loop0i:
2779  case Hexagon::J2_loop1i:
2780  return isUInt<10>(Offset);
2781 
2782  case Hexagon::S4_storeirb_io:
2783  case Hexagon::S4_storeirbt_io:
2784  case Hexagon::S4_storeirbf_io:
2785  return isUInt<6>(Offset);
2786 
2787  case Hexagon::S4_storeirh_io:
2788  case Hexagon::S4_storeirht_io:
2789  case Hexagon::S4_storeirhf_io:
2790  return isShiftedUInt<6,1>(Offset);
2791 
2792  case Hexagon::S4_storeiri_io:
2793  case Hexagon::S4_storeirit_io:
2794  case Hexagon::S4_storeirif_io:
2795  return isShiftedUInt<6,2>(Offset);
2796  // Handle these two compare instructions that are not extendable.
2797  case Hexagon::A4_cmpbeqi:
2798  return isUInt<8>(Offset);
2799  case Hexagon::A4_cmpbgti:
2800  return isInt<8>(Offset);
2801  }
2802 
2803  if (Extend)
2804  return true;
2805 
2806  switch (Opcode) {
2807  case Hexagon::L2_loadri_io:
2808  case Hexagon::S2_storeri_io:
2809  return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2810  (Offset <= Hexagon_MEMW_OFFSET_MAX);
2811 
2812  case Hexagon::L2_loadrd_io:
2813  case Hexagon::S2_storerd_io:
2814  return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2815  (Offset <= Hexagon_MEMD_OFFSET_MAX);
2816 
2817  case Hexagon::L2_loadrh_io:
2818  case Hexagon::L2_loadruh_io:
2819  case Hexagon::S2_storerh_io:
2820  case Hexagon::S2_storerf_io:
2821  return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2822  (Offset <= Hexagon_MEMH_OFFSET_MAX);
2823 
2824  case Hexagon::L2_loadrb_io:
2825  case Hexagon::L2_loadrub_io:
2826  case Hexagon::S2_storerb_io:
2827  return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2828  (Offset <= Hexagon_MEMB_OFFSET_MAX);
2829 
2830  case Hexagon::A2_addi:
2831  return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2832  (Offset <= Hexagon_ADDI_OFFSET_MAX);
2833 
2834  case Hexagon::L4_iadd_memopw_io:
2835  case Hexagon::L4_isub_memopw_io:
2836  case Hexagon::L4_add_memopw_io:
2837  case Hexagon::L4_sub_memopw_io:
2838  case Hexagon::L4_iand_memopw_io:
2839  case Hexagon::L4_ior_memopw_io:
2840  case Hexagon::L4_and_memopw_io:
2841  case Hexagon::L4_or_memopw_io:
2842  return (0 <= Offset && Offset <= 255);
2843 
2844  case Hexagon::L4_iadd_memoph_io:
2845  case Hexagon::L4_isub_memoph_io:
2846  case Hexagon::L4_add_memoph_io:
2847  case Hexagon::L4_sub_memoph_io:
2848  case Hexagon::L4_iand_memoph_io:
2849  case Hexagon::L4_ior_memoph_io:
2850  case Hexagon::L4_and_memoph_io:
2851  case Hexagon::L4_or_memoph_io:
2852  return (0 <= Offset && Offset <= 127);
2853 
2854  case Hexagon::L4_iadd_memopb_io:
2855  case Hexagon::L4_isub_memopb_io:
2856  case Hexagon::L4_add_memopb_io:
2857  case Hexagon::L4_sub_memopb_io:
2858  case Hexagon::L4_iand_memopb_io:
2859  case Hexagon::L4_ior_memopb_io:
2860  case Hexagon::L4_and_memopb_io:
2861  case Hexagon::L4_or_memopb_io:
2862  return (0 <= Offset && Offset <= 63);
2863 
2864  // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2865  // any size. Later pass knows how to handle it.
2866  case Hexagon::STriw_pred:
2867  case Hexagon::LDriw_pred:
2868  case Hexagon::STriw_ctr:
2869  case Hexagon::LDriw_ctr:
2870  return true;
2871 
2872  case Hexagon::PS_fi:
2873  case Hexagon::PS_fia:
2874  case Hexagon::INLINEASM:
2875  return true;
2876 
2877  case Hexagon::L2_ploadrbt_io:
2878  case Hexagon::L2_ploadrbf_io:
2879  case Hexagon::L2_ploadrubt_io:
2880  case Hexagon::L2_ploadrubf_io:
2881  case Hexagon::S2_pstorerbt_io:
2882  case Hexagon::S2_pstorerbf_io:
2883  return isUInt<6>(Offset);
2884 
2885  case Hexagon::L2_ploadrht_io:
2886  case Hexagon::L2_ploadrhf_io:
2887  case Hexagon::L2_ploadruht_io:
2888  case Hexagon::L2_ploadruhf_io:
2889  case Hexagon::S2_pstorerht_io:
2890  case Hexagon::S2_pstorerhf_io:
2891  return isShiftedUInt<6,1>(Offset);
2892 
2893  case Hexagon::L2_ploadrit_io:
2894  case Hexagon::L2_ploadrif_io:
2895  case Hexagon::S2_pstorerit_io:
2896  case Hexagon::S2_pstorerif_io:
2897  return isShiftedUInt<6,2>(Offset);
2898 
2899  case Hexagon::L2_ploadrdt_io:
2900  case Hexagon::L2_ploadrdf_io:
2901  case Hexagon::S2_pstorerdt_io:
2902  case Hexagon::S2_pstorerdf_io:
2903  return isShiftedUInt<6,3>(Offset);
2904 
2905  case Hexagon::L2_loadbsw2_io:
2906  case Hexagon::L2_loadbzw2_io:
2907  return isShiftedInt<11,1>(Offset);
2908 
2909  case Hexagon::L2_loadbsw4_io:
2910  case Hexagon::L2_loadbzw4_io:
2911  return isShiftedInt<11,2>(Offset);
2912  } // switch
2913 
2914  dbgs() << "Failed Opcode is : " << Opcode << " (" << getName(Opcode)
2915  << ")\n";
2916  llvm_unreachable("No offset range is defined for this opcode. "
2917  "Please define it in the above switch statement!");
2918 }
2919 
2921  return isHVXVec(MI) && isAccumulator(MI);
2922 }
2923 
2925  const uint64_t F = get(MI.getOpcode()).TSFlags;
2926  const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2927  return
2928  V == HexagonII::TypeCVI_VA ||
2930 }
2931 
2933  const MachineInstr &ConsMI) const {
2934  if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2935  return true;
2936 
2937  if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2938  return true;
2939 
2940  if (mayBeNewStore(ConsMI))
2941  return true;
2942 
2943  return false;
2944 }
2945 
2947  switch (MI.getOpcode()) {
2948  // Byte
2949  case Hexagon::L2_loadrub_io:
2950  case Hexagon::L4_loadrub_ur:
2951  case Hexagon::L4_loadrub_ap:
2952  case Hexagon::L2_loadrub_pr:
2953  case Hexagon::L2_loadrub_pbr:
2954  case Hexagon::L2_loadrub_pi:
2955  case Hexagon::L2_loadrub_pci:
2956  case Hexagon::L2_loadrub_pcr:
2957  case Hexagon::L2_loadbzw2_io:
2958  case Hexagon::L4_loadbzw2_ur:
2959  case Hexagon::L4_loadbzw2_ap:
2960  case Hexagon::L2_loadbzw2_pr:
2961  case Hexagon::L2_loadbzw2_pbr:
2962  case Hexagon::L2_loadbzw2_pi:
2963  case Hexagon::L2_loadbzw2_pci:
2964  case Hexagon::L2_loadbzw2_pcr:
2965  case Hexagon::L2_loadbzw4_io:
2966  case Hexagon::L4_loadbzw4_ur:
2967  case Hexagon::L4_loadbzw4_ap:
2968  case Hexagon::L2_loadbzw4_pr:
2969  case Hexagon::L2_loadbzw4_pbr:
2970  case Hexagon::L2_loadbzw4_pi:
2971  case Hexagon::L2_loadbzw4_pci:
2972  case Hexagon::L2_loadbzw4_pcr:
2973  case Hexagon::L4_loadrub_rr:
2974  case Hexagon::L2_ploadrubt_io:
2975  case Hexagon::L2_ploadrubt_pi:
2976  case Hexagon::L2_ploadrubf_io:
2977  case Hexagon::L2_ploadrubf_pi:
2978  case Hexagon::L2_ploadrubtnew_io:
2979  case Hexagon::L2_ploadrubfnew_io:
2980  case Hexagon::L4_ploadrubt_rr:
2981  case Hexagon::L4_ploadrubf_rr:
2982  case Hexagon::L4_ploadrubtnew_rr:
2983  case Hexagon::L4_ploadrubfnew_rr:
2984  case Hexagon::L2_ploadrubtnew_pi:
2985  case Hexagon::L2_ploadrubfnew_pi:
2986  case Hexagon::L4_ploadrubt_abs:
2987  case Hexagon::L4_ploadrubf_abs:
2988  case Hexagon::L4_ploadrubtnew_abs:
2989  case Hexagon::L4_ploadrubfnew_abs:
2990  case Hexagon::L2_loadrubgp:
2991  // Half
2992  case Hexagon::L2_loadruh_io:
2993  case Hexagon::L4_loadruh_ur:
2994  case Hexagon::L4_loadruh_ap:
2995  case Hexagon::L2_loadruh_pr:
2996  case Hexagon::L2_loadruh_pbr:
2997  case Hexagon::L2_loadruh_pi:
2998  case Hexagon::L2_loadruh_pci:
2999  case Hexagon::L2_loadruh_pcr:
3000  case Hexagon::L4_loadruh_rr:
3001  case Hexagon::L2_ploadruht_io:
3002  case Hexagon::L2_ploadruht_pi:
3003  case Hexagon::L2_ploadruhf_io:
3004  case Hexagon::L2_ploadruhf_pi:
3005  case Hexagon::L2_ploadruhtnew_io:
3006  case Hexagon::L2_ploadruhfnew_io:
3007  case Hexagon::L4_ploadruht_rr:
3008  case Hexagon::L4_ploadruhf_rr:
3009  case Hexagon::L4_ploadruhtnew_rr:
3010  case Hexagon::L4_ploadruhfnew_rr:
3011  case Hexagon::L2_ploadruhtnew_pi:
3012  case Hexagon::L2_ploadruhfnew_pi:
3013  case Hexagon::L4_ploadruht_abs:
3014  case Hexagon::L4_ploadruhf_abs:
3015  case Hexagon::L4_ploadruhtnew_abs:
3016  case Hexagon::L4_ploadruhfnew_abs:
3017  case Hexagon::L2_loadruhgp:
3018  return true;
3019  default:
3020  return false;
3021  }
3022 }
3023 
3024 // Add latency to instruction.
3026  const MachineInstr &MI2) const {
3027  if (isHVXVec(MI1) && isHVXVec(MI2))
3028  if (!isVecUsableNextPacket(MI1, MI2))
3029  return true;
3030  return false;
3031 }
3032 
3033 /// Get the base register and byte offset of a load/store instr.
3036  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
3037  const TargetRegisterInfo *TRI) const {
3038  OffsetIsScalable = false;
3039  const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width);
3040  if (!BaseOp || !BaseOp->isReg())
3041  return false;
3042  BaseOps.push_back(BaseOp);
3043  return true;
3044 }
3045 
3046 /// Can these instructions execute at the same time in a bundle.
3048  const MachineInstr &Second) const {
3049  if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
3050  const MachineOperand &Op = Second.getOperand(0);
3051  if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
3052  return true;
3053  }
3054  if (DisableNVSchedule)
3055  return false;
3056  if (mayBeNewStore(Second)) {
3057  // Make sure the definition of the first instruction is the value being
3058  // stored.
3059  const MachineOperand &Stored =
3060  Second.getOperand(Second.getNumOperands() - 1);
3061  if (!Stored.isReg())
3062  return false;
3063  for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
3064  const MachineOperand &Op = First.getOperand(i);
3065  if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3066  return true;
3067  }
3068  }
3069  return false;
3070 }
3071 
3073  unsigned Opc = CallMI.getOpcode();
3074  return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
3075 }
3076 
3078  for (auto &I : *B)
3079  if (I.isEHLabel())
3080  return true;
3081  return false;
3082 }
3083 
3084 // Returns true if an instruction can be converted into a non-extended
3085 // equivalent instruction.
3087  short NonExtOpcode;
3088  // Check if the instruction has a register form that uses register in place
3089  // of the extended operand, if so return that as the non-extended form.
3090  if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
3091  return true;
3092 
3093  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
3094  // Check addressing mode and retrieve non-ext equivalent instruction.
3095 
3096  switch (getAddrMode(MI)) {
3097  case HexagonII::Absolute:
3098  // Load/store with absolute addressing mode can be converted into
3099  // base+offset mode.
3100  NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
3101  break;
3103  // Load/store with base+offset addressing mode can be converted into
3104  // base+register offset addressing mode. However left shift operand should
3105  // be set to 0.
3106  NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
3107  break;
3109  NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
3110  break;
3111  default:
3112  return false;
3113  }
3114  if (NonExtOpcode < 0)
3115  return false;
3116  return true;
3117  }
3118  return false;
3119 }
3120 
3122  return Hexagon::getRealHWInstr(MI.getOpcode(),
3123  Hexagon::InstrType_Pseudo) >= 0;
3124 }
3125 
3127  const {
3128  MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
3129  while (I != E) {
3130  if (I->isBarrier())
3131  return true;
3132  ++I;
3133  }
3134  return false;
3135 }
3136 
3137 // Returns true, if a LD insn can be promoted to a cur load.
3139  const uint64_t F = MI.getDesc().TSFlags;
3141  Subtarget.hasV60Ops();
3142 }
3143 
3144 // Returns true, if a ST insn can be promoted to a new-value store.
3146  if (MI.mayStore() && !Subtarget.useNewValueStores())
3147  return false;
3148 
3149  const uint64_t F = MI.getDesc().TSFlags;
3151 }
3152 
3154  const MachineInstr &ConsMI) const {
3155  // There is no stall when ProdMI is not a V60 vector.
3156  if (!isHVXVec(ProdMI))
3157  return false;
3158 
3159  // There is no stall when ProdMI and ConsMI are not dependent.
3160  if (!isDependent(ProdMI, ConsMI))
3161  return false;
3162 
3163  // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3164  // are scheduled in consecutive packets.
3165  if (isVecUsableNextPacket(ProdMI, ConsMI))
3166  return false;
3167 
3168  return true;
3169 }
3170 
3173  // There is no stall when I is not a V60 vector.
3174  if (!isHVXVec(MI))
3175  return false;
3176 
3178  MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3179 
3180  if (!MII->isBundle())
3181  return producesStall(*MII, MI);
3182 
3183  for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3184  const MachineInstr &J = *MII;
3185  if (producesStall(J, MI))
3186  return true;
3187  }
3188  return false;
3189 }
3190 
3192  Register PredReg) const {
3193  for (const MachineOperand &MO : MI.operands()) {
3194  // Predicate register must be explicitly defined.
3195  if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3196  return false;
3197  if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3198  return false;
3199  }
3200 
3201  // Instruction that produce late predicate cannot be used as sources of
3202  // dot-new.
3203  switch (MI.getOpcode()) {
3204  case Hexagon::A4_addp_c:
3205  case Hexagon::A4_subp_c:
3206  case Hexagon::A4_tlbmatch:
3207  case Hexagon::A5_ACS:
3208  case Hexagon::F2_sfinvsqrta:
3209  case Hexagon::F2_sfrecipa:
3210  case Hexagon::J2_endloop0:
3211  case Hexagon::J2_endloop01:
3212  case Hexagon::J2_ploop1si:
3213  case Hexagon::J2_ploop1sr:
3214  case Hexagon::J2_ploop2si:
3215  case Hexagon::J2_ploop2sr:
3216  case Hexagon::J2_ploop3si:
3217  case Hexagon::J2_ploop3sr:
3218  case Hexagon::S2_cabacdecbin:
3219  case Hexagon::S2_storew_locked:
3220  case Hexagon::S4_stored_locked:
3221  return false;
3222  }
3223  return true;
3224 }
3225 
3226 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3227  return Opcode == Hexagon::J2_jumpt ||
3228  Opcode == Hexagon::J2_jumptpt ||
3229  Opcode == Hexagon::J2_jumpf ||
3230  Opcode == Hexagon::J2_jumpfpt ||
3231  Opcode == Hexagon::J2_jumptnew ||
3232  Opcode == Hexagon::J2_jumpfnew ||
3233  Opcode == Hexagon::J2_jumptnewpt ||
3234  Opcode == Hexagon::J2_jumpfnewpt;
3235 }
3236 
3238  if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3239  return false;
3240  return !isPredicatedTrue(Cond[0].getImm());
3241 }
3242 
3244  const uint64_t F = MI.getDesc().TSFlags;
3246 }
3247 
3248 // Returns the base register in a memory access (load/store). The offset is
3249 // returned in Offset and the access size is returned in AccessSize.
3250 // If the base operand has a subregister or the offset field does not contain
3251 // an immediate value, return nullptr.
3253  int64_t &Offset,
3254  unsigned &AccessSize) const {
3255  // Return if it is not a base+offset type instruction or a MemOp.
3258  !isMemOp(MI) && !isPostIncrement(MI))
3259  return nullptr;
3260 
3261  AccessSize = getMemAccessSize(MI);
3262 
3263  unsigned BasePos = 0, OffsetPos = 0;
3264  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3265  return nullptr;
3266 
3267  // Post increment updates its EA after the mem access,
3268  // so we need to treat its offset as zero.
3269  if (isPostIncrement(MI)) {
3270  Offset = 0;
3271  } else {
3272  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3273  if (!OffsetOp.isImm())
3274  return nullptr;
3275  Offset = OffsetOp.getImm();
3276  }
3277 
3278  const MachineOperand &BaseOp = MI.getOperand(BasePos);
3279  if (BaseOp.getSubReg() != 0)
3280  return nullptr;
3281  return &const_cast<MachineOperand&>(BaseOp);
3282 }
3283 
3284 /// Return the position of the base and offset operands for this instruction.
3286  unsigned &BasePos, unsigned &OffsetPos) const {
3288  return false;
3289 
3290  // Deal with memops first.
3291  if (isMemOp(MI)) {
3292  BasePos = 0;
3293  OffsetPos = 1;
3294  } else if (MI.mayStore()) {
3295  BasePos = 0;
3296  OffsetPos = 1;
3297  } else if (MI.mayLoad()) {
3298  BasePos = 1;
3299  OffsetPos = 2;
3300  } else
3301  return false;
3302 
3303  if (isPredicated(MI)) {
3304  BasePos++;
3305  OffsetPos++;
3306  }
3307  if (isPostIncrement(MI)) {
3308  BasePos++;
3309  OffsetPos++;
3310  }
3311 
3312  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3313  return false;
3314 
3315  return true;
3316 }
3317 
3318 // Inserts branching instructions in reverse order of their occurrence.
3319 // e.g. jump_t t1 (i1)
3320 // jump t2 (i2)
3321 // Jumpers = {i2, i1}
3323  MachineBasicBlock& MBB) const {
3325  // If the block has no terminators, it just falls into the block after it.
3327  if (I == MBB.instr_begin())
3328  return Jumpers;
3329 
3330  // A basic block may looks like this:
3331  //
3332  // [ insn
3333  // EH_LABEL
3334  // insn
3335  // insn
3336  // insn
3337  // EH_LABEL
3338  // insn ]
3339  //
3340  // It has two succs but does not have a terminator
3341  // Don't know how to handle it.
3342  do {
3343  --I;
3344  if (I->isEHLabel())
3345  return Jumpers;
3346  } while (I != MBB.instr_begin());
3347 
3348  I = MBB.instr_end();
3349  --I;
3350 
3351  while (I->isDebugInstr()) {
3352  if (I == MBB.instr_begin())
3353  return Jumpers;
3354  --I;
3355  }
3356  if (!isUnpredicatedTerminator(*I))
3357  return Jumpers;
3358 
3359  // Get the last instruction in the block.
3360  MachineInstr *LastInst = &*I;
3361  Jumpers.push_back(LastInst);
3362  MachineInstr *SecondLastInst = nullptr;
3363  // Find one more terminator if present.
3364  do {
3365  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3366  if (!SecondLastInst) {
3367  SecondLastInst = &*I;
3368  Jumpers.push_back(SecondLastInst);
3369  } else // This is a third branch.
3370  return Jumpers;
3371  }
3372  if (I == MBB.instr_begin())
3373  break;
3374  --I;
3375  } while (true);
3376  return Jumpers;
3377 }
3378 
3379 // Returns Operand Index for the constant extended instruction.
3381  const uint64_t F = MI.getDesc().TSFlags;
3383 }
3384 
3385 // See if instruction could potentially be a duplex candidate.
3386 // If so, return its group. Zero otherwise.
3388  const MachineInstr &MI) const {
3389  Register DstReg, SrcReg, Src1Reg, Src2Reg;
3390 
3391  switch (MI.getOpcode()) {
3392  default:
3393  return HexagonII::HCG_None;
3394  //
3395  // Compound pairs.
3396  // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3397  // "Rd16=#U6 ; jump #r9:2"
3398  // "Rd16=Rs16 ; jump #r9:2"
3399  //
3400  case Hexagon::C2_cmpeq:
3401  case Hexagon::C2_cmpgt:
3402  case Hexagon::C2_cmpgtu:
3403  DstReg = MI.getOperand(0).getReg();
3404  Src1Reg = MI.getOperand(1).getReg();
3405  Src2Reg = MI.getOperand(2).getReg();
3406  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3407  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3408  isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3409  return HexagonII::HCG_A;
3410  break;
3411  case Hexagon::C2_cmpeqi:
3412  case Hexagon::C2_cmpgti:
3413  case Hexagon::C2_cmpgtui:
3414  // P0 = cmp.eq(Rs,#u2)
3415  DstReg = MI.getOperand(0).getReg();
3416  SrcReg = MI.getOperand(1).getReg();
3417  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3418  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3419  isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3420  ((isUInt<5>(MI.getOperand(2).getImm())) ||
3421  (MI.getOperand(2).getImm() == -1)))
3422  return HexagonII::HCG_A;
3423  break;
3424  case Hexagon::A2_tfr:
3425  // Rd = Rs
3426  DstReg = MI.getOperand(0).getReg();
3427  SrcReg = MI.getOperand(1).getReg();
3428  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3429  return HexagonII::HCG_A;
3430  break;
3431  case Hexagon::A2_tfrsi:
3432  // Rd = #u6
3433  // Do not test for #u6 size since the const is getting extended
3434  // regardless and compound could be formed.
3435  DstReg = MI.getOperand(0).getReg();
3436  if (isIntRegForSubInst(DstReg))
3437  return HexagonII::HCG_A;
3438  break;
3439  case Hexagon::S2_tstbit_i:
3440  DstReg = MI.getOperand(0).getReg();
3441  Src1Reg = MI.getOperand(1).getReg();
3442  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3443  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3444  MI.getOperand(2).isImm() &&
3445  isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3446  return HexagonII::HCG_A;
3447  break;
3448  // The fact that .new form is used pretty much guarantees
3449  // that predicate register will match. Nevertheless,
3450  // there could be some false positives without additional
3451  // checking.
3452  case Hexagon::J2_jumptnew:
3453  case Hexagon::J2_jumpfnew:
3454  case Hexagon::J2_jumptnewpt:
3455  case Hexagon::J2_jumpfnewpt:
3456  Src1Reg = MI.getOperand(0).getReg();
3457  if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3458  (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3459  return HexagonII::HCG_B;
3460  break;
3461  // Transfer and jump:
3462  // Rd=#U6 ; jump #r9:2
3463  // Rd=Rs ; jump #r9:2
3464  // Do not test for jump range here.
3465  case Hexagon::J2_jump:
3466  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3467  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3468  return HexagonII::HCG_C;
3469  }
3470 
3471  return HexagonII::HCG_None;
3472 }
3473 
3474 // Returns -1 when there is no opcode found.
3476  const MachineInstr &GB) const {
3479  if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3480  (GB.getOpcode() != Hexagon::J2_jumptnew))
3481  return -1u;
3482  Register DestReg = GA.getOperand(0).getReg();
3483  if (!GB.readsRegister(DestReg))
3484  return -1u;
3485  if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3486  return -1u;
3487  // The value compared against must be either u5 or -1.
3488  const MachineOperand &CmpOp = GA.getOperand(2);
3489  if (!CmpOp.isImm())
3490  return -1u;
3491  int V = CmpOp.getImm();
3492  if (V == -1)
3493  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3494  : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3495  if (!isUInt<5>(V))
3496  return -1u;
3497  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3498  : Hexagon::J4_cmpeqi_tp1_jump_nt;
3499 }
3500 
3501 // Returns -1 if there is no opcode found.
3503  bool ForBigCore) const {
3504  // Static table to switch the opcodes across Tiny Core and Big Core.
3505  // dup_ opcodes are Big core opcodes.
3506  // NOTE: There are special instructions that need to handled later.
3507  // L4_return* instructions, they will only occupy SLOT0 (on big core too).
3508  // PS_jmpret - This pseudo translates to J2_jumpr which occupies only SLOT2.
3509  // The compiler need to base the root instruction to L6_return_map_to_raw
3510  // which can go any slot.
3511  static const std::map<unsigned, unsigned> DupMap = {
3512  {Hexagon::A2_add, Hexagon::dup_A2_add},
3513  {Hexagon::A2_addi, Hexagon::dup_A2_addi},
3514  {Hexagon::A2_andir, Hexagon::dup_A2_andir},
3515  {Hexagon::A2_combineii, Hexagon::dup_A2_combineii},
3516  {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb},
3517  {Hexagon::A2_sxth, Hexagon::dup_A2_sxth},
3518  {Hexagon::A2_tfr, Hexagon::dup_A2_tfr},
3519  {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi},
3520  {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb},
3521  {Hexagon::A2_zxth, Hexagon::dup_A2_zxth},
3522  {Hexagon::A4_combineii, Hexagon::dup_A4_combineii},
3523  {Hexagon::A4_combineir, Hexagon::dup_A4_combineir},
3524  {Hexagon::A4_combineri, Hexagon::dup_A4_combineri},
3525  {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif},
3526  {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit},
3527  {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif},
3528  {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit},
3529  {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi},
3530  {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe},
3531  {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io},
3532  {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io},
3533  {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io},
3534  {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io},
3535  {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io},
3536  {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io},
3537  {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe},
3538  {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io},
3539  {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io},
3540  {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io},
3541  {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io},
3542  {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io},
3543  {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io},
3544  };
3545  unsigned OpNum = MI.getOpcode();
3546  // Conversion to Big core.
3547  if (ForBigCore) {
3548  auto Iter = DupMap.find(OpNum);
3549  if (Iter != DupMap.end())
3550  return Iter->second;
3551  } else { // Conversion to Tiny core.
3552  for (const auto &Iter : DupMap)
3553  if (Iter.second == OpNum)
3554  return Iter.first;
3555  }
3556  return -1;
3557 }
3558 
3559 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3560  enum Hexagon::PredSense inPredSense;
3561  inPredSense = invertPredicate ? Hexagon::PredSense_false :
3562  Hexagon::PredSense_true;
3563  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3564  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3565  return CondOpcode;
3566 
3567  llvm_unreachable("Unexpected predicable instruction");
3568 }
3569 
3570 // Return the cur value instruction for a given store.
3572  switch (MI.getOpcode()) {
3573  default: llvm_unreachable("Unknown .cur type");
3574  case Hexagon::V6_vL32b_pi:
3575  return Hexagon::V6_vL32b_cur_pi;
3576  case Hexagon::V6_vL32b_ai:
3577  return Hexagon::V6_vL32b_cur_ai;
3578  case Hexagon::V6_vL32b_nt_pi:
3579  return Hexagon::V6_vL32b_nt_cur_pi;
3580  case Hexagon::V6_vL32b_nt_ai:
3581  return Hexagon::V6_vL32b_nt_cur_ai;
3582  case Hexagon::V6_vL32b_ppu:
3583  return Hexagon::V6_vL32b_cur_ppu;
3584  case Hexagon::V6_vL32b_nt_ppu:
3585  return Hexagon::V6_vL32b_nt_cur_ppu;
3586  }
3587  return 0;
3588 }
3589 
3590 // Return the regular version of the .cur instruction.
3592  switch (MI.getOpcode()) {
3593  default: llvm_unreachable("Unknown .cur type");
3594  case Hexagon::V6_vL32b_cur_pi:
3595  return Hexagon::V6_vL32b_pi;
3596  case Hexagon::V6_vL32b_cur_ai:
3597  return Hexagon::V6_vL32b_ai;
3598  case Hexagon::V6_vL32b_nt_cur_pi:
3599  return Hexagon::V6_vL32b_nt_pi;
3600  case Hexagon::V6_vL32b_nt_cur_ai:
3601  return Hexagon::V6_vL32b_nt_ai;
3602  case Hexagon::V6_vL32b_cur_ppu:
3603  return Hexagon::V6_vL32b_ppu;
3604  case Hexagon::V6_vL32b_nt_cur_ppu:
3605  return Hexagon::V6_vL32b_nt_ppu;
3606  }
3607  return 0;
3608 }
3609 
3610 // The diagram below shows the steps involved in the conversion of a predicated
3611 // store instruction to its .new predicated new-value form.
3612 //
3613 // Note: It doesn't include conditional new-value stores as they can't be
3614 // converted to .new predicate.
3615 //
3616 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3617 // ^ ^
3618 // / \ (not OK. it will cause new-value store to be
3619 // / X conditional on p0.new while R2 producer is
3620 // / \ on p0)
3621 // / \.
3622 // p.new store p.old NV store
3623 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3624 // ^ ^
3625 // \ /
3626 // \ /
3627 // \ /
3628 // p.old store
3629 // [if (p0)memw(R0+#0)=R2]
3630 //
3631 // The following set of instructions further explains the scenario where
3632 // conditional new-value store becomes invalid when promoted to .new predicate
3633 // form.
3634 //
3635 // { 1) if (p0) r0 = add(r1, r2)
3636 // 2) p0 = cmp.eq(r3, #0) }
3637 //
3638 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3639 // the first two instructions because in instr 1, r0 is conditional on old value
3640 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3641 // is not valid for new-value stores.
3642 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3643 // from the "Conditional Store" list. Because a predicated new value store
3644 // would NOT be promoted to a double dot new store. See diagram below:
3645 // This function returns yes for those stores that are predicated but not
3646 // yet promoted to predicate dot new instructions.
3647 //
3648 // +---------------------+
3649 // /-----| if (p0) memw(..)=r0 |---------\~
3650 // || +---------------------+ ||
3651 // promote || /\ /\ || promote
3652 // || /||\ /||\ ||
3653 // \||/ demote || \||/
3654 // \/ || || \/
3655 // +-------------------------+ || +-------------------------+
3656 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3657 // +-------------------------+ || +-------------------------+
3658 // || || ||
3659 // || demote \||/
3660 // promote || \/ NOT possible
3661 // || || /\~
3662 // \||/ || /||\~
3663 // \/ || ||
3664 // +-----------------------------+
3665 // | if (p0.new) memw(..)=r0.new |
3666 // +-----------------------------+
3667 // Double Dot New Store
3668 //
3669 // Returns the most basic instruction for the .new predicated instructions and
3670 // new-value stores.
3671 // For example, all of the following instructions will be converted back to the
3672 // same instruction:
3673 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3674 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3675 // 3) if (p0.new) memw(R0+#0) = R1 --->
3676 //
3677 // To understand the translation of instruction 1 to its original form, consider
3678 // a packet with 3 instructions.
3679 // { p0 = cmp.eq(R0,R1)
3680 // if (p0.new) R2 = add(R3, R4)
3681 // R5 = add (R3, R1)
3682 // }
3683 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3684 //
3685 // This instruction can be part of the previous packet only if both p0 and R2
3686 // are promoted to .new values. This promotion happens in steps, first
3687 // predicate register is promoted to .new and in the next iteration R2 is
3688 // promoted. Therefore, in case of dependence check failure (due to R5) during
3689 // next iteration, it should be converted back to its most basic form.
3690 
3691 // Return the new value instruction for a given store.
3693  int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3694  if (NVOpcode >= 0) // Valid new-value store instruction.
3695  return NVOpcode;
3696 
3697  switch (MI.getOpcode()) {
3698  default:
3699  report_fatal_error(Twine("Unknown .new type: ") +
3700  std::to_string(MI.getOpcode()));
3701  case Hexagon::S4_storerb_ur:
3702  return Hexagon::S4_storerbnew_ur;
3703 
3704  case Hexagon::S2_storerb_pci:
3705  return Hexagon::S2_storerb_pci;
3706 
3707  case Hexagon::S2_storeri_pci:
3708  return Hexagon::S2_storeri_pci;
3709 
3710  case Hexagon::S2_storerh_pci:
3711  return Hexagon::S2_storerh_pci;
3712 
3713  case Hexagon::S2_storerd_pci:
3714  return Hexagon::S2_storerd_pci;
3715 
3716  case Hexagon::S2_storerf_pci:
3717  return Hexagon::S2_storerf_pci;
3718 
3719  case Hexagon::V6_vS32b_ai:
3720  return Hexagon::V6_vS32b_new_ai;
3721 
3722  case Hexagon::V6_vS32b_pi:
3723  return Hexagon::V6_vS32b_new_pi;
3724  }
3725  return 0;
3726 }
3727 
3728 // Returns the opcode to use when converting MI, which is a conditional jump,
3729 // into a conditional instruction which uses the .new value of the predicate.
3730 // We also use branch probabilities to add a hint to the jump.
3731 // If MBPI is null, all edges will be treated as equally likely for the
3732 // purposes of establishing a predication hint.
3734  const MachineBranchProbabilityInfo *MBPI) const {
3735  // We assume that block can have at most two successors.
3736  const MachineBasicBlock *Src = MI.getParent();
3737  const MachineOperand &BrTarget = MI.getOperand(1);
3738  bool Taken = false;
3739  const BranchProbability OneHalf(1, 2);
3740 
3741  auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3742  const MachineBasicBlock *Dst) {
3743  if (MBPI)
3744  return MBPI->getEdgeProbability(Src, Dst);
3745  return BranchProbability(1, Src->succ_size());
3746  };
3747 
3748  if (BrTarget.isMBB()) {
3749  const MachineBasicBlock *Dst = BrTarget.getMBB();
3750  Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3751  } else {
3752  // The branch target is not a basic block (most likely a function).
3753  // Since BPI only gives probabilities for targets that are basic blocks,
3754  // try to identify another target of this branch (potentially a fall-
3755  // -through) and check the probability of that target.
3756  //
3757  // The only handled branch combinations are:
3758  // - one conditional branch,
3759  // - one conditional branch followed by one unconditional branch.
3760  // Otherwise, assume not-taken.
3761  assert(MI.isConditionalBranch());
3762  const MachineBasicBlock &B = *MI.getParent();
3763  bool SawCond = false, Bad = false;
3764  for (const MachineInstr &I : B) {
3765  if (!I.isBranch())
3766  continue;
3767  if (I.isConditionalBranch()) {
3768  SawCond = true;
3769  if (&I != &MI) {
3770  Bad = true;
3771  break;
3772  }
3773  }
3774  if (I.isUnconditionalBranch() && !SawCond) {
3775  Bad = true;
3776  break;
3777  }
3778  }
3779  if (!Bad) {
3781  MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3782  if (NextIt == B.instr_end()) {
3783  // If this branch is the last, look for the fall-through block.
3784  for (const MachineBasicBlock *SB : B.successors()) {
3785  if (!B.isLayoutSuccessor(SB))
3786  continue;
3787  Taken = getEdgeProbability(Src, SB) < OneHalf;
3788  break;
3789  }
3790  } else {
3791  assert(NextIt->isUnconditionalBranch());
3792  // Find the first MBB operand and assume it's the target.
3793  const MachineBasicBlock *BT = nullptr;
3794  for (const MachineOperand &Op : NextIt->operands()) {
3795  if (!Op.isMBB())
3796  continue;
3797  BT = Op.getMBB();
3798  break;
3799  }
3800  Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3801  }
3802  } // if (!Bad)
3803  }
3804 
3805  // The Taken flag should be set to something reasonable by this point.
3806 
3807  switch (MI.getOpcode()) {
3808  case Hexagon::J2_jumpt:
3809  return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3810  case Hexagon::J2_jumpf:
3811  return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3812 
3813  default:
3814  llvm_unreachable("Unexpected jump instruction.");
3815  }
3816 }
3817 
3818 // Return .new predicate version for an instruction.
3820  const MachineBranchProbabilityInfo *MBPI) const {
3821  switch (MI.getOpcode()) {
3822  // Condtional Jumps
3823  case Hexagon::J2_jumpt:
3824  case Hexagon::J2_jumpf:
3825  return getDotNewPredJumpOp(MI, MBPI);
3826  }
3827 
3828  int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3829  if (NewOpcode >= 0)
3830  return NewOpcode;
3831  return 0;
3832 }
3833 
3835  int NewOp = MI.getOpcode();
3836  if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3837  NewOp = Hexagon::getPredOldOpcode(NewOp);
3838  // All Hexagon architectures have prediction bits on dot-new branches,
3839  // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3840  // to pick the right opcode when converting back to dot-old.
3841  if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3842  switch (NewOp) {
3843  case Hexagon::J2_jumptpt:
3844  NewOp = Hexagon::J2_jumpt;
3845  break;
3846  case Hexagon::J2_jumpfpt:
3847  NewOp = Hexagon::J2_jumpf;
3848  break;
3849  case Hexagon::J2_jumprtpt:
3850  NewOp = Hexagon::J2_jumprt;
3851  break;
3852  case Hexagon::J2_jumprfpt:
3853  NewOp = Hexagon::J2_jumprf;
3854  break;
3855  }
3856  }
3857  assert(NewOp >= 0 &&
3858  "Couldn't change predicate new instruction to its old form.");
3859  }
3860 
3861  if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3862  NewOp = Hexagon::getNonNVStore(NewOp);
3863  assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3864  }
3865 
3866  if (Subtarget.hasV60Ops())
3867  return NewOp;
3868 
3869  // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3870  switch (NewOp) {
3871  case Hexagon::J2_jumpfpt:
3872  return Hexagon::J2_jumpf;
3873  case Hexagon::J2_jumptpt:
3874  return Hexagon::J2_jumpt;
3875  case Hexagon::J2_jumprfpt:
3876  return Hexagon::J2_jumprf;
3877  case Hexagon::J2_jumprtpt:
3878  return Hexagon::J2_jumprt;
3879  }
3880  return NewOp;
3881 }
3882 
3883 // See if instruction could potentially be a duplex candidate.
3884 // If so, return its group. Zero otherwise.
3886  const MachineInstr &MI) const {
3887  Register DstReg, SrcReg, Src1Reg, Src2Reg;
3888  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3889 
3890  switch (MI.getOpcode()) {
3891  default:
3892  return HexagonII::HSIG_None;
3893  //
3894  // Group L1:
3895  //
3896  // Rd = memw(Rs+#u4:2)
3897  // Rd = memub(Rs+#u4:0)
3898  case Hexagon::L2_loadri_io:
3899  case Hexagon::dup_L2_loadri_io:
3900  DstReg = MI.getOperand(0).getReg();
3901  SrcReg = MI.getOperand(1).getReg();
3902  // Special case this one from Group L2.
3903  // Rd = memw(r29+#u5:2)
3904  if (isIntRegForSubInst(DstReg)) {
3905  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3906  HRI.getStackRegister() == SrcReg &&
3907  MI.getOperand(2).isImm() &&
3908  isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3909  return HexagonII::HSIG_L2;
3910  // Rd = memw(Rs+#u4:2)
3911  if (isIntRegForSubInst(SrcReg) &&
3912  (MI.getOperand(2).isImm() &&
3913  isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3914  return HexagonII::HSIG_L1;
3915  }
3916  break;
3917  case Hexagon::L2_loadrub_io:
3918  case Hexagon::dup_L2_loadrub_io:
3919  // Rd = memub(Rs+#u4:0)
3920  DstReg = MI.getOperand(0).getReg();
3921  SrcReg = MI.getOperand(1).getReg();
3922  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3923  MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3924  return HexagonII::HSIG_L1;
3925  break;
3926  //
3927  // Group L2:
3928  //
3929  // Rd = memh/memuh(Rs+#u3:1)
3930  // Rd = memb(Rs+#u3:0)
3931  // Rd = memw(r29+#u5:2) - Handled above.
3932  // Rdd = memd(r29+#u5:3)
3933  // deallocframe
3934  // [if ([!]p0[.new])] dealloc_return
3935  // [if ([!]p0[.new])] jumpr r31
3936  case Hexagon::L2_loadrh_io:
3937  case Hexagon::L2_loadruh_io:
3938  case Hexagon::dup_L2_loadrh_io:
3939  case Hexagon::dup_L2_loadruh_io:
3940  // Rd = memh/memuh(Rs+#u3:1)
3941  DstReg = MI.getOperand(0).getReg();
3942  SrcReg = MI.getOperand(1).getReg();
3943  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3944  MI.getOperand(2).isImm() &&
3945  isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3946  return HexagonII::HSIG_L2;
3947  break;
3948  case Hexagon::L2_loadrb_io:
3949  case Hexagon::dup_L2_loadrb_io:
3950  // Rd = memb(Rs+#u3:0)
3951  DstReg = MI.getOperand(0).getReg();
3952  SrcReg = MI.getOperand(1).getReg();
3953  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3954  MI.getOperand(2).isImm() &&
3955  isUInt<3>(MI.getOperand(2).getImm()))
3956  return HexagonII::HSIG_L2;
3957  break;
3958  case Hexagon::L2_loadrd_io:
3959  case Hexagon::dup_L2_loadrd_io:
3960  // Rdd = memd(r29+#u5:3)
3961  DstReg = MI.getOperand(0).getReg();
3962  SrcReg = MI.getOperand(1).getReg();
3963  if (isDblRegForSubInst(DstReg, HRI) &&
3964  Hexagon::IntRegsRegClass.contains(SrcReg) &&
3965  HRI.getStackRegister() == SrcReg &&
3966  MI.getOperand(2).isImm() &&
3967  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3968  return HexagonII::HSIG_L2;
3969  break;
3970  // dealloc_return is not documented in Hexagon Manual, but marked
3971  // with A_SUBINSN attribute in iset_v4classic.py.
3972  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3973  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3974  case Hexagon::L4_return:
3975  case Hexagon::L2_deallocframe:
3976  case Hexagon::dup_L2_deallocframe:
3977  return HexagonII::HSIG_L2;
3978  case Hexagon::EH_RETURN_JMPR:
3979  case Hexagon::PS_jmpret:
3980  case Hexagon::SL2_jumpr31:
3981  // jumpr r31
3982  // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
3983  DstReg = MI.getOperand(0).getReg();
3984  if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3985  return HexagonII::HSIG_L2;
3986  break;
3987  case Hexagon::PS_jmprett:
3988  case Hexagon::PS_jmpretf:
3989  case Hexagon::PS_jmprettnewpt:
3990  case Hexagon::PS_jmpretfnewpt:
3991  case Hexagon::PS_jmprettnew:
3992  case Hexagon::PS_jmpretfnew:
3993  case Hexagon::SL2_jumpr31_t:
3994  case Hexagon::SL2_jumpr31_f:
3995  case Hexagon::SL2_jumpr31_tnew:
3996  case Hexagon::SL2_jumpr31_fnew:
3997  DstReg = MI.getOperand(1).getReg();
3998  SrcReg = MI.getOperand(0).getReg();
3999  // [if ([!]p0[.new])] jumpr r31
4000  if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
4001  (Hexagon::P0 == SrcReg)) &&
4002  (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
4003  return HexagonII::HSIG_L2;
4004  break;
4005  case Hexagon::L4_return_t:
4006  case Hexagon::L4_return_f:
4007  case Hexagon::L4_return_tnew_pnt:
4008  case Hexagon::L4_return_fnew_pnt:
4009  case Hexagon::L4_return_tnew_pt:
4010  case Hexagon::L4_return_fnew_pt:
4011  // [if ([!]p0[.new])] dealloc_return
4012  SrcReg = MI.getOperand(0).getReg();
4013  if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
4014  return HexagonII::HSIG_L2;
4015  break;
4016  //
4017  // Group S1:
4018  //
4019  // memw(Rs+#u4:2) = Rt
4020  // memb(Rs+#u4:0) = Rt
4021  case Hexagon::S2_storeri_io:
4022  case Hexagon::dup_S2_storeri_io:
4023  // Special case this one from Group S2.
4024  // memw(r29+#u5:2) = Rt
4025  Src1Reg = MI.getOperand(0).getReg();
4026  Src2Reg = MI.getOperand(2).getReg();
4027  if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4028  isIntRegForSubInst(Src2Reg) &&
4029  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
4030  isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
4031  return HexagonII::HSIG_S2;
4032  // memw(Rs+#u4:2) = Rt
4033  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4034  MI.getOperand(1).isImm() &&
4035  isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
4036  return HexagonII::HSIG_S1;
4037  break;
4038  case Hexagon::S2_storerb_io:
4039  case Hexagon::dup_S2_storerb_io:
4040  // memb(Rs+#u4:0) = Rt
4041  Src1Reg = MI.getOperand(0).getReg();
4042  Src2Reg = MI.getOperand(2).getReg();
4043  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4044  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
4045  return HexagonII::HSIG_S1;
4046  break;
4047  //
4048  // Group S2:
4049  //
4050  // memh(Rs+#u3:1) = Rt
4051  // memw(r29+#u5:2) = Rt
4052  // memd(r29+#s6:3) = Rtt
4053  // memw(Rs+#u4:2) = #U1
4054  // memb(Rs+#u4) = #U1
4055  // allocframe(#u5:3)
4056  case Hexagon::S2_storerh_io:
4057  case Hexagon::dup_S2_storerh_io:
4058  // memh(Rs+#u3:1) = Rt
4059  Src1Reg = MI.getOperand(0).getReg();
4060  Src2Reg = MI.getOperand(2).getReg();
4061  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4062  MI.getOperand(1).isImm() &&
4063  isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
4064  return HexagonII::HSIG_S1;
4065  break;
4066  case Hexagon::S2_storerd_io:
4067  case Hexagon::dup_S2_storerd_io:
4068  // memd(r29+#s6:3) = Rtt
4069  Src1Reg = MI.getOperand(0).getReg();
4070  Src2Reg = MI.getOperand(2).getReg();
4071  if (isDblRegForSubInst(Src2Reg, HRI) &&
4072  Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4073  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
4074  isShiftedInt<6,3>(MI.getOperand(1).getImm()))
4075  return HexagonII::HSIG_S2;
4076  break;
4077  case Hexagon::S4_storeiri_io:
4078  case Hexagon::dup_S4_storeiri_io:
4079  // memw(Rs+#u4:2) = #U1
4080  Src1Reg = MI.getOperand(0).getReg();
4081  if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
4082  isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
4083  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4084  return HexagonII::HSIG_S2;
4085  break;
4086  case Hexagon::S4_storeirb_io:
4087  case Hexagon::dup_S4_storeirb_io:
4088  // memb(Rs+#u4) = #U1
4089  Src1Reg = MI.getOperand(0).getReg();
4090  if (isIntRegForSubInst(Src1Reg) &&
4091  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
4092  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4093  return HexagonII::HSIG_S2;
4094  break;
4095  case Hexagon::S2_allocframe:
4096  case Hexagon::dup_S2_allocframe:
4097  if (MI.getOperand(2).isImm() &&
4098  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
4099  return HexagonII::HSIG_S1;
4100  break;
4101  //
4102  // Group A:
4103  //
4104  // Rx = add(Rx,#s7)
4105  // Rd = Rs
4106  // Rd = #u6
4107  // Rd = #-1
4108  // if ([!]P0[.new]) Rd = #0
4109  // Rd = add(r29,#u6:2)
4110  // Rx = add(Rx,Rs)
4111  // P0 = cmp.eq(Rs,#u2)
4112  // Rdd = combine(#0,Rs)
4113  // Rdd = combine(Rs,#0)
4114  // Rdd = combine(#u2,#U2)
4115  // Rd = add(Rs,#1)
4116  // Rd = add(Rs,#-1)
4117  // Rd = sxth/sxtb/zxtb/zxth(Rs)
4118  // Rd = and(Rs,#1)
4119  case Hexagon::A2_addi:
4120  case Hexagon::dup_A2_addi:
4121  DstReg = MI.getOperand(0).getReg();
4122  SrcReg = MI.getOperand(1).getReg();
4123  if (isIntRegForSubInst(DstReg)) {
4124  // Rd = add(r29,#u6:2)
4125  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
4126  HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
4127  isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
4128  return HexagonII::HSIG_A;
4129  // Rx = add(Rx,#s7)
4130  if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
4131  isInt<7>(MI.getOperand(2).getImm()))
4132  return HexagonII::HSIG_A;
4133  // Rd = add(Rs,#1)
4134  // Rd = add(Rs,#-1)
4135  if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
4136  ((MI.getOperand(2).getImm() == 1) ||
4137  (MI.getOperand(2).getImm() == -1)))
4138  return HexagonII::HSIG_A;
4139  }
4140  break;
4141  case Hexagon::A2_add:
4142  case Hexagon::dup_A2_add:
4143  // Rx = add(Rx,Rs)
4144  DstReg = MI.getOperand(0).getReg();
4145  Src1Reg = MI.getOperand(1).getReg();
4146  Src2Reg = MI.getOperand(2).getReg();
4147  if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
4148  isIntRegForSubInst(Src2Reg))
4149  return HexagonII::HSIG_A;
4150  break;
4151  case Hexagon::A2_andir:
4152  case Hexagon::dup_A2_andir:
4153  // Same as zxtb.
4154  // Rd16=and(Rs16,#255)
4155  // Rd16=and(Rs16,#1)
4156  DstReg = MI.getOperand(0).getReg();
4157  SrcReg = MI.getOperand(1).getReg();
4158  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
4159  MI.getOperand(2).isImm() &&
4160  ((MI.getOperand(2).getImm() == 1) ||
4161  (MI.getOperand(2).getImm() == 255)))
4162  return HexagonII::HSIG_A;
4163  break;
4164  case Hexagon::A2_tfr:
4165  case Hexagon::dup_A2_tfr:
4166  // Rd = Rs
4167  DstReg = MI.getOperand(0).getReg();
4168  SrcReg = MI.getOperand(1).getReg();
4169  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4170  return HexagonII::HSIG_A;
4171  break;
4172  case Hexagon::A2_tfrsi:
4173  case Hexagon::dup_A2_tfrsi:
4174  // Rd = #u6
4175  // Do not test for #u6 size since the const is getting extended
4176  // regardless and compound could be formed.
4177  // Rd = #-1
4178  DstReg = MI.getOperand(0).getReg();
4179  if (isIntRegForSubInst(DstReg))
4180  return HexagonII::HSIG_A;
4181  break;
4182  case Hexagon::C2_cmoveit:
4183  case Hexagon::C2_cmovenewit:
4184  case Hexagon::C2_cmoveif:
4185  case Hexagon::C2_cmovenewif:
4186  case Hexagon::dup_C2_cmoveit:
4187  case Hexagon::dup_C2_cmovenewit:
4188  case Hexagon::dup_C2_cmoveif:
4189  case Hexagon::dup_C2_cmovenewif:
4190  // if ([!]P0[.new]) Rd = #0
4191  // Actual form:
4192  // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
4193  DstReg = MI.getOperand(0).getReg();
4194  SrcReg = MI.getOperand(1).getReg();
4195  if (isIntRegForSubInst(DstReg) &&
4196  Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4197  MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4198  return HexagonII::HSIG_A;
4199  break;
4200  case Hexagon::C2_cmpeqi:
4201  case Hexagon::dup_C2_cmpeqi:
4202  // P0 = cmp.eq(Rs,#u2)
4203  DstReg = MI.getOperand(0).getReg();
4204  SrcReg = MI.getOperand(1).getReg();
4205  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
4206  Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
4207  MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4208  return HexagonII::HSIG_A;
4209  break;
4210  case Hexagon::A2_combineii:
4211  case Hexagon::A4_combineii:
4212  case Hexagon::dup_A2_combineii:
4213  case Hexagon::dup_A4_combineii:
4214  // Rdd = combine(#u2,#U2)
4215  DstReg = MI.getOperand(0).getReg();
4216  if (isDblRegForSubInst(DstReg, HRI) &&
4217  ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4218  (MI.getOperand(1).isGlobal() &&
4219  isUInt<2>(MI.getOperand(1).getOffset()))) &&
4220  ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4221  (MI.getOperand(2).isGlobal() &&
4222  isUInt<2>(MI.getOperand(2).getOffset()))))
4223  return HexagonII::HSIG_A;
4224  break;
4225  case Hexagon::A4_combineri:
4226  case Hexagon::dup_A4_combineri:
4227  // Rdd = combine(Rs,#0)
4228  // Rdd = combine(Rs,#0)
4229  DstReg = MI.getOperand(0).getReg();
4230  SrcReg = MI.getOperand(1).getReg();
4231  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4232  ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4233  (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4234  return HexagonII::HSIG_A;
4235  break;
4236  case Hexagon::A4_combineir:
4237  case Hexagon::dup_A4_combineir:
4238  // Rdd = combine(#0,Rs)
4239  DstReg = MI.getOperand(0).getReg();
4240  SrcReg = MI.getOperand(2).getReg();
4241  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4242  ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4243  (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4244  return HexagonII::HSIG_A;
4245  break;
4246  case Hexagon::A2_sxtb:
4247  case Hexagon::A2_sxth:
4248  case Hexagon::A2_zxtb:
4249  case Hexagon::A2_zxth:
4250  case Hexagon::dup_A2_sxtb:
4251  case Hexagon::dup_A2_sxth:
4252  case Hexagon::dup_A2_zxtb:
4253  case Hexagon::dup_A2_zxth:
4254  // Rd = sxth/sxtb/zxtb/zxth(Rs)
4255  DstReg = MI.getOperand(0).getReg();
4256  SrcReg = MI.getOperand(1).getReg();
4257  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4258  return HexagonII::HSIG_A;
4259  break;
4260  }
4261 
4262  return HexagonII::HSIG_None;
4263 }
4264 
4266  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4267 }
4268 
4270  const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4271  // Default to one cycle for no itinerary. However, an "empty" itinerary may
4272  // still have a MinLatency property, which getStageLatency checks.
4273  if (!ItinData)
4274  return getInstrLatency(ItinData, MI);
4275 
4276  if (MI.isTransient())
4277  return 0;
4278  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4279 }
4280 
4281 /// getOperandLatency - Compute and return the use operand latency of a given
4282 /// pair of def and use.
4283 /// In most cases, the static scheduling itinerary was enough to determine the
4284 /// operand latency. But it may not be possible for instructions with variable
4285 /// number of defs / uses.
4286 ///
4287 /// This is a raw interface to the itinerary that may be directly overriden by
4288 /// a target. Use computeOperandLatency to get the best estimate of latency.
4290  const MachineInstr &DefMI,
4291  unsigned DefIdx,
4292  const MachineInstr &UseMI,
4293  unsigned UseIdx) const {
4294  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4295 
4296  // Get DefIdx and UseIdx for super registers.
4297  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4298 
4299  if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) {
4300  if (DefMO.isImplicit()) {
4301  for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
4302  int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
4303  if (Idx != -1) {
4304  DefIdx = Idx;
4305  break;
4306  }
4307  }
4308  }
4309 
4310  const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4311  if (UseMO.isImplicit()) {
4312  for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
4313  int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
4314  if (Idx != -1) {
4315  UseIdx = Idx;
4316  break;
4317  }
4318  }
4319  }
4320  }
4321 
4322  int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
4323  UseMI, UseIdx);
4324  if (!Latency)
4325  // We should never have 0 cycle latency between two instructions unless
4326  // they can be packetized together. However, this decision can't be made
4327  // here.
4328  Latency = 1;
4329  return Latency;
4330 }
4331 
4332 // inverts the predication logic.
4333 // p -> NotP
4334 // NotP -> P
4337  if (Cond.empty())
4338  return false;
4339  unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4340  Cond[0].setImm(Opc);
4341  return true;
4342 }
4343 
4344 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4345  int InvPredOpcode;
4346  InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4347  : Hexagon::getTruePredOpcode(Opc);
4348  if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4349  return InvPredOpcode;
4350 
4351  llvm_unreachable("Unexpected predicated instruction");
4352 }
4353 
4354 // Returns the max value that doesn't need to be extended.
4356  const uint64_t F = MI.getDesc().TSFlags;
4357  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4359  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4361 
4362  if (isSigned) // if value is signed
4363  return ~(-1U << (bits - 1));
4364  else
4365  return ~(-1U << bits);
4366 }
4367 
4368 
4370  switch (MI.getOpcode()) {
4371  case Hexagon::L2_loadrbgp:
4372  case Hexagon::L2_loadrdgp:
4373  case Hexagon::L2_loadrhgp:
4374  case Hexagon::L2_loadrigp:
4375  case Hexagon::L2_loadrubgp:
4376  case Hexagon::L2_loadruhgp:
4377  case Hexagon::S2_storerbgp:
4378  case Hexagon::S2_storerbnewgp:
4379  case Hexagon::S2_storerhgp:
4380  case Hexagon::S2_storerhnewgp:
4381  case Hexagon::S2_storerigp:
4382  case Hexagon::S2_storerinewgp:
4383  case Hexagon::S2_storerdgp:
4384  case Hexagon::S2_storerfgp:
4385  return true;
4386  }
4387  const uint64_t F = MI.getDesc().TSFlags;
4388  unsigned addrMode =
4390  // Disallow any base+offset instruction. The assembler does not yet reorder
4391  // based up any zero offset instruction.
4392  return (addrMode == HexagonII::BaseRegOffset ||
4393  addrMode == HexagonII::BaseImmOffset ||
4394  addrMode == HexagonII::BaseLongOffset);
4395 }
4396 
4398  // Workaround for the Global Scheduler. Sometimes, it creates
4399  // A4_ext as a Pseudo instruction and calls this function to see if
4400  // it can be added to an existing bundle. Since the instruction doesn't
4401  // belong to any BB yet, we can't use getUnits API.
4402  if (MI.getOpcode() == Hexagon::A4_ext)
4403  return false;
4404 
4405  unsigned FuncUnits = getUnits(MI);
4406  return HexagonFUnits::isSlot0Only(FuncUnits);
4407 }
4408 
4410  const uint64_t F = MI.getDesc().TSFlags;
4411  return ((F >> HexagonII::RestrictNoSlot1StorePos) &
4413 }
4414 
4416  bool ToBigInstrs) const {
4417  int Opcode = -1;
4418  if (ToBigInstrs) { // To BigCore Instr.
4419  // Check if the instruction can form a Duplex.
4420  if (getDuplexCandidateGroup(*MII))
4421  // Get the opcode marked "dup_*" tag.
4422  Opcode = getDuplexOpcode(*MII, ToBigInstrs);
4423  } else // To TinyCore Instr.
4424  Opcode = getDuplexOpcode(*MII, ToBigInstrs);
4425 
4426  // Change the opcode of the instruction.
4427  if (Opcode >= 0)
4428  MII->setDesc(get(Opcode));
4429 }
4430 
4431 // This function is used to translate instructions to facilitate generating
4432 // Duplexes on TinyCore.
4434  bool ToBigInstrs) const {
4435  for (auto &MB : MF)
4436  for (MachineBasicBlock::instr_iterator Instr = MB.instr_begin(),
4437  End = MB.instr_end();
4438  Instr != End; ++Instr)
4439  changeDuplexOpcode(Instr, ToBigInstrs);
4440 }
4441 
4442 // This is a specialized form of above function.
4444  MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const {
4445  MachineBasicBlock *MBB = MII->getParent();
4446  while ((MII != MBB->instr_end()) && MII->isInsideBundle()) {
4447  changeDuplexOpcode(MII, ToBigInstrs);
4448  ++MII;
4449  }
4450 }
4451 
4453  using namespace HexagonII;
4454 
4455  const uint64_t F = MI.getDesc().TSFlags;
4456  unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4457  unsigned Size = getMemAccessSizeInBytes(MemAccessSize(S));
4458  if (Size != 0)
4459  return Size;
4460  // Y2_dcfetchbo is special
4461  if (MI.getOpcode() == Hexagon::Y2_dcfetchbo)
4463 
4464  // Handle vector access sizes.
4465  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4466  switch (S) {
4468  return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4469  default:
4470  llvm_unreachable("Unexpected instruction");
4471  }
4472 }
4473 
4474 // Returns the min value that doesn't need to be extended.
4476  const uint64_t F = MI.getDesc().TSFlags;
4477  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4479  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4481 
4482  if (isSigned) // if value is signed
4483  return -1U << (bits - 1);
4484  else
4485  return 0;
4486 }
4487 
4488 // Returns opcode of the non-extended equivalent instruction.
4490  // Check if the instruction has a register form that uses register in place
4491  // of the extended operand, if so return that as the non-extended form.
4492  short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4493  if (NonExtOpcode >= 0)
4494  return NonExtOpcode;
4495 
4496  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4497  // Check addressing mode and retrieve non-ext equivalent instruction.
4498  switch (getAddrMode(MI)) {
4499  case HexagonII::Absolute:
4500  return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4502  return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4504  return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4505 
4506  default:
4507  return -1;
4508  }
4509  }
4510  return -1;
4511 }
4512 
4514  Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4515  if (Cond.empty())
4516  return false;
4517  assert(Cond.size() == 2);
4518  if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4519  LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4520  return false;
4521  }
4522  PredReg = Cond[1].getReg();
4523  PredRegPos = 1;
4524  // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4525  PredRegFlags = 0;
4526  if (Cond[1].isImplicit())
4527  PredRegFlags = RegState::Implicit;
4528  if (Cond[1].isUndef())
4529  PredRegFlags |= RegState::Undef;
4530  return true;
4531 }
4532 
4534  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4535 }
4536 
4538  return Hexagon::getRegForm(MI.getOpcode());
4539 }
4540 
4541 // Return the number of bytes required to encode the instruction.
4542 // Hexagon instructions are fixed length, 4 bytes, unless they
4543 // use a constant extender, which requires another 4 bytes.
4544 // For debug instructions and prolog labels, return 0.
4546  if (MI.isDebugInstr() || MI.isPosition())
4547  return 0;
4548 
4549  unsigned Size = MI.getDesc().getSize();
4550  if (!Size)
4551  // Assume the default insn size in case it cannot be determined
4552  // for whatever reason.
4553  Size = HEXAGON_INSTR_SIZE;
4554 
4555  if (isConstExtended(MI) || isExtended(MI))
4556  Size += HEXAGON_INSTR_SIZE;
4557 
4558  // Try and compute number of instructions in asm.
4559  if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) {
4560  const MachineBasicBlock &MBB = *MI.getParent();
4561  const MachineFunction *MF = MBB.getParent();
4562  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4563 
4564  // Count the number of register definitions to find the asm string.
4565  unsigned NumDefs = 0;
4566  for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4567  ++NumDefs)
4568  assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4569 
4570  assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4571  // Disassemble the AsmStr and approximate number of instructions.
4572  const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4573  Size = getInlineAsmLength(AsmStr, *MAI);
4574  }
4575 
4576  return Size;
4577 }
4578 
4580  const uint64_t F = MI.getDesc().TSFlags;
4582 }
4583 
4585  const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4586  const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4587 
4588  return IS.getUnits();
4589 }
4590 
4591 // Calculate size of the basic block without debug instructions.
4593  return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4594 }
4595 
4597  MachineBasicBlock::const_iterator BundleHead) const {
4598  assert(BundleHead->isBundle() && "Not a bundle header");
4599  auto MII = BundleHead.getInstrIterator();
4600  // Skip the bundle header.
4601  return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4602 }
4603 
4604 /// immediateExtend - Changes the instruction in place to one using an immediate
4605 /// extender.
4608  "Instruction must be extendable");
4609  // Find which operand is extendable.
4610  short ExtOpNum = getCExtOpNum(MI);
4611  MachineOperand &MO = MI.getOperand(ExtOpNum);
4612  // This needs to be something we understand.
4613  assert((MO.isMBB() || MO.isImm()) &&
4614  "Branch with unknown extendable field type");
4615  // Mark given operand as extended.
4617 }
4618 
4620  MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4621  LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4622  << printMBBReference(*NewTarget);
4623  MI.dump(););
4624  assert(MI.isBranch());
4625  unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4626  int TargetPos = MI.getNumOperands() - 1;
4627  // In general branch target is the last operand,
4628  // but some implicit defs added at the end might change it.
4629  while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4630  --TargetPos;
4631  assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4632  MI.getOperand(TargetPos).setMBB(NewTarget);
4634  NewOpcode = reversePrediction(NewOpcode);
4635  }
4636  MI.setDesc(get(NewOpcode));
4637  return true;
4638 }
4639 
4641  /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4643  MachineBasicBlock &B = *A;
4644  MachineBasicBlock::iterator I = B.begin();
4645  DebugLoc DL = I->getDebugLoc();
4646  MachineInstr *NewMI;
4647 
4648  for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4649  insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4650  NewMI = BuildMI(B, I, DL, get(insn));
4651  LLVM_DEBUG(dbgs() << "\n"
4652  << getName(NewMI->getOpcode())
4653  << " Class: " << NewMI->getDesc().getSchedClass());
4654  NewMI->eraseFromParent();
4655  }
4656  /* --- The code above is used to generate complete set of Hexagon Insn --- */
4657 }
4658 
4659 // inverts the predication logic.
4660 // p -> NotP
4661 // NotP -> P
4663  LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4664  MI.setDesc(get(getInvertedPredicatedOpcode(MI.getOpcode())));
4665  return true;
4666 }
4667 
4668 // Reverse the branch prediction.
4669 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4670  int PredRevOpcode = -1;
4671  if (isPredictedTaken(Opcode))
4672  PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4673  else
4674  PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4675  assert(PredRevOpcode > 0);
4676  return PredRevOpcode;
4677 }
4678 
4679 // TODO: Add more rigorous validation.
4681  const {
4682  return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4683 }
4684 
4685 void HexagonInstrInfo::
4687  assert(MIB->isBundle());
4688  MachineOperand &Operand = MIB->getOperand(0);
4689  if (Operand.isImm())
4690  Operand.setImm(Operand.getImm() | memShufDisabledMask);
4691  else
4692  MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4693 }
4694 
4696  assert(MIB.isBundle());
4697  const MachineOperand &Operand = MIB.getOperand(0);
4698  return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4699 }
4700 
4701 // Addressing mode relations.
4703  return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4704 }
4705 
4707  return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4708 }
4709 
4711  return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4712 }
4713 
4715  return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4716 }
4717 
4719  return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4720 }
4721 
4723  return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4724 }
4725 
4727  return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4728 }
4729 
4731  return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4732 }
4733 
4735  static const MCInst Nop = MCInstBuilder(Hexagon::A2_nop);
4736 
4737  return MCInstBuilder(Hexagon::BUNDLE)
4738  .addImm(0)
4739  .addInst(&Nop);
4740 }
i
i
Definition: README.txt:29
llvm::HexagonInstrInfo::isTailCall
bool isTailCall(const MachineInstr &MI) const override
Definition: HexagonInstrInfo.cpp:2645
llvm::HexagonII::CompoundGroup
CompoundGroup
Definition: HexagonBaseInfo.h:242
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:245
llvm::M68kBeads::Term
@ Term
Definition: M68kBaseInfo.h:71
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:62
llvm::HexagonII::TakenMask
@ TakenMask
Definition: HexagonBaseInfo.h:136
llvm::HexagonII::HSIG_Compound
@ HSIG_Compound
Definition: HexagonBaseInfo.h:238
llvm::HexagonInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Test if the given instruction should be considered a scheduling boundary.
Definition: HexagonInstrInfo.cpp:1785
parseOperands
static void parseOperands(const MachineInstr &MI, SmallVectorImpl< Register > &Defs, SmallVectorImpl< Register > &Uses)
Gather register def/uses from MI.
Definition: HexagonInstrInfo.cpp:235
llvm::HexagonInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Definition: HexagonInstrInfo.cpp:335
getName
static StringRef getName(Value *V)
Definition: ProvenanceAnalysisEvaluator.cpp:20
llvm::HexagonSubtarget::useNewValueStores
bool useNewValueStores() const
Definition: HexagonSubtarget.h:220
ScheduleDAG.h
llvm::HexagonII::HSIG_S2
@ HSIG_S2
Definition: HexagonBaseInfo.h:236
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MCAsmInfo::getCommentString
StringRef getCommentString() const
Definition: MCAsmInfo.h:653
llvm::HexagonInstrInfo::nonDbgBBSize
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
Definition: HexagonInstrInfo.cpp:4592
llvm::ARMII::MO_HI16
@ MO_HI16
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address.
Definition: ARMBaseInfo.h:254
llvm::HexagonInstrInfo::HexagonInstrInfo
HexagonInstrInfo(HexagonSubtarget &ST)
Definition: HexagonInstrInfo.cpp:119
llvm::MachineOperand::isBlockAddress
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Definition: MachineOperand.h:342
llvm::MCAsmInfo::getSeparatorString
const char * getSeparatorString() const
Definition: MCAsmInfo.h:647
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:107
llvm::MachineInstr::isIndirectBranch
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:910
llvm::HexagonInstrInfo::isAbsoluteSet
bool isAbsoluteSet(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2110
llvm::HexagonInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
Definition: HexagonInstrInfo.cpp:1872
llvm::HexagonInstrInfo::changeAddrMode_io_rr
short changeAddrMode_io_rr(short Opc) const
Definition: