LLVM 19.0.0git
HexagonInstrInfo.cpp
Go to the documentation of this file.
1//===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Hexagon implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "HexagonInstrInfo.h"
14#include "Hexagon.h"
17#include "HexagonRegisterInfo.h"
18#include "HexagonSubtarget.h"
19#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/StringRef.h"
43#include "llvm/IR/DebugLoc.h"
45#include "llvm/MC/MCAsmInfo.h"
47#include "llvm/MC/MCInstrDesc.h"
52#include "llvm/Support/Debug.h"
57#include <cassert>
58#include <cctype>
59#include <cstdint>
60#include <cstring>
61#include <iterator>
62#include <optional>
63#include <string>
64#include <utility>
65
66using namespace llvm;
67
68#define DEBUG_TYPE "hexagon-instrinfo"
69
70#define GET_INSTRINFO_CTOR_DTOR
71#define GET_INSTRMAP_INFO
73#include "HexagonGenDFAPacketizer.inc"
74#include "HexagonGenInstrInfo.inc"
75
76cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
77 cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
78 "packetization boundary."));
79
80static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
81 cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
82
84 "disable-hexagon-nv-schedule", cl::Hidden,
85 cl::desc("Disable schedule adjustment for new value stores."));
86
88 "enable-timing-class-latency", cl::Hidden, cl::init(false),
89 cl::desc("Enable timing class latency"));
90
92 "enable-alu-forwarding", cl::Hidden, cl::init(true),
93 cl::desc("Enable vec alu forwarding"));
94
96 "enable-acc-forwarding", cl::Hidden, cl::init(true),
97 cl::desc("Enable vec acc forwarding"));
98
99static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
100 cl::init(true), cl::Hidden,
101 cl::desc("branch relax asm"));
102
103static cl::opt<bool>
104 UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden,
105 cl::desc("Use the DFA based hazard recognizer."));
106
107/// Constants for Hexagon instructions.
108const int Hexagon_MEMW_OFFSET_MAX = 4095;
109const int Hexagon_MEMW_OFFSET_MIN = -4096;
110const int Hexagon_MEMD_OFFSET_MAX = 8191;
111const int Hexagon_MEMD_OFFSET_MIN = -8192;
112const int Hexagon_MEMH_OFFSET_MAX = 2047;
113const int Hexagon_MEMH_OFFSET_MIN = -2048;
114const int Hexagon_MEMB_OFFSET_MAX = 1023;
115const int Hexagon_MEMB_OFFSET_MIN = -1024;
116const int Hexagon_ADDI_OFFSET_MAX = 32767;
117const int Hexagon_ADDI_OFFSET_MIN = -32768;
118
119// Pin the vtable to this file.
120void HexagonInstrInfo::anchor() {}
121
123 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
124 Subtarget(ST) {}
125
126namespace llvm {
127namespace HexagonFUnits {
128 bool isSlot0Only(unsigned units);
129}
130}
131
132static bool isIntRegForSubInst(Register Reg) {
133 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
134 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
135}
136
137static bool isDblRegForSubInst(Register Reg, const HexagonRegisterInfo &HRI) {
138 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
139 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
140}
141
142/// Calculate number of instructions excluding the debug instructions.
145 unsigned Count = 0;
146 for (; MIB != MIE; ++MIB) {
147 if (!MIB->isDebugInstr())
148 ++Count;
149 }
150 return Count;
151}
152
153// Check if the A2_tfrsi instruction is cheap or not. If the operand has
154// to be constant-extendend it is not cheap since it occupies two slots
155// in a packet.
157 // Enable the following steps only at Os/Oz
158 if (!(MI.getMF()->getFunction().hasOptSize()))
159 return MI.isAsCheapAsAMove();
160
161 if (MI.getOpcode() == Hexagon::A2_tfrsi) {
162 auto Op = MI.getOperand(1);
163 // If the instruction has a global address as operand, it is not cheap
164 // since the operand will be constant extended.
165 if (Op.isGlobal())
166 return false;
167 // If the instruction has an operand of size > 16bits, its will be
168 // const-extended and hence, it is not cheap.
169 if (Op.isImm()) {
170 int64_t Imm = Op.getImm();
171 if (!isInt<16>(Imm))
172 return false;
173 }
174 }
175 return MI.isAsCheapAsAMove();
176}
177
178// Do not sink floating point instructions that updates USR register.
179// Example:
180// feclearexcept
181// F2_conv_w2sf
182// fetestexcept
183// MachineSink sinks F2_conv_w2sf and we are not able to catch exceptions.
184// TODO: On some of these floating point instructions, USR is marked as Use.
185// In reality, these instructions also Def the USR. If USR is marked as Def,
186// some of the assumptions in assembler packetization are broken.
188 // Assumption: A floating point instruction that reads the USR will write
189 // the USR as well.
190 if (isFloat(MI) && MI.hasRegisterImplicitUseOperand(Hexagon::USR))
191 return false;
192 return true;
193}
194
195/// Find the hardware loop instruction used to set-up the specified loop.
196/// On Hexagon, we have two instructions used to set-up the hardware loop
197/// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
198/// to indicate the end of a loop.
200 unsigned EndLoopOp, MachineBasicBlock *TargetBB,
202 unsigned LOOPi;
203 unsigned LOOPr;
204 if (EndLoopOp == Hexagon::ENDLOOP0) {
205 LOOPi = Hexagon::J2_loop0i;
206 LOOPr = Hexagon::J2_loop0r;
207 } else { // EndLoopOp == Hexagon::EndLOOP1
208 LOOPi = Hexagon::J2_loop1i;
209 LOOPr = Hexagon::J2_loop1r;
210 }
211
212 // The loop set-up instruction will be in a predecessor block
213 for (MachineBasicBlock *PB : BB->predecessors()) {
214 // If this has been visited, already skip it.
215 if (!Visited.insert(PB).second)
216 continue;
217 if (PB == BB)
218 continue;
219 for (MachineInstr &I : llvm::reverse(PB->instrs())) {
220 unsigned Opc = I.getOpcode();
221 if (Opc == LOOPi || Opc == LOOPr)
222 return &I;
223 // We've reached a different loop, which means the loop01 has been
224 // removed.
225 if (Opc == EndLoopOp && I.getOperand(0).getMBB() != TargetBB)
226 return nullptr;
227 }
228 // Check the predecessors for the LOOP instruction.
229 if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
230 return Loop;
231 }
232 return nullptr;
233}
234
235/// Gather register def/uses from MI.
236/// This treats possible (predicated) defs as actually happening ones
237/// (conservatively).
238static inline void parseOperands(const MachineInstr &MI,
240 Defs.clear();
241 Uses.clear();
242
243 for (const MachineOperand &MO : MI.operands()) {
244 if (!MO.isReg())
245 continue;
246
247 Register Reg = MO.getReg();
248 if (!Reg)
249 continue;
250
251 if (MO.isUse())
252 Uses.push_back(MO.getReg());
253
254 if (MO.isDef())
255 Defs.push_back(MO.getReg());
256 }
257}
258
259// Position dependent, so check twice for swap.
260static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
261 switch (Ga) {
263 default:
264 return false;
266 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
268 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
269 Gb == HexagonII::HSIG_A);
271 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
274 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
275 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
276 Gb == HexagonII::HSIG_A);
278 return (Gb == HexagonII::HSIG_A);
280 return (Gb == HexagonII::HSIG_Compound);
281 }
282 return false;
283}
284
285/// isLoadFromStackSlot - If the specified machine instruction is a direct
286/// load from a stack slot, return the virtual or physical register number of
287/// the destination along with the FrameIndex of the loaded stack slot. If
288/// not, return 0. This predicate must return 0 if the instruction has
289/// any side effects other than loading from the stack slot.
291 int &FrameIndex) const {
292 switch (MI.getOpcode()) {
293 default:
294 break;
295 case Hexagon::L2_loadri_io:
296 case Hexagon::L2_loadrd_io:
297 case Hexagon::V6_vL32b_ai:
298 case Hexagon::V6_vL32b_nt_ai:
299 case Hexagon::V6_vL32Ub_ai:
300 case Hexagon::LDriw_pred:
301 case Hexagon::LDriw_ctr:
302 case Hexagon::PS_vloadrq_ai:
303 case Hexagon::PS_vloadrw_ai:
304 case Hexagon::PS_vloadrw_nt_ai: {
305 const MachineOperand OpFI = MI.getOperand(1);
306 if (!OpFI.isFI())
307 return 0;
308 const MachineOperand OpOff = MI.getOperand(2);
309 if (!OpOff.isImm() || OpOff.getImm() != 0)
310 return 0;
311 FrameIndex = OpFI.getIndex();
312 return MI.getOperand(0).getReg();
313 }
314
315 case Hexagon::L2_ploadrit_io:
316 case Hexagon::L2_ploadrif_io:
317 case Hexagon::L2_ploadrdt_io:
318 case Hexagon::L2_ploadrdf_io: {
319 const MachineOperand OpFI = MI.getOperand(2);
320 if (!OpFI.isFI())
321 return 0;
322 const MachineOperand OpOff = MI.getOperand(3);
323 if (!OpOff.isImm() || OpOff.getImm() != 0)
324 return 0;
325 FrameIndex = OpFI.getIndex();
326 return MI.getOperand(0).getReg();
327 }
328 }
329
330 return 0;
331}
332
333/// isStoreToStackSlot - If the specified machine instruction is a direct
334/// store to a stack slot, return the virtual or physical register number of
335/// the source reg along with the FrameIndex of the loaded stack slot. If
336/// not, return 0. This predicate must return 0 if the instruction has
337/// any side effects other than storing to the stack slot.
339 int &FrameIndex) const {
340 switch (MI.getOpcode()) {
341 default:
342 break;
343 case Hexagon::S2_storerb_io:
344 case Hexagon::S2_storerh_io:
345 case Hexagon::S2_storeri_io:
346 case Hexagon::S2_storerd_io:
347 case Hexagon::V6_vS32b_ai:
348 case Hexagon::V6_vS32Ub_ai:
349 case Hexagon::STriw_pred:
350 case Hexagon::STriw_ctr:
351 case Hexagon::PS_vstorerq_ai:
352 case Hexagon::PS_vstorerw_ai: {
353 const MachineOperand &OpFI = MI.getOperand(0);
354 if (!OpFI.isFI())
355 return 0;
356 const MachineOperand &OpOff = MI.getOperand(1);
357 if (!OpOff.isImm() || OpOff.getImm() != 0)
358 return 0;
359 FrameIndex = OpFI.getIndex();
360 return MI.getOperand(2).getReg();
361 }
362
363 case Hexagon::S2_pstorerbt_io:
364 case Hexagon::S2_pstorerbf_io:
365 case Hexagon::S2_pstorerht_io:
366 case Hexagon::S2_pstorerhf_io:
367 case Hexagon::S2_pstorerit_io:
368 case Hexagon::S2_pstorerif_io:
369 case Hexagon::S2_pstorerdt_io:
370 case Hexagon::S2_pstorerdf_io: {
371 const MachineOperand &OpFI = MI.getOperand(1);
372 if (!OpFI.isFI())
373 return 0;
374 const MachineOperand &OpOff = MI.getOperand(2);
375 if (!OpOff.isImm() || OpOff.getImm() != 0)
376 return 0;
377 FrameIndex = OpFI.getIndex();
378 return MI.getOperand(3).getReg();
379 }
380 }
381
382 return 0;
383}
384
385/// This function checks if the instruction or bundle of instructions
386/// has load from stack slot and returns frameindex and machine memory
387/// operand of that instruction if true.
389 const MachineInstr &MI,
391 if (MI.isBundle()) {
392 const MachineBasicBlock *MBB = MI.getParent();
394 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
395 if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
396 return true;
397 return false;
398 }
399
401}
402
403/// This function checks if the instruction or bundle of instructions
404/// has store to stack slot and returns frameindex and machine memory
405/// operand of that instruction if true.
407 const MachineInstr &MI,
409 if (MI.isBundle()) {
410 const MachineBasicBlock *MBB = MI.getParent();
412 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
413 if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
414 return true;
415 return false;
416 }
417
419}
420
421/// This function can analyze one/two way branching only and should (mostly) be
422/// called by target independent side.
423/// First entry is always the opcode of the branching instruction, except when
424/// the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a
425/// BB with only unconditional jump. Subsequent entries depend upon the opcode,
426/// e.g. Jump_c p will have
427/// Cond[0] = Jump_c
428/// Cond[1] = p
429/// HW-loop ENDLOOP:
430/// Cond[0] = ENDLOOP
431/// Cond[1] = MBB
432/// New value jump:
433/// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
434/// Cond[1] = R
435/// Cond[2] = Imm
438 MachineBasicBlock *&FBB,
440 bool AllowModify) const {
441 TBB = nullptr;
442 FBB = nullptr;
443 Cond.clear();
444
445 // If the block has no terminators, it just falls into the block after it.
447 if (I == MBB.instr_begin())
448 return false;
449
450 // A basic block may looks like this:
451 //
452 // [ insn
453 // EH_LABEL
454 // insn
455 // insn
456 // insn
457 // EH_LABEL
458 // insn ]
459 //
460 // It has two succs but does not have a terminator
461 // Don't know how to handle it.
462 do {
463 --I;
464 if (I->isEHLabel())
465 // Don't analyze EH branches.
466 return true;
467 } while (I != MBB.instr_begin());
468
469 I = MBB.instr_end();
470 --I;
471
472 while (I->isDebugInstr()) {
473 if (I == MBB.instr_begin())
474 return false;
475 --I;
476 }
477
478 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
479 I->getOperand(0).isMBB();
480 // Delete the J2_jump if it's equivalent to a fall-through.
481 if (AllowModify && JumpToBlock &&
482 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
483 LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
484 I->eraseFromParent();
485 I = MBB.instr_end();
486 if (I == MBB.instr_begin())
487 return false;
488 --I;
489 }
490 if (!isUnpredicatedTerminator(*I))
491 return false;
492
493 // Get the last instruction in the block.
494 MachineInstr *LastInst = &*I;
495 MachineInstr *SecondLastInst = nullptr;
496 // Find one more terminator if present.
497 while (true) {
498 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
499 if (!SecondLastInst)
500 SecondLastInst = &*I;
501 else
502 // This is a third branch.
503 return true;
504 }
505 if (I == MBB.instr_begin())
506 break;
507 --I;
508 }
509
510 int LastOpcode = LastInst->getOpcode();
511 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
512 // If the branch target is not a basic block, it could be a tail call.
513 // (It is, if the target is a function.)
514 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
515 return true;
516 if (SecLastOpcode == Hexagon::J2_jump &&
517 !SecondLastInst->getOperand(0).isMBB())
518 return true;
519
520 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
521 bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
522
523 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
524 return true;
525
526 // If there is only one terminator instruction, process it.
527 if (LastInst && !SecondLastInst) {
528 if (LastOpcode == Hexagon::J2_jump) {
529 TBB = LastInst->getOperand(0).getMBB();
530 return false;
531 }
532 if (isEndLoopN(LastOpcode)) {
533 TBB = LastInst->getOperand(0).getMBB();
534 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
535 Cond.push_back(LastInst->getOperand(0));
536 return false;
537 }
538 if (LastOpcodeHasJMP_c) {
539 TBB = LastInst->getOperand(1).getMBB();
540 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
541 Cond.push_back(LastInst->getOperand(0));
542 return false;
543 }
544 // Only supporting rr/ri versions of new-value jumps.
545 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
546 TBB = LastInst->getOperand(2).getMBB();
547 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
548 Cond.push_back(LastInst->getOperand(0));
549 Cond.push_back(LastInst->getOperand(1));
550 return false;
551 }
552 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
553 << " with one jump\n";);
554 // Otherwise, don't know what this is.
555 return true;
556 }
557
558 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
559 bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
560 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
561 if (!SecondLastInst->getOperand(1).isMBB())
562 return true;
563 TBB = SecondLastInst->getOperand(1).getMBB();
564 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
565 Cond.push_back(SecondLastInst->getOperand(0));
566 FBB = LastInst->getOperand(0).getMBB();
567 return false;
568 }
569
570 // Only supporting rr/ri versions of new-value jumps.
571 if (SecLastOpcodeHasNVJump &&
572 (SecondLastInst->getNumExplicitOperands() == 3) &&
573 (LastOpcode == Hexagon::J2_jump)) {
574 TBB = SecondLastInst->getOperand(2).getMBB();
575 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
576 Cond.push_back(SecondLastInst->getOperand(0));
577 Cond.push_back(SecondLastInst->getOperand(1));
578 FBB = LastInst->getOperand(0).getMBB();
579 return false;
580 }
581
582 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
583 // executed, so remove it.
584 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
585 TBB = SecondLastInst->getOperand(0).getMBB();
586 I = LastInst->getIterator();
587 if (AllowModify)
588 I->eraseFromParent();
589 return false;
590 }
591
592 // If the block ends with an ENDLOOP, and J2_jump, handle it.
593 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
594 TBB = SecondLastInst->getOperand(0).getMBB();
595 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
596 Cond.push_back(SecondLastInst->getOperand(0));
597 FBB = LastInst->getOperand(0).getMBB();
598 return false;
599 }
600 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
601 << " with two jumps";);
602 // Otherwise, can't handle this.
603 return true;
604}
605
607 int *BytesRemoved) const {
608 assert(!BytesRemoved && "code size not handled");
609
610 LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
612 unsigned Count = 0;
613 while (I != MBB.begin()) {
614 --I;
615 if (I->isDebugInstr())
616 continue;
617 // Only removing branches from end of MBB.
618 if (!I->isBranch())
619 return Count;
620 if (Count && (I->getOpcode() == Hexagon::J2_jump))
621 llvm_unreachable("Malformed basic block: unconditional branch not last");
622 MBB.erase(&MBB.back());
623 I = MBB.end();
624 ++Count;
625 }
626 return Count;
627}
628
633 const DebugLoc &DL,
634 int *BytesAdded) const {
635 unsigned BOpc = Hexagon::J2_jump;
636 unsigned BccOpc = Hexagon::J2_jumpt;
637 assert(validateBranchCond(Cond) && "Invalid branching condition");
638 assert(TBB && "insertBranch must not be told to insert a fallthrough");
639 assert(!BytesAdded && "code size not handled");
640
641 // Check if reverseBranchCondition has asked to reverse this branch
642 // If we want to reverse the branch an odd number of times, we want
643 // J2_jumpf.
644 if (!Cond.empty() && Cond[0].isImm())
645 BccOpc = Cond[0].getImm();
646
647 if (!FBB) {
648 if (Cond.empty()) {
649 // Due to a bug in TailMerging/CFG Optimization, we need to add a
650 // special case handling of a predicated jump followed by an
651 // unconditional jump. If not, Tail Merging and CFG Optimization go
652 // into an infinite loop.
653 MachineBasicBlock *NewTBB, *NewFBB;
655 auto Term = MBB.getFirstTerminator();
656 if (Term != MBB.end() && isPredicated(*Term) &&
657 !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
661 return insertBranch(MBB, TBB, nullptr, Cond, DL);
662 }
663 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
664 } else if (isEndLoopN(Cond[0].getImm())) {
665 int EndLoopOp = Cond[0].getImm();
666 assert(Cond[1].isMBB());
667 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
668 // Check for it, and change the BB target if needed.
670 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
671 VisitedBBs);
672 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
673 Loop->getOperand(0).setMBB(TBB);
674 // Add the ENDLOOP after the finding the LOOP0.
675 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
676 } else if (isNewValueJump(Cond[0].getImm())) {
677 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
678 // New value jump
679 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
680 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
681 unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
682 LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
684 if (Cond[2].isReg()) {
685 unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
686 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
687 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
688 } else if(Cond[2].isImm()) {
689 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
690 addImm(Cond[2].getImm()).addMBB(TBB);
691 } else
692 llvm_unreachable("Invalid condition for branching");
693 } else {
694 assert((Cond.size() == 2) && "Malformed cond vector");
695 const MachineOperand &RO = Cond[1];
696 unsigned Flags = getUndefRegState(RO.isUndef());
697 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
698 }
699 return 1;
700 }
701 assert((!Cond.empty()) &&
702 "Cond. cannot be empty when multiple branchings are required");
703 assert((!isNewValueJump(Cond[0].getImm())) &&
704 "NV-jump cannot be inserted with another branch");
705 // Special case for hardware loops. The condition is a basic block.
706 if (isEndLoopN(Cond[0].getImm())) {
707 int EndLoopOp = Cond[0].getImm();
708 assert(Cond[1].isMBB());
709 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
710 // Check for it, and change the BB target if needed.
712 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
713 VisitedBBs);
714 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
715 Loop->getOperand(0).setMBB(TBB);
716 // Add the ENDLOOP after the finding the LOOP0.
717 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
718 } else {
719 const MachineOperand &RO = Cond[1];
720 unsigned Flags = getUndefRegState(RO.isUndef());
721 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
722 }
723 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
724
725 return 2;
726}
727
728namespace {
729class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
730 MachineInstr *Loop, *EndLoop;
731 MachineFunction *MF;
732 const HexagonInstrInfo *TII;
733 int64_t TripCount;
734 Register LoopCount;
735 DebugLoc DL;
736
737public:
738 HexagonPipelinerLoopInfo(MachineInstr *Loop, MachineInstr *EndLoop)
739 : Loop(Loop), EndLoop(EndLoop), MF(Loop->getParent()->getParent()),
740 TII(MF->getSubtarget<HexagonSubtarget>().getInstrInfo()),
741 DL(Loop->getDebugLoc()) {
742 // Inspect the Loop instruction up-front, as it may be deleted when we call
743 // createTripCountGreaterCondition.
744 TripCount = Loop->getOpcode() == Hexagon::J2_loop0r
745 ? -1
746 : Loop->getOperand(1).getImm();
747 if (TripCount == -1)
748 LoopCount = Loop->getOperand(1).getReg();
749 }
750
751 bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
752 // Only ignore the terminator.
753 return MI == EndLoop;
754 }
755
756 std::optional<bool> createTripCountGreaterCondition(
757 int TC, MachineBasicBlock &MBB,
759 if (TripCount == -1) {
760 // Check if we're done with the loop.
761 Register Done = TII->createVR(MF, MVT::i1);
762 MachineInstr *NewCmp = BuildMI(&MBB, DL,
763 TII->get(Hexagon::C2_cmpgtui), Done)
764 .addReg(LoopCount)
765 .addImm(TC);
766 Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
767 Cond.push_back(NewCmp->getOperand(0));
768 return {};
769 }
770
771 return TripCount > TC;
772 }
773
774 void setPreheader(MachineBasicBlock *NewPreheader) override {
775 NewPreheader->splice(NewPreheader->getFirstTerminator(), Loop->getParent(),
776 Loop);
777 }
778
779 void adjustTripCount(int TripCountAdjust) override {
780 // If the loop trip count is a compile-time value, then just change the
781 // value.
782 if (Loop->getOpcode() == Hexagon::J2_loop0i ||
783 Loop->getOpcode() == Hexagon::J2_loop1i) {
784 int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust;
785 assert(TripCount > 0 && "Can't create an empty or negative loop!");
786 Loop->getOperand(1).setImm(TripCount);
787 return;
788 }
789
790 // The loop trip count is a run-time value. We generate code to subtract
791 // one from the trip count, and update the loop instruction.
792 Register LoopCount = Loop->getOperand(1).getReg();
793 Register NewLoopCount = TII->createVR(MF, MVT::i32);
794 BuildMI(*Loop->getParent(), Loop, Loop->getDebugLoc(),
795 TII->get(Hexagon::A2_addi), NewLoopCount)
796 .addReg(LoopCount)
797 .addImm(TripCountAdjust);
798 Loop->getOperand(1).setReg(NewLoopCount);
799 }
800
801 void disposed() override { Loop->eraseFromParent(); }
802};
803} // namespace
804
805std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
807 // We really "analyze" only hardware loops right now.
809
810 if (I != LoopBB->end() && isEndLoopN(I->getOpcode())) {
812 MachineInstr *LoopInst = findLoopInstr(
813 LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
814 if (LoopInst)
815 return std::make_unique<HexagonPipelinerLoopInfo>(LoopInst, &*I);
816 }
817 return nullptr;
818}
819
821 unsigned NumCycles, unsigned ExtraPredCycles,
822 BranchProbability Probability) const {
823 return nonDbgBBSize(&MBB) <= 3;
824}
825
827 unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
828 unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
829 const {
830 return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
831}
832
834 unsigned NumInstrs, BranchProbability Probability) const {
835 return NumInstrs <= 4;
836}
837
838static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
840 const MachineBasicBlock &B = *MI.getParent();
841 Regs.addLiveIns(B);
842 auto E = MachineBasicBlock::const_iterator(MI.getIterator());
843 for (auto I = B.begin(); I != E; ++I) {
844 Clobbers.clear();
845 Regs.stepForward(*I, Clobbers);
846 }
847}
848
849static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
850 const MachineBasicBlock &B = *MI.getParent();
851 Regs.addLiveOuts(B);
852 auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
853 for (auto I = B.rbegin(); I != E; ++I)
854 Regs.stepBackward(*I);
855}
856
859 const DebugLoc &DL, MCRegister DestReg,
860 MCRegister SrcReg, bool KillSrc) const {
861 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
862 unsigned KillFlag = getKillRegState(KillSrc);
863
864 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
865 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
866 .addReg(SrcReg, KillFlag);
867 return;
868 }
869 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
870 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
871 .addReg(SrcReg, KillFlag);
872 return;
873 }
874 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
875 // Map Pd = Ps to Pd = or(Ps, Ps).
876 BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
877 .addReg(SrcReg).addReg(SrcReg, KillFlag);
878 return;
879 }
880 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
881 Hexagon::IntRegsRegClass.contains(SrcReg)) {
882 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
883 .addReg(SrcReg, KillFlag);
884 return;
885 }
886 if (Hexagon::IntRegsRegClass.contains(DestReg) &&
887 Hexagon::CtrRegsRegClass.contains(SrcReg)) {
888 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
889 .addReg(SrcReg, KillFlag);
890 return;
891 }
892 if (Hexagon::ModRegsRegClass.contains(DestReg) &&
893 Hexagon::IntRegsRegClass.contains(SrcReg)) {
894 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
895 .addReg(SrcReg, KillFlag);
896 return;
897 }
898 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
899 Hexagon::IntRegsRegClass.contains(DestReg)) {
900 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
901 .addReg(SrcReg, KillFlag);
902 return;
903 }
904 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
905 Hexagon::PredRegsRegClass.contains(DestReg)) {
906 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
907 .addReg(SrcReg, KillFlag);
908 return;
909 }
910 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
911 Hexagon::IntRegsRegClass.contains(DestReg)) {
912 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
913 .addReg(SrcReg, KillFlag);
914 return;
915 }
916 if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
917 BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
918 addReg(SrcReg, KillFlag);
919 return;
920 }
921 if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
922 LivePhysRegs LiveAtMI(HRI);
923 getLiveInRegsAt(LiveAtMI, *I);
924 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
925 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
926 unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo));
927 unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi));
928 BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
929 .addReg(SrcHi, KillFlag | UndefHi)
930 .addReg(SrcLo, KillFlag | UndefLo);
931 return;
932 }
933 if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
934 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
935 .addReg(SrcReg)
936 .addReg(SrcReg, KillFlag);
937 return;
938 }
939 if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
940 Hexagon::HvxVRRegClass.contains(DestReg)) {
941 llvm_unreachable("Unimplemented pred to vec");
942 return;
943 }
944 if (Hexagon::HvxQRRegClass.contains(DestReg) &&
945 Hexagon::HvxVRRegClass.contains(SrcReg)) {
946 llvm_unreachable("Unimplemented vec to pred");
947 return;
948 }
949
950#ifndef NDEBUG
951 // Show the invalid registers to ease debugging.
952 dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
953 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
954#endif
955 llvm_unreachable("Unimplemented");
956}
957
960 Register SrcReg, bool isKill, int FI,
961 const TargetRegisterClass *RC,
962 const TargetRegisterInfo *TRI,
963 Register VReg) const {
966 MachineFrameInfo &MFI = MF.getFrameInfo();
967 unsigned KillFlag = getKillRegState(isKill);
968
971 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
972
973 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
974 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
975 .addFrameIndex(FI).addImm(0)
976 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
977 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
978 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
979 .addFrameIndex(FI).addImm(0)
980 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
981 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
982 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
983 .addFrameIndex(FI).addImm(0)
984 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
985 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
986 BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
987 .addFrameIndex(FI).addImm(0)
988 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
989 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
990 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
991 .addFrameIndex(FI).addImm(0)
992 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
993 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
994 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerv_ai))
995 .addFrameIndex(FI).addImm(0)
996 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
997 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
998 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerw_ai))
999 .addFrameIndex(FI).addImm(0)
1000 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
1001 } else {
1002 llvm_unreachable("Unimplemented");
1003 }
1004}
1005
1008 Register DestReg, int FI,
1009 const TargetRegisterClass *RC,
1010 const TargetRegisterInfo *TRI,
1011 Register VReg) const {
1013 MachineFunction &MF = *MBB.getParent();
1014 MachineFrameInfo &MFI = MF.getFrameInfo();
1015
1018 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
1019
1020 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
1021 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
1022 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1023 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
1024 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
1025 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1026 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
1027 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
1028 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1029 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
1030 BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
1031 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1032 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
1033 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
1034 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1035 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
1036 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrv_ai), DestReg)
1037 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1038 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1039 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrw_ai), DestReg)
1040 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1041 } else {
1042 llvm_unreachable("Can't store this register to stack slot");
1043 }
1044}
1045
1046/// expandPostRAPseudo - This function is called for all pseudo instructions
1047/// that remain after register allocation. Many pseudo instructions are
1048/// created to help register allocation. This is the place to convert them
1049/// into real instructions. The target can edit MI in place, or it can insert
1050/// new instructions and erase MI. The function should return true if
1051/// anything was changed.
1053 MachineBasicBlock &MBB = *MI.getParent();
1054 MachineFunction &MF = *MBB.getParent();
1056 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1057 LivePhysRegs LiveIn(HRI), LiveOut(HRI);
1058 DebugLoc DL = MI.getDebugLoc();
1059 unsigned Opc = MI.getOpcode();
1060
1061 auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1062 Register Mx = MI.getOperand(MxOp).getReg();
1063 Register CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1064 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1065 .add(MI.getOperand((HasImm ? 5 : 4)));
1066 auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1067 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1068 if (HasImm)
1069 MIB.add(MI.getOperand(4));
1070 MIB.addReg(CSx, RegState::Implicit);
1071 MBB.erase(MI);
1072 return true;
1073 };
1074
1075 auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) {
1076 if (MI.memoperands().empty())
1077 return false;
1078 return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) {
1079 return MMO->getAlign() >= NeedAlign;
1080 });
1081 };
1082
1083 switch (Opc) {
1084 case Hexagon::PS_call_instrprof_custom: {
1085 auto Op0 = MI.getOperand(0);
1086 assert(Op0.isGlobal() &&
1087 "First operand must be a global containing handler name.");
1088 const GlobalValue *NameVar = Op0.getGlobal();
1089 const GlobalVariable *GV = dyn_cast<GlobalVariable>(NameVar);
1090 auto *Arr = cast<ConstantDataArray>(GV->getInitializer());
1091 StringRef NameStr = Arr->isCString() ? Arr->getAsCString() : Arr->getAsString();
1092
1093 MachineOperand &Op1 = MI.getOperand(1);
1094 // Set R0 with the imm value to be passed to the custom profiling handler.
1095 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrsi), Hexagon::R0)
1096 .addImm(Op1.getImm());
1097 // The call to the custom handler is being treated as a special one as the
1098 // callee is responsible for saving and restoring all the registers
1099 // (including caller saved registers) it needs to modify. This is
1100 // done to reduce the impact of instrumentation on the code being
1101 // instrumented/profiled.
1102 // NOTE: R14, R15 and R28 are reserved for PLT handling. These registers
1103 // are in the Def list of the Hexagon::PS_call_instrprof_custom and
1104 // therefore will be handled appropriately duing register allocation.
1105
1106 // TODO: It may be a good idea to add a separate pseudo instruction for
1107 // static relocation which doesn't need to reserve r14, r15 and r28.
1108
1109 auto MIB = BuildMI(MBB, MI, DL, get(Hexagon::J2_call))
1111 .addDef(Hexagon::R29, RegState::ImplicitDefine)
1112 .addDef(Hexagon::R30, RegState::ImplicitDefine)
1113 .addDef(Hexagon::R14, RegState::ImplicitDefine)
1114 .addDef(Hexagon::R15, RegState::ImplicitDefine)
1115 .addDef(Hexagon::R28, RegState::ImplicitDefine);
1116 const char *cstr = MF.createExternalSymbolName(NameStr);
1117 MIB.addExternalSymbol(cstr);
1118 MBB.erase(MI);
1119 return true;
1120 }
1121 case TargetOpcode::COPY: {
1122 MachineOperand &MD = MI.getOperand(0);
1123 MachineOperand &MS = MI.getOperand(1);
1124 MachineBasicBlock::iterator MBBI = MI.getIterator();
1125 if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1126 copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1127 std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1128 }
1129 MBB.erase(MBBI);
1130 return true;
1131 }
1132 case Hexagon::PS_aligna:
1133 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1134 .addReg(HRI.getFrameRegister())
1135 .addImm(-MI.getOperand(1).getImm());
1136 MBB.erase(MI);
1137 return true;
1138 case Hexagon::V6_vassignp: {
1139 Register SrcReg = MI.getOperand(1).getReg();
1140 Register DstReg = MI.getOperand(0).getReg();
1141 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1142 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1143 getLiveInRegsAt(LiveIn, MI);
1144 unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
1145 unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));
1146 unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1147 BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1148 .addReg(SrcHi, UndefHi)
1149 .addReg(SrcLo, Kill | UndefLo);
1150 MBB.erase(MI);
1151 return true;
1152 }
1153 case Hexagon::V6_lo: {
1154 Register SrcReg = MI.getOperand(1).getReg();
1155 Register DstReg = MI.getOperand(0).getReg();
1156 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1157 copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1158 MBB.erase(MI);
1159 MRI.clearKillFlags(SrcSubLo);
1160 return true;
1161 }
1162 case Hexagon::V6_hi: {
1163 Register SrcReg = MI.getOperand(1).getReg();
1164 Register DstReg = MI.getOperand(0).getReg();
1165 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1166 copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1167 MBB.erase(MI);
1168 MRI.clearKillFlags(SrcSubHi);
1169 return true;
1170 }
1171 case Hexagon::PS_vloadrv_ai: {
1172 Register DstReg = MI.getOperand(0).getReg();
1173 const MachineOperand &BaseOp = MI.getOperand(1);
1174 assert(BaseOp.getSubReg() == 0);
1175 int Offset = MI.getOperand(2).getImm();
1176 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1177 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1178 : Hexagon::V6_vL32Ub_ai;
1179 BuildMI(MBB, MI, DL, get(NewOpc), DstReg)
1180 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1181 .addImm(Offset)
1182 .cloneMemRefs(MI);
1183 MBB.erase(MI);
1184 return true;
1185 }
1186 case Hexagon::PS_vloadrw_ai: {
1187 Register DstReg = MI.getOperand(0).getReg();
1188 const MachineOperand &BaseOp = MI.getOperand(1);
1189 assert(BaseOp.getSubReg() == 0);
1190 int Offset = MI.getOperand(2).getImm();
1191 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1192 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1193 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1194 : Hexagon::V6_vL32Ub_ai;
1195 BuildMI(MBB, MI, DL, get(NewOpc),
1196 HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1197 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1198 .addImm(Offset)
1199 .cloneMemRefs(MI);
1200 BuildMI(MBB, MI, DL, get(NewOpc),
1201 HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1202 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1203 .addImm(Offset + VecOffset)
1204 .cloneMemRefs(MI);
1205 MBB.erase(MI);
1206 return true;
1207 }
1208 case Hexagon::PS_vstorerv_ai: {
1209 const MachineOperand &SrcOp = MI.getOperand(2);
1210 assert(SrcOp.getSubReg() == 0);
1211 const MachineOperand &BaseOp = MI.getOperand(0);
1212 assert(BaseOp.getSubReg() == 0);
1213 int Offset = MI.getOperand(1).getImm();
1214 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1215 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1216 : Hexagon::V6_vS32Ub_ai;
1217 BuildMI(MBB, MI, DL, get(NewOpc))
1218 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1219 .addImm(Offset)
1221 .cloneMemRefs(MI);
1222 MBB.erase(MI);
1223 return true;
1224 }
1225 case Hexagon::PS_vstorerw_ai: {
1226 Register SrcReg = MI.getOperand(2).getReg();
1227 const MachineOperand &BaseOp = MI.getOperand(0);
1228 assert(BaseOp.getSubReg() == 0);
1229 int Offset = MI.getOperand(1).getImm();
1230 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1231 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1232 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1233 : Hexagon::V6_vS32Ub_ai;
1234 BuildMI(MBB, MI, DL, get(NewOpc))
1235 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1236 .addImm(Offset)
1237 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo))
1238 .cloneMemRefs(MI);
1239 BuildMI(MBB, MI, DL, get(NewOpc))
1240 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1241 .addImm(Offset + VecOffset)
1242 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi))
1243 .cloneMemRefs(MI);
1244 MBB.erase(MI);
1245 return true;
1246 }
1247 case Hexagon::PS_true: {
1248 Register Reg = MI.getOperand(0).getReg();
1249 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1250 .addReg(Reg, RegState::Undef)
1251 .addReg(Reg, RegState::Undef);
1252 MBB.erase(MI);
1253 return true;
1254 }
1255 case Hexagon::PS_false: {
1256 Register Reg = MI.getOperand(0).getReg();
1257 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1258 .addReg(Reg, RegState::Undef)
1259 .addReg(Reg, RegState::Undef);
1260 MBB.erase(MI);
1261 return true;
1262 }
1263 case Hexagon::PS_qtrue: {
1264 BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1265 .addReg(Hexagon::V0, RegState::Undef)
1266 .addReg(Hexagon::V0, RegState::Undef);
1267 MBB.erase(MI);
1268 return true;
1269 }
1270 case Hexagon::PS_qfalse: {
1271 BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1272 .addReg(Hexagon::V0, RegState::Undef)
1273 .addReg(Hexagon::V0, RegState::Undef);
1274 MBB.erase(MI);
1275 return true;
1276 }
1277 case Hexagon::PS_vdd0: {
1278 Register Vd = MI.getOperand(0).getReg();
1279 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1281 .addReg(Vd, RegState::Undef);
1282 MBB.erase(MI);
1283 return true;
1284 }
1285 case Hexagon::PS_vmulw: {
1286 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1287 Register DstReg = MI.getOperand(0).getReg();
1288 Register Src1Reg = MI.getOperand(1).getReg();
1289 Register Src2Reg = MI.getOperand(2).getReg();
1290 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1291 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1292 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1293 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1294 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1295 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1296 .addReg(Src1SubHi)
1297 .addReg(Src2SubHi);
1298 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1299 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1300 .addReg(Src1SubLo)
1301 .addReg(Src2SubLo);
1302 MBB.erase(MI);
1303 MRI.clearKillFlags(Src1SubHi);
1304 MRI.clearKillFlags(Src1SubLo);
1305 MRI.clearKillFlags(Src2SubHi);
1306 MRI.clearKillFlags(Src2SubLo);
1307 return true;
1308 }
1309 case Hexagon::PS_vmulw_acc: {
1310 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1311 Register DstReg = MI.getOperand(0).getReg();
1312 Register Src1Reg = MI.getOperand(1).getReg();
1313 Register Src2Reg = MI.getOperand(2).getReg();
1314 Register Src3Reg = MI.getOperand(3).getReg();
1315 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1316 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1317 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1318 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1319 Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1320 Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1321 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1322 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1323 .addReg(Src1SubHi)
1324 .addReg(Src2SubHi)
1325 .addReg(Src3SubHi);
1326 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1327 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1328 .addReg(Src1SubLo)
1329 .addReg(Src2SubLo)
1330 .addReg(Src3SubLo);
1331 MBB.erase(MI);
1332 MRI.clearKillFlags(Src1SubHi);
1333 MRI.clearKillFlags(Src1SubLo);
1334 MRI.clearKillFlags(Src2SubHi);
1335 MRI.clearKillFlags(Src2SubLo);
1336 MRI.clearKillFlags(Src3SubHi);
1337 MRI.clearKillFlags(Src3SubLo);
1338 return true;
1339 }
1340 case Hexagon::PS_pselect: {
1341 const MachineOperand &Op0 = MI.getOperand(0);
1342 const MachineOperand &Op1 = MI.getOperand(1);
1343 const MachineOperand &Op2 = MI.getOperand(2);
1344 const MachineOperand &Op3 = MI.getOperand(3);
1345 Register Rd = Op0.getReg();
1346 Register Pu = Op1.getReg();
1347 Register Rs = Op2.getReg();
1348 Register Rt = Op3.getReg();
1349 DebugLoc DL = MI.getDebugLoc();
1350 unsigned K1 = getKillRegState(Op1.isKill());
1351 unsigned K2 = getKillRegState(Op2.isKill());
1352 unsigned K3 = getKillRegState(Op3.isKill());
1353 if (Rd != Rs)
1354 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1355 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1356 .addReg(Rs, K2);
1357 if (Rd != Rt)
1358 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1359 .addReg(Pu, K1)
1360 .addReg(Rt, K3);
1361 MBB.erase(MI);
1362 return true;
1363 }
1364 case Hexagon::PS_vselect: {
1365 const MachineOperand &Op0 = MI.getOperand(0);
1366 const MachineOperand &Op1 = MI.getOperand(1);
1367 const MachineOperand &Op2 = MI.getOperand(2);
1368 const MachineOperand &Op3 = MI.getOperand(3);
1369 getLiveOutRegsAt(LiveOut, MI);
1370 bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
1371 Register PReg = Op1.getReg();
1372 assert(Op1.getSubReg() == 0);
1373 unsigned PState = getRegState(Op1);
1374
1375 if (Op0.getReg() != Op2.getReg()) {
1376 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1377 : PState;
1378 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1379 .add(Op0)
1380 .addReg(PReg, S)
1381 .add(Op2);
1382 if (IsDestLive)
1383 T.addReg(Op0.getReg(), RegState::Implicit);
1384 IsDestLive = true;
1385 }
1386 if (Op0.getReg() != Op3.getReg()) {
1387 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1388 .add(Op0)
1389 .addReg(PReg, PState)
1390 .add(Op3);
1391 if (IsDestLive)
1392 T.addReg(Op0.getReg(), RegState::Implicit);
1393 }
1394 MBB.erase(MI);
1395 return true;
1396 }
1397 case Hexagon::PS_wselect: {
1398 MachineOperand &Op0 = MI.getOperand(0);
1399 MachineOperand &Op1 = MI.getOperand(1);
1400 MachineOperand &Op2 = MI.getOperand(2);
1401 MachineOperand &Op3 = MI.getOperand(3);
1402 getLiveOutRegsAt(LiveOut, MI);
1403 bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
1404 Register PReg = Op1.getReg();
1405 assert(Op1.getSubReg() == 0);
1406 unsigned PState = getRegState(Op1);
1407
1408 if (Op0.getReg() != Op2.getReg()) {
1409 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1410 : PState;
1411 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1412 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1413 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1414 .add(Op0)
1415 .addReg(PReg, S)
1416 .addReg(SrcHi)
1417 .addReg(SrcLo);
1418 if (IsDestLive)
1419 T.addReg(Op0.getReg(), RegState::Implicit);
1420 IsDestLive = true;
1421 }
1422 if (Op0.getReg() != Op3.getReg()) {
1423 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1424 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1425 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1426 .add(Op0)
1427 .addReg(PReg, PState)
1428 .addReg(SrcHi)
1429 .addReg(SrcLo);
1430 if (IsDestLive)
1431 T.addReg(Op0.getReg(), RegState::Implicit);
1432 }
1433 MBB.erase(MI);
1434 return true;
1435 }
1436
1437 case Hexagon::PS_crash: {
1438 // Generate a misaligned load that is guaranteed to cause a crash.
1439 class CrashPseudoSourceValue : public PseudoSourceValue {
1440 public:
1441 CrashPseudoSourceValue(const TargetMachine &TM)
1442 : PseudoSourceValue(TargetCustom, TM) {}
1443
1444 bool isConstant(const MachineFrameInfo *) const override {
1445 return false;
1446 }
1447 bool isAliased(const MachineFrameInfo *) const override {
1448 return false;
1449 }
1450 bool mayAlias(const MachineFrameInfo *) const override {
1451 return false;
1452 }
1453 void printCustom(raw_ostream &OS) const override {
1454 OS << "MisalignedCrash";
1455 }
1456 };
1457
1458 static const CrashPseudoSourceValue CrashPSV(MF.getTarget());
1460 MachinePointerInfo(&CrashPSV),
1462 Align(1));
1463 BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
1464 .addImm(0xBADC0FEE) // Misaligned load.
1465 .addMemOperand(MMO);
1466 MBB.erase(MI);
1467 return true;
1468 }
1469
1470 case Hexagon::PS_tailcall_i:
1471 MI.setDesc(get(Hexagon::J2_jump));
1472 return true;
1473 case Hexagon::PS_tailcall_r:
1474 case Hexagon::PS_jmpret:
1475 MI.setDesc(get(Hexagon::J2_jumpr));
1476 return true;
1477 case Hexagon::PS_jmprett:
1478 MI.setDesc(get(Hexagon::J2_jumprt));
1479 return true;
1480 case Hexagon::PS_jmpretf:
1481 MI.setDesc(get(Hexagon::J2_jumprf));
1482 return true;
1483 case Hexagon::PS_jmprettnewpt:
1484 MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1485 return true;
1486 case Hexagon::PS_jmpretfnewpt:
1487 MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1488 return true;
1489 case Hexagon::PS_jmprettnew:
1490 MI.setDesc(get(Hexagon::J2_jumprtnew));
1491 return true;
1492 case Hexagon::PS_jmpretfnew:
1493 MI.setDesc(get(Hexagon::J2_jumprfnew));
1494 return true;
1495
1496 case Hexagon::PS_loadrub_pci:
1497 return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1498 case Hexagon::PS_loadrb_pci:
1499 return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1500 case Hexagon::PS_loadruh_pci:
1501 return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1502 case Hexagon::PS_loadrh_pci:
1503 return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1504 case Hexagon::PS_loadri_pci:
1505 return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1506 case Hexagon::PS_loadrd_pci:
1507 return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1508 case Hexagon::PS_loadrub_pcr:
1509 return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1510 case Hexagon::PS_loadrb_pcr:
1511 return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1512 case Hexagon::PS_loadruh_pcr:
1513 return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1514 case Hexagon::PS_loadrh_pcr:
1515 return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1516 case Hexagon::PS_loadri_pcr:
1517 return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1518 case Hexagon::PS_loadrd_pcr:
1519 return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1520 case Hexagon::PS_storerb_pci:
1521 return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1522 case Hexagon::PS_storerh_pci:
1523 return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1524 case Hexagon::PS_storerf_pci:
1525 return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1526 case Hexagon::PS_storeri_pci:
1527 return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1528 case Hexagon::PS_storerd_pci:
1529 return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1530 case Hexagon::PS_storerb_pcr:
1531 return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1532 case Hexagon::PS_storerh_pcr:
1533 return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1534 case Hexagon::PS_storerf_pcr:
1535 return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1536 case Hexagon::PS_storeri_pcr:
1537 return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1538 case Hexagon::PS_storerd_pcr:
1539 return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1540 }
1541
1542 return false;
1543}
1544
1547 MachineBasicBlock &MBB = *MI.getParent();
1548 const DebugLoc &DL = MI.getDebugLoc();
1549 unsigned Opc = MI.getOpcode();
1551
1552 switch (Opc) {
1553 case Hexagon::V6_vgathermh_pseudo:
1554 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1555 .add(MI.getOperand(2))
1556 .add(MI.getOperand(3))
1557 .add(MI.getOperand(4));
1558 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1559 .add(MI.getOperand(0))
1560 .addImm(MI.getOperand(1).getImm())
1561 .addReg(Hexagon::VTMP);
1562 MBB.erase(MI);
1563 return First.getInstrIterator();
1564
1565 case Hexagon::V6_vgathermw_pseudo:
1566 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1567 .add(MI.getOperand(2))
1568 .add(MI.getOperand(3))
1569 .add(MI.getOperand(4));
1570 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1571 .add(MI.getOperand(0))
1572 .addImm(MI.getOperand(1).getImm())
1573 .addReg(Hexagon::VTMP);
1574 MBB.erase(MI);
1575 return First.getInstrIterator();
1576
1577 case Hexagon::V6_vgathermhw_pseudo:
1578 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1579 .add(MI.getOperand(2))
1580 .add(MI.getOperand(3))
1581 .add(MI.getOperand(4));
1582 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1583 .add(MI.getOperand(0))
1584 .addImm(MI.getOperand(1).getImm())
1585 .addReg(Hexagon::VTMP);
1586 MBB.erase(MI);
1587 return First.getInstrIterator();
1588
1589 case Hexagon::V6_vgathermhq_pseudo:
1590 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1591 .add(MI.getOperand(2))
1592 .add(MI.getOperand(3))
1593 .add(MI.getOperand(4))
1594 .add(MI.getOperand(5));
1595 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1596 .add(MI.getOperand(0))
1597 .addImm(MI.getOperand(1).getImm())
1598 .addReg(Hexagon::VTMP);
1599 MBB.erase(MI);
1600 return First.getInstrIterator();
1601
1602 case Hexagon::V6_vgathermwq_pseudo:
1603 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1604 .add(MI.getOperand(2))
1605 .add(MI.getOperand(3))
1606 .add(MI.getOperand(4))
1607 .add(MI.getOperand(5));
1608 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1609 .add(MI.getOperand(0))
1610 .addImm(MI.getOperand(1).getImm())
1611 .addReg(Hexagon::VTMP);
1612 MBB.erase(MI);
1613 return First.getInstrIterator();
1614
1615 case Hexagon::V6_vgathermhwq_pseudo:
1616 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1617 .add(MI.getOperand(2))
1618 .add(MI.getOperand(3))
1619 .add(MI.getOperand(4))
1620 .add(MI.getOperand(5));
1621 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1622 .add(MI.getOperand(0))
1623 .addImm(MI.getOperand(1).getImm())
1624 .addReg(Hexagon::VTMP);
1625 MBB.erase(MI);
1626 return First.getInstrIterator();
1627 }
1628
1629 return MI.getIterator();
1630}
1631
1632// We indicate that we want to reverse the branch by
1633// inserting the reversed branching opcode.
1636 if (Cond.empty())
1637 return true;
1638 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1639 unsigned opcode = Cond[0].getImm();
1640 //unsigned temp;
1641 assert(get(opcode).isBranch() && "Should be a branching condition.");
1642 if (isEndLoopN(opcode))
1643 return true;
1644 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1645 Cond[0].setImm(NewOpcode);
1646 return false;
1647}
1648
1651 DebugLoc DL;
1652 BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1653}
1654
1657}
1658
1659// Returns true if an instruction is predicated irrespective of the predicate
1660// sense. For example, all of the following will return true.
1661// if (p0) R1 = add(R2, R3)
1662// if (!p0) R1 = add(R2, R3)
1663// if (p0.new) R1 = add(R2, R3)
1664// if (!p0.new) R1 = add(R2, R3)
1665// Note: New-value stores are not included here as in the current
1666// implementation, we don't need to check their predicate sense.
1668 const uint64_t F = MI.getDesc().TSFlags;
1670}
1671
1674 if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1675 isEndLoopN(Cond[0].getImm())) {
1676 LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1677 return false;
1678 }
1679 int Opc = MI.getOpcode();
1680 assert (isPredicable(MI) && "Expected predicable instruction");
1681 bool invertJump = predOpcodeHasNot(Cond);
1682
1683 // We have to predicate MI "in place", i.e. after this function returns,
1684 // MI will need to be transformed into a predicated form. To avoid com-
1685 // plicated manipulations with the operands (handling tied operands,
1686 // etc.), build a new temporary instruction, then overwrite MI with it.
1687
1688 MachineBasicBlock &B = *MI.getParent();
1689 DebugLoc DL = MI.getDebugLoc();
1690 unsigned PredOpc = getCondOpcode(Opc, invertJump);
1691 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1692 unsigned NOp = 0, NumOps = MI.getNumOperands();
1693 while (NOp < NumOps) {
1694 MachineOperand &Op = MI.getOperand(NOp);
1695 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1696 break;
1697 T.add(Op);
1698 NOp++;
1699 }
1700
1701 Register PredReg;
1702 unsigned PredRegPos, PredRegFlags;
1703 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1704 (void)GotPredReg;
1705 assert(GotPredReg);
1706 T.addReg(PredReg, PredRegFlags);
1707 while (NOp < NumOps)
1708 T.add(MI.getOperand(NOp++));
1709
1710 MI.setDesc(get(PredOpc));
1711 while (unsigned n = MI.getNumOperands())
1712 MI.removeOperand(n-1);
1713 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1714 MI.addOperand(T->getOperand(i));
1715
1716 MachineBasicBlock::instr_iterator TI = T->getIterator();
1717 B.erase(TI);
1718
1719 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1720 MRI.clearKillFlags(PredReg);
1721 return true;
1722}
1723
1725 ArrayRef<MachineOperand> Pred2) const {
1726 // TODO: Fix this
1727 return false;
1728}
1729
1731 std::vector<MachineOperand> &Pred,
1732 bool SkipDead) const {
1733 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1734
1735 for (const MachineOperand &MO : MI.operands()) {
1736 if (MO.isReg()) {
1737 if (!MO.isDef())
1738 continue;
1739 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1740 if (RC == &Hexagon::PredRegsRegClass) {
1741 Pred.push_back(MO);
1742 return true;
1743 }
1744 continue;
1745 } else if (MO.isRegMask()) {
1746 for (Register PR : Hexagon::PredRegsRegClass) {
1747 if (!MI.modifiesRegister(PR, &HRI))
1748 continue;
1749 Pred.push_back(MO);
1750 return true;
1751 }
1752 }
1753 }
1754 return false;
1755}
1756
1758 if (!MI.getDesc().isPredicable())
1759 return false;
1760
1761 if (MI.isCall() || isTailCall(MI)) {
1762 if (!Subtarget.usePredicatedCalls())
1763 return false;
1764 }
1765
1766 // HVX loads are not predicable on v60, but are on v62.
1767 if (!Subtarget.hasV62Ops()) {
1768 switch (MI.getOpcode()) {
1769 case Hexagon::V6_vL32b_ai:
1770 case Hexagon::V6_vL32b_pi:
1771 case Hexagon::V6_vL32b_ppu:
1772 case Hexagon::V6_vL32b_cur_ai:
1773 case Hexagon::V6_vL32b_cur_pi:
1774 case Hexagon::V6_vL32b_cur_ppu:
1775 case Hexagon::V6_vL32b_nt_ai:
1776 case Hexagon::V6_vL32b_nt_pi:
1777 case Hexagon::V6_vL32b_nt_ppu:
1778 case Hexagon::V6_vL32b_tmp_ai:
1779 case Hexagon::V6_vL32b_tmp_pi:
1780 case Hexagon::V6_vL32b_tmp_ppu:
1781 case Hexagon::V6_vL32b_nt_cur_ai:
1782 case Hexagon::V6_vL32b_nt_cur_pi:
1783 case Hexagon::V6_vL32b_nt_cur_ppu:
1784 case Hexagon::V6_vL32b_nt_tmp_ai:
1785 case Hexagon::V6_vL32b_nt_tmp_pi:
1786 case Hexagon::V6_vL32b_nt_tmp_ppu:
1787 return false;
1788 }
1789 }
1790 return true;
1791}
1792
1794 const MachineBasicBlock *MBB,
1795 const MachineFunction &MF) const {
1796 // Debug info is never a scheduling boundary. It's necessary to be explicit
1797 // due to the special treatment of IT instructions below, otherwise a
1798 // dbg_value followed by an IT will result in the IT instruction being
1799 // considered a scheduling hazard, which is wrong. It should be the actual
1800 // instruction preceding the dbg_value instruction(s), just like it is
1801 // when debug info is not present.
1802 if (MI.isDebugInstr())
1803 return false;
1804
1805 // Throwing call is a boundary.
1806 if (MI.isCall()) {
1807 // Don't mess around with no return calls.
1808 if (doesNotReturn(MI))
1809 return true;
1810 // If any of the block's successors is a landing pad, this could be a
1811 // throwing call.
1812 for (auto *I : MBB->successors())
1813 if (I->isEHPad())
1814 return true;
1815 }
1816
1817 // Terminators and labels can't be scheduled around.
1818 if (MI.getDesc().isTerminator() || MI.isPosition())
1819 return true;
1820
1821 // INLINEASM_BR can jump to another block
1822 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1823 return true;
1824
1825 if (MI.isInlineAsm() && !ScheduleInlineAsm)
1826 return true;
1827
1828 return false;
1829}
1830
1831/// Measure the specified inline asm to determine an approximation of its
1832/// length.
1833/// Comments (which run till the next SeparatorString or newline) do not
1834/// count as an instruction.
1835/// Any other non-whitespace text is considered an instruction, with
1836/// multiple instructions separated by SeparatorString or newlines.
1837/// Variable-length instructions are not handled here; this function
1838/// may be overloaded in the target code to do that.
1839/// Hexagon counts the number of ##'s and adjust for that many
1840/// constant exenders.
1842 const MCAsmInfo &MAI,
1843 const TargetSubtargetInfo *STI) const {
1844 StringRef AStr(Str);
1845 // Count the number of instructions in the asm.
1846 bool atInsnStart = true;
1847 unsigned Length = 0;
1848 const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
1849 for (; *Str; ++Str) {
1850 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1851 strlen(MAI.getSeparatorString())) == 0)
1852 atInsnStart = true;
1853 if (atInsnStart && !isSpace(static_cast<unsigned char>(*Str))) {
1854 Length += MaxInstLength;
1855 atInsnStart = false;
1856 }
1857 if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1858 MAI.getCommentString().size()) == 0)
1859 atInsnStart = false;
1860 }
1861
1862 // Add to size number of constant extenders seen * 4.
1863 StringRef Occ("##");
1864 Length += AStr.count(Occ)*4;
1865 return Length;
1866}
1867
1870 const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1871 if (UseDFAHazardRec)
1872 return new HexagonHazardRecognizer(II, this, Subtarget);
1874}
1875
1876/// For a comparison instruction, return the source registers in
1877/// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1878/// compares against in CmpValue. Return true if the comparison instruction
1879/// can be analyzed.
1881 Register &SrcReg2, int64_t &Mask,
1882 int64_t &Value) const {
1883 unsigned Opc = MI.getOpcode();
1884
1885 // Set mask and the first source register.
1886 switch (Opc) {
1887 case Hexagon::C2_cmpeq:
1888 case Hexagon::C2_cmpeqp:
1889 case Hexagon::C2_cmpgt:
1890 case Hexagon::C2_cmpgtp:
1891 case Hexagon::C2_cmpgtu:
1892 case Hexagon::C2_cmpgtup:
1893 case Hexagon::C4_cmpneq:
1894 case Hexagon::C4_cmplte:
1895 case Hexagon::C4_cmplteu:
1896 case Hexagon::C2_cmpeqi:
1897 case Hexagon::C2_cmpgti:
1898 case Hexagon::C2_cmpgtui:
1899 case Hexagon::C4_cmpneqi:
1900 case Hexagon::C4_cmplteui:
1901 case Hexagon::C4_cmpltei:
1902 SrcReg = MI.getOperand(1).getReg();
1903 Mask = ~0;
1904 break;
1905 case Hexagon::A4_cmpbeq:
1906 case Hexagon::A4_cmpbgt:
1907 case Hexagon::A4_cmpbgtu:
1908 case Hexagon::A4_cmpbeqi:
1909 case Hexagon::A4_cmpbgti:
1910 case Hexagon::A4_cmpbgtui:
1911 SrcReg = MI.getOperand(1).getReg();
1912 Mask = 0xFF;
1913 break;
1914 case Hexagon::A4_cmpheq:
1915 case Hexagon::A4_cmphgt:
1916 case Hexagon::A4_cmphgtu:
1917 case Hexagon::A4_cmpheqi:
1918 case Hexagon::A4_cmphgti:
1919 case Hexagon::A4_cmphgtui:
1920 SrcReg = MI.getOperand(1).getReg();
1921 Mask = 0xFFFF;
1922 break;
1923 }
1924
1925 // Set the value/second source register.
1926 switch (Opc) {
1927 case Hexagon::C2_cmpeq:
1928 case Hexagon::C2_cmpeqp:
1929 case Hexagon::C2_cmpgt:
1930 case Hexagon::C2_cmpgtp:
1931 case Hexagon::C2_cmpgtu:
1932 case Hexagon::C2_cmpgtup:
1933 case Hexagon::A4_cmpbeq:
1934 case Hexagon::A4_cmpbgt:
1935 case Hexagon::A4_cmpbgtu:
1936 case Hexagon::A4_cmpheq:
1937 case Hexagon::A4_cmphgt:
1938 case Hexagon::A4_cmphgtu:
1939 case Hexagon::C4_cmpneq:
1940 case Hexagon::C4_cmplte:
1941 case Hexagon::C4_cmplteu:
1942 SrcReg2 = MI.getOperand(2).getReg();
1943 Value = 0;
1944 return true;
1945
1946 case Hexagon::C2_cmpeqi:
1947 case Hexagon::C2_cmpgtui:
1948 case Hexagon::C2_cmpgti:
1949 case Hexagon::C4_cmpneqi:
1950 case Hexagon::C4_cmplteui:
1951 case Hexagon::C4_cmpltei:
1952 case Hexagon::A4_cmpbeqi:
1953 case Hexagon::A4_cmpbgti:
1954 case Hexagon::A4_cmpbgtui:
1955 case Hexagon::A4_cmpheqi:
1956 case Hexagon::A4_cmphgti:
1957 case Hexagon::A4_cmphgtui: {
1958 SrcReg2 = 0;
1959 const MachineOperand &Op2 = MI.getOperand(2);
1960 if (!Op2.isImm())
1961 return false;
1962 Value = MI.getOperand(2).getImm();
1963 return true;
1964 }
1965 }
1966
1967 return false;
1968}
1969
1971 const MachineInstr &MI,
1972 unsigned *PredCost) const {
1973 return getInstrTimingClassLatency(ItinData, MI);
1974}
1975
1977 const TargetSubtargetInfo &STI) const {
1979 return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1980}
1981
1982// Inspired by this pair:
1983// %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1984// S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1985// Currently AA considers the addresses in these instructions to be aliasing.
1987 const MachineInstr &MIa, const MachineInstr &MIb) const {
1990 return false;
1991
1992 // Instructions that are pure loads, not loads and stores like memops are not
1993 // dependent.
1994 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1995 return true;
1996
1997 // Get the base register in MIa.
1998 unsigned BasePosA, OffsetPosA;
1999 if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
2000 return false;
2001 const MachineOperand &BaseA = MIa.getOperand(BasePosA);
2002 Register BaseRegA = BaseA.getReg();
2003 unsigned BaseSubA = BaseA.getSubReg();
2004
2005 // Get the base register in MIb.
2006 unsigned BasePosB, OffsetPosB;
2007 if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
2008 return false;
2009 const MachineOperand &BaseB = MIb.getOperand(BasePosB);
2010 Register BaseRegB = BaseB.getReg();
2011 unsigned BaseSubB = BaseB.getSubReg();
2012
2013 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
2014 return false;
2015
2016 // Get the access sizes.
2017 unsigned SizeA = getMemAccessSize(MIa);
2018 unsigned SizeB = getMemAccessSize(MIb);
2019
2020 // Get the offsets. Handle immediates only for now.
2021 const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
2022 const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
2023 if (!MIa.getOperand(OffsetPosA).isImm() ||
2024 !MIb.getOperand(OffsetPosB).isImm())
2025 return false;
2026 int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
2027 int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
2028
2029 // This is a mem access with the same base register and known offsets from it.
2030 // Reason about it.
2031 if (OffsetA > OffsetB) {
2032 uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
2033 return SizeB <= OffDiff;
2034 }
2035 if (OffsetA < OffsetB) {
2036 uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
2037 return SizeA <= OffDiff;
2038 }
2039
2040 return false;
2041}
2042
2043/// If the instruction is an increment of a constant value, return the amount.
2045 int &Value) const {
2046 if (isPostIncrement(MI)) {
2047 unsigned BasePos = 0, OffsetPos = 0;
2048 if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
2049 return false;
2050 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
2051 if (OffsetOp.isImm()) {
2052 Value = OffsetOp.getImm();
2053 return true;
2054 }
2055 } else if (MI.getOpcode() == Hexagon::A2_addi) {
2056 const MachineOperand &AddOp = MI.getOperand(2);
2057 if (AddOp.isImm()) {
2058 Value = AddOp.getImm();
2059 return true;
2060 }
2061 }
2062
2063 return false;
2064}
2065
2066std::pair<unsigned, unsigned>
2068 return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
2070}
2071
2074 using namespace HexagonII;
2075
2076 static const std::pair<unsigned, const char*> Flags[] = {
2077 {MO_PCREL, "hexagon-pcrel"},
2078 {MO_GOT, "hexagon-got"},
2079 {MO_LO16, "hexagon-lo16"},
2080 {MO_HI16, "hexagon-hi16"},
2081 {MO_GPREL, "hexagon-gprel"},
2082 {MO_GDGOT, "hexagon-gdgot"},
2083 {MO_GDPLT, "hexagon-gdplt"},
2084 {MO_IE, "hexagon-ie"},
2085 {MO_IEGOT, "hexagon-iegot"},
2086 {MO_TPREL, "hexagon-tprel"}
2087 };
2088 return ArrayRef(Flags);
2089}
2090
2093 using namespace HexagonII;
2094
2095 static const std::pair<unsigned, const char*> Flags[] = {
2096 {HMOTF_ConstExtended, "hexagon-ext"}
2097 };
2098 return ArrayRef(Flags);
2099}
2100
2103 const TargetRegisterClass *TRC;
2104 if (VT == MVT::i1) {
2105 TRC = &Hexagon::PredRegsRegClass;
2106 } else if (VT == MVT::i32 || VT == MVT::f32) {
2107 TRC = &Hexagon::IntRegsRegClass;
2108 } else if (VT == MVT::i64 || VT == MVT::f64) {
2109 TRC = &Hexagon::DoubleRegsRegClass;
2110 } else {
2111 llvm_unreachable("Cannot handle this register class");
2112 }
2113
2114 Register NewReg = MRI.createVirtualRegister(TRC);
2115 return NewReg;
2116}
2117
2120}
2121
2123 const uint64_t F = MI.getDesc().TSFlags;
2125}
2126
2129}
2130
2132 return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
2133 !MI.getDesc().mayStore() &&
2134 MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2135 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2136 !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
2137}
2138
2139// Return true if the instruction is a compound branch instruction.
2141 return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
2142}
2143
2144// TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
2145// isFPImm and later getFPImm as well.
2147 const uint64_t F = MI.getDesc().TSFlags;
2149 if (isExtended) // Instruction must be extended.
2150 return true;
2151
2152 unsigned isExtendable =
2154 if (!isExtendable)
2155 return false;
2156
2157 if (MI.isCall())
2158 return false;
2159
2160 short ExtOpNum = getCExtOpNum(MI);
2161 const MachineOperand &MO = MI.getOperand(ExtOpNum);
2162 // Use MO operand flags to determine if MO
2163 // has the HMOTF_ConstExtended flag set.
2165 return true;
2166 // If this is a Machine BB address we are talking about, and it is
2167 // not marked as extended, say so.
2168 if (MO.isMBB())
2169 return false;
2170
2171 // We could be using an instruction with an extendable immediate and shoehorn
2172 // a global address into it. If it is a global address it will be constant
2173 // extended. We do this for COMBINE.
2174 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2175 MO.isJTI() || MO.isCPI() || MO.isFPImm())
2176 return true;
2177
2178 // If the extendable operand is not 'Immediate' type, the instruction should
2179 // have 'isExtended' flag set.
2180 assert(MO.isImm() && "Extendable operand must be Immediate type");
2181
2182 int64_t Value = MO.getImm();
2184 int32_t SValue = Value;
2185 int32_t MinValue = getMinValue(MI);
2186 int32_t MaxValue = getMaxValue(MI);
2187 return SValue < MinValue || SValue > MaxValue;
2188 }
2189 uint32_t UValue = Value;
2190 uint32_t MinValue = getMinValue(MI);
2191 uint32_t MaxValue = getMaxValue(MI);
2192 return UValue < MinValue || UValue > MaxValue;
2193}
2194
2196 switch (MI.getOpcode()) {
2197 case Hexagon::L4_return:
2198 case Hexagon::L4_return_t:
2199 case Hexagon::L4_return_f:
2200 case Hexagon::L4_return_tnew_pnt:
2201 case Hexagon::L4_return_fnew_pnt:
2202 case Hexagon::L4_return_tnew_pt:
2203 case Hexagon::L4_return_fnew_pt:
2204 return true;
2205 }
2206 return false;
2207}
2208
2209// Return true when ConsMI uses a register defined by ProdMI.
2211 const MachineInstr &ConsMI) const {
2212 if (!ProdMI.getDesc().getNumDefs())
2213 return false;
2214 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2215
2220
2221 parseOperands(ProdMI, DefsA, UsesA);
2222 parseOperands(ConsMI, DefsB, UsesB);
2223
2224 for (auto &RegA : DefsA)
2225 for (auto &RegB : UsesB) {
2226 // True data dependency.
2227 if (RegA == RegB)
2228 return true;
2229
2230 if (RegA.isPhysical() && llvm::is_contained(HRI.subregs(RegA), RegB))
2231 return true;
2232
2233 if (RegB.isPhysical() && llvm::is_contained(HRI.subregs(RegB), RegA))
2234 return true;
2235 }
2236
2237 return false;
2238}
2239
2240// Returns true if the instruction is alread a .cur.
2242 switch (MI.getOpcode()) {
2243 case Hexagon::V6_vL32b_cur_pi:
2244 case Hexagon::V6_vL32b_cur_ai:
2245 return true;
2246 }
2247 return false;
2248}
2249
2250// Returns true, if any one of the operands is a dot new
2251// insn, whether it is predicated dot new or register dot new.
2254 return true;
2255
2256 return false;
2257}
2258
2259/// Symmetrical. See if these two instructions are fit for duplex pair.
2261 const MachineInstr &MIb) const {
2264 return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2265}
2266
2267bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2268 return (Opcode == Hexagon::ENDLOOP0 ||
2269 Opcode == Hexagon::ENDLOOP1);
2270}
2271
2272bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2273 switch(OpType) {
2280 return true;
2281 default:
2282 return false;
2283 }
2284}
2285
2287 const MCInstrDesc &MID = MI.getDesc();
2288 const uint64_t F = MID.TSFlags;
2290 return true;
2291
2292 // TODO: This is largely obsolete now. Will need to be removed
2293 // in consecutive patches.
2294 switch (MI.getOpcode()) {
2295 // PS_fi and PS_fia remain special cases.
2296 case Hexagon::PS_fi:
2297 case Hexagon::PS_fia:
2298 return true;
2299 default:
2300 return false;
2301 }
2302 return false;
2303}
2304
2305// This returns true in two cases:
2306// - The OP code itself indicates that this is an extended instruction.
2307// - One of MOs has been marked with HMOTF_ConstExtended flag.
2309 // First check if this is permanently extended op code.
2310 const uint64_t F = MI.getDesc().TSFlags;
2312 return true;
2313 // Use MO operand flags to determine if one of MI's operands
2314 // has HMOTF_ConstExtended flag set.
2315 for (const MachineOperand &MO : MI.operands())
2316 if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2317 return true;
2318 return false;
2319}
2320
2322 unsigned Opcode = MI.getOpcode();
2323 const uint64_t F = get(Opcode).TSFlags;
2324 return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2325}
2326
2327// No V60 HVX VMEM with A_INDIRECT.
2329 const MachineInstr &J) const {
2330 if (!isHVXVec(I))
2331 return false;
2332 if (!I.mayLoad() && !I.mayStore())
2333 return false;
2334 return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2335}
2336
2338 switch (MI.getOpcode()) {
2339 case Hexagon::J2_callr:
2340 case Hexagon::J2_callrf:
2341 case Hexagon::J2_callrt:
2342 case Hexagon::PS_call_nr:
2343 return true;
2344 }
2345 return false;
2346}
2347
2349 switch (MI.getOpcode()) {
2350 case Hexagon::L4_return:
2351 case Hexagon::L4_return_t:
2352 case Hexagon::L4_return_f:
2353 case Hexagon::L4_return_fnew_pnt:
2354 case Hexagon::L4_return_fnew_pt:
2355 case Hexagon::L4_return_tnew_pnt:
2356 case Hexagon::L4_return_tnew_pt:
2357 return true;
2358 }
2359 return false;
2360}
2361
2363 switch (MI.getOpcode()) {
2364 case Hexagon::J2_jumpr:
2365 case Hexagon::J2_jumprt:
2366 case Hexagon::J2_jumprf:
2367 case Hexagon::J2_jumprtnewpt:
2368 case Hexagon::J2_jumprfnewpt:
2369 case Hexagon::J2_jumprtnew:
2370 case Hexagon::J2_jumprfnew:
2371 return true;
2372 }
2373 return false;
2374}
2375
2376// Return true if a given MI can accommodate given offset.
2377// Use abs estimate as oppose to the exact number.
2378// TODO: This will need to be changed to use MC level
2379// definition of instruction extendable field size.
2381 unsigned offset) const {
2382 // This selection of jump instructions matches to that what
2383 // analyzeBranch can parse, plus NVJ.
2384 if (isNewValueJump(MI)) // r9:2
2385 return isInt<11>(offset);
2386
2387 switch (MI.getOpcode()) {
2388 // Still missing Jump to address condition on register value.
2389 default:
2390 return false;
2391 case Hexagon::J2_jump: // bits<24> dst; // r22:2
2392 case Hexagon::J2_call:
2393 case Hexagon::PS_call_nr:
2394 return isInt<24>(offset);
2395 case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2396 case Hexagon::J2_jumpf:
2397 case Hexagon::J2_jumptnew:
2398 case Hexagon::J2_jumptnewpt:
2399 case Hexagon::J2_jumpfnew:
2400 case Hexagon::J2_jumpfnewpt:
2401 case Hexagon::J2_callt:
2402 case Hexagon::J2_callf:
2403 return isInt<17>(offset);
2404 case Hexagon::J2_loop0i:
2405 case Hexagon::J2_loop0iext:
2406 case Hexagon::J2_loop0r:
2407 case Hexagon::J2_loop0rext:
2408 case Hexagon::J2_loop1i:
2409 case Hexagon::J2_loop1iext:
2410 case Hexagon::J2_loop1r:
2411 case Hexagon::J2_loop1rext:
2412 return isInt<9>(offset);
2413 // TODO: Add all the compound branches here. Can we do this in Relation model?
2414 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2415 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2416 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2417 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2418 return isInt<11>(offset);
2419 }
2420}
2421
2423 // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2424 // resource, but all operands can be received late like an ALU instruction.
2426}
2427
2429 unsigned Opcode = MI.getOpcode();
2430 return Opcode == Hexagon::J2_loop0i ||
2431 Opcode == Hexagon::J2_loop0r ||
2432 Opcode == Hexagon::J2_loop0iext ||
2433 Opcode == Hexagon::J2_loop0rext ||
2434 Opcode == Hexagon::J2_loop1i ||
2435 Opcode == Hexagon::J2_loop1r ||
2436 Opcode == Hexagon::J2_loop1iext ||
2437 Opcode == Hexagon::J2_loop1rext;
2438}
2439
2441 switch (MI.getOpcode()) {
2442 default: return false;
2443 case Hexagon::L4_iadd_memopw_io:
2444 case Hexagon::L4_isub_memopw_io:
2445 case Hexagon::L4_add_memopw_io:
2446 case Hexagon::L4_sub_memopw_io:
2447 case Hexagon::L4_and_memopw_io:
2448 case Hexagon::L4_or_memopw_io:
2449 case Hexagon::L4_iadd_memoph_io:
2450 case Hexagon::L4_isub_memoph_io:
2451 case Hexagon::L4_add_memoph_io:
2452 case Hexagon::L4_sub_memoph_io:
2453 case Hexagon::L4_and_memoph_io:
2454 case Hexagon::L4_or_memoph_io:
2455 case Hexagon::L4_iadd_memopb_io:
2456 case Hexagon::L4_isub_memopb_io:
2457 case Hexagon::L4_add_memopb_io:
2458 case Hexagon::L4_sub_memopb_io:
2459 case Hexagon::L4_and_memopb_io:
2460 case Hexagon::L4_or_memopb_io:
2461 case Hexagon::L4_ior_memopb_io:
2462 case Hexagon::L4_ior_memoph_io:
2463 case Hexagon::L4_ior_memopw_io:
2464 case Hexagon::L4_iand_memopb_io:
2465 case Hexagon::L4_iand_memoph_io:
2466 case Hexagon::L4_iand_memopw_io:
2467 return true;
2468 }
2469 return false;
2470}
2471
2473 const uint64_t F = MI.getDesc().TSFlags;
2475}
2476
2477bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2478 const uint64_t F = get(Opcode).TSFlags;
2480}
2481
2483 return isNewValueJump(MI) || isNewValueStore(MI);
2484}
2485
2487 return isNewValue(MI) && MI.isBranch();
2488}
2489
2490bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2491 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2492}
2493
2495 const uint64_t F = MI.getDesc().TSFlags;
2497}
2498
2499bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2500 const uint64_t F = get(Opcode).TSFlags;
2502}
2503
2504// Returns true if a particular operand is extendable for an instruction.
2506 unsigned OperandNum) const {
2507 const uint64_t F = MI.getDesc().TSFlags;
2509 == OperandNum;
2510}
2511
2513 const uint64_t F = MI.getDesc().TSFlags;
2516}
2517
2518bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2519 const uint64_t F = get(Opcode).TSFlags;
2520 assert(isPredicated(Opcode));
2522}
2523
2525 const uint64_t F = MI.getDesc().TSFlags;
2526 return !((F >> HexagonII::PredicatedFalsePos) &
2528}
2529
2530bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2531 const uint64_t F = get(Opcode).TSFlags;
2532 // Make sure that the instruction is predicated.
2534 return !((F >> HexagonII::PredicatedFalsePos) &
2536}
2537
2538bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2539 const uint64_t F = get(Opcode).TSFlags;
2541}
2542
2543bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2544 const uint64_t F = get(Opcode).TSFlags;
2546}
2547
2548bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2549 const uint64_t F = get(Opcode).TSFlags;
2550 assert(get(Opcode).isBranch() &&
2551 (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2553}
2554
2556 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2557 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2558 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2559 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2560}
2561
2563 switch (MI.getOpcode()) {
2564 // Byte
2565 case Hexagon::L2_loadrb_io:
2566 case Hexagon::L4_loadrb_ur:
2567 case Hexagon::L4_loadrb_ap:
2568 case Hexagon::L2_loadrb_pr:
2569 case Hexagon::L2_loadrb_pbr:
2570 case Hexagon::L2_loadrb_pi:
2571 case Hexagon::L2_loadrb_pci:
2572 case Hexagon::L2_loadrb_pcr:
2573 case Hexagon::L2_loadbsw2_io:
2574 case Hexagon::L4_loadbsw2_ur:
2575 case Hexagon::L4_loadbsw2_ap:
2576 case Hexagon::L2_loadbsw2_pr:
2577 case Hexagon::L2_loadbsw2_pbr:
2578 case Hexagon::L2_loadbsw2_pi:
2579 case Hexagon::L2_loadbsw2_pci:
2580 case Hexagon::L2_loadbsw2_pcr:
2581 case Hexagon::L2_loadbsw4_io:
2582 case Hexagon::L4_loadbsw4_ur:
2583 case Hexagon::L4_loadbsw4_ap:
2584 case Hexagon::L2_loadbsw4_pr:
2585 case Hexagon::L2_loadbsw4_pbr:
2586 case Hexagon::L2_loadbsw4_pi:
2587 case Hexagon::L2_loadbsw4_pci:
2588 case Hexagon::L2_loadbsw4_pcr:
2589 case Hexagon::L4_loadrb_rr:
2590 case Hexagon::L2_ploadrbt_io:
2591 case Hexagon::L2_ploadrbt_pi:
2592 case Hexagon::L2_ploadrbf_io:
2593 case Hexagon::L2_ploadrbf_pi:
2594 case Hexagon::L2_ploadrbtnew_io:
2595 case Hexagon::L2_ploadrbfnew_io:
2596 case Hexagon::L4_ploadrbt_rr:
2597 case Hexagon::L4_ploadrbf_rr:
2598 case Hexagon::L4_ploadrbtnew_rr:
2599 case Hexagon::L4_ploadrbfnew_rr:
2600 case Hexagon::L2_ploadrbtnew_pi:
2601 case Hexagon::L2_ploadrbfnew_pi:
2602 case Hexagon::L4_ploadrbt_abs:
2603 case Hexagon::L4_ploadrbf_abs:
2604 case Hexagon::L4_ploadrbtnew_abs:
2605 case Hexagon::L4_ploadrbfnew_abs:
2606 case Hexagon::L2_loadrbgp:
2607 // Half
2608 case Hexagon::L2_loadrh_io:
2609 case Hexagon::L4_loadrh_ur:
2610 case Hexagon::L4_loadrh_ap:
2611 case Hexagon::L2_loadrh_pr:
2612 case Hexagon::L2_loadrh_pbr:
2613 case Hexagon::L2_loadrh_pi:
2614 case Hexagon::L2_loadrh_pci:
2615 case Hexagon::L2_loadrh_pcr:
2616 case Hexagon::L4_loadrh_rr:
2617 case Hexagon::L2_ploadrht_io:
2618 case Hexagon::L2_ploadrht_pi:
2619 case Hexagon::L2_ploadrhf_io:
2620 case Hexagon::L2_ploadrhf_pi:
2621 case Hexagon::L2_ploadrhtnew_io:
2622 case Hexagon::L2_ploadrhfnew_io:
2623 case Hexagon::L4_ploadrht_rr:
2624 case Hexagon::L4_ploadrhf_rr:
2625 case Hexagon::L4_ploadrhtnew_rr:
2626 case Hexagon::L4_ploadrhfnew_rr:
2627 case Hexagon::L2_ploadrhtnew_pi:
2628 case Hexagon::L2_ploadrhfnew_pi:
2629 case Hexagon::L4_ploadrht_abs:
2630 case Hexagon::L4_ploadrhf_abs:
2631 case Hexagon::L4_ploadrhtnew_abs:
2632 case Hexagon::L4_ploadrhfnew_abs:
2633 case Hexagon::L2_loadrhgp:
2634 return true;
2635 default:
2636 return false;
2637 }
2638}
2639
2641 const uint64_t F = MI.getDesc().TSFlags;
2643}
2644
2646 switch (MI.getOpcode()) {
2647 case Hexagon::STriw_pred:
2648 case Hexagon::LDriw_pred:
2649 return true;
2650 default:
2651 return false;
2652 }
2653}
2654
2656 if (!MI.isBranch())
2657 return false;
2658
2659 for (auto &Op : MI.operands())
2660 if (Op.isGlobal() || Op.isSymbol())
2661 return true;
2662 return false;
2663}
2664
2665// Returns true when SU has a timing class TC1.
2667 unsigned SchedClass = MI.getDesc().getSchedClass();
2668 return is_TC1(SchedClass);
2669}
2670
2672 unsigned SchedClass = MI.getDesc().getSchedClass();
2673 return is_TC2(SchedClass);
2674}
2675
2677 unsigned SchedClass = MI.getDesc().getSchedClass();
2678 return is_TC2early(SchedClass);
2679}
2680
2682 unsigned SchedClass = MI.getDesc().getSchedClass();
2683 return is_TC4x(SchedClass);
2684}
2685
2686// Schedule this ASAP.
2688 const MachineInstr &MI2) const {
2689 if (mayBeCurLoad(MI1)) {
2690 // if (result of SU is used in Next) return true;
2691 Register DstReg = MI1.getOperand(0).getReg();
2692 int N = MI2.getNumOperands();
2693 for (int I = 0; I < N; I++)
2694 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2695 return true;
2696 }
2697 if (mayBeNewStore(MI2))
2698 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2699 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2700 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2701 return true;
2702 return false;
2703}
2704
2706 const uint64_t V = getType(MI);
2708}
2709
2710// Check if the Offset is a valid auto-inc imm by Load/Store Type.
2712 int Size = VT.getSizeInBits() / 8;
2713 if (Offset % Size != 0)
2714 return false;
2715 int Count = Offset / Size;
2716
2717 switch (VT.getSimpleVT().SimpleTy) {
2718 // For scalars the auto-inc is s4
2719 case MVT::i8:
2720 case MVT::i16:
2721 case MVT::i32:
2722 case MVT::i64:
2723 case MVT::f32:
2724 case MVT::f64:
2725 case MVT::v2i16:
2726 case MVT::v2i32:
2727 case MVT::v4i8:
2728 case MVT::v4i16:
2729 case MVT::v8i8:
2730 return isInt<4>(Count);
2731 // For HVX vectors the auto-inc is s3
2732 case MVT::v64i8:
2733 case MVT::v32i16:
2734 case MVT::v16i32:
2735 case MVT::v8i64:
2736 case MVT::v128i8:
2737 case MVT::v64i16:
2738 case MVT::v32i32:
2739 case MVT::v16i64:
2740 return isInt<3>(Count);
2741 default:
2742 break;
2743 }
2744
2745 llvm_unreachable("Not an valid type!");
2746}
2747
2748bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2749 const TargetRegisterInfo *TRI, bool Extend) const {
2750 // This function is to check whether the "Offset" is in the correct range of
2751 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2752 // inserted to calculate the final address. Due to this reason, the function
2753 // assumes that the "Offset" has correct alignment.
2754 // We used to assert if the offset was not properly aligned, however,
2755 // there are cases where a misaligned pointer recast can cause this
2756 // problem, and we need to allow for it. The front end warns of such
2757 // misaligns with respect to load size.
2758 switch (Opcode) {
2759 case Hexagon::PS_vstorerq_ai:
2760 case Hexagon::PS_vstorerv_ai:
2761 case Hexagon::PS_vstorerw_ai:
2762 case Hexagon::PS_vstorerw_nt_ai:
2763 case Hexagon::PS_vloadrq_ai:
2764 case Hexagon::PS_vloadrv_ai:
2765 case Hexagon::PS_vloadrw_ai:
2766 case Hexagon::PS_vloadrw_nt_ai:
2767 case Hexagon::V6_vL32b_ai:
2768 case Hexagon::V6_vS32b_ai:
2769 case Hexagon::V6_vS32b_pred_ai:
2770 case Hexagon::V6_vS32b_npred_ai:
2771 case Hexagon::V6_vS32b_qpred_ai:
2772 case Hexagon::V6_vS32b_nqpred_ai:
2773 case Hexagon::V6_vS32b_new_ai:
2774 case Hexagon::V6_vS32b_new_pred_ai:
2775 case Hexagon::V6_vS32b_new_npred_ai:
2776 case Hexagon::V6_vS32b_nt_pred_ai:
2777 case Hexagon::V6_vS32b_nt_npred_ai:
2778 case Hexagon::V6_vS32b_nt_new_ai:
2779 case Hexagon::V6_vS32b_nt_new_pred_ai:
2780 case Hexagon::V6_vS32b_nt_new_npred_ai:
2781 case Hexagon::V6_vS32b_nt_qpred_ai:
2782 case Hexagon::V6_vS32b_nt_nqpred_ai:
2783 case Hexagon::V6_vL32b_nt_ai:
2784 case Hexagon::V6_vS32b_nt_ai:
2785 case Hexagon::V6_vL32Ub_ai:
2786 case Hexagon::V6_vS32Ub_ai:
2787 case Hexagon::V6_vL32b_cur_ai:
2788 case Hexagon::V6_vL32b_tmp_ai:
2789 case Hexagon::V6_vL32b_pred_ai:
2790 case Hexagon::V6_vL32b_npred_ai:
2791 case Hexagon::V6_vL32b_cur_pred_ai:
2792 case Hexagon::V6_vL32b_cur_npred_ai:
2793 case Hexagon::V6_vL32b_tmp_pred_ai:
2794 case Hexagon::V6_vL32b_tmp_npred_ai:
2795 case Hexagon::V6_vL32b_nt_cur_ai:
2796 case Hexagon::V6_vL32b_nt_tmp_ai:
2797 case Hexagon::V6_vL32b_nt_pred_ai:
2798 case Hexagon::V6_vL32b_nt_npred_ai:
2799 case Hexagon::V6_vL32b_nt_cur_pred_ai:
2800 case Hexagon::V6_vL32b_nt_cur_npred_ai:
2801 case Hexagon::V6_vL32b_nt_tmp_pred_ai:
2802 case Hexagon::V6_vL32b_nt_tmp_npred_ai:
2803 case Hexagon::V6_vgathermh_pseudo:
2804 case Hexagon::V6_vgathermw_pseudo:
2805 case Hexagon::V6_vgathermhw_pseudo:
2806 case Hexagon::V6_vgathermhq_pseudo:
2807 case Hexagon::V6_vgathermwq_pseudo:
2808 case Hexagon::V6_vgathermhwq_pseudo: {
2809 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2810 assert(isPowerOf2_32(VectorSize));
2811 if (Offset & (VectorSize-1))
2812 return false;
2813 return isInt<4>(Offset >> Log2_32(VectorSize));
2814 }
2815
2816 case Hexagon::J2_loop0i:
2817 case Hexagon::J2_loop1i:
2818 return isUInt<10>(Offset);
2819
2820 case Hexagon::S4_storeirb_io:
2821 case Hexagon::S4_storeirbt_io:
2822 case Hexagon::S4_storeirbf_io:
2823 return isUInt<6>(Offset);
2824
2825 case Hexagon::S4_storeirh_io:
2826 case Hexagon::S4_storeirht_io:
2827 case Hexagon::S4_storeirhf_io:
2828 return isShiftedUInt<6,1>(Offset);
2829
2830 case Hexagon::S4_storeiri_io:
2831 case Hexagon::S4_storeirit_io:
2832 case Hexagon::S4_storeirif_io:
2833 return isShiftedUInt<6,2>(Offset);
2834 // Handle these two compare instructions that are not extendable.
2835 case Hexagon::A4_cmpbeqi:
2836 return isUInt<8>(Offset);
2837 case Hexagon::A4_cmpbgti:
2838 return isInt<8>(Offset);
2839 }
2840
2841 if (Extend)
2842 return true;
2843
2844 switch (Opcode) {
2845 case Hexagon::L2_loadri_io:
2846 case Hexagon::S2_storeri_io:
2847 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2849
2850 case Hexagon::L2_loadrd_io:
2851 case Hexagon::S2_storerd_io:
2852 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2854
2855 case Hexagon::L2_loadrh_io:
2856 case Hexagon::L2_loadruh_io:
2857 case Hexagon::S2_storerh_io:
2858 case Hexagon::S2_storerf_io:
2859 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2861
2862 case Hexagon::L2_loadrb_io:
2863 case Hexagon::L2_loadrub_io:
2864 case Hexagon::S2_storerb_io:
2865 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2867
2868 case Hexagon::A2_addi:
2869 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2871
2872 case Hexagon::L4_iadd_memopw_io:
2873 case Hexagon::L4_isub_memopw_io:
2874 case Hexagon::L4_add_memopw_io:
2875 case Hexagon::L4_sub_memopw_io:
2876 case Hexagon::L4_iand_memopw_io:
2877 case Hexagon::L4_ior_memopw_io:
2878 case Hexagon::L4_and_memopw_io:
2879 case Hexagon::L4_or_memopw_io:
2880 return (0 <= Offset && Offset <= 255);
2881
2882 case Hexagon::L4_iadd_memoph_io:
2883 case Hexagon::L4_isub_memoph_io:
2884 case Hexagon::L4_add_memoph_io:
2885 case Hexagon::L4_sub_memoph_io:
2886 case Hexagon::L4_iand_memoph_io:
2887 case Hexagon::L4_ior_memoph_io:
2888 case Hexagon::L4_and_memoph_io:
2889 case Hexagon::L4_or_memoph_io:
2890 return (0 <= Offset && Offset <= 127);
2891
2892 case Hexagon::L4_iadd_memopb_io:
2893 case Hexagon::L4_isub_memopb_io:
2894 case Hexagon::L4_add_memopb_io:
2895 case Hexagon::L4_sub_memopb_io:
2896 case Hexagon::L4_iand_memopb_io:
2897 case Hexagon::L4_ior_memopb_io:
2898 case Hexagon::L4_and_memopb_io:
2899 case Hexagon::L4_or_memopb_io:
2900 return (0 <= Offset && Offset <= 63);
2901
2902 // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2903 // any size. Later pass knows how to handle it.
2904 case Hexagon::STriw_pred:
2905 case Hexagon::LDriw_pred:
2906 case Hexagon::STriw_ctr:
2907 case Hexagon::LDriw_ctr:
2908 return true;
2909
2910 case Hexagon::PS_fi:
2911 case Hexagon::PS_fia:
2912 case Hexagon::INLINEASM:
2913 return true;
2914
2915 case Hexagon::L2_ploadrbt_io:
2916 case Hexagon::L2_ploadrbf_io:
2917 case Hexagon::L2_ploadrubt_io:
2918 case Hexagon::L2_ploadrubf_io:
2919 case Hexagon::S2_pstorerbt_io:
2920 case Hexagon::S2_pstorerbf_io:
2921 return isUInt<6>(Offset);
2922
2923 case Hexagon::L2_ploadrht_io:
2924 case Hexagon::L2_ploadrhf_io:
2925 case Hexagon::L2_ploadruht_io:
2926 case Hexagon::L2_ploadruhf_io:
2927 case Hexagon::S2_pstorerht_io:
2928 case Hexagon::S2_pstorerhf_io:
2929 return isShiftedUInt<6,1>(Offset);
2930
2931 case Hexagon::L2_ploadrit_io:
2932 case Hexagon::L2_ploadrif_io:
2933 case Hexagon::S2_pstorerit_io:
2934 case Hexagon::S2_pstorerif_io:
2935 return isShiftedUInt<6,2>(Offset);
2936
2937 case Hexagon::L2_ploadrdt_io:
2938 case Hexagon::L2_ploadrdf_io:
2939 case Hexagon::S2_pstorerdt_io:
2940 case Hexagon::S2_pstorerdf_io:
2941 return isShiftedUInt<6,3>(Offset);
2942
2943 case Hexagon::L2_loadbsw2_io:
2944 case Hexagon::L2_loadbzw2_io:
2945 return isShiftedInt<11,1>(Offset);
2946
2947 case Hexagon::L2_loadbsw4_io:
2948 case Hexagon::L2_loadbzw4_io:
2949 return isShiftedInt<11,2>(Offset);
2950 } // switch
2951
2952 dbgs() << "Failed Opcode is : " << Opcode << " (" << getName(Opcode)
2953 << ")\n";
2954 llvm_unreachable("No offset range is defined for this opcode. "
2955 "Please define it in the above switch statement!");
2956}
2957
2959 return isHVXVec(MI) && isAccumulator(MI);
2960}
2961
2963 const uint64_t F = get(MI.getOpcode()).TSFlags;
2965 return
2966 V == HexagonII::TypeCVI_VA ||
2968}
2969
2971 const MachineInstr &ConsMI) const {
2972 if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2973 return true;
2974
2975 if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2976 return true;
2977
2978 if (mayBeNewStore(ConsMI))
2979 return true;
2980
2981 return false;
2982}
2983
2985 switch (MI.getOpcode()) {
2986 // Byte
2987 case Hexagon::L2_loadrub_io:
2988 case Hexagon::L4_loadrub_ur:
2989 case Hexagon::L4_loadrub_ap:
2990 case Hexagon::L2_loadrub_pr:
2991 case Hexagon::L2_loadrub_pbr:
2992 case Hexagon::L2_loadrub_pi:
2993 case Hexagon::L2_loadrub_pci:
2994 case Hexagon::L2_loadrub_pcr:
2995 case Hexagon::L2_loadbzw2_io:
2996 case Hexagon::L4_loadbzw2_ur:
2997 case Hexagon::L4_loadbzw2_ap:
2998 case Hexagon::L2_loadbzw2_pr:
2999 case Hexagon::L2_loadbzw2_pbr:
3000 case Hexagon::L2_loadbzw2_pi:
3001 case Hexagon::L2_loadbzw2_pci:
3002 case Hexagon::L2_loadbzw2_pcr:
3003 case Hexagon::L2_loadbzw4_io:
3004 case Hexagon::L4_loadbzw4_ur:
3005 case Hexagon::L4_loadbzw4_ap:
3006 case Hexagon::L2_loadbzw4_pr:
3007 case Hexagon::L2_loadbzw4_pbr:
3008 case Hexagon::L2_loadbzw4_pi:
3009 case Hexagon::L2_loadbzw4_pci:
3010 case Hexagon::L2_loadbzw4_pcr:
3011 case Hexagon::L4_loadrub_rr:
3012 case Hexagon::L2_ploadrubt_io:
3013 case Hexagon::L2_ploadrubt_pi:
3014 case Hexagon::L2_ploadrubf_io:
3015 case Hexagon::L2_ploadrubf_pi:
3016 case Hexagon::L2_ploadrubtnew_io:
3017 case Hexagon::L2_ploadrubfnew_io:
3018 case Hexagon::L4_ploadrubt_rr:
3019 case Hexagon::L4_ploadrubf_rr:
3020 case Hexagon::L4_ploadrubtnew_rr:
3021 case Hexagon::L4_ploadrubfnew_rr:
3022 case Hexagon::L2_ploadrubtnew_pi:
3023 case Hexagon::L2_ploadrubfnew_pi:
3024 case Hexagon::L4_ploadrubt_abs:
3025 case Hexagon::L4_ploadrubf_abs:
3026 case Hexagon::L4_ploadrubtnew_abs:
3027 case Hexagon::L4_ploadrubfnew_abs:
3028 case Hexagon::L2_loadrubgp:
3029 // Half
3030 case Hexagon::L2_loadruh_io:
3031 case Hexagon::L4_loadruh_ur:
3032 case Hexagon::L4_loadruh_ap:
3033 case Hexagon::L2_loadruh_pr:
3034 case Hexagon::L2_loadruh_pbr:
3035 case Hexagon::L2_loadruh_pi:
3036 case Hexagon::L2_loadruh_pci:
3037 case Hexagon::L2_loadruh_pcr:
3038 case Hexagon::L4_loadruh_rr:
3039 case Hexagon::L2_ploadruht_io:
3040 case Hexagon::L2_ploadruht_pi:
3041 case Hexagon::L2_ploadruhf_io:
3042 case Hexagon::L2_ploadruhf_pi:
3043 case Hexagon::L2_ploadruhtnew_io:
3044 case Hexagon::L2_ploadruhfnew_io:
3045 case Hexagon::L4_ploadruht_rr:
3046 case Hexagon::L4_ploadruhf_rr:
3047 case Hexagon::L4_ploadruhtnew_rr:
3048 case Hexagon::L4_ploadruhfnew_rr:
3049 case Hexagon::L2_ploadruhtnew_pi:
3050 case Hexagon::L2_ploadruhfnew_pi:
3051 case Hexagon::L4_ploadruht_abs:
3052 case Hexagon::L4_ploadruhf_abs:
3053 case Hexagon::L4_ploadruhtnew_abs:
3054 case Hexagon::L4_ploadruhfnew_abs:
3055 case Hexagon::L2_loadruhgp:
3056 return true;
3057 default:
3058 return false;
3059 }
3060}
3061
3062// Add latency to instruction.
3064 const MachineInstr &MI2) const {
3065 if (isHVXVec(MI1) && isHVXVec(MI2))
3066 if (!isVecUsableNextPacket(MI1, MI2))
3067 return true;
3068 return false;
3069}
3070
3071/// Get the base register and byte offset of a load/store instr.
3074 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
3075 const TargetRegisterInfo *TRI) const {
3076 OffsetIsScalable = false;
3077 const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width);
3078 if (!BaseOp || !BaseOp->isReg())
3079 return false;
3080 BaseOps.push_back(BaseOp);
3081 return true;
3082}
3083
3084/// Can these instructions execute at the same time in a bundle.
3086 const MachineInstr &Second) const {
3087 if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
3088 const MachineOperand &Op = Second.getOperand(0);
3089 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
3090 return true;
3091 }
3093 return false;
3094 if (mayBeNewStore(Second)) {
3095 // Make sure the definition of the first instruction is the value being
3096 // stored.
3097 const MachineOperand &Stored =
3098 Second.getOperand(Second.getNumOperands() - 1);
3099 if (!Stored.isReg())
3100 return false;
3101 for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
3102 const MachineOperand &Op = First.getOperand(i);
3103 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3104 return true;
3105 }
3106 }
3107 return false;
3108}
3109
3111 unsigned Opc = CallMI.getOpcode();
3112 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
3113}
3114
3116 for (auto &I : *B)
3117 if (I.isEHLabel())
3118 return true;
3119 return false;
3120}
3121
3122// Returns true if an instruction can be converted into a non-extended
3123// equivalent instruction.
3125 short NonExtOpcode;
3126 // Check if the instruction has a register form that uses register in place
3127 // of the extended operand, if so return that as the non-extended form.
3128 if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
3129 return true;
3130
3131 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
3132 // Check addressing mode and retrieve non-ext equivalent instruction.
3133
3134 switch (getAddrMode(MI)) {
3136 // Load/store with absolute addressing mode can be converted into
3137 // base+offset mode.
3138 NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
3139 break;
3141 // Load/store with base+offset addressing mode can be converted into
3142 // base+register offset addressing mode. However left shift operand should
3143 // be set to 0.
3144 NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
3145 break;
3147 NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
3148 break;
3149 default:
3150 return false;
3151 }
3152 if (NonExtOpcode < 0)
3153 return false;
3154 return true;
3155 }
3156 return false;
3157}
3158
3160 return Hexagon::getRealHWInstr(MI.getOpcode(),
3161 Hexagon::InstrType_Pseudo) >= 0;
3162}
3163
3165 const {
3166 MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
3167 while (I != E) {
3168 if (I->isBarrier())
3169 return true;
3170 ++I;
3171 }
3172 return false;
3173}
3174
3175// Returns true, if a LD insn can be promoted to a cur load.
3177 const uint64_t F = MI.getDesc().TSFlags;
3179 Subtarget.hasV60Ops();
3180}
3181
3182// Returns true, if a ST insn can be promoted to a new-value store.
3184 if (MI.mayStore() && !Subtarget.useNewValueStores())
3185 return false;
3186
3187 const uint64_t F = MI.getDesc().TSFlags;
3189}
3190
3192 const MachineInstr &ConsMI) const {
3193 // There is no stall when ProdMI is not a V60 vector.
3194 if (!isHVXVec(ProdMI))
3195 return false;
3196
3197 // There is no stall when ProdMI and ConsMI are not dependent.
3198 if (!isDependent(ProdMI, ConsMI))
3199 return false;
3200
3201 // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3202 // are scheduled in consecutive packets.
3203 if (isVecUsableNextPacket(ProdMI, ConsMI))
3204 return false;
3205
3206 return true;
3207}
3208
3211 // There is no stall when I is not a V60 vector.
3212 if (!isHVXVec(MI))
3213 return false;
3214
3216 MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3217
3218 if (!MII->isBundle())
3219 return producesStall(*MII, MI);
3220
3221 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3222 const MachineInstr &J = *MII;
3223 if (producesStall(J, MI))
3224 return true;
3225 }
3226 return false;
3227}
3228
3230 Register PredReg) const {
3231 for (const MachineOperand &MO : MI.operands()) {
3232 // Predicate register must be explicitly defined.
3233 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3234 return false;
3235 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3236 return false;
3237 }
3238
3239 // Instruction that produce late predicate cannot be used as sources of
3240 // dot-new.
3241 switch (MI.getOpcode()) {
3242 case Hexagon::A4_addp_c:
3243 case Hexagon::A4_subp_c:
3244 case Hexagon::A4_tlbmatch:
3245 case Hexagon::A5_ACS:
3246 case Hexagon::F2_sfinvsqrta:
3247 case Hexagon::F2_sfrecipa:
3248 case Hexagon::J2_endloop0:
3249 case Hexagon::J2_endloop01:
3250 case Hexagon::J2_ploop1si:
3251 case Hexagon::J2_ploop1sr:
3252 case Hexagon::J2_ploop2si:
3253 case Hexagon::J2_ploop2sr:
3254 case Hexagon::J2_ploop3si:
3255 case Hexagon::J2_ploop3sr:
3256 case Hexagon::S2_cabacdecbin:
3257 case Hexagon::S2_storew_locked:
3258 case Hexagon::S4_stored_locked:
3259 return false;
3260 }
3261 return true;
3262}
3263
3264bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3265 return Opcode == Hexagon::J2_jumpt ||
3266 Opcode == Hexagon::J2_jumptpt ||
3267 Opcode == Hexagon::J2_jumpf ||
3268 Opcode == Hexagon::J2_jumpfpt ||
3269 Opcode == Hexagon::J2_jumptnew ||
3270 Opcode == Hexagon::J2_jumpfnew ||
3271 Opcode == Hexagon::J2_jumptnewpt ||
3272 Opcode == Hexagon::J2_jumpfnewpt;
3273}
3274
3276 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3277 return false;
3278 return !isPredicatedTrue(Cond[0].getImm());
3279}
3280
3282 const uint64_t F = MI.getDesc().TSFlags;
3284}
3285
3286// Returns the base register in a memory access (load/store). The offset is
3287// returned in Offset and the access size is returned in AccessSize.
3288// If the base operand has a subregister or the offset field does not contain
3289// an immediate value, return nullptr.
3292 LocationSize &AccessSize) const {
3293 // Return if it is not a base+offset type instruction or a MemOp.
3297 return nullptr;
3298
3299 AccessSize = getMemAccessSize(MI);
3300
3301 unsigned BasePos = 0, OffsetPos = 0;
3302 if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3303 return nullptr;
3304
3305 // Post increment updates its EA after the mem access,
3306 // so we need to treat its offset as zero.
3307 if (isPostIncrement(MI)) {
3308 Offset = 0;
3309 } else {
3310 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3311 if (!OffsetOp.isImm())
3312 return nullptr;
3313 Offset = OffsetOp.getImm();
3314 }
3315
3316 const MachineOperand &BaseOp = MI.getOperand(BasePos);
3317 if (BaseOp.getSubReg() != 0)
3318 return nullptr;
3319 return &const_cast<MachineOperand&>(BaseOp);
3320}
3321
3322/// Return the position of the base and offset operands for this instruction.
3324 unsigned &BasePos, unsigned &OffsetPos) const {
3326 return false;
3327
3328 // Deal with memops first.
3329 if (isMemOp(MI)) {
3330 BasePos = 0;
3331 OffsetPos = 1;
3332 } else if (MI.mayStore()) {
3333 BasePos = 0;
3334 OffsetPos = 1;
3335 } else if (MI.mayLoad()) {
3336 BasePos = 1;
3337 OffsetPos = 2;
3338 } else
3339 return false;
3340
3341 if (isPredicated(MI)) {
3342 BasePos++;
3343 OffsetPos++;
3344 }
3345 if (isPostIncrement(MI)) {
3346 BasePos++;
3347 OffsetPos++;
3348 }
3349
3350 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3351 return false;
3352
3353 return true;
3354}
3355
3356// Inserts branching instructions in reverse order of their occurrence.
3357// e.g. jump_t t1 (i1)
3358// jump t2 (i2)
3359// Jumpers = {i2, i1}
3361 MachineBasicBlock& MBB) const {
3363 // If the block has no terminators, it just falls into the block after it.
3365 if (I == MBB.instr_begin())
3366 return Jumpers;
3367
3368 // A basic block may looks like this:
3369 //
3370 // [ insn
3371 // EH_LABEL
3372 // insn
3373 // insn
3374 // insn
3375 // EH_LABEL
3376 // insn ]
3377 //
3378 // It has two succs but does not have a terminator
3379 // Don't know how to handle it.
3380 do {
3381 --I;
3382 if (I->isEHLabel())
3383 return Jumpers;
3384 } while (I != MBB.instr_begin());
3385
3386 I = MBB.instr_end();
3387 --I;
3388
3389 while (I->isDebugInstr()) {
3390 if (I == MBB.instr_begin())
3391 return Jumpers;
3392 --I;
3393 }
3394 if (!isUnpredicatedTerminator(*I))
3395 return Jumpers;
3396
3397 // Get the last instruction in the block.
3398 MachineInstr *LastInst = &*I;
3399 Jumpers.push_back(LastInst);
3400 MachineInstr *SecondLastInst = nullptr;
3401 // Find one more terminator if present.
3402 do {
3403 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3404 if (!SecondLastInst) {
3405 SecondLastInst = &*I;
3406 Jumpers.push_back(SecondLastInst);
3407 } else // This is a third branch.
3408 return Jumpers;
3409 }
3410 if (I == MBB.instr_begin())
3411 break;
3412 --I;
3413 } while (true);
3414 return Jumpers;
3415}
3416
3417// Returns Operand Index for the constant extended instruction.
3419 const uint64_t F = MI.getDesc().TSFlags;
3421}
3422
3423// See if instruction could potentially be a duplex candidate.
3424// If so, return its group. Zero otherwise.
3426 const MachineInstr &MI) const {
3427 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3428
3429 switch (MI.getOpcode()) {
3430 default:
3431 return HexagonII::HCG_None;
3432 //
3433 // Compound pairs.
3434 // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3435 // "Rd16=#U6 ; jump #r9:2"
3436 // "Rd16=Rs16 ; jump #r9:2"
3437 //
3438 case Hexagon::C2_cmpeq:
3439 case Hexagon::C2_cmpgt:
3440 case Hexagon::C2_cmpgtu:
3441 DstReg = MI.getOperand(0).getReg();
3442 Src1Reg = MI.getOperand(1).getReg();
3443 Src2Reg = MI.getOperand(2).getReg();
3444 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3445 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3446 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3447 return HexagonII::HCG_A;
3448 break;
3449 case Hexagon::C2_cmpeqi:
3450 case Hexagon::C2_cmpgti:
3451 case Hexagon::C2_cmpgtui:
3452 // P0 = cmp.eq(Rs,#u2)
3453 DstReg = MI.getOperand(0).getReg();
3454 SrcReg = MI.getOperand(1).getReg();
3455 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3456 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3457 isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3458 ((isUInt<5>(MI.getOperand(2).getImm())) ||
3459 (MI.getOperand(2).getImm() == -1)))
3460 return HexagonII::HCG_A;
3461 break;
3462 case Hexagon::A2_tfr:
3463 // Rd = Rs
3464 DstReg = MI.getOperand(0).getReg();
3465 SrcReg = MI.getOperand(1).getReg();
3466 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3467 return HexagonII::HCG_A;
3468 break;
3469 case Hexagon::A2_tfrsi:
3470 // Rd = #u6
3471 // Do not test for #u6 size since the const is getting extended
3472 // regardless and compound could be formed.
3473 DstReg = MI.getOperand(0).getReg();
3474 if (isIntRegForSubInst(DstReg))
3475 return HexagonII::HCG_A;
3476 break;
3477 case Hexagon::S2_tstbit_i:
3478 DstReg = MI.getOperand(0).getReg();
3479 Src1Reg = MI.getOperand(1).getReg();
3480 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3481 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3482 MI.getOperand(2).isImm() &&
3483 isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3484 return HexagonII::HCG_A;
3485 break;
3486 // The fact that .new form is used pretty much guarantees
3487 // that predicate register will match. Nevertheless,
3488 // there could be some false positives without additional
3489 // checking.
3490 case Hexagon::J2_jumptnew:
3491 case Hexagon::J2_jumpfnew:
3492 case Hexagon::J2_jumptnewpt:
3493 case Hexagon::J2_jumpfnewpt:
3494 Src1Reg = MI.getOperand(0).getReg();
3495 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3496 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3497 return HexagonII::HCG_B;
3498 break;
3499 // Transfer and jump:
3500 // Rd=#U6 ; jump #r9:2
3501 // Rd=Rs ; jump #r9:2
3502 // Do not test for jump range here.
3503 case Hexagon::J2_jump:
3504 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3505 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3506 return HexagonII::HCG_C;
3507 }
3508
3509 return HexagonII::HCG_None;
3510}
3511
3512// Returns -1 when there is no opcode found.
3514 const MachineInstr &GB) const {
3517 if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3518 (GB.getOpcode() != Hexagon::J2_jumptnew))
3519 return -1u;
3520 Register DestReg = GA.getOperand(0).getReg();
3521 if (!GB.readsRegister(DestReg, /*TRI=*/nullptr))
3522 return -1u;
3523 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3524 return -1u;
3525 // The value compared against must be either u5 or -1.
3526 const MachineOperand &CmpOp = GA.getOperand(2);
3527 if (!CmpOp.isImm())
3528 return -1u;
3529 int V = CmpOp.getImm();
3530 if (V == -1)
3531 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3532 : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3533 if (!isUInt<5>(V))
3534 return -1u;
3535 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3536 : Hexagon::J4_cmpeqi_tp1_jump_nt;
3537}
3538
3539// Returns -1 if there is no opcode found.
3541 bool ForBigCore) const {
3542 // Static table to switch the opcodes across Tiny Core and Big Core.
3543 // dup_ opcodes are Big core opcodes.
3544 // NOTE: There are special instructions that need to handled later.
3545 // L4_return* instructions, they will only occupy SLOT0 (on big core too).
3546 // PS_jmpret - This pseudo translates to J2_jumpr which occupies only SLOT2.
3547 // The compiler need to base the root instruction to L6_return_map_to_raw
3548 // which can go any slot.
3549 static const std::map<unsigned, unsigned> DupMap = {
3550 {Hexagon::A2_add, Hexagon::dup_A2_add},
3551 {Hexagon::A2_addi, Hexagon::dup_A2_addi},
3552 {Hexagon::A2_andir, Hexagon::dup_A2_andir},
3553 {Hexagon::A2_combineii, Hexagon::dup_A2_combineii},
3554 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb},
3555 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth},
3556 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr},
3557 {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi},
3558 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb},
3559 {Hexagon::A2_zxth, Hexagon::dup_A2_zxth},
3560 {Hexagon::A4_combineii, Hexagon::dup_A4_combineii},
3561 {Hexagon::A4_combineir, Hexagon::dup_A4_combineir},
3562 {Hexagon::A4_combineri, Hexagon::dup_A4_combineri},
3563 {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif},
3564 {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit},
3565 {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif},
3566 {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit},
3567 {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi},
3568 {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe},
3569 {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io},
3570 {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io},
3571 {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io},
3572 {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io},
3573 {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io},
3574 {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io},
3575 {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe},
3576 {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io},
3577 {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io},
3578 {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io},
3579 {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io},
3580 {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io},
3581 {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io},
3582 };
3583 unsigned OpNum = MI.getOpcode();
3584 // Conversion to Big core.
3585 if (ForBigCore) {
3586 auto Iter = DupMap.find(OpNum);
3587 if (Iter != DupMap.end())
3588 return Iter->second;
3589 } else { // Conversion to Tiny core.
3590 for (const auto &Iter : DupMap)
3591 if (Iter.second == OpNum)
3592 return Iter.first;
3593 }
3594 return -1;
3595}
3596
3597int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3598 enum Hexagon::PredSense inPredSense;
3599 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3600 Hexagon::PredSense_true;
3601 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3602 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3603 return CondOpcode;
3604
3605 llvm_unreachable("Unexpected predicable instruction");
3606}
3607
3608// Return the cur value instruction for a given store.
3610 switch (MI.getOpcode()) {
3611 default: llvm_unreachable("Unknown .cur type");
3612 case Hexagon::V6_vL32b_pi:
3613 return Hexagon::V6_vL32b_cur_pi;
3614 case Hexagon::V6_vL32b_ai:
3615 return Hexagon::V6_vL32b_cur_ai;
3616 case Hexagon::V6_vL32b_nt_pi:
3617 return Hexagon::V6_vL32b_nt_cur_pi;
3618 case Hexagon::V6_vL32b_nt_ai:
3619 return Hexagon::V6_vL32b_nt_cur_ai;
3620 case Hexagon::V6_vL32b_ppu:
3621 return Hexagon::V6_vL32b_cur_ppu;
3622 case Hexagon::V6_vL32b_nt_ppu:
3623 return Hexagon::V6_vL32b_nt_cur_ppu;
3624 }
3625 return 0;
3626}
3627
3628// Return the regular version of the .cur instruction.
3630 switch (MI.getOpcode()) {
3631 default: llvm_unreachable("Unknown .cur type");
3632 case Hexagon::V6_vL32b_cur_pi:
3633 return Hexagon::V6_vL32b_pi;
3634 case Hexagon::V6_vL32b_cur_ai:
3635 return Hexagon::V6_vL32b_ai;
3636 case Hexagon::V6_vL32b_nt_cur_pi:
3637 return Hexagon::V6_vL32b_nt_pi;
3638 case Hexagon::V6_vL32b_nt_cur_ai:
3639 return Hexagon::V6_vL32b_nt_ai;
3640 case Hexagon::V6_vL32b_cur_ppu:
3641 return Hexagon::V6_vL32b_ppu;
3642 case Hexagon::V6_vL32b_nt_cur_ppu:
3643 return Hexagon::V6_vL32b_nt_ppu;
3644 }
3645 return 0;
3646}
3647
3648// The diagram below shows the steps involved in the conversion of a predicated
3649// store instruction to its .new predicated new-value form.
3650//
3651// Note: It doesn't include conditional new-value stores as they can't be
3652// converted to .new predicate.
3653//
3654// p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3655// ^ ^
3656// / \ (not OK. it will cause new-value store to be
3657// / X conditional on p0.new while R2 producer is
3658// / \ on p0)
3659// / \.
3660// p.new store p.old NV store
3661// [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3662// ^ ^
3663// \ /
3664// \ /
3665// \ /
3666// p.old store
3667// [if (p0)memw(R0+#0)=R2]
3668//
3669// The following set of instructions further explains the scenario where
3670// conditional new-value store becomes invalid when promoted to .new predicate
3671// form.
3672//
3673// { 1) if (p0) r0 = add(r1, r2)
3674// 2) p0 = cmp.eq(r3, #0) }
3675//
3676// 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3677// the first two instructions because in instr 1, r0 is conditional on old value
3678// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3679// is not valid for new-value stores.
3680// Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3681// from the "Conditional Store" list. Because a predicated new value store
3682// would NOT be promoted to a double dot new store. See diagram below:
3683// This function returns yes for those stores that are predicated but not
3684// yet promoted to predicate dot new instructions.
3685//
3686// +---------------------+
3687// /-----| if (p0) memw(..)=r0 |---------\~
3688// || +---------------------+ ||
3689// promote || /\ /\ || promote
3690// || /||\ /||\ ||
3691// \||/ demote || \||/
3692// \/ || || \/
3693// +-------------------------+ || +-------------------------+
3694// | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3695// +-------------------------+ || +-------------------------+
3696// || || ||
3697// || demote \||/
3698// promote || \/ NOT possible
3699// || || /\~
3700// \||/ || /||\~
3701// \/ || ||
3702// +-----------------------------+
3703// | if (p0.new) memw(..)=r0.new |
3704// +-----------------------------+
3705// Double Dot New Store
3706//
3707// Returns the most basic instruction for the .new predicated instructions and
3708// new-value stores.
3709// For example, all of the following instructions will be converted back to the
3710// same instruction:
3711// 1) if (p0.new) memw(R0+#0) = R1.new --->
3712// 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3713// 3) if (p0.new) memw(R0+#0) = R1 --->
3714//
3715// To understand the translation of instruction 1 to its original form, consider
3716// a packet with 3 instructions.
3717// { p0 = cmp.eq(R0,R1)
3718// if (p0.new) R2 = add(R3, R4)
3719// R5 = add (R3, R1)
3720// }
3721// if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3722//
3723// This instruction can be part of the previous packet only if both p0 and R2
3724// are promoted to .new values. This promotion happens in steps, first
3725// predicate register is promoted to .new and in the next iteration R2 is
3726// promoted. Therefore, in case of dependence check failure (due to R5) during
3727// next iteration, it should be converted back to its most basic form.
3728
3729// Return the new value instruction for a given store.
3731 int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3732 if (NVOpcode >= 0) // Valid new-value store instruction.
3733 return NVOpcode;
3734
3735 switch (MI.getOpcode()) {
3736 default:
3737 report_fatal_error(Twine("Unknown .new type: ") +
3738 std::to_string(MI.getOpcode()));
3739 case Hexagon::S4_storerb_ur:
3740 return Hexagon::S4_storerbnew_ur;
3741
3742 case Hexagon::S2_storerb_pci:
3743 return Hexagon::S2_storerb_pci;
3744
3745 case Hexagon::S2_storeri_pci:
3746 return Hexagon::S2_storeri_pci;
3747
3748 case Hexagon::S2_storerh_pci:
3749 return Hexagon::S2_storerh_pci;
3750
3751 case Hexagon::S2_storerd_pci:
3752 return Hexagon::S2_storerd_pci;
3753
3754 case Hexagon::S2_storerf_pci:
3755 return Hexagon::S2_storerf_pci;
3756
3757 case Hexagon::V6_vS32b_ai:
3758 return Hexagon::V6_vS32b_new_ai;
3759
3760 case Hexagon::V6_vS32b_pi:
3761 return Hexagon::V6_vS32b_new_pi;
3762 }
3763 return 0;
3764}
3765
3766// Returns the opcode to use when converting MI, which is a conditional jump,
3767// into a conditional instruction which uses the .new value of the predicate.
3768// We also use branch probabilities to add a hint to the jump.
3769// If MBPI is null, all edges will be treated as equally likely for the
3770// purposes of establishing a predication hint.
3772 const MachineBranchProbabilityInfo *MBPI) const {
3773 // We assume that block can have at most two successors.
3774 const MachineBasicBlock *Src = MI.getParent();
3775 const MachineOperand &BrTarget = MI.getOperand(1);
3776 bool Taken = false;
3777 const BranchProbability OneHalf(1, 2);
3778
3779 auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3780 const MachineBasicBlock *Dst) {
3781 if (MBPI)
3782 return MBPI->getEdgeProbability(Src, Dst);
3783 return BranchProbability(1, Src->succ_size());
3784 };
3785
3786 if (BrTarget.isMBB()) {
3787 const MachineBasicBlock *Dst = BrTarget.getMBB();
3788 Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3789 } else {
3790 // The branch target is not a basic block (most likely a function).
3791 // Since BPI only gives probabilities for targets that are basic blocks,
3792 // try to identify another target of this branch (potentially a fall-
3793 // -through) and check the probability of that target.
3794 //
3795 // The only handled branch combinations are:
3796 // - one conditional branch,
3797 // - one conditional branch followed by one unconditional branch.
3798 // Otherwise, assume not-taken.
3799 assert(MI.isConditionalBranch());
3800 const MachineBasicBlock &B = *MI.getParent();
3801 bool SawCond = false, Bad = false;
3802 for (const MachineInstr &I : B) {
3803 if (!I.isBranch())
3804 continue;
3805 if (I.isConditionalBranch()) {
3806 SawCond = true;
3807 if (&I != &MI) {
3808 Bad = true;
3809 break;
3810 }
3811 }
3812 if (I.isUnconditionalBranch() && !SawCond) {
3813 Bad = true;
3814 break;
3815 }
3816 }
3817 if (!Bad) {
3819 MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3820 if (NextIt == B.instr_end()) {
3821 // If this branch is the last, look for the fall-through block.
3822 for (const MachineBasicBlock *SB : B.successors()) {
3823 if (!B.isLayoutSuccessor(SB))
3824 continue;
3825 Taken = getEdgeProbability(Src, SB) < OneHalf;
3826 break;
3827 }
3828 } else {
3829 assert(NextIt->isUnconditionalBranch());
3830 // Find the first MBB operand and assume it's the target.
3831 const MachineBasicBlock *BT = nullptr;
3832 for (const MachineOperand &Op : NextIt->operands()) {
3833 if (!Op.isMBB())
3834 continue;
3835 BT = Op.getMBB();
3836 break;
3837 }
3838 Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3839 }
3840 } // if (!Bad)
3841 }
3842
3843 // The Taken flag should be set to something reasonable by this point.
3844
3845 switch (MI.getOpcode()) {
3846 case Hexagon::J2_jumpt:
3847 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3848 case Hexagon::J2_jumpf:
3849 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3850
3851 default:
3852 llvm_unreachable("Unexpected jump instruction.");
3853 }
3854}
3855
3856// Return .new predicate version for an instruction.
3858 const MachineBranchProbabilityInfo *MBPI) const {
3859 switch (MI.getOpcode()) {
3860 // Condtional Jumps
3861 case Hexagon::J2_jumpt:
3862 case Hexagon::J2_jumpf:
3863 return getDotNewPredJumpOp(MI, MBPI);
3864 }
3865
3866 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3867 if (NewOpcode >= 0)
3868 return NewOpcode;
3869 return 0;
3870}
3871
3873 int NewOp = MI.getOpcode();
3874 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3875 NewOp = Hexagon::getPredOldOpcode(NewOp);
3876 // All Hexagon architectures have prediction bits on dot-new branches,
3877 // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3878 // to pick the right opcode when converting back to dot-old.
3879 if (!Subtarget.hasFeature(Hexagon::ArchV60)) {
3880 switch (NewOp) {
3881 case Hexagon::J2_jumptpt:
3882 NewOp = Hexagon::J2_jumpt;
3883 break;
3884 case Hexagon::J2_jumpfpt:
3885 NewOp = Hexagon::J2_jumpf;
3886 break;
3887 case Hexagon::J2_jumprtpt:
3888 NewOp = Hexagon::J2_jumprt;
3889 break;
3890 case Hexagon::J2_jumprfpt:
3891 NewOp = Hexagon::J2_jumprf;
3892 break;
3893 }
3894 }
3895 assert(NewOp >= 0 &&
3896 "Couldn't change predicate new instruction to its old form.");
3897 }
3898
3899 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3900 NewOp = Hexagon::getNonNVStore(NewOp);
3901 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3902 }
3903
3904 if (Subtarget.hasV60Ops())
3905 return NewOp;
3906
3907 // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3908 switch (NewOp) {
3909 case Hexagon::J2_jumpfpt:
3910 return Hexagon::J2_jumpf;
3911 case Hexagon::J2_jumptpt:
3912 return Hexagon::J2_jumpt;
3913 case Hexagon::J2_jumprfpt:
3914 return Hexagon::J2_jumprf;
3915 case Hexagon::J2_jumprtpt:
3916 return Hexagon::J2_jumprt;
3917 }
3918 return NewOp;
3919}
3920
3921// See if instruction could potentially be a duplex candidate.
3922// If so, return its group. Zero otherwise.
3924 const MachineInstr &MI) const {
3925 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3926 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3927
3928 switch (MI.getOpcode()) {
3929 default:
3930 return HexagonII::HSIG_None;
3931 //
3932 // Group L1:
3933 //
3934 // Rd = memw(Rs+#u4:2)
3935 // Rd = memub(Rs+#u4:0)
3936 case Hexagon::L2_loadri_io:
3937 case Hexagon::dup_L2_loadri_io:
3938 DstReg = MI.getOperand(0).getReg();
3939 SrcReg = MI.getOperand(1).getReg();
3940 // Special case this one from Group L2.
3941 // Rd = memw(r29+#u5:2)
3942 if (isIntRegForSubInst(DstReg)) {
3943 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3944 HRI.getStackRegister() == SrcReg &&
3945 MI.getOperand(2).isImm() &&
3946 isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3947 return HexagonII::HSIG_L2;
3948 // Rd = memw(Rs+#u4:2)
3949 if (isIntRegForSubInst(SrcReg) &&
3950 (MI.getOperand(2).isImm() &&
3951 isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3952 return HexagonII::HSIG_L1;
3953 }
3954 break;
3955 case Hexagon::L2_loadrub_io:
3956 case Hexagon::dup_L2_loadrub_io:
3957 // Rd = memub(Rs+#u4:0)
3958 DstReg = MI.getOperand(0).getReg();
3959 SrcReg = MI.getOperand(1).getReg();
3960 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3961 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3962 return HexagonII::HSIG_L1;
3963 break;
3964 //
3965 // Group L2:
3966 //
3967 // Rd = memh/memuh(Rs+#u3:1)
3968 // Rd = memb(Rs+#u3:0)
3969 // Rd = memw(r29+#u5:2) - Handled above.
3970 // Rdd = memd(r29+#u5:3)
3971 // deallocframe
3972 // [if ([!]p0[.new])] dealloc_return
3973 // [if ([!]p0[.new])] jumpr r31
3974 case Hexagon::L2_loadrh_io:
3975 case Hexagon::L2_loadruh_io:
3976 case Hexagon::dup_L2_loadrh_io:
3977 case Hexagon::dup_L2_loadruh_io:
3978 // Rd = memh/memuh(Rs+#u3:1)
3979 DstReg = MI.getOperand(0).getReg();
3980 SrcReg = MI.getOperand(1).getReg();
3981 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3982 MI.getOperand(2).isImm() &&
3983 isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3984 return HexagonII::HSIG_L2;
3985 break;
3986 case Hexagon::L2_loadrb_io:
3987 case Hexagon::dup_L2_loadrb_io:
3988 // Rd = memb(Rs+#u3:0)
3989 DstReg = MI.getOperand(0).getReg();
3990 SrcReg = MI.getOperand(1).getReg();
3991 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3992 MI.getOperand(2).isImm() &&
3993 isUInt<3>(MI.getOperand(2).getImm()))
3994 return HexagonII::HSIG_L2;
3995 break;
3996 case Hexagon::L2_loadrd_io:
3997 case Hexagon::dup_L2_loadrd_io:
3998 // Rdd = memd(r29+#u5:3)
3999 DstReg = MI.getOperand(0).getReg();
4000 SrcReg = MI.getOperand(1).getReg();
4001 if (isDblRegForSubInst(DstReg, HRI) &&
4002 Hexagon::IntRegsRegClass.contains(SrcReg) &&
4003 HRI.getStackRegister() == SrcReg &&
4004 MI.getOperand(2).isImm() &&
4005 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
4006 return HexagonII::HSIG_L2;
4007 break;
4008 // dealloc_return is not documented in Hexagon Manual, but marked
4009 // with A_SUBINSN attribute in iset_v4classic.py.
4010 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
4011 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
4012 case Hexagon::L4_return:
4013 case Hexagon::L2_deallocframe:
4014 case Hexagon::dup_L2_deallocframe:
4015 return HexagonII::HSIG_L2;
4016 case Hexagon::EH_RETURN_JMPR:
4017 case Hexagon::PS_jmpret:
4018 case Hexagon::SL2_jumpr31:
4019 // jumpr r31
4020 // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
4021 DstReg = MI.getOperand(0).getReg();
4022 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
4023 return HexagonII::HSIG_L2;
4024 break;
4025 case Hexagon::PS_jmprett:
4026 case Hexagon::PS_jmpretf:
4027 case Hexagon::PS_jmprettnewpt:
4028 case Hexagon::PS_jmpretfnewpt:
4029 case Hexagon::PS_jmprettnew:
4030 case Hexagon::PS_jmpretfnew:
4031 case Hexagon::SL2_jumpr31_t:
4032 case Hexagon::SL2_jumpr31_f:
4033 case Hexagon::SL2_jumpr31_tnew:
4034 case Hexagon::SL2_jumpr31_fnew:
4035 DstReg = MI.getOperand(1).getReg();
4036 SrcReg = MI.getOperand(0).getReg();
4037 // [if ([!]p0[.new])] jumpr r31
4038 if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
4039 (Hexagon::P0 == SrcReg)) &&
4040 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
4041 return HexagonII::HSIG_L2;
4042 break;
4043 case Hexagon::L4_return_t:
4044 case Hexagon::L4_return_f:
4045 case Hexagon::L4_return_tnew_pnt:
4046 case Hexagon::L4_return_fnew_pnt:
4047 case Hexagon::L4_return_tnew_pt:
4048 case Hexagon::L4_return_fnew_pt:
4049 // [if ([!]p0[.new])] dealloc_return
4050 SrcReg = MI.getOperand(0).getReg();
4051 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
4052 return HexagonII::HSIG_L2;
4053 break;
4054 //
4055 // Group S1:
4056 //
4057 // memw(Rs+#u4:2) = Rt
4058 // memb(Rs+#u4:0) = Rt
4059 case Hexagon::S2_storeri_io:
4060 case Hexagon::dup_S2_storeri_io:
4061 // Special case this one from Group S2.
4062 // memw(r29+#u5:2) = Rt
4063 Src1Reg = MI.getOperand(0).getReg();
4064 Src2Reg = MI.getOperand(2).getReg();
4065 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4066 isIntRegForSubInst(Src2Reg) &&
4067 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
4068 isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
4069 return HexagonII::HSIG_S2;
4070 // memw(Rs+#u4:2) = Rt
4071 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4072 MI.getOperand(1).isImm() &&
4073 isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
4074 return HexagonII::HSIG_S1;
4075 break;
4076 case Hexagon::S2_storerb_io:
4077 case Hexagon::dup_S2_storerb_io:
4078 // memb(Rs+#u4:0) = Rt
4079 Src1Reg = MI.getOperand(0).getReg();
4080 Src2Reg = MI.getOperand(2).getReg();
4081 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4082 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
4083 return HexagonII::HSIG_S1;
4084 break;
4085 //
4086 // Group S2:
4087 //
4088 // memh(Rs+#u3:1) = Rt
4089 // memw(r29+#u5:2) = Rt
4090 // memd(r29+#s6:3) = Rtt
4091 // memw(Rs+#u4:2) = #U1
4092 // memb(Rs+#u4) = #U1
4093 // allocframe(#u5:3)
4094 case Hexagon::S2_storerh_io:
4095 case Hexagon::dup_S2_storerh_io:
4096 // memh(Rs+#u3:1) = Rt
4097 Src1Reg = MI.getOperand(0).getReg();
4098 Src2Reg = MI.getOperand(2).getReg();
4099 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4100 MI.getOperand(1).isImm() &&
4101 isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
4102 return HexagonII::HSIG_S1;
4103 break;
4104 case Hexagon::S2_storerd_io:
4105 case Hexagon::dup_S2_storerd_io:
4106 // memd(r29+#s6:3) = Rtt
4107 Src1Reg = MI.getOperand(0).getReg();
4108 Src2Reg = MI.getOperand(2).getReg();
4109 if (isDblRegForSubInst(Src2Reg, HRI) &&
4110 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4111 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
4112 isShiftedInt<6,3>(MI.getOperand(1).getImm()))
4113 return HexagonII::HSIG_S2;
4114 break;
4115 case Hexagon::S4_storeiri_io:
4116 case Hexagon::dup_S4_storeiri_io:
4117 // memw(Rs+#u4:2) = #U1
4118 Src1Reg = MI.getOperand(0).getReg();
4119 if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
4120 isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
4121 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4122 return HexagonII::HSIG_S2;
4123 break;
4124 case Hexagon::S4_storeirb_io:
4125 case Hexagon::dup_S4_storeirb_io:
4126 // memb(Rs+#u4) = #U1
4127 Src1Reg = MI.getOperand(0).getReg();
4128 if (isIntRegForSubInst(Src1Reg) &&
4129 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
4130 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4131 return HexagonII::HSIG_S2;
4132 break;
4133 case Hexagon::S2_allocframe:
4134 case Hexagon::dup_S2_allocframe:
4135 if (MI.getOperand(2).isImm() &&
4136 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
4137 return HexagonII::HSIG_S1;
4138 break;
4139 //
4140 // Group A:
4141 //
4142 // Rx = add(Rx,#s7)
4143 // Rd = Rs
4144 // Rd = #u6
4145 // Rd = #-1
4146 // if ([!]P0[.new]) Rd = #0
4147 // Rd = add(r29,#u6:2)
4148 // Rx = add(Rx,Rs)
4149 // P0 = cmp.eq(Rs,#u2)
4150 // Rdd = combine(#0,Rs)
4151 // Rdd = combine(Rs,#0)
4152 // Rdd = combine(#u2,#U2)
4153 // Rd = add(Rs,#1)
4154 // Rd = add(Rs,#-1)
4155 // Rd = sxth/sxtb/zxtb/zxth(Rs)
4156 // Rd = and(Rs,#1)
4157 case Hexagon::A2_addi:
4158 case Hexagon::dup_A2_addi:
4159 DstReg = MI.getOperand(0).getReg();
4160 SrcReg = MI.getOperand(1).getReg();
4161 if (isIntRegForSubInst(DstReg)) {
4162 // Rd = add(r29,#u6:2)
4163 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
4164 HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
4165 isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
4166 return HexagonII::HSIG_A;
4167 // Rx = add(Rx,#s7)
4168 if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
4169 isInt<7>(MI.getOperand(2).getImm()))
4170 return HexagonII::HSIG_A;
4171 // Rd = add(Rs,#1)
4172 // Rd = add(Rs,#-1)
4173 if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
4174 ((MI.getOperand(2).getImm() == 1) ||
4175 (MI.getOperand(2).getImm() == -1)))
4176 return HexagonII::HSIG_A;
4177 }
4178 break;
4179 case Hexagon::A2_add:
4180 case Hexagon::dup_A2_add:
4181 // Rx = add(Rx,Rs)
4182 DstReg = MI.getOperand(0).getReg();
4183 Src1Reg = MI.getOperand(1).getReg();
4184 Src2Reg = MI.getOperand(2).getReg();
4185 if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
4186 isIntRegForSubInst(Src2Reg))
4187 return HexagonII::HSIG_A;
4188 break;
4189 case Hexagon::A2_andir:
4190 case Hexagon::dup_A2_andir:
4191 // Same as zxtb.
4192 // Rd16=and(Rs16,#255)
4193 // Rd16=and(Rs16,#1)
4194 DstReg = MI.getOperand(0).getReg();
4195 SrcReg = MI.getOperand(1).getReg();
4196 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
4197 MI.getOperand(2).isImm() &&
4198 ((MI.getOperand(2).getImm() == 1) ||
4199 (MI.getOperand(2).getImm() == 255)))
4200 return HexagonII::HSIG_A;
4201 break;
4202 case Hexagon::A2_tfr:
4203 case Hexagon::dup_A2_tfr:
4204 // Rd = Rs
4205 DstReg = MI.getOperand(0).getReg();
4206 SrcReg = MI.getOperand(1).getReg();
4207 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4208 return HexagonII::HSIG_A;
4209 break;
4210 case Hexagon::A2_tfrsi:
4211 case Hexagon::dup_A2_tfrsi:
4212 // Rd = #u6
4213 // Do not test for #u6 size since the const is getting extended
4214 // regardless and compound could be formed.
4215 // Rd = #-1
4216 DstReg = MI.getOperand(0).getReg();
4217 if (isIntRegForSubInst(DstReg))
4218 return HexagonII::HSIG_A;
4219 break;
4220 case Hexagon::C2_cmoveit:
4221 case Hexagon::C2_cmovenewit:
4222 case Hexagon::C2_cmoveif:
4223 case Hexagon::C2_cmovenewif:
4224 case Hexagon::dup_C2_cmoveit:
4225 case Hexagon::dup_C2_cmovenewit:
4226 case Hexagon::dup_C2_cmoveif:
4227 case Hexagon::dup_C2_cmovenewif:
4228 // if ([!]P0[.new]) Rd = #0
4229 // Actual form:
4230 // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
4231 DstReg = MI.getOperand(0).getReg();
4232 SrcReg = MI.getOperand(1).getReg();
4233 if (isIntRegForSubInst(DstReg) &&
4234 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4235 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4236 return HexagonII::HSIG_A;
4237 break;
4238 case Hexagon::C2_cmpeqi:
4239 case Hexagon::dup_C2_cmpeqi:
4240 // P0 = cmp.eq(Rs,#u2)
4241 DstReg = MI.getOperand(0).getReg();
4242 SrcReg = MI.getOperand(1).getReg();
4243 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
4244 Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
4245 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4246 return HexagonII::HSIG_A;
4247 break;
4248 case Hexagon::A2_combineii:
4249 case Hexagon::A4_combineii:
4250 case Hexagon::dup_A2_combineii:
4251 case Hexagon::dup_A4_combineii:
4252 // Rdd = combine(#u2,#U2)
4253 DstReg = MI.getOperand(0).getReg();
4254 if (isDblRegForSubInst(DstReg, HRI) &&
4255 ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4256 (MI.getOperand(1).isGlobal() &&
4257 isUInt<2>(MI.getOperand(1).getOffset()))) &&
4258 ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4259 (MI.getOperand(2).isGlobal() &&
4260 isUInt<2>(MI.getOperand(2).getOffset()))))
4261 return HexagonII::HSIG_A;
4262 break;
4263 case Hexagon::A4_combineri:
4264 case Hexagon::dup_A4_combineri:
4265 // Rdd = combine(Rs,#0)
4266 // Rdd = combine(Rs,#0)
4267 DstReg = MI.getOperand(0).getReg();
4268 SrcReg = MI.getOperand(1).getReg();
4269 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4270 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4271 (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4272 return HexagonII::HSIG_A;
4273 break;
4274 case Hexagon::A4_combineir:
4275 case Hexagon::dup_A4_combineir:
4276 // Rdd = combine(#0,Rs)
4277 DstReg = MI.getOperand(0).getReg();
4278 SrcReg = MI.getOperand(2).getReg();
4279 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4280 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4281 (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4282 return HexagonII::HSIG_A;
4283 break;
4284 case Hexagon::A2_sxtb:
4285 case Hexagon::A2_sxth:
4286 case Hexagon::A2_zxtb:
4287 case Hexagon::A2_zxth:
4288 case Hexagon::dup_A2_sxtb:
4289 case Hexagon::dup_A2_sxth:
4290 case Hexagon::dup_A2_zxtb:
4291 case Hexagon::dup_A2_zxth:
4292 // Rd = sxth/sxtb/zxtb/zxth(Rs)
4293 DstReg = MI.getOperand(0).getReg();
4294 SrcReg = MI.getOperand(1).getReg();
4295 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4296 return HexagonII::HSIG_A;
4297 break;
4298 }
4299
4300 return HexagonII::HSIG_None;
4301}
4302
4304 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4305}
4306
4308 const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4309 // Default to one cycle for no itinerary. However, an "empty" itinerary may
4310 // still have a MinLatency property, which getStageLatency checks.
4311 if (!ItinData)
4312 return getInstrLatency(ItinData, MI);
4313
4314 if (MI.isTransient())
4315 return 0;
4316 return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4317}
4318
4319/// getOperandLatency - Compute and return the use operand latency of a given
4320/// pair of def and use.
4321/// In most cases, the static scheduling itinerary was enough to determine the
4322/// operand latency. But it may not be possible for instructions with variable
4323/// number of defs / uses.
4324///
4325/// This is a raw interface to the itinerary that may be directly overriden by
4326/// a target. Use computeOperandLatency to get the best estimate of latency.
4328 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4329 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {
4330 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4331
4332 // Get DefIdx and UseIdx for super registers.
4333 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4334
4335 if (DefMO.isReg() && DefMO.getReg().isPhysical()) {
4336 if (DefMO.isImplicit()) {
4337 for (MCPhysReg SR : HRI.superregs(DefMO.getReg())) {
4338 int Idx = DefMI.findRegisterDefOperandIdx(SR, &HRI, false, false);
4339 if (Idx != -1) {
4340 DefIdx = Idx;
4341 break;
4342 }
4343 }
4344 }
4345
4346 const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4347 if (UseMO.isImplicit()) {
4348 for (MCPhysReg SR : HRI.superregs(UseMO.getReg())) {
4349 int Idx = UseMI.findRegisterUseOperandIdx(SR, &HRI, false);
4350 if (Idx != -1) {
4351 UseIdx = Idx;
4352 break;
4353 }
4354 }
4355 }
4356 }
4357
4358 std::optional<unsigned> Latency = TargetInstrInfo::getOperandLatency(
4359 ItinData, DefMI, DefIdx, UseMI, UseIdx);
4360 if (Latency == 0)
4361 // We should never have 0 cycle latency between two instructions unless
4362 // they can be packetized together. However, this decision can't be made
4363 // here.
4364 Latency = 1;
4365 return Latency;
4366}
4367
4368// inverts the predication logic.
4369// p -> NotP
4370// NotP -> P
4373 if (Cond.empty())
4374 return false;
4375 unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4376 Cond[0].setImm(Opc);
4377 return true;
4378}
4379
4381 int InvPredOpcode;
4382 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4383 : Hexagon::getTruePredOpcode(Opc);
4384 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4385 return InvPredOpcode;
4386
4387 llvm_unreachable("Unexpected predicated instruction");
4388}
4389
4390// Returns the max value that doesn't need to be extended.
4392 const uint64_t F = MI.getDesc().TSFlags;
4393 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4395 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4397
4398 if (isSigned) // if value is signed
4399 return ~(-1U << (bits - 1));
4400 else
4401 return ~(-1U << bits);
4402}
4403
4404
4406 switch (MI.getOpcode()) {
4407 case Hexagon::L2_loadrbgp:
4408 case Hexagon::L2_loadrdgp:
4409 case Hexagon::L2_loadrhgp:
4410 case Hexagon::L2_loadrigp:
4411 case Hexagon::L2_loadrubgp:
4412 case Hexagon::L2_loadruhgp:
4413 case Hexagon::S2_storerbgp:
4414 case Hexagon::S2_storerbnewgp:
4415 case Hexagon::S2_storerhgp:
4416 case Hexagon::S2_storerhnewgp:
4417 case Hexagon::S2_storerigp:
4418 case Hexagon::S2_storerinewgp:
4419 case Hexagon::S2_storerdgp:
4420 case Hexagon::S2_storerfgp:
4421 return true;
4422 }
4423 const uint64_t F = MI.getDesc().TSFlags;
4424 unsigned addrMode =
4426 // Disallow any base+offset instruction. The assembler does not yet reorder
4427 // based up any zero offset instruction.
4428 return (addrMode == HexagonII::BaseRegOffset ||
4429 addrMode == HexagonII::BaseImmOffset ||
4430 addrMode == HexagonII::BaseLongOffset);
4431}
4432
4434 // Workaround for the Global Scheduler. Sometimes, it creates
4435 // A4_ext as a Pseudo instruction and calls this function to see if
4436 // it can be added to an existing bundle. Since the instruction doesn't
4437 // belong to any BB yet, we can't use getUnits API.
4438 if (MI.getOpcode() == Hexagon::A4_ext)
4439 return false;
4440
4441 unsigned FuncUnits = getUnits(MI);
4442 return HexagonFUnits::isSlot0Only(FuncUnits);
4443}
4444
4446 const uint64_t F = MI.getDesc().TSFlags;
4449}
4450
4452 bool ToBigInstrs) const {
4453 int Opcode = -1;
4454 if (ToBigInstrs) { // To BigCore Instr.
4455 // Check if the instruction can form a Duplex.
4456 if (getDuplexCandidateGroup(*MII))
4457 // Get the opcode marked "dup_*" tag.
4458 Opcode = getDuplexOpcode(*MII, ToBigInstrs);
4459 } else // To TinyCore Instr.
4460 Opcode = getDuplexOpcode(*MII, ToBigInstrs);
4461
4462 // Change the opcode of the instruction.
4463 if (Opcode >= 0)
4464 MII->setDesc(get(Opcode));
4465}
4466
4467// This function is used to translate instructions to facilitate generating
4468// Duplexes on TinyCore.
4470 bool ToBigInstrs) const {
4471 for (auto &MB : MF)
4472 for (MachineBasicBlock::instr_iterator Instr = MB.instr_begin(),
4473 End = MB.instr_end();
4474 Instr != End; ++Instr)
4475 changeDuplexOpcode(Instr, ToBigInstrs);
4476}
4477
4478// This is a specialized form of above function.
4480 MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const {
4482 while ((MII != MBB->instr_end()) && MII->isInsideBundle()) {
4483 changeDuplexOpcode(MII, ToBigInstrs);
4484 ++MII;
4485 }
4486}
4487
4489 using namespace HexagonII;
4490
4491 const uint64_t F = MI.getDesc().TSFlags;
4492 unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4493 unsigned Size = getMemAccessSizeInBytes(MemAccessSize(S));
4494 if (Size != 0)
4495 return Size;
4496 // Y2_dcfetchbo is special
4497 if (MI.getOpcode() == Hexagon::Y2_dcfetchbo)
4499
4500 // Handle vector access sizes.
4501 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4502 switch (S) {
4504 return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4505 default:
4506 llvm_unreachable("Unexpected instruction");
4507 }
4508}
4509
4510// Returns the min value that doesn't need to be extended.
4512 const uint64_t F = MI.getDesc().TSFlags;
4513 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4515 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4517
4518 if (isSigned) // if value is signed
4519 return -1U << (bits - 1);
4520 else
4521 return 0;
4522}
4523
4524// Returns opcode of the non-extended equivalent instruction.
4526 // Check if the instruction has a register form that uses register in place
4527 // of the extended operand, if so return that as the non-extended form.
4528 short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4529 if (NonExtOpcode >= 0)
4530 return NonExtOpcode;
4531
4532 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4533 // Check addressing mode and retrieve non-ext equivalent instruction.
4534 switch (getAddrMode(MI)) {
4536 return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4538 return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4540 return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4541
4542 default:
4543 return -1;
4544 }
4545 }
4546 return -1;
4547}
4548
4550 Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4551 if (Cond.empty())
4552 return false;
4553 assert(Cond.size() == 2);
4554 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4555 LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4556 return false;
4557 }
4558 PredReg = Cond[1].getReg();
4559 PredRegPos = 1;
4560 // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4561 PredRegFlags = 0;