LLVM  15.0.0git
HexagonInstrInfo.cpp
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1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonInstrInfo.h"
14 #include "Hexagon.h"
15 #include "HexagonFrameLowering.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCInstBuilder.h"
44 #include "llvm/MC/MCInstrDesc.h"
46 #include "llvm/MC/MCRegisterInfo.h"
49 #include "llvm/Support/Debug.h"
55 #include <cassert>
56 #include <cctype>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <utility>
62 
63 using namespace llvm;
64 
65 #define DEBUG_TYPE "hexagon-instrinfo"
66 
67 #define GET_INSTRINFO_CTOR_DTOR
68 #define GET_INSTRMAP_INFO
70 #include "HexagonGenDFAPacketizer.inc"
71 #include "HexagonGenInstrInfo.inc"
72 
73 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
74  cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
75  "packetization boundary."));
76 
77 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
78  cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
79 
81  "disable-hexagon-nv-schedule", cl::Hidden,
82  cl::desc("Disable schedule adjustment for new value stores."));
83 
85  "enable-timing-class-latency", cl::Hidden, cl::init(false),
86  cl::desc("Enable timing class latency"));
87 
89  "enable-alu-forwarding", cl::Hidden, cl::init(true),
90  cl::desc("Enable vec alu forwarding"));
91 
93  "enable-acc-forwarding", cl::Hidden, cl::init(true),
94  cl::desc("Enable vec acc forwarding"));
95 
96 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
97  cl::init(true), cl::Hidden,
98  cl::desc("branch relax asm"));
99 
100 static cl::opt<bool>
101  UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden,
102  cl::desc("Use the DFA based hazard recognizer."));
103 
104 /// Constants for Hexagon instructions.
105 const int Hexagon_MEMW_OFFSET_MAX = 4095;
106 const int Hexagon_MEMW_OFFSET_MIN = -4096;
107 const int Hexagon_MEMD_OFFSET_MAX = 8191;
108 const int Hexagon_MEMD_OFFSET_MIN = -8192;
109 const int Hexagon_MEMH_OFFSET_MAX = 2047;
110 const int Hexagon_MEMH_OFFSET_MIN = -2048;
111 const int Hexagon_MEMB_OFFSET_MAX = 1023;
112 const int Hexagon_MEMB_OFFSET_MIN = -1024;
113 const int Hexagon_ADDI_OFFSET_MAX = 32767;
114 const int Hexagon_ADDI_OFFSET_MIN = -32768;
115 
116 // Pin the vtable to this file.
117 void HexagonInstrInfo::anchor() {}
118 
120  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
121  Subtarget(ST) {}
122 
123 namespace llvm {
124 namespace HexagonFUnits {
125  bool isSlot0Only(unsigned units);
126 }
127 }
128 
129 static bool isIntRegForSubInst(unsigned Reg) {
130  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
131  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
132 }
133 
134 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
135  return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
136  isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
137 }
138 
139 /// Calculate number of instructions excluding the debug instructions.
142  unsigned Count = 0;
143  for (; MIB != MIE; ++MIB) {
144  if (!MIB->isDebugInstr())
145  ++Count;
146  }
147  return Count;
148 }
149 
150 // Check if the A2_tfrsi instruction is cheap or not. If the operand has
151 // to be constant-extendend it is not cheap since it occupies two slots
152 // in a packet.
154  // Enable the following steps only at Os/Oz
155  if (!(MI.getMF()->getFunction().hasOptSize()))
156  return MI.isAsCheapAsAMove();
157 
158  if (MI.getOpcode() == Hexagon::A2_tfrsi) {
159  auto Op = MI.getOperand(1);
160  // If the instruction has a global address as operand, it is not cheap
161  // since the operand will be constant extended.
162  if (Op.isGlobal())
163  return false;
164  // If the instruction has an operand of size > 16bits, its will be
165  // const-extended and hence, it is not cheap.
166  if (Op.isImm()) {
167  int64_t Imm = Op.getImm();
168  if (!isInt<16>(Imm))
169  return false;
170  }
171  }
172  return MI.isAsCheapAsAMove();
173 }
174 
175 // Do not sink floating point instructions that updates USR register.
176 // Example:
177 // feclearexcept
178 // F2_conv_w2sf
179 // fetestexcept
180 // MachineSink sinks F2_conv_w2sf and we are not able to catch exceptions.
181 // TODO: On some of these floating point instructions, USR is marked as Use.
182 // In reality, these instructions also Def the USR. If USR is marked as Def,
183 // some of the assumptions in assembler packetization are broken.
185  // Assumption: A floating point instruction that reads the USR will write
186  // the USR as well.
187  if (isFloat(MI) && MI.hasRegisterImplicitUseOperand(Hexagon::USR))
188  return false;
189  return true;
190 }
191 
192 /// Find the hardware loop instruction used to set-up the specified loop.
193 /// On Hexagon, we have two instructions used to set-up the hardware loop
194 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
195 /// to indicate the end of a loop.
197  unsigned EndLoopOp, MachineBasicBlock *TargetBB,
198  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
199  unsigned LOOPi;
200  unsigned LOOPr;
201  if (EndLoopOp == Hexagon::ENDLOOP0) {
202  LOOPi = Hexagon::J2_loop0i;
203  LOOPr = Hexagon::J2_loop0r;
204  } else { // EndLoopOp == Hexagon::EndLOOP1
205  LOOPi = Hexagon::J2_loop1i;
206  LOOPr = Hexagon::J2_loop1r;
207  }
208 
209  // The loop set-up instruction will be in a predecessor block
210  for (MachineBasicBlock *PB : BB->predecessors()) {
211  // If this has been visited, already skip it.
212  if (!Visited.insert(PB).second)
213  continue;
214  if (PB == BB)
215  continue;
216  for (MachineInstr &I : llvm::reverse(PB->instrs())) {
217  unsigned Opc = I.getOpcode();
218  if (Opc == LOOPi || Opc == LOOPr)
219  return &I;
220  // We've reached a different loop, which means the loop01 has been
221  // removed.
222  if (Opc == EndLoopOp && I.getOperand(0).getMBB() != TargetBB)
223  return nullptr;
224  }
225  // Check the predecessors for the LOOP instruction.
226  if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
227  return Loop;
228  }
229  return nullptr;
230 }
231 
232 /// Gather register def/uses from MI.
233 /// This treats possible (predicated) defs as actually happening ones
234 /// (conservatively).
235 static inline void parseOperands(const MachineInstr &MI,
237  Defs.clear();
238  Uses.clear();
239 
240  for (const MachineOperand &MO : MI.operands()) {
241  if (!MO.isReg())
242  continue;
243 
244  Register Reg = MO.getReg();
245  if (!Reg)
246  continue;
247 
248  if (MO.isUse())
249  Uses.push_back(MO.getReg());
250 
251  if (MO.isDef())
252  Defs.push_back(MO.getReg());
253  }
254 }
255 
256 // Position dependent, so check twice for swap.
257 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
258  switch (Ga) {
260  default:
261  return false;
262  case HexagonII::HSIG_L1:
263  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
264  case HexagonII::HSIG_L2:
265  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
266  Gb == HexagonII::HSIG_A);
267  case HexagonII::HSIG_S1:
268  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
269  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
270  case HexagonII::HSIG_S2:
271  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
272  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
273  Gb == HexagonII::HSIG_A);
274  case HexagonII::HSIG_A:
275  return (Gb == HexagonII::HSIG_A);
277  return (Gb == HexagonII::HSIG_Compound);
278  }
279  return false;
280 }
281 
282 /// isLoadFromStackSlot - If the specified machine instruction is a direct
283 /// load from a stack slot, return the virtual or physical register number of
284 /// the destination along with the FrameIndex of the loaded stack slot. If
285 /// not, return 0. This predicate must return 0 if the instruction has
286 /// any side effects other than loading from the stack slot.
288  int &FrameIndex) const {
289  switch (MI.getOpcode()) {
290  default:
291  break;
292  case Hexagon::L2_loadri_io:
293  case Hexagon::L2_loadrd_io:
294  case Hexagon::V6_vL32b_ai:
295  case Hexagon::V6_vL32b_nt_ai:
296  case Hexagon::V6_vL32Ub_ai:
297  case Hexagon::LDriw_pred:
298  case Hexagon::LDriw_ctr:
299  case Hexagon::PS_vloadrq_ai:
300  case Hexagon::PS_vloadrw_ai:
301  case Hexagon::PS_vloadrw_nt_ai: {
302  const MachineOperand OpFI = MI.getOperand(1);
303  if (!OpFI.isFI())
304  return 0;
305  const MachineOperand OpOff = MI.getOperand(2);
306  if (!OpOff.isImm() || OpOff.getImm() != 0)
307  return 0;
308  FrameIndex = OpFI.getIndex();
309  return MI.getOperand(0).getReg();
310  }
311 
312  case Hexagon::L2_ploadrit_io:
313  case Hexagon::L2_ploadrif_io:
314  case Hexagon::L2_ploadrdt_io:
315  case Hexagon::L2_ploadrdf_io: {
316  const MachineOperand OpFI = MI.getOperand(2);
317  if (!OpFI.isFI())
318  return 0;
319  const MachineOperand OpOff = MI.getOperand(3);
320  if (!OpOff.isImm() || OpOff.getImm() != 0)
321  return 0;
322  FrameIndex = OpFI.getIndex();
323  return MI.getOperand(0).getReg();
324  }
325  }
326 
327  return 0;
328 }
329 
330 /// isStoreToStackSlot - If the specified machine instruction is a direct
331 /// store to a stack slot, return the virtual or physical register number of
332 /// the source reg along with the FrameIndex of the loaded stack slot. If
333 /// not, return 0. This predicate must return 0 if the instruction has
334 /// any side effects other than storing to the stack slot.
336  int &FrameIndex) const {
337  switch (MI.getOpcode()) {
338  default:
339  break;
340  case Hexagon::S2_storerb_io:
341  case Hexagon::S2_storerh_io:
342  case Hexagon::S2_storeri_io:
343  case Hexagon::S2_storerd_io:
344  case Hexagon::V6_vS32b_ai:
345  case Hexagon::V6_vS32Ub_ai:
346  case Hexagon::STriw_pred:
347  case Hexagon::STriw_ctr:
348  case Hexagon::PS_vstorerq_ai:
349  case Hexagon::PS_vstorerw_ai: {
350  const MachineOperand &OpFI = MI.getOperand(0);
351  if (!OpFI.isFI())
352  return 0;
353  const MachineOperand &OpOff = MI.getOperand(1);
354  if (!OpOff.isImm() || OpOff.getImm() != 0)
355  return 0;
356  FrameIndex = OpFI.getIndex();
357  return MI.getOperand(2).getReg();
358  }
359 
360  case Hexagon::S2_pstorerbt_io:
361  case Hexagon::S2_pstorerbf_io:
362  case Hexagon::S2_pstorerht_io:
363  case Hexagon::S2_pstorerhf_io:
364  case Hexagon::S2_pstorerit_io:
365  case Hexagon::S2_pstorerif_io:
366  case Hexagon::S2_pstorerdt_io:
367  case Hexagon::S2_pstorerdf_io: {
368  const MachineOperand &OpFI = MI.getOperand(1);
369  if (!OpFI.isFI())
370  return 0;
371  const MachineOperand &OpOff = MI.getOperand(2);
372  if (!OpOff.isImm() || OpOff.getImm() != 0)
373  return 0;
374  FrameIndex = OpFI.getIndex();
375  return MI.getOperand(3).getReg();
376  }
377  }
378 
379  return 0;
380 }
381 
382 /// This function checks if the instruction or bundle of instructions
383 /// has load from stack slot and returns frameindex and machine memory
384 /// operand of that instruction if true.
386  const MachineInstr &MI,
388  if (MI.isBundle()) {
389  const MachineBasicBlock *MBB = MI.getParent();
390  MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
391  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
392  if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
393  return true;
394  return false;
395  }
396 
397  return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
398 }
399 
400 /// This function checks if the instruction or bundle of instructions
401 /// has store to stack slot and returns frameindex and machine memory
402 /// operand of that instruction if true.
404  const MachineInstr &MI,
406  if (MI.isBundle()) {
407  const MachineBasicBlock *MBB = MI.getParent();
408  MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
409  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
410  if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
411  return true;
412  return false;
413  }
414 
415  return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
416 }
417 
418 /// This function can analyze one/two way branching only and should (mostly) be
419 /// called by target independent side.
420 /// First entry is always the opcode of the branching instruction, except when
421 /// the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a
422 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
423 /// e.g. Jump_c p will have
424 /// Cond[0] = Jump_c
425 /// Cond[1] = p
426 /// HW-loop ENDLOOP:
427 /// Cond[0] = ENDLOOP
428 /// Cond[1] = MBB
429 /// New value jump:
430 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
431 /// Cond[1] = R
432 /// Cond[2] = Imm
434  MachineBasicBlock *&TBB,
435  MachineBasicBlock *&FBB,
437  bool AllowModify) const {
438  TBB = nullptr;
439  FBB = nullptr;
440  Cond.clear();
441 
442  // If the block has no terminators, it just falls into the block after it.
444  if (I == MBB.instr_begin())
445  return false;
446 
447  // A basic block may looks like this:
448  //
449  // [ insn
450  // EH_LABEL
451  // insn
452  // insn
453  // insn
454  // EH_LABEL
455  // insn ]
456  //
457  // It has two succs but does not have a terminator
458  // Don't know how to handle it.
459  do {
460  --I;
461  if (I->isEHLabel())
462  // Don't analyze EH branches.
463  return true;
464  } while (I != MBB.instr_begin());
465 
466  I = MBB.instr_end();
467  --I;
468 
469  while (I->isDebugInstr()) {
470  if (I == MBB.instr_begin())
471  return false;
472  --I;
473  }
474 
475  bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
476  I->getOperand(0).isMBB();
477  // Delete the J2_jump if it's equivalent to a fall-through.
478  if (AllowModify && JumpToBlock &&
479  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
480  LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
481  I->eraseFromParent();
482  I = MBB.instr_end();
483  if (I == MBB.instr_begin())
484  return false;
485  --I;
486  }
487  if (!isUnpredicatedTerminator(*I))
488  return false;
489 
490  // Get the last instruction in the block.
491  MachineInstr *LastInst = &*I;
492  MachineInstr *SecondLastInst = nullptr;
493  // Find one more terminator if present.
494  while (true) {
495  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
496  if (!SecondLastInst)
497  SecondLastInst = &*I;
498  else
499  // This is a third branch.
500  return true;
501  }
502  if (I == MBB.instr_begin())
503  break;
504  --I;
505  }
506 
507  int LastOpcode = LastInst->getOpcode();
508  int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
509  // If the branch target is not a basic block, it could be a tail call.
510  // (It is, if the target is a function.)
511  if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
512  return true;
513  if (SecLastOpcode == Hexagon::J2_jump &&
514  !SecondLastInst->getOperand(0).isMBB())
515  return true;
516 
517  bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
518  bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
519 
520  if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
521  return true;
522 
523  // If there is only one terminator instruction, process it.
524  if (LastInst && !SecondLastInst) {
525  if (LastOpcode == Hexagon::J2_jump) {
526  TBB = LastInst->getOperand(0).getMBB();
527  return false;
528  }
529  if (isEndLoopN(LastOpcode)) {
530  TBB = LastInst->getOperand(0).getMBB();
531  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
532  Cond.push_back(LastInst->getOperand(0));
533  return false;
534  }
535  if (LastOpcodeHasJMP_c) {
536  TBB = LastInst->getOperand(1).getMBB();
537  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
538  Cond.push_back(LastInst->getOperand(0));
539  return false;
540  }
541  // Only supporting rr/ri versions of new-value jumps.
542  if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
543  TBB = LastInst->getOperand(2).getMBB();
544  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
545  Cond.push_back(LastInst->getOperand(0));
546  Cond.push_back(LastInst->getOperand(1));
547  return false;
548  }
549  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
550  << " with one jump\n";);
551  // Otherwise, don't know what this is.
552  return true;
553  }
554 
555  bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
556  bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
557  if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
558  if (!SecondLastInst->getOperand(1).isMBB())
559  return true;
560  TBB = SecondLastInst->getOperand(1).getMBB();
561  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
562  Cond.push_back(SecondLastInst->getOperand(0));
563  FBB = LastInst->getOperand(0).getMBB();
564  return false;
565  }
566 
567  // Only supporting rr/ri versions of new-value jumps.
568  if (SecLastOpcodeHasNVJump &&
569  (SecondLastInst->getNumExplicitOperands() == 3) &&
570  (LastOpcode == Hexagon::J2_jump)) {
571  TBB = SecondLastInst->getOperand(2).getMBB();
572  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
573  Cond.push_back(SecondLastInst->getOperand(0));
574  Cond.push_back(SecondLastInst->getOperand(1));
575  FBB = LastInst->getOperand(0).getMBB();
576  return false;
577  }
578 
579  // If the block ends with two Hexagon:JMPs, handle it. The second one is not
580  // executed, so remove it.
581  if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
582  TBB = SecondLastInst->getOperand(0).getMBB();
583  I = LastInst->getIterator();
584  if (AllowModify)
585  I->eraseFromParent();
586  return false;
587  }
588 
589  // If the block ends with an ENDLOOP, and J2_jump, handle it.
590  if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
591  TBB = SecondLastInst->getOperand(0).getMBB();
592  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
593  Cond.push_back(SecondLastInst->getOperand(0));
594  FBB = LastInst->getOperand(0).getMBB();
595  return false;
596  }
597  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
598  << " with two jumps";);
599  // Otherwise, can't handle this.
600  return true;
601 }
602 
604  int *BytesRemoved) const {
605  assert(!BytesRemoved && "code size not handled");
606 
607  LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
609  unsigned Count = 0;
610  while (I != MBB.begin()) {
611  --I;
612  if (I->isDebugInstr())
613  continue;
614  // Only removing branches from end of MBB.
615  if (!I->isBranch())
616  return Count;
617  if (Count && (I->getOpcode() == Hexagon::J2_jump))
618  llvm_unreachable("Malformed basic block: unconditional branch not last");
619  MBB.erase(&MBB.back());
620  I = MBB.end();
621  ++Count;
622  }
623  return Count;
624 }
625 
627  MachineBasicBlock *TBB,
628  MachineBasicBlock *FBB,
630  const DebugLoc &DL,
631  int *BytesAdded) const {
632  unsigned BOpc = Hexagon::J2_jump;
633  unsigned BccOpc = Hexagon::J2_jumpt;
634  assert(validateBranchCond(Cond) && "Invalid branching condition");
635  assert(TBB && "insertBranch must not be told to insert a fallthrough");
636  assert(!BytesAdded && "code size not handled");
637 
638  // Check if reverseBranchCondition has asked to reverse this branch
639  // If we want to reverse the branch an odd number of times, we want
640  // J2_jumpf.
641  if (!Cond.empty() && Cond[0].isImm())
642  BccOpc = Cond[0].getImm();
643 
644  if (!FBB) {
645  if (Cond.empty()) {
646  // Due to a bug in TailMerging/CFG Optimization, we need to add a
647  // special case handling of a predicated jump followed by an
648  // unconditional jump. If not, Tail Merging and CFG Optimization go
649  // into an infinite loop.
650  MachineBasicBlock *NewTBB, *NewFBB;
652  auto Term = MBB.getFirstTerminator();
653  if (Term != MBB.end() && isPredicated(*Term) &&
654  !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
655  MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
657  removeBranch(MBB);
658  return insertBranch(MBB, TBB, nullptr, Cond, DL);
659  }
660  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
661  } else if (isEndLoopN(Cond[0].getImm())) {
662  int EndLoopOp = Cond[0].getImm();
663  assert(Cond[1].isMBB());
664  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
665  // Check for it, and change the BB target if needed.
667  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
668  VisitedBBs);
669  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
670  Loop->getOperand(0).setMBB(TBB);
671  // Add the ENDLOOP after the finding the LOOP0.
672  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
673  } else if (isNewValueJump(Cond[0].getImm())) {
674  assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
675  // New value jump
676  // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
677  // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
678  unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
679  LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
680  << printMBBReference(MBB););
681  if (Cond[2].isReg()) {
682  unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
683  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
684  addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
685  } else if(Cond[2].isImm()) {
686  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
687  addImm(Cond[2].getImm()).addMBB(TBB);
688  } else
689  llvm_unreachable("Invalid condition for branching");
690  } else {
691  assert((Cond.size() == 2) && "Malformed cond vector");
692  const MachineOperand &RO = Cond[1];
693  unsigned Flags = getUndefRegState(RO.isUndef());
694  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
695  }
696  return 1;
697  }
698  assert((!Cond.empty()) &&
699  "Cond. cannot be empty when multiple branchings are required");
700  assert((!isNewValueJump(Cond[0].getImm())) &&
701  "NV-jump cannot be inserted with another branch");
702  // Special case for hardware loops. The condition is a basic block.
703  if (isEndLoopN(Cond[0].getImm())) {
704  int EndLoopOp = Cond[0].getImm();
705  assert(Cond[1].isMBB());
706  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
707  // Check for it, and change the BB target if needed.
709  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
710  VisitedBBs);
711  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
712  Loop->getOperand(0).setMBB(TBB);
713  // Add the ENDLOOP after the finding the LOOP0.
714  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
715  } else {
716  const MachineOperand &RO = Cond[1];
717  unsigned Flags = getUndefRegState(RO.isUndef());
718  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
719  }
720  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
721 
722  return 2;
723 }
724 
725 namespace {
726 class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
727  MachineInstr *Loop, *EndLoop;
728  MachineFunction *MF;
729  const HexagonInstrInfo *TII;
730  int64_t TripCount;
731  Register LoopCount;
732  DebugLoc DL;
733 
734 public:
735  HexagonPipelinerLoopInfo(MachineInstr *Loop, MachineInstr *EndLoop)
736  : Loop(Loop), EndLoop(EndLoop), MF(Loop->getParent()->getParent()),
737  TII(MF->getSubtarget<HexagonSubtarget>().getInstrInfo()),
738  DL(Loop->getDebugLoc()) {
739  // Inspect the Loop instruction up-front, as it may be deleted when we call
740  // createTripCountGreaterCondition.
741  TripCount = Loop->getOpcode() == Hexagon::J2_loop0r
742  ? -1
743  : Loop->getOperand(1).getImm();
744  if (TripCount == -1)
745  LoopCount = Loop->getOperand(1).getReg();
746  }
747 
748  bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
749  // Only ignore the terminator.
750  return MI == EndLoop;
751  }
752 
754  createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
756  if (TripCount == -1) {
757  // Check if we're done with the loop.
758  unsigned Done = TII->createVR(MF, MVT::i1);
759  MachineInstr *NewCmp = BuildMI(&MBB, DL,
760  TII->get(Hexagon::C2_cmpgtui), Done)
761  .addReg(LoopCount)
762  .addImm(TC);
763  Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
764  Cond.push_back(NewCmp->getOperand(0));
765  return {};
766  }
767 
768  return TripCount > TC;
769  }
770 
771  void setPreheader(MachineBasicBlock *NewPreheader) override {
772  NewPreheader->splice(NewPreheader->getFirstTerminator(), Loop->getParent(),
773  Loop);
774  }
775 
776  void adjustTripCount(int TripCountAdjust) override {
777  // If the loop trip count is a compile-time value, then just change the
778  // value.
779  if (Loop->getOpcode() == Hexagon::J2_loop0i ||
780  Loop->getOpcode() == Hexagon::J2_loop1i) {
781  int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust;
782  assert(TripCount > 0 && "Can't create an empty or negative loop!");
783  Loop->getOperand(1).setImm(TripCount);
784  return;
785  }
786 
787  // The loop trip count is a run-time value. We generate code to subtract
788  // one from the trip count, and update the loop instruction.
789  Register LoopCount = Loop->getOperand(1).getReg();
790  Register NewLoopCount = TII->createVR(MF, MVT::i32);
791  BuildMI(*Loop->getParent(), Loop, Loop->getDebugLoc(),
792  TII->get(Hexagon::A2_addi), NewLoopCount)
793  .addReg(LoopCount)
794  .addImm(TripCountAdjust);
795  Loop->getOperand(1).setReg(NewLoopCount);
796  }
797 
798  void disposed() override { Loop->eraseFromParent(); }
799 };
800 } // namespace
801 
802 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
804  // We really "analyze" only hardware loops right now.
806 
807  if (I != LoopBB->end() && isEndLoopN(I->getOpcode())) {
809  MachineInstr *LoopInst = findLoopInstr(
810  LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
811  if (LoopInst)
812  return std::make_unique<HexagonPipelinerLoopInfo>(LoopInst, &*I);
813  }
814  return nullptr;
815 }
816 
818  unsigned NumCycles, unsigned ExtraPredCycles,
819  BranchProbability Probability) const {
820  return nonDbgBBSize(&MBB) <= 3;
821 }
822 
824  unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
825  unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
826  const {
827  return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
828 }
829 
831  unsigned NumInstrs, BranchProbability Probability) const {
832  return NumInstrs <= 4;
833 }
834 
835 static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
837  const MachineBasicBlock &B = *MI.getParent();
838  Regs.addLiveIns(B);
839  auto E = MachineBasicBlock::const_iterator(MI.getIterator());
840  for (auto I = B.begin(); I != E; ++I) {
841  Clobbers.clear();
842  Regs.stepForward(*I, Clobbers);
843  }
844 }
845 
846 static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
847  const MachineBasicBlock &B = *MI.getParent();
848  Regs.addLiveOuts(B);
849  auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
850  for (auto I = B.rbegin(); I != E; ++I)
851  Regs.stepBackward(*I);
852 }
853 
856  const DebugLoc &DL, MCRegister DestReg,
857  MCRegister SrcReg, bool KillSrc) const {
858  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
859  unsigned KillFlag = getKillRegState(KillSrc);
860 
861  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
862  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
863  .addReg(SrcReg, KillFlag);
864  return;
865  }
866  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
867  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
868  .addReg(SrcReg, KillFlag);
869  return;
870  }
871  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
872  // Map Pd = Ps to Pd = or(Ps, Ps).
873  BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
874  .addReg(SrcReg).addReg(SrcReg, KillFlag);
875  return;
876  }
877  if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
878  Hexagon::IntRegsRegClass.contains(SrcReg)) {
879  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
880  .addReg(SrcReg, KillFlag);
881  return;
882  }
883  if (Hexagon::IntRegsRegClass.contains(DestReg) &&
884  Hexagon::CtrRegsRegClass.contains(SrcReg)) {
885  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
886  .addReg(SrcReg, KillFlag);
887  return;
888  }
889  if (Hexagon::ModRegsRegClass.contains(DestReg) &&
890  Hexagon::IntRegsRegClass.contains(SrcReg)) {
891  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
892  .addReg(SrcReg, KillFlag);
893  return;
894  }
895  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
896  Hexagon::IntRegsRegClass.contains(DestReg)) {
897  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
898  .addReg(SrcReg, KillFlag);
899  return;
900  }
901  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
902  Hexagon::PredRegsRegClass.contains(DestReg)) {
903  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
904  .addReg(SrcReg, KillFlag);
905  return;
906  }
907  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
908  Hexagon::IntRegsRegClass.contains(DestReg)) {
909  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
910  .addReg(SrcReg, KillFlag);
911  return;
912  }
913  if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
914  BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
915  addReg(SrcReg, KillFlag);
916  return;
917  }
918  if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
919  LivePhysRegs LiveAtMI(HRI);
920  getLiveInRegsAt(LiveAtMI, *I);
921  Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
922  Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
923  unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo));
924  unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi));
925  BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
926  .addReg(SrcHi, KillFlag | UndefHi)
927  .addReg(SrcLo, KillFlag | UndefLo);
928  return;
929  }
930  if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
931  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
932  .addReg(SrcReg)
933  .addReg(SrcReg, KillFlag);
934  return;
935  }
936  if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
937  Hexagon::HvxVRRegClass.contains(DestReg)) {
938  llvm_unreachable("Unimplemented pred to vec");
939  return;
940  }
941  if (Hexagon::HvxQRRegClass.contains(DestReg) &&
942  Hexagon::HvxVRRegClass.contains(SrcReg)) {
943  llvm_unreachable("Unimplemented vec to pred");
944  return;
945  }
946 
947 #ifndef NDEBUG
948  // Show the invalid registers to ease debugging.
949  dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
950  << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
951 #endif
952  llvm_unreachable("Unimplemented");
953 }
954 
956  MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI,
957  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
959  MachineFunction &MF = *MBB.getParent();
960  MachineFrameInfo &MFI = MF.getFrameInfo();
961  unsigned KillFlag = getKillRegState(isKill);
962 
965  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
966 
967  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
968  BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
969  .addFrameIndex(FI).addImm(0)
970  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
971  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
972  BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
973  .addFrameIndex(FI).addImm(0)
974  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
975  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
976  BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
977  .addFrameIndex(FI).addImm(0)
978  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
979  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
980  BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
981  .addFrameIndex(FI).addImm(0)
982  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
983  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
984  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
985  .addFrameIndex(FI).addImm(0)
986  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
987  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
988  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerv_ai))
989  .addFrameIndex(FI).addImm(0)
990  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
991  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
992  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerw_ai))
993  .addFrameIndex(FI).addImm(0)
994  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
995  } else {
996  llvm_unreachable("Unimplemented");
997  }
998 }
999 
1002  int FI, const TargetRegisterClass *RC,
1003  const TargetRegisterInfo *TRI) const {
1005  MachineFunction &MF = *MBB.getParent();
1006  MachineFrameInfo &MFI = MF.getFrameInfo();
1007 
1010  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
1011 
1012  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
1013  BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
1014  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1015  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
1016  BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
1017  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1018  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
1019  BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
1020  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1021  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
1022  BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
1023  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1024  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
1025  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
1026  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1027  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
1028  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrv_ai), DestReg)
1029  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1030  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1031  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrw_ai), DestReg)
1032  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1033  } else {
1034  llvm_unreachable("Can't store this register to stack slot");
1035  }
1036 }
1037 
1038 /// expandPostRAPseudo - This function is called for all pseudo instructions
1039 /// that remain after register allocation. Many pseudo instructions are
1040 /// created to help register allocation. This is the place to convert them
1041 /// into real instructions. The target can edit MI in place, or it can insert
1042 /// new instructions and erase MI. The function should return true if
1043 /// anything was changed.
1045  MachineBasicBlock &MBB = *MI.getParent();
1046  MachineFunction &MF = *MBB.getParent();
1048  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1049  LivePhysRegs LiveIn(HRI), LiveOut(HRI);
1050  DebugLoc DL = MI.getDebugLoc();
1051  unsigned Opc = MI.getOpcode();
1052 
1053  auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1054  Register Mx = MI.getOperand(MxOp).getReg();
1055  unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1056  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1057  .add(MI.getOperand((HasImm ? 5 : 4)));
1058  auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1059  .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1060  if (HasImm)
1061  MIB.add(MI.getOperand(4));
1062  MIB.addReg(CSx, RegState::Implicit);
1063  MBB.erase(MI);
1064  return true;
1065  };
1066 
1067  auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) {
1068  if (MI.memoperands().empty())
1069  return false;
1070  return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) {
1071  return MMO->getAlign() >= NeedAlign;
1072  });
1073  };
1074 
1075  switch (Opc) {
1076  case Hexagon::PS_call_instrprof_custom: {
1077  auto Op0 = MI.getOperand(0);
1078  assert(Op0.isGlobal() &&
1079  "First operand must be a global containing handler name.");
1080  const GlobalValue *NameVar = Op0.getGlobal();
1081  const GlobalVariable *GV = dyn_cast<GlobalVariable>(NameVar);
1082  auto *Arr = cast<ConstantDataArray>(GV->getInitializer());
1083  StringRef NameStr = Arr->isCString() ? Arr->getAsCString() : Arr->getAsString();
1084 
1085  MachineOperand &Op1 = MI.getOperand(1);
1086  // Set R0 with the imm value to be passed to the custom profiling handler.
1087  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrsi), Hexagon::R0)
1088  .addImm(Op1.getImm());
1089  // The call to the custom handler is being treated as a special one as the
1090  // callee is responsible for saving and restoring all the registers
1091  // (including caller saved registers) it needs to modify. This is
1092  // done to reduce the impact of instrumentation on the code being
1093  // instrumented/profiled.
1094  // NOTE: R14, R15 and R28 are reserved for PLT handling. These registers
1095  // are in the Def list of the Hexagon::PS_call_instrprof_custom and
1096  // therefore will be handled appropriately duing register allocation.
1097 
1098  // TODO: It may be a good idea to add a separate pseudo instruction for
1099  // static relocation which doesn't need to reserve r14, r15 and r28.
1100 
1101  auto MIB = BuildMI(MBB, MI, DL, get(Hexagon::J2_call))
1103  .addDef(Hexagon::R29, RegState::ImplicitDefine)
1104  .addDef(Hexagon::R30, RegState::ImplicitDefine)
1105  .addDef(Hexagon::R14, RegState::ImplicitDefine)
1106  .addDef(Hexagon::R15, RegState::ImplicitDefine)
1107  .addDef(Hexagon::R28, RegState::ImplicitDefine);
1108  const char *cstr = MF.createExternalSymbolName(NameStr);
1109  MIB.addExternalSymbol(cstr);
1110  MBB.erase(MI);
1111  return true;
1112  }
1113  case TargetOpcode::COPY: {
1114  MachineOperand &MD = MI.getOperand(0);
1115  MachineOperand &MS = MI.getOperand(1);
1116  MachineBasicBlock::iterator MBBI = MI.getIterator();
1117  if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1118  copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1119  std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1120  }
1121  MBB.erase(MBBI);
1122  return true;
1123  }
1124  case Hexagon::PS_aligna:
1125  BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1126  .addReg(HRI.getFrameRegister())
1127  .addImm(-MI.getOperand(1).getImm());
1128  MBB.erase(MI);
1129  return true;
1130  case Hexagon::V6_vassignp: {
1131  Register SrcReg = MI.getOperand(1).getReg();
1132  Register DstReg = MI.getOperand(0).getReg();
1133  Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1134  Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1135  getLiveInRegsAt(LiveIn, MI);
1136  unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
1137  unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));
1138  unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1139  BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1140  .addReg(SrcHi, UndefHi)
1141  .addReg(SrcLo, Kill | UndefLo);
1142  MBB.erase(MI);
1143  return true;
1144  }
1145  case Hexagon::V6_lo: {
1146  Register SrcReg = MI.getOperand(1).getReg();
1147  Register DstReg = MI.getOperand(0).getReg();
1148  Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1149  copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1150  MBB.erase(MI);
1151  MRI.clearKillFlags(SrcSubLo);
1152  return true;
1153  }
1154  case Hexagon::V6_hi: {
1155  Register SrcReg = MI.getOperand(1).getReg();
1156  Register DstReg = MI.getOperand(0).getReg();
1157  Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1158  copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1159  MBB.erase(MI);
1160  MRI.clearKillFlags(SrcSubHi);
1161  return true;
1162  }
1163  case Hexagon::PS_vloadrv_ai: {
1164  Register DstReg = MI.getOperand(0).getReg();
1165  const MachineOperand &BaseOp = MI.getOperand(1);
1166  assert(BaseOp.getSubReg() == 0);
1167  int Offset = MI.getOperand(2).getImm();
1168  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1169  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1170  : Hexagon::V6_vL32Ub_ai;
1171  BuildMI(MBB, MI, DL, get(NewOpc), DstReg)
1172  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1173  .addImm(Offset)
1174  .cloneMemRefs(MI);
1175  MBB.erase(MI);
1176  return true;
1177  }
1178  case Hexagon::PS_vloadrw_ai: {
1179  Register DstReg = MI.getOperand(0).getReg();
1180  const MachineOperand &BaseOp = MI.getOperand(1);
1181  assert(BaseOp.getSubReg() == 0);
1182  int Offset = MI.getOperand(2).getImm();
1183  unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1184  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1185  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1186  : Hexagon::V6_vL32Ub_ai;
1187  BuildMI(MBB, MI, DL, get(NewOpc),
1188  HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1189  .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1190  .addImm(Offset)
1191  .cloneMemRefs(MI);
1192  BuildMI(MBB, MI, DL, get(NewOpc),
1193  HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1194  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1195  .addImm(Offset + VecOffset)
1196  .cloneMemRefs(MI);
1197  MBB.erase(MI);
1198  return true;
1199  }
1200  case Hexagon::PS_vstorerv_ai: {
1201  const MachineOperand &SrcOp = MI.getOperand(2);
1202  assert(SrcOp.getSubReg() == 0);
1203  const MachineOperand &BaseOp = MI.getOperand(0);
1204  assert(BaseOp.getSubReg() == 0);
1205  int Offset = MI.getOperand(1).getImm();
1206  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1207  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1208  : Hexagon::V6_vS32Ub_ai;
1209  BuildMI(MBB, MI, DL, get(NewOpc))
1210  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1211  .addImm(Offset)
1213  .cloneMemRefs(MI);
1214  MBB.erase(MI);
1215  return true;
1216  }
1217  case Hexagon::PS_vstorerw_ai: {
1218  Register SrcReg = MI.getOperand(2).getReg();
1219  const MachineOperand &BaseOp = MI.getOperand(0);
1220  assert(BaseOp.getSubReg() == 0);
1221  int Offset = MI.getOperand(1).getImm();
1222  unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1223  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1224  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1225  : Hexagon::V6_vS32Ub_ai;
1226  BuildMI(MBB, MI, DL, get(NewOpc))
1227  .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1228  .addImm(Offset)
1229  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo))
1230  .cloneMemRefs(MI);
1231  BuildMI(MBB, MI, DL, get(NewOpc))
1232  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1233  .addImm(Offset + VecOffset)
1234  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi))
1235  .cloneMemRefs(MI);
1236  MBB.erase(MI);
1237  return true;
1238  }
1239  case Hexagon::PS_true: {
1240  Register Reg = MI.getOperand(0).getReg();
1241  BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1244  MBB.erase(MI);
1245  return true;
1246  }
1247  case Hexagon::PS_false: {
1248  Register Reg = MI.getOperand(0).getReg();
1249  BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1252  MBB.erase(MI);
1253  return true;
1254  }
1255  case Hexagon::PS_qtrue: {
1256  BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1257  .addReg(Hexagon::V0, RegState::Undef)
1258  .addReg(Hexagon::V0, RegState::Undef);
1259  MBB.erase(MI);
1260  return true;
1261  }
1262  case Hexagon::PS_qfalse: {
1263  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1264  .addReg(Hexagon::V0, RegState::Undef)
1265  .addReg(Hexagon::V0, RegState::Undef);
1266  MBB.erase(MI);
1267  return true;
1268  }
1269  case Hexagon::PS_vdd0: {
1270  Register Vd = MI.getOperand(0).getReg();
1271  BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1272  .addReg(Vd, RegState::Undef)
1273  .addReg(Vd, RegState::Undef);
1274  MBB.erase(MI);
1275  return true;
1276  }
1277  case Hexagon::PS_vmulw: {
1278  // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1279  Register DstReg = MI.getOperand(0).getReg();
1280  Register Src1Reg = MI.getOperand(1).getReg();
1281  Register Src2Reg = MI.getOperand(2).getReg();
1282  Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1283  Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1284  Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1285  Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1286  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1287  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1288  .addReg(Src1SubHi)
1289  .addReg(Src2SubHi);
1290  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1291  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1292  .addReg(Src1SubLo)
1293  .addReg(Src2SubLo);
1294  MBB.erase(MI);
1295  MRI.clearKillFlags(Src1SubHi);
1296  MRI.clearKillFlags(Src1SubLo);
1297  MRI.clearKillFlags(Src2SubHi);
1298  MRI.clearKillFlags(Src2SubLo);
1299  return true;
1300  }
1301  case Hexagon::PS_vmulw_acc: {
1302  // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1303  Register DstReg = MI.getOperand(0).getReg();
1304  Register Src1Reg = MI.getOperand(1).getReg();
1305  Register Src2Reg = MI.getOperand(2).getReg();
1306  Register Src3Reg = MI.getOperand(3).getReg();
1307  Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1308  Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1309  Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1310  Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1311  Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1312  Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1313  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1314  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1315  .addReg(Src1SubHi)
1316  .addReg(Src2SubHi)
1317  .addReg(Src3SubHi);
1318  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1319  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1320  .addReg(Src1SubLo)
1321  .addReg(Src2SubLo)
1322  .addReg(Src3SubLo);
1323  MBB.erase(MI);
1324  MRI.clearKillFlags(Src1SubHi);
1325  MRI.clearKillFlags(Src1SubLo);
1326  MRI.clearKillFlags(Src2SubHi);
1327  MRI.clearKillFlags(Src2SubLo);
1328  MRI.clearKillFlags(Src3SubHi);
1329  MRI.clearKillFlags(Src3SubLo);
1330  return true;
1331  }
1332  case Hexagon::PS_pselect: {
1333  const MachineOperand &Op0 = MI.getOperand(0);
1334  const MachineOperand &Op1 = MI.getOperand(1);
1335  const MachineOperand &Op2 = MI.getOperand(2);
1336  const MachineOperand &Op3 = MI.getOperand(3);
1337  Register Rd = Op0.getReg();
1338  Register Pu = Op1.getReg();
1339  Register Rs = Op2.getReg();
1340  Register Rt = Op3.getReg();
1341  DebugLoc DL = MI.getDebugLoc();
1342  unsigned K1 = getKillRegState(Op1.isKill());
1343  unsigned K2 = getKillRegState(Op2.isKill());
1344  unsigned K3 = getKillRegState(Op3.isKill());
1345  if (Rd != Rs)
1346  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1347  .addReg(Pu, (Rd == Rt) ? K1 : 0)
1348  .addReg(Rs, K2);
1349  if (Rd != Rt)
1350  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1351  .addReg(Pu, K1)
1352  .addReg(Rt, K3);
1353  MBB.erase(MI);
1354  return true;
1355  }
1356  case Hexagon::PS_vselect: {
1357  const MachineOperand &Op0 = MI.getOperand(0);
1358  const MachineOperand &Op1 = MI.getOperand(1);
1359  const MachineOperand &Op2 = MI.getOperand(2);
1360  const MachineOperand &Op3 = MI.getOperand(3);
1361  getLiveOutRegsAt(LiveOut, MI);
1362  bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
1363  Register PReg = Op1.getReg();
1364  assert(Op1.getSubReg() == 0);
1365  unsigned PState = getRegState(Op1);
1366 
1367  if (Op0.getReg() != Op2.getReg()) {
1368  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1369  : PState;
1370  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1371  .add(Op0)
1372  .addReg(PReg, S)
1373  .add(Op2);
1374  if (IsDestLive)
1375  T.addReg(Op0.getReg(), RegState::Implicit);
1376  IsDestLive = true;
1377  }
1378  if (Op0.getReg() != Op3.getReg()) {
1379  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1380  .add(Op0)
1381  .addReg(PReg, PState)
1382  .add(Op3);
1383  if (IsDestLive)
1384  T.addReg(Op0.getReg(), RegState::Implicit);
1385  }
1386  MBB.erase(MI);
1387  return true;
1388  }
1389  case Hexagon::PS_wselect: {
1390  MachineOperand &Op0 = MI.getOperand(0);
1391  MachineOperand &Op1 = MI.getOperand(1);
1392  MachineOperand &Op2 = MI.getOperand(2);
1393  MachineOperand &Op3 = MI.getOperand(3);
1394  getLiveOutRegsAt(LiveOut, MI);
1395  bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
1396  Register PReg = Op1.getReg();
1397  assert(Op1.getSubReg() == 0);
1398  unsigned PState = getRegState(Op1);
1399 
1400  if (Op0.getReg() != Op2.getReg()) {
1401  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1402  : PState;
1403  Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1404  Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1405  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1406  .add(Op0)
1407  .addReg(PReg, S)
1408  .addReg(SrcHi)
1409  .addReg(SrcLo);
1410  if (IsDestLive)
1411  T.addReg(Op0.getReg(), RegState::Implicit);
1412  IsDestLive = true;
1413  }
1414  if (Op0.getReg() != Op3.getReg()) {
1415  Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1416  Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1417  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1418  .add(Op0)
1419  .addReg(PReg, PState)
1420  .addReg(SrcHi)
1421  .addReg(SrcLo);
1422  if (IsDestLive)
1423  T.addReg(Op0.getReg(), RegState::Implicit);
1424  }
1425  MBB.erase(MI);
1426  return true;
1427  }
1428 
1429  case Hexagon::PS_crash: {
1430  // Generate a misaligned load that is guaranteed to cause a crash.
1431  class CrashPseudoSourceValue : public PseudoSourceValue {
1432  public:
1433  CrashPseudoSourceValue(const TargetMachine &TM)
1434  : PseudoSourceValue(TargetCustom, TM) {}
1435 
1436  bool isConstant(const MachineFrameInfo *) const override {
1437  return false;
1438  }
1439  bool isAliased(const MachineFrameInfo *) const override {
1440  return false;
1441  }
1442  bool mayAlias(const MachineFrameInfo *) const override {
1443  return false;
1444  }
1445  void printCustom(raw_ostream &OS) const override {
1446  OS << "MisalignedCrash";
1447  }
1448  };
1449 
1450  static const CrashPseudoSourceValue CrashPSV(MF.getTarget());
1452  MachinePointerInfo(&CrashPSV),
1454  Align(1));
1455  BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
1456  .addImm(0xBADC0FEE) // Misaligned load.
1457  .addMemOperand(MMO);
1458  MBB.erase(MI);
1459  return true;
1460  }
1461 
1462  case Hexagon::PS_tailcall_i:
1463  MI.setDesc(get(Hexagon::J2_jump));
1464  return true;
1465  case Hexagon::PS_tailcall_r:
1466  case Hexagon::PS_jmpret:
1467  MI.setDesc(get(Hexagon::J2_jumpr));
1468  return true;
1469  case Hexagon::PS_jmprett:
1470  MI.setDesc(get(Hexagon::J2_jumprt));
1471  return true;
1472  case Hexagon::PS_jmpretf:
1473  MI.setDesc(get(Hexagon::J2_jumprf));
1474  return true;
1475  case Hexagon::PS_jmprettnewpt:
1476  MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1477  return true;
1478  case Hexagon::PS_jmpretfnewpt:
1479  MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1480  return true;
1481  case Hexagon::PS_jmprettnew:
1482  MI.setDesc(get(Hexagon::J2_jumprtnew));
1483  return true;
1484  case Hexagon::PS_jmpretfnew:
1485  MI.setDesc(get(Hexagon::J2_jumprfnew));
1486  return true;
1487 
1488  case Hexagon::PS_loadrub_pci:
1489  return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1490  case Hexagon::PS_loadrb_pci:
1491  return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1492  case Hexagon::PS_loadruh_pci:
1493  return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1494  case Hexagon::PS_loadrh_pci:
1495  return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1496  case Hexagon::PS_loadri_pci:
1497  return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1498  case Hexagon::PS_loadrd_pci:
1499  return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1500  case Hexagon::PS_loadrub_pcr:
1501  return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1502  case Hexagon::PS_loadrb_pcr:
1503  return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1504  case Hexagon::PS_loadruh_pcr:
1505  return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1506  case Hexagon::PS_loadrh_pcr:
1507  return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1508  case Hexagon::PS_loadri_pcr:
1509  return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1510  case Hexagon::PS_loadrd_pcr:
1511  return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1512  case Hexagon::PS_storerb_pci:
1513  return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1514  case Hexagon::PS_storerh_pci:
1515  return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1516  case Hexagon::PS_storerf_pci:
1517  return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1518  case Hexagon::PS_storeri_pci:
1519  return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1520  case Hexagon::PS_storerd_pci:
1521  return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1522  case Hexagon::PS_storerb_pcr:
1523  return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1524  case Hexagon::PS_storerh_pcr:
1525  return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1526  case Hexagon::PS_storerf_pcr:
1527  return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1528  case Hexagon::PS_storeri_pcr:
1529  return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1530  case Hexagon::PS_storerd_pcr:
1531  return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1532  }
1533 
1534  return false;
1535 }
1536 
1539  MachineBasicBlock &MBB = *MI.getParent();
1540  const DebugLoc &DL = MI.getDebugLoc();
1541  unsigned Opc = MI.getOpcode();
1543 
1544  switch (Opc) {
1545  case Hexagon::V6_vgathermh_pseudo:
1546  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1547  .add(MI.getOperand(2))
1548  .add(MI.getOperand(3))
1549  .add(MI.getOperand(4));
1550  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1551  .add(MI.getOperand(0))
1552  .addImm(MI.getOperand(1).getImm())
1553  .addReg(Hexagon::VTMP);
1554  MBB.erase(MI);
1555  return First.getInstrIterator();
1556 
1557  case Hexagon::V6_vgathermw_pseudo:
1558  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1559  .add(MI.getOperand(2))
1560  .add(MI.getOperand(3))
1561  .add(MI.getOperand(4));
1562  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1563  .add(MI.getOperand(0))
1564  .addImm(MI.getOperand(1).getImm())
1565  .addReg(Hexagon::VTMP);
1566  MBB.erase(MI);
1567  return First.getInstrIterator();
1568 
1569  case Hexagon::V6_vgathermhw_pseudo:
1570  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1571  .add(MI.getOperand(2))
1572  .add(MI.getOperand(3))
1573  .add(MI.getOperand(4));
1574  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1575  .add(MI.getOperand(0))
1576  .addImm(MI.getOperand(1).getImm())
1577  .addReg(Hexagon::VTMP);
1578  MBB.erase(MI);
1579  return First.getInstrIterator();
1580 
1581  case Hexagon::V6_vgathermhq_pseudo:
1582  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1583  .add(MI.getOperand(2))
1584  .add(MI.getOperand(3))
1585  .add(MI.getOperand(4))
1586  .add(MI.getOperand(5));
1587  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1588  .add(MI.getOperand(0))
1589  .addImm(MI.getOperand(1).getImm())
1590  .addReg(Hexagon::VTMP);
1591  MBB.erase(MI);
1592  return First.getInstrIterator();
1593 
1594  case Hexagon::V6_vgathermwq_pseudo:
1595  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1596  .add(MI.getOperand(2))
1597  .add(MI.getOperand(3))
1598  .add(MI.getOperand(4))
1599  .add(MI.getOperand(5));
1600  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1601  .add(MI.getOperand(0))
1602  .addImm(MI.getOperand(1).getImm())
1603  .addReg(Hexagon::VTMP);
1604  MBB.erase(MI);
1605  return First.getInstrIterator();
1606 
1607  case Hexagon::V6_vgathermhwq_pseudo:
1608  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1609  .add(MI.getOperand(2))
1610  .add(MI.getOperand(3))
1611  .add(MI.getOperand(4))
1612  .add(MI.getOperand(5));
1613  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1614  .add(MI.getOperand(0))
1615  .addImm(MI.getOperand(1).getImm())
1616  .addReg(Hexagon::VTMP);
1617  MBB.erase(MI);
1618  return First.getInstrIterator();
1619  }
1620 
1621  return MI.getIterator();
1622 }
1623 
1624 // We indicate that we want to reverse the branch by
1625 // inserting the reversed branching opcode.
1628  if (Cond.empty())
1629  return true;
1630  assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1631  unsigned opcode = Cond[0].getImm();
1632  //unsigned temp;
1633  assert(get(opcode).isBranch() && "Should be a branching condition.");
1634  if (isEndLoopN(opcode))
1635  return true;
1636  unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1637  Cond[0].setImm(NewOpcode);
1638  return false;
1639 }
1640 
1643  DebugLoc DL;
1644  BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1645 }
1646 
1648  return getAddrMode(MI) == HexagonII::PostInc;
1649 }
1650 
1651 // Returns true if an instruction is predicated irrespective of the predicate
1652 // sense. For example, all of the following will return true.
1653 // if (p0) R1 = add(R2, R3)
1654 // if (!p0) R1 = add(R2, R3)
1655 // if (p0.new) R1 = add(R2, R3)
1656 // if (!p0.new) R1 = add(R2, R3)
1657 // Note: New-value stores are not included here as in the current
1658 // implementation, we don't need to check their predicate sense.
1660  const uint64_t F = MI.getDesc().TSFlags;
1662 }
1663 
1666  if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1667  isEndLoopN(Cond[0].getImm())) {
1668  LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1669  return false;
1670  }
1671  int Opc = MI.getOpcode();
1672  assert (isPredicable(MI) && "Expected predicable instruction");
1673  bool invertJump = predOpcodeHasNot(Cond);
1674 
1675  // We have to predicate MI "in place", i.e. after this function returns,
1676  // MI will need to be transformed into a predicated form. To avoid com-
1677  // plicated manipulations with the operands (handling tied operands,
1678  // etc.), build a new temporary instruction, then overwrite MI with it.
1679 
1680  MachineBasicBlock &B = *MI.getParent();
1681  DebugLoc DL = MI.getDebugLoc();
1682  unsigned PredOpc = getCondOpcode(Opc, invertJump);
1683  MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1684  unsigned NOp = 0, NumOps = MI.getNumOperands();
1685  while (NOp < NumOps) {
1686  MachineOperand &Op = MI.getOperand(NOp);
1687  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1688  break;
1689  T.add(Op);
1690  NOp++;
1691  }
1692 
1693  unsigned PredReg, PredRegPos, PredRegFlags;
1694  bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1695  (void)GotPredReg;
1696  assert(GotPredReg);
1697  T.addReg(PredReg, PredRegFlags);
1698  while (NOp < NumOps)
1699  T.add(MI.getOperand(NOp++));
1700 
1701  MI.setDesc(get(PredOpc));
1702  while (unsigned n = MI.getNumOperands())
1703  MI.removeOperand(n-1);
1704  for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1705  MI.addOperand(T->getOperand(i));
1706 
1707  MachineBasicBlock::instr_iterator TI = T->getIterator();
1708  B.erase(TI);
1709 
1710  MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1711  MRI.clearKillFlags(PredReg);
1712  return true;
1713 }
1714 
1716  ArrayRef<MachineOperand> Pred2) const {
1717  // TODO: Fix this
1718  return false;
1719 }
1720 
1722  std::vector<MachineOperand> &Pred,
1723  bool SkipDead) const {
1724  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1725 
1726  for (const MachineOperand &MO : MI.operands()) {
1727  if (MO.isReg()) {
1728  if (!MO.isDef())
1729  continue;
1730  const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1731  if (RC == &Hexagon::PredRegsRegClass) {
1732  Pred.push_back(MO);
1733  return true;
1734  }
1735  continue;
1736  } else if (MO.isRegMask()) {
1737  for (unsigned PR : Hexagon::PredRegsRegClass) {
1738  if (!MI.modifiesRegister(PR, &HRI))
1739  continue;
1740  Pred.push_back(MO);
1741  return true;
1742  }
1743  }
1744  }
1745  return false;
1746 }
1747 
1749  if (!MI.getDesc().isPredicable())
1750  return false;
1751 
1752  if (MI.isCall() || isTailCall(MI)) {
1753  if (!Subtarget.usePredicatedCalls())
1754  return false;
1755  }
1756 
1757  // HVX loads are not predicable on v60, but are on v62.
1758  if (!Subtarget.hasV62Ops()) {
1759  switch (MI.getOpcode()) {
1760  case Hexagon::V6_vL32b_ai:
1761  case Hexagon::V6_vL32b_pi:
1762  case Hexagon::V6_vL32b_ppu:
1763  case Hexagon::V6_vL32b_cur_ai:
1764  case Hexagon::V6_vL32b_cur_pi:
1765  case Hexagon::V6_vL32b_cur_ppu:
1766  case Hexagon::V6_vL32b_nt_ai:
1767  case Hexagon::V6_vL32b_nt_pi:
1768  case Hexagon::V6_vL32b_nt_ppu:
1769  case Hexagon::V6_vL32b_tmp_ai:
1770  case Hexagon::V6_vL32b_tmp_pi:
1771  case Hexagon::V6_vL32b_tmp_ppu:
1772  case Hexagon::V6_vL32b_nt_cur_ai:
1773  case Hexagon::V6_vL32b_nt_cur_pi:
1774  case Hexagon::V6_vL32b_nt_cur_ppu:
1775  case Hexagon::V6_vL32b_nt_tmp_ai:
1776  case Hexagon::V6_vL32b_nt_tmp_pi:
1777  case Hexagon::V6_vL32b_nt_tmp_ppu:
1778  return false;
1779  }
1780  }
1781  return true;
1782 }
1783 
1785  const MachineBasicBlock *MBB,
1786  const MachineFunction &MF) const {
1787  // Debug info is never a scheduling boundary. It's necessary to be explicit
1788  // due to the special treatment of IT instructions below, otherwise a
1789  // dbg_value followed by an IT will result in the IT instruction being
1790  // considered a scheduling hazard, which is wrong. It should be the actual
1791  // instruction preceding the dbg_value instruction(s), just like it is
1792  // when debug info is not present.
1793  if (MI.isDebugInstr())
1794  return false;
1795 
1796  // Throwing call is a boundary.
1797  if (MI.isCall()) {
1798  // Don't mess around with no return calls.
1799  if (doesNotReturn(MI))
1800  return true;
1801  // If any of the block's successors is a landing pad, this could be a
1802  // throwing call.
1803  for (auto I : MBB->successors())
1804  if (I->isEHPad())
1805  return true;
1806  }
1807 
1808  // Terminators and labels can't be scheduled around.
1809  if (MI.getDesc().isTerminator() || MI.isPosition())
1810  return true;
1811 
1812  // INLINEASM_BR can jump to another block
1813  if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1814  return true;
1815 
1816  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1817  return true;
1818 
1819  return false;
1820 }
1821 
1822 /// Measure the specified inline asm to determine an approximation of its
1823 /// length.
1824 /// Comments (which run till the next SeparatorString or newline) do not
1825 /// count as an instruction.
1826 /// Any other non-whitespace text is considered an instruction, with
1827 /// multiple instructions separated by SeparatorString or newlines.
1828 /// Variable-length instructions are not handled here; this function
1829 /// may be overloaded in the target code to do that.
1830 /// Hexagon counts the number of ##'s and adjust for that many
1831 /// constant exenders.
1832 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1833  const MCAsmInfo &MAI,
1834  const TargetSubtargetInfo *STI) const {
1835  StringRef AStr(Str);
1836  // Count the number of instructions in the asm.
1837  bool atInsnStart = true;
1838  unsigned Length = 0;
1839  const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
1840  for (; *Str; ++Str) {
1841  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1842  strlen(MAI.getSeparatorString())) == 0)
1843  atInsnStart = true;
1844  if (atInsnStart && !isSpace(static_cast<unsigned char>(*Str))) {
1845  Length += MaxInstLength;
1846  atInsnStart = false;
1847  }
1848  if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1849  MAI.getCommentString().size()) == 0)
1850  atInsnStart = false;
1851  }
1852 
1853  // Add to size number of constant extenders seen * 4.
1854  StringRef Occ("##");
1855  Length += AStr.count(Occ)*4;
1856  return Length;
1857 }
1858 
1861  const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1862  if (UseDFAHazardRec)
1863  return new HexagonHazardRecognizer(II, this, Subtarget);
1865 }
1866 
1867 /// For a comparison instruction, return the source registers in
1868 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1869 /// compares against in CmpValue. Return true if the comparison instruction
1870 /// can be analyzed.
1872  Register &SrcReg2, int64_t &Mask,
1873  int64_t &Value) const {
1874  unsigned Opc = MI.getOpcode();
1875 
1876  // Set mask and the first source register.
1877  switch (Opc) {
1878  case Hexagon::C2_cmpeq:
1879  case Hexagon::C2_cmpeqp:
1880  case Hexagon::C2_cmpgt:
1881  case Hexagon::C2_cmpgtp:
1882  case Hexagon::C2_cmpgtu:
1883  case Hexagon::C2_cmpgtup:
1884  case Hexagon::C4_cmpneq:
1885  case Hexagon::C4_cmplte:
1886  case Hexagon::C4_cmplteu:
1887  case Hexagon::C2_cmpeqi:
1888  case Hexagon::C2_cmpgti:
1889  case Hexagon::C2_cmpgtui:
1890  case Hexagon::C4_cmpneqi:
1891  case Hexagon::C4_cmplteui:
1892  case Hexagon::C4_cmpltei:
1893  SrcReg = MI.getOperand(1).getReg();
1894  Mask = ~0;
1895  break;
1896  case Hexagon::A4_cmpbeq:
1897  case Hexagon::A4_cmpbgt:
1898  case Hexagon::A4_cmpbgtu:
1899  case Hexagon::A4_cmpbeqi:
1900  case Hexagon::A4_cmpbgti:
1901  case Hexagon::A4_cmpbgtui:
1902  SrcReg = MI.getOperand(1).getReg();
1903  Mask = 0xFF;
1904  break;
1905  case Hexagon::A4_cmpheq:
1906  case Hexagon::A4_cmphgt:
1907  case Hexagon::A4_cmphgtu:
1908  case Hexagon::A4_cmpheqi:
1909  case Hexagon::A4_cmphgti:
1910  case Hexagon::A4_cmphgtui:
1911  SrcReg = MI.getOperand(1).getReg();
1912  Mask = 0xFFFF;
1913  break;
1914  }
1915 
1916  // Set the value/second source register.
1917  switch (Opc) {
1918  case Hexagon::C2_cmpeq:
1919  case Hexagon::C2_cmpeqp:
1920  case Hexagon::C2_cmpgt:
1921  case Hexagon::C2_cmpgtp:
1922  case Hexagon::C2_cmpgtu:
1923  case Hexagon::C2_cmpgtup:
1924  case Hexagon::A4_cmpbeq:
1925  case Hexagon::A4_cmpbgt:
1926  case Hexagon::A4_cmpbgtu:
1927  case Hexagon::A4_cmpheq:
1928  case Hexagon::A4_cmphgt:
1929  case Hexagon::A4_cmphgtu:
1930  case Hexagon::C4_cmpneq:
1931  case Hexagon::C4_cmplte:
1932  case Hexagon::C4_cmplteu:
1933  SrcReg2 = MI.getOperand(2).getReg();
1934  Value = 0;
1935  return true;
1936 
1937  case Hexagon::C2_cmpeqi:
1938  case Hexagon::C2_cmpgtui:
1939  case Hexagon::C2_cmpgti:
1940  case Hexagon::C4_cmpneqi:
1941  case Hexagon::C4_cmplteui:
1942  case Hexagon::C4_cmpltei:
1943  case Hexagon::A4_cmpbeqi:
1944  case Hexagon::A4_cmpbgti:
1945  case Hexagon::A4_cmpbgtui:
1946  case Hexagon::A4_cmpheqi:
1947  case Hexagon::A4_cmphgti:
1948  case Hexagon::A4_cmphgtui: {
1949  SrcReg2 = 0;
1950  const MachineOperand &Op2 = MI.getOperand(2);
1951  if (!Op2.isImm())
1952  return false;
1953  Value = MI.getOperand(2).getImm();
1954  return true;
1955  }
1956  }
1957 
1958  return false;
1959 }
1960 
1962  const MachineInstr &MI,
1963  unsigned *PredCost) const {
1964  return getInstrTimingClassLatency(ItinData, MI);
1965 }
1966 
1968  const TargetSubtargetInfo &STI) const {
1969  const InstrItineraryData *II = STI.getInstrItineraryData();
1970  return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1971 }
1972 
1973 // Inspired by this pair:
1974 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1975 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1976 // Currently AA considers the addresses in these instructions to be aliasing.
1978  const MachineInstr &MIa, const MachineInstr &MIb) const {
1979  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1981  return false;
1982 
1983  // Instructions that are pure loads, not loads and stores like memops are not
1984  // dependent.
1985  if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1986  return true;
1987 
1988  // Get the base register in MIa.
1989  unsigned BasePosA, OffsetPosA;
1990  if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1991  return false;
1992  const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1993  Register BaseRegA = BaseA.getReg();
1994  unsigned BaseSubA = BaseA.getSubReg();
1995 
1996  // Get the base register in MIb.
1997  unsigned BasePosB, OffsetPosB;
1998  if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1999  return false;
2000  const MachineOperand &BaseB = MIb.getOperand(BasePosB);
2001  Register BaseRegB = BaseB.getReg();
2002  unsigned BaseSubB = BaseB.getSubReg();
2003 
2004  if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
2005  return false;
2006 
2007  // Get the access sizes.
2008  unsigned SizeA = getMemAccessSize(MIa);
2009  unsigned SizeB = getMemAccessSize(MIb);
2010 
2011  // Get the offsets. Handle immediates only for now.
2012  const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
2013  const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
2014  if (!MIa.getOperand(OffsetPosA).isImm() ||
2015  !MIb.getOperand(OffsetPosB).isImm())
2016  return false;
2017  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
2018  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
2019 
2020  // This is a mem access with the same base register and known offsets from it.
2021  // Reason about it.
2022  if (OffsetA > OffsetB) {
2023  uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
2024  return SizeB <= OffDiff;
2025  }
2026  if (OffsetA < OffsetB) {
2027  uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
2028  return SizeA <= OffDiff;
2029  }
2030 
2031  return false;
2032 }
2033 
2034 /// If the instruction is an increment of a constant value, return the amount.
2036  int &Value) const {
2037  if (isPostIncrement(MI)) {
2038  unsigned BasePos = 0, OffsetPos = 0;
2039  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
2040  return false;
2041  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
2042  if (OffsetOp.isImm()) {
2043  Value = OffsetOp.getImm();
2044  return true;
2045  }
2046  } else if (MI.getOpcode() == Hexagon::A2_addi) {
2047  const MachineOperand &AddOp = MI.getOperand(2);
2048  if (AddOp.isImm()) {
2049  Value = AddOp.getImm();
2050  return true;
2051  }
2052  }
2053 
2054  return false;
2055 }
2056 
2057 std::pair<unsigned, unsigned>
2059  return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
2060  TF & HexagonII::MO_Bitmasks);
2061 }
2062 
2065  using namespace HexagonII;
2066 
2067  static const std::pair<unsigned, const char*> Flags[] = {
2068  {MO_PCREL, "hexagon-pcrel"},
2069  {MO_GOT, "hexagon-got"},
2070  {MO_LO16, "hexagon-lo16"},
2071  {MO_HI16, "hexagon-hi16"},
2072  {MO_GPREL, "hexagon-gprel"},
2073  {MO_GDGOT, "hexagon-gdgot"},
2074  {MO_GDPLT, "hexagon-gdplt"},
2075  {MO_IE, "hexagon-ie"},
2076  {MO_IEGOT, "hexagon-iegot"},
2077  {MO_TPREL, "hexagon-tprel"}
2078  };
2079  return makeArrayRef(Flags);
2080 }
2081 
2084  using namespace HexagonII;
2085 
2086  static const std::pair<unsigned, const char*> Flags[] = {
2087  {HMOTF_ConstExtended, "hexagon-ext"}
2088  };
2089  return makeArrayRef(Flags);
2090 }
2091 
2094  const TargetRegisterClass *TRC;
2095  if (VT == MVT::i1) {
2096  TRC = &Hexagon::PredRegsRegClass;
2097  } else if (VT == MVT::i32 || VT == MVT::f32) {
2098  TRC = &Hexagon::IntRegsRegClass;
2099  } else if (VT == MVT::i64 || VT == MVT::f64) {
2100  TRC = &Hexagon::DoubleRegsRegClass;
2101  } else {
2102  llvm_unreachable("Cannot handle this register class");
2103  }
2104 
2105  Register NewReg = MRI.createVirtualRegister(TRC);
2106  return NewReg;
2107 }
2108 
2110  return (getAddrMode(MI) == HexagonII::AbsoluteSet);
2111 }
2112 
2114  const uint64_t F = MI.getDesc().TSFlags;
2116 }
2117 
2120 }
2121 
2123  return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
2124  !MI.getDesc().mayStore() &&
2125  MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2126  MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2127  !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
2128 }
2129 
2130 // Return true if the instruction is a compund branch instruction.
2132  return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
2133 }
2134 
2135 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
2136 // isFPImm and later getFPImm as well.
2138  const uint64_t F = MI.getDesc().TSFlags;
2140  if (isExtended) // Instruction must be extended.
2141  return true;
2142 
2143  unsigned isExtendable =
2145  if (!isExtendable)
2146  return false;
2147 
2148  if (MI.isCall())
2149  return false;
2150 
2151  short ExtOpNum = getCExtOpNum(MI);
2152  const MachineOperand &MO = MI.getOperand(ExtOpNum);
2153  // Use MO operand flags to determine if MO
2154  // has the HMOTF_ConstExtended flag set.
2156  return true;
2157  // If this is a Machine BB address we are talking about, and it is
2158  // not marked as extended, say so.
2159  if (MO.isMBB())
2160  return false;
2161 
2162  // We could be using an instruction with an extendable immediate and shoehorn
2163  // a global address into it. If it is a global address it will be constant
2164  // extended. We do this for COMBINE.
2165  if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2166  MO.isJTI() || MO.isCPI() || MO.isFPImm())
2167  return true;
2168 
2169  // If the extendable operand is not 'Immediate' type, the instruction should
2170  // have 'isExtended' flag set.
2171  assert(MO.isImm() && "Extendable operand must be Immediate type");
2172 
2173  int MinValue = getMinValue(MI);
2174  int MaxValue = getMaxValue(MI);
2175  int ImmValue = MO.getImm();
2176 
2177  return (ImmValue < MinValue || ImmValue > MaxValue);
2178 }
2179 
2181  switch (MI.getOpcode()) {
2182  case Hexagon::L4_return:
2183  case Hexagon::L4_return_t:
2184  case Hexagon::L4_return_f:
2185  case Hexagon::L4_return_tnew_pnt:
2186  case Hexagon::L4_return_fnew_pnt:
2187  case Hexagon::L4_return_tnew_pt:
2188  case Hexagon::L4_return_fnew_pt:
2189  return true;
2190  }
2191  return false;
2192 }
2193 
2194 // Return true when ConsMI uses a register defined by ProdMI.
2196  const MachineInstr &ConsMI) const {
2197  if (!ProdMI.getDesc().getNumDefs())
2198  return false;
2199  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2200 
2205 
2206  parseOperands(ProdMI, DefsA, UsesA);
2207  parseOperands(ConsMI, DefsB, UsesB);
2208 
2209  for (auto &RegA : DefsA)
2210  for (auto &RegB : UsesB) {
2211  // True data dependency.
2212  if (RegA == RegB)
2213  return true;
2214 
2215  if (Register::isPhysicalRegister(RegA))
2216  for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
2217  if (RegB == *SubRegs)
2218  return true;
2219 
2220  if (Register::isPhysicalRegister(RegB))
2221  for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
2222  if (RegA == *SubRegs)
2223  return true;
2224  }
2225 
2226  return false;
2227 }
2228 
2229 // Returns true if the instruction is alread a .cur.
2231  switch (MI.getOpcode()) {
2232  case Hexagon::V6_vL32b_cur_pi:
2233  case Hexagon::V6_vL32b_cur_ai:
2234  return true;
2235  }
2236  return false;
2237 }
2238 
2239 // Returns true, if any one of the operands is a dot new
2240 // insn, whether it is predicated dot new or register dot new.
2243  return true;
2244 
2245  return false;
2246 }
2247 
2248 /// Symmetrical. See if these two instructions are fit for duplex pair.
2250  const MachineInstr &MIb) const {
2253  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2254 }
2255 
2257  if (MI.mayLoadOrStore() || MI.isCompare())
2258  return true;
2259 
2260  // Multiply
2261  unsigned SchedClass = MI.getDesc().getSchedClass();
2262  return is_TC4x(SchedClass) || is_TC3x(SchedClass);
2263 }
2264 
2265 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2266  return (Opcode == Hexagon::ENDLOOP0 ||
2267  Opcode == Hexagon::ENDLOOP1);
2268 }
2269 
2270 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2271  switch(OpType) {
2278  return true;
2279  default:
2280  return false;
2281  }
2282 }
2283 
2285  const MCInstrDesc &MID = MI.getDesc();
2286  const uint64_t F = MID.TSFlags;
2288  return true;
2289 
2290  // TODO: This is largely obsolete now. Will need to be removed
2291  // in consecutive patches.
2292  switch (MI.getOpcode()) {
2293  // PS_fi and PS_fia remain special cases.
2294  case Hexagon::PS_fi:
2295  case Hexagon::PS_fia:
2296  return true;
2297  default:
2298  return false;
2299  }
2300  return false;
2301 }
2302 
2303 // This returns true in two cases:
2304 // - The OP code itself indicates that this is an extended instruction.
2305 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2307  // First check if this is permanently extended op code.
2308  const uint64_t F = MI.getDesc().TSFlags;
2310  return true;
2311  // Use MO operand flags to determine if one of MI's operands
2312  // has HMOTF_ConstExtended flag set.
2313  for (const MachineOperand &MO : MI.operands())
2314  if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2315  return true;
2316  return false;
2317 }
2318 
2320  unsigned Opcode = MI.getOpcode();
2321  const uint64_t F = get(Opcode).TSFlags;
2322  return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2323 }
2324 
2325 // No V60 HVX VMEM with A_INDIRECT.
2327  const MachineInstr &J) const {
2328  if (!isHVXVec(I))
2329  return false;
2330  if (!I.mayLoad() && !I.mayStore())
2331  return false;
2332  return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2333 }
2334 
2336  switch (MI.getOpcode()) {
2337  case Hexagon::J2_callr:
2338  case Hexagon::J2_callrf:
2339  case Hexagon::J2_callrt:
2340  case Hexagon::PS_call_nr:
2341  return true;
2342  }
2343  return false;
2344 }
2345 
2347  switch (MI.getOpcode()) {
2348  case Hexagon::L4_return:
2349  case Hexagon::L4_return_t:
2350  case Hexagon::L4_return_f:
2351  case Hexagon::L4_return_fnew_pnt:
2352  case Hexagon::L4_return_fnew_pt:
2353  case Hexagon::L4_return_tnew_pnt:
2354  case Hexagon::L4_return_tnew_pt:
2355  return true;
2356  }
2357  return false;
2358 }
2359 
2361  switch (MI.getOpcode()) {
2362  case Hexagon::J2_jumpr:
2363  case Hexagon::J2_jumprt:
2364  case Hexagon::J2_jumprf:
2365  case Hexagon::J2_jumprtnewpt:
2366  case Hexagon::J2_jumprfnewpt:
2367  case Hexagon::J2_jumprtnew:
2368  case Hexagon::J2_jumprfnew:
2369  return true;
2370  }
2371  return false;
2372 }
2373 
2374 // Return true if a given MI can accommodate given offset.
2375 // Use abs estimate as oppose to the exact number.
2376 // TODO: This will need to be changed to use MC level
2377 // definition of instruction extendable field size.
2379  unsigned offset) const {
2380  // This selection of jump instructions matches to that what
2381  // analyzeBranch can parse, plus NVJ.
2382  if (isNewValueJump(MI)) // r9:2
2383  return isInt<11>(offset);
2384 
2385  switch (MI.getOpcode()) {
2386  // Still missing Jump to address condition on register value.
2387  default:
2388  return false;
2389  case Hexagon::J2_jump: // bits<24> dst; // r22:2
2390  case Hexagon::J2_call:
2391  case Hexagon::PS_call_nr:
2392  return isInt<24>(offset);
2393  case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2394  case Hexagon::J2_jumpf:
2395  case Hexagon::J2_jumptnew:
2396  case Hexagon::J2_jumptnewpt:
2397  case Hexagon::J2_jumpfnew:
2398  case Hexagon::J2_jumpfnewpt:
2399  case Hexagon::J2_callt:
2400  case Hexagon::J2_callf:
2401  return isInt<17>(offset);
2402  case Hexagon::J2_loop0i:
2403  case Hexagon::J2_loop0iext:
2404  case Hexagon::J2_loop0r:
2405  case Hexagon::J2_loop0rext:
2406  case Hexagon::J2_loop1i:
2407  case Hexagon::J2_loop1iext:
2408  case Hexagon::J2_loop1r:
2409  case Hexagon::J2_loop1rext:
2410  return isInt<9>(offset);
2411  // TODO: Add all the compound branches here. Can we do this in Relation model?
2412  case Hexagon::J4_cmpeqi_tp0_jump_nt:
2413  case Hexagon::J4_cmpeqi_tp1_jump_nt:
2414  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2415  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2416  return isInt<11>(offset);
2417  }
2418 }
2419 
2421  const MachineInstr &ESMI) const {
2422  bool isLate = isLateResultInstr(LRMI);
2423  bool isEarly = isEarlySourceInstr(ESMI);
2424 
2425  LLVM_DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2426  LLVM_DEBUG(LRMI.dump());
2427  LLVM_DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2428  LLVM_DEBUG(ESMI.dump());
2429 
2430  if (isLate && isEarly) {
2431  LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2432  return true;
2433  }
2434 
2435  return false;
2436 }
2437 
2439  switch (MI.getOpcode()) {
2440  case TargetOpcode::EXTRACT_SUBREG:
2441  case TargetOpcode::INSERT_SUBREG:
2442  case TargetOpcode::SUBREG_TO_REG:
2443  case TargetOpcode::REG_SEQUENCE:
2444  case TargetOpcode::IMPLICIT_DEF:
2445  case TargetOpcode::COPY:
2447  case TargetOpcode::PHI:
2448  return false;
2449  default:
2450  break;
2451  }
2452 
2453  unsigned SchedClass = MI.getDesc().getSchedClass();
2454  return !is_TC1(SchedClass);
2455 }
2456 
2458  // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2459  // resource, but all operands can be received late like an ALU instruction.
2461 }
2462 
2464  unsigned Opcode = MI.getOpcode();
2465  return Opcode == Hexagon::J2_loop0i ||
2466  Opcode == Hexagon::J2_loop0r ||
2467  Opcode == Hexagon::J2_loop0iext ||
2468  Opcode == Hexagon::J2_loop0rext ||
2469  Opcode == Hexagon::J2_loop1i ||
2470  Opcode == Hexagon::J2_loop1r ||
2471  Opcode == Hexagon::J2_loop1iext ||
2472  Opcode == Hexagon::J2_loop1rext;
2473 }
2474 
2476  switch (MI.getOpcode()) {
2477  default: return false;
2478  case Hexagon::L4_iadd_memopw_io:
2479  case Hexagon::L4_isub_memopw_io:
2480  case Hexagon::L4_add_memopw_io:
2481  case Hexagon::L4_sub_memopw_io:
2482  case Hexagon::L4_and_memopw_io:
2483  case Hexagon::L4_or_memopw_io:
2484  case Hexagon::L4_iadd_memoph_io:
2485  case Hexagon::L4_isub_memoph_io:
2486  case Hexagon::L4_add_memoph_io:
2487  case Hexagon::L4_sub_memoph_io:
2488  case Hexagon::L4_and_memoph_io:
2489  case Hexagon::L4_or_memoph_io:
2490  case Hexagon::L4_iadd_memopb_io:
2491  case Hexagon::L4_isub_memopb_io:
2492  case Hexagon::L4_add_memopb_io:
2493  case Hexagon::L4_sub_memopb_io:
2494  case Hexagon::L4_and_memopb_io:
2495  case Hexagon::L4_or_memopb_io:
2496  case Hexagon::L4_ior_memopb_io:
2497  case Hexagon::L4_ior_memoph_io:
2498  case Hexagon::L4_ior_memopw_io:
2499  case Hexagon::L4_iand_memopb_io:
2500  case Hexagon::L4_iand_memoph_io:
2501  case Hexagon::L4_iand_memopw_io:
2502  return true;
2503  }
2504  return false;
2505 }
2506 
2508  const uint64_t F = MI.getDesc().TSFlags;
2510 }
2511 
2512 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2513  const uint64_t F = get(Opcode).TSFlags;
2515 }
2516 
2518  return isNewValueJump(MI) || isNewValueStore(MI);
2519 }
2520 
2522  return isNewValue(MI) && MI.isBranch();
2523 }
2524 
2525 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2526  return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2527 }
2528 
2530  const uint64_t F = MI.getDesc().TSFlags;
2532 }
2533 
2534 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2535  const uint64_t F = get(Opcode).TSFlags;
2537 }
2538 
2539 // Returns true if a particular operand is extendable for an instruction.
2541  unsigned OperandNum) const {
2542  const uint64_t F = MI.getDesc().TSFlags;
2544  == OperandNum;
2545 }
2546 
2548  const uint64_t F = MI.getDesc().TSFlags;
2551 }
2552 
2553 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2554  const uint64_t F = get(Opcode).TSFlags;
2555  assert(isPredicated(Opcode));
2557 }
2558 
2560  const uint64_t F = MI.getDesc().TSFlags;
2561  return !((F >> HexagonII::PredicatedFalsePos) &
2563 }
2564 
2565 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2566  const uint64_t F = get(Opcode).TSFlags;
2567  // Make sure that the instruction is predicated.
2569  return !((F >> HexagonII::PredicatedFalsePos) &
2571 }
2572 
2573 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2574  const uint64_t F = get(Opcode).TSFlags;
2576 }
2577 
2578 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2579  const uint64_t F = get(Opcode).TSFlags;
2581 }
2582 
2583 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2584  const uint64_t F = get(Opcode).TSFlags;
2585  assert(get(Opcode).isBranch() &&
2586  (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2588 }
2589 
2591  return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2592  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2593  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2594  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2595 }
2596 
2598  switch (MI.getOpcode()) {
2599  // Byte
2600  case Hexagon::L2_loadrb_io:
2601  case Hexagon::L4_loadrb_ur:
2602  case Hexagon::L4_loadrb_ap:
2603  case Hexagon::L2_loadrb_pr:
2604  case Hexagon::L2_loadrb_pbr:
2605  case Hexagon::L2_loadrb_pi:
2606  case Hexagon::L2_loadrb_pci:
2607  case Hexagon::L2_loadrb_pcr:
2608  case Hexagon::L2_loadbsw2_io:
2609  case Hexagon::L4_loadbsw2_ur:
2610  case Hexagon::L4_loadbsw2_ap:
2611  case Hexagon::L2_loadbsw2_pr:
2612  case Hexagon::L2_loadbsw2_pbr:
2613  case Hexagon::L2_loadbsw2_pi:
2614  case Hexagon::L2_loadbsw2_pci:
2615  case Hexagon::L2_loadbsw2_pcr:
2616  case Hexagon::L2_loadbsw4_io:
2617  case Hexagon::L4_loadbsw4_ur:
2618  case Hexagon::L4_loadbsw4_ap:
2619  case Hexagon::L2_loadbsw4_pr:
2620  case Hexagon::L2_loadbsw4_pbr:
2621  case Hexagon::L2_loadbsw4_pi:
2622  case Hexagon::L2_loadbsw4_pci:
2623  case Hexagon::L2_loadbsw4_pcr:
2624  case Hexagon::L4_loadrb_rr:
2625  case Hexagon::L2_ploadrbt_io:
2626  case Hexagon::L2_ploadrbt_pi:
2627  case Hexagon::L2_ploadrbf_io:
2628  case Hexagon::L2_ploadrbf_pi:
2629  case Hexagon::L2_ploadrbtnew_io:
2630  case Hexagon::L2_ploadrbfnew_io:
2631  case Hexagon::L4_ploadrbt_rr:
2632  case Hexagon::L4_ploadrbf_rr:
2633  case Hexagon::L4_ploadrbtnew_rr:
2634  case Hexagon::L4_ploadrbfnew_rr:
2635  case Hexagon::L2_ploadrbtnew_pi:
2636  case Hexagon::L2_ploadrbfnew_pi:
2637  case Hexagon::L4_ploadrbt_abs:
2638  case Hexagon::L4_ploadrbf_abs:
2639  case Hexagon::L4_ploadrbtnew_abs:
2640  case Hexagon::L4_ploadrbfnew_abs:
2641  case Hexagon::L2_loadrbgp:
2642  // Half
2643  case Hexagon::L2_loadrh_io:
2644  case Hexagon::L4_loadrh_ur:
2645  case Hexagon::L4_loadrh_ap:
2646  case Hexagon::L2_loadrh_pr:
2647  case Hexagon::L2_loadrh_pbr:
2648  case Hexagon::L2_loadrh_pi:
2649  case Hexagon::L2_loadrh_pci:
2650  case Hexagon::L2_loadrh_pcr:
2651  case Hexagon::L4_loadrh_rr:
2652  case Hexagon::L2_ploadrht_io:
2653  case Hexagon::L2_ploadrht_pi:
2654  case Hexagon::L2_ploadrhf_io:
2655  case Hexagon::L2_ploadrhf_pi:
2656  case Hexagon::L2_ploadrhtnew_io:
2657  case Hexagon::L2_ploadrhfnew_io:
2658  case Hexagon::L4_ploadrht_rr:
2659  case Hexagon::L4_ploadrhf_rr:
2660  case Hexagon::L4_ploadrhtnew_rr:
2661  case Hexagon::L4_ploadrhfnew_rr:
2662  case Hexagon::L2_ploadrhtnew_pi:
2663  case Hexagon::L2_ploadrhfnew_pi:
2664  case Hexagon::L4_ploadrht_abs:
2665  case Hexagon::L4_ploadrhf_abs:
2666  case Hexagon::L4_ploadrhtnew_abs:
2667  case Hexagon::L4_ploadrhfnew_abs:
2668  case Hexagon::L2_loadrhgp:
2669  return true;
2670  default:
2671  return false;
2672  }
2673 }
2674 
2676  const uint64_t F = MI.getDesc().TSFlags;
2678 }
2679 
2681  switch (MI.getOpcode()) {
2682  case Hexagon::STriw_pred:
2683  case Hexagon::LDriw_pred:
2684  return true;
2685  default:
2686  return false;
2687  }
2688 }
2689 
2691  if (!MI.isBranch())
2692  return false;
2693 
2694  for (auto &Op : MI.operands())
2695  if (Op.isGlobal() || Op.isSymbol())
2696  return true;
2697  return false;
2698 }
2699 
2700 // Returns true when SU has a timing class TC1.
2702  unsigned SchedClass = MI.getDesc().getSchedClass();
2703  return is_TC1(SchedClass);
2704 }
2705 
2707  unsigned SchedClass = MI.getDesc().getSchedClass();
2708  return is_TC2(SchedClass);
2709 }
2710 
2712  unsigned SchedClass = MI.getDesc().getSchedClass();
2713  return is_TC2early(SchedClass);
2714 }
2715 
2717  unsigned SchedClass = MI.getDesc().getSchedClass();
2718  return is_TC4x(SchedClass);
2719 }
2720 
2721 // Schedule this ASAP.
2723  const MachineInstr &MI2) const {
2724  if (mayBeCurLoad(MI1)) {
2725  // if (result of SU is used in Next) return true;
2726  Register DstReg = MI1.getOperand(0).getReg();
2727  int N = MI2.getNumOperands();
2728  for (int I = 0; I < N; I++)
2729  if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2730  return true;
2731  }
2732  if (mayBeNewStore(MI2))
2733  if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2734  if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2735  MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2736  return true;
2737  return false;
2738 }
2739 
2741  const uint64_t V = getType(MI);
2743 }
2744 
2745 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2746 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const {
2747  int Size = VT.getSizeInBits() / 8;
2748  if (Offset % Size != 0)
2749  return false;
2750  int Count = Offset / Size;
2751 
2752  switch (VT.getSimpleVT().SimpleTy) {
2753  // For scalars the auto-inc is s4
2754  case MVT::i8:
2755  case MVT::i16:
2756  case MVT::i32:
2757  case MVT::i64:
2758  case MVT::f32:
2759  case MVT::f64:
2760  case MVT::v2i16:
2761  case MVT::v2i32:
2762  case MVT::v4i8:
2763  case MVT::v4i16:
2764  case MVT::v8i8:
2765  return isInt<4>(Count);
2766  // For HVX vectors the auto-inc is s3
2767  case MVT::v64i8:
2768  case MVT::v32i16:
2769  case MVT::v16i32:
2770  case MVT::v8i64:
2771  case MVT::v128i8:
2772  case MVT::v64i16:
2773  case MVT::v32i32:
2774  case MVT::v16i64:
2775  return isInt<3>(Count);
2776  default:
2777  break;
2778  }
2779 
2780  llvm_unreachable("Not an valid type!");
2781 }
2782 
2783 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2784  const TargetRegisterInfo *TRI, bool Extend) const {
2785  // This function is to check whether the "Offset" is in the correct range of
2786  // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2787  // inserted to calculate the final address. Due to this reason, the function
2788  // assumes that the "Offset" has correct alignment.
2789  // We used to assert if the offset was not properly aligned, however,
2790  // there are cases where a misaligned pointer recast can cause this
2791  // problem, and we need to allow for it. The front end warns of such
2792  // misaligns with respect to load size.
2793  switch (Opcode) {
2794  case Hexagon::PS_vstorerq_ai:
2795  case Hexagon::PS_vstorerv_ai:
2796  case Hexagon::PS_vstorerw_ai:
2797  case Hexagon::PS_vstorerw_nt_ai:
2798  case Hexagon::PS_vloadrq_ai:
2799  case Hexagon::PS_vloadrv_ai:
2800  case Hexagon::PS_vloadrw_ai:
2801  case Hexagon::PS_vloadrw_nt_ai:
2802  case Hexagon::V6_vL32b_ai:
2803  case Hexagon::V6_vS32b_ai:
2804  case Hexagon::V6_vS32b_qpred_ai:
2805  case Hexagon::V6_vS32b_nqpred_ai:
2806  case Hexagon::V6_vL32b_nt_ai:
2807  case Hexagon::V6_vS32b_nt_ai:
2808  case Hexagon::V6_vL32Ub_ai:
2809  case Hexagon::V6_vS32Ub_ai:
2810  case Hexagon::V6_vgathermh_pseudo:
2811  case Hexagon::V6_vgathermw_pseudo:
2812  case Hexagon::V6_vgathermhw_pseudo:
2813  case Hexagon::V6_vgathermhq_pseudo:
2814  case Hexagon::V6_vgathermwq_pseudo:
2815  case Hexagon::V6_vgathermhwq_pseudo: {
2816  unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2817  assert(isPowerOf2_32(VectorSize));
2818  if (Offset & (VectorSize-1))
2819  return false;
2820  return isInt<4>(Offset >> Log2_32(VectorSize));
2821  }
2822 
2823  case Hexagon::J2_loop0i:
2824  case Hexagon::J2_loop1i:
2825  return isUInt<10>(Offset);
2826 
2827  case Hexagon::S4_storeirb_io:
2828  case Hexagon::S4_storeirbt_io:
2829  case Hexagon::S4_storeirbf_io:
2830  return isUInt<6>(Offset);
2831 
2832  case Hexagon::S4_storeirh_io:
2833  case Hexagon::S4_storeirht_io:
2834  case Hexagon::S4_storeirhf_io:
2835  return isShiftedUInt<6,1>(Offset);
2836 
2837  case Hexagon::S4_storeiri_io:
2838  case Hexagon::S4_storeirit_io:
2839  case Hexagon::S4_storeirif_io:
2840  return isShiftedUInt<6,2>(Offset);
2841  // Handle these two compare instructions that are not extendable.
2842  case Hexagon::A4_cmpbeqi:
2843  return isUInt<8>(Offset);
2844  case Hexagon::A4_cmpbgti:
2845  return isInt<8>(Offset);
2846  }
2847 
2848  if (Extend)
2849  return true;
2850 
2851  switch (Opcode) {
2852  case Hexagon::L2_loadri_io:
2853  case Hexagon::S2_storeri_io:
2854  return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2855  (Offset <= Hexagon_MEMW_OFFSET_MAX);
2856 
2857  case Hexagon::L2_loadrd_io:
2858  case Hexagon::S2_storerd_io:
2859  return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2860  (Offset <= Hexagon_MEMD_OFFSET_MAX);
2861 
2862  case Hexagon::L2_loadrh_io:
2863  case Hexagon::L2_loadruh_io:
2864  case Hexagon::S2_storerh_io:
2865  case Hexagon::S2_storerf_io:
2866  return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2867  (Offset <= Hexagon_MEMH_OFFSET_MAX);
2868 
2869  case Hexagon::L2_loadrb_io:
2870  case Hexagon::L2_loadrub_io:
2871  case Hexagon::S2_storerb_io:
2872  return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2873  (Offset <= Hexagon_MEMB_OFFSET_MAX);
2874 
2875  case Hexagon::A2_addi:
2876  return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2877  (Offset <= Hexagon_ADDI_OFFSET_MAX);
2878 
2879  case Hexagon::L4_iadd_memopw_io:
2880  case Hexagon::L4_isub_memopw_io:
2881  case Hexagon::L4_add_memopw_io:
2882  case Hexagon::L4_sub_memopw_io:
2883  case Hexagon::L4_iand_memopw_io:
2884  case Hexagon::L4_ior_memopw_io:
2885  case Hexagon::L4_and_memopw_io:
2886  case Hexagon::L4_or_memopw_io:
2887  return (0 <= Offset && Offset <= 255);
2888 
2889  case Hexagon::L4_iadd_memoph_io:
2890  case Hexagon::L4_isub_memoph_io:
2891  case Hexagon::L4_add_memoph_io:
2892  case Hexagon::L4_sub_memoph_io:
2893  case Hexagon::L4_iand_memoph_io:
2894  case Hexagon::L4_ior_memoph_io:
2895  case Hexagon::L4_and_memoph_io:
2896  case Hexagon::L4_or_memoph_io:
2897  return (0 <= Offset && Offset <= 127);
2898 
2899  case Hexagon::L4_iadd_memopb_io:
2900  case Hexagon::L4_isub_memopb_io:
2901  case Hexagon::L4_add_memopb_io:
2902  case Hexagon::L4_sub_memopb_io:
2903  case Hexagon::L4_iand_memopb_io:
2904  case Hexagon::L4_ior_memopb_io:
2905  case Hexagon::L4_and_memopb_io:
2906  case Hexagon::L4_or_memopb_io:
2907  return (0 <= Offset && Offset <= 63);
2908 
2909  // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2910  // any size. Later pass knows how to handle it.
2911  case Hexagon::STriw_pred:
2912  case Hexagon::LDriw_pred:
2913  case Hexagon::STriw_ctr:
2914  case Hexagon::LDriw_ctr:
2915  return true;
2916 
2917  case Hexagon::PS_fi:
2918  case Hexagon::PS_fia:
2919  case Hexagon::INLINEASM:
2920  return true;
2921 
2922  case Hexagon::L2_ploadrbt_io:
2923  case Hexagon::L2_ploadrbf_io:
2924  case Hexagon::L2_ploadrubt_io:
2925  case Hexagon::L2_ploadrubf_io:
2926  case Hexagon::S2_pstorerbt_io:
2927  case Hexagon::S2_pstorerbf_io:
2928  return isUInt<6>(Offset);
2929 
2930  case Hexagon::L2_ploadrht_io:
2931  case Hexagon::L2_ploadrhf_io:
2932  case Hexagon::L2_ploadruht_io:
2933  case Hexagon::L2_ploadruhf_io:
2934  case Hexagon::S2_pstorerht_io:
2935  case Hexagon::S2_pstorerhf_io:
2936  return isShiftedUInt<6,1>(Offset);
2937 
2938  case Hexagon::L2_ploadrit_io:
2939  case Hexagon::L2_ploadrif_io:
2940  case Hexagon::S2_pstorerit_io:
2941  case Hexagon::S2_pstorerif_io:
2942  return isShiftedUInt<6,2>(Offset);
2943 
2944  case Hexagon::L2_ploadrdt_io:
2945  case Hexagon::L2_ploadrdf_io:
2946  case Hexagon::S2_pstorerdt_io:
2947  case Hexagon::S2_pstorerdf_io:
2948  return isShiftedUInt<6,3>(Offset);
2949 
2950  case Hexagon::L2_loadbsw2_io:
2951  case Hexagon::L2_loadbzw2_io:
2952  return isShiftedInt<11,1>(Offset);
2953 
2954  case Hexagon::L2_loadbsw4_io:
2955  case Hexagon::L2_loadbzw4_io:
2956  return isShiftedInt<11,2>(Offset);
2957  } // switch
2958 
2959  dbgs() << "Failed Opcode is : " << Opcode << " (" << getName(Opcode)
2960  << ")\n";
2961  llvm_unreachable("No offset range is defined for this opcode. "
2962  "Please define it in the above switch statement!");
2963 }
2964 
2966  return isHVXVec(MI) && isAccumulator(MI);
2967 }
2968 
2970  const uint64_t F = get(MI.getOpcode()).TSFlags;
2971  const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2972  return
2973  V == HexagonII::TypeCVI_VA ||
2975 }
2976 
2978  const MachineInstr &ConsMI) const {
2979  if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2980  return true;
2981 
2982  if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2983  return true;
2984 
2985  if (mayBeNewStore(ConsMI))
2986  return true;
2987 
2988  return false;
2989 }
2990 
2992  switch (MI.getOpcode()) {
2993  // Byte
2994  case Hexagon::L2_loadrub_io:
2995  case Hexagon::L4_loadrub_ur:
2996  case Hexagon::L4_loadrub_ap:
2997  case Hexagon::L2_loadrub_pr:
2998  case Hexagon::L2_loadrub_pbr:
2999  case Hexagon::L2_loadrub_pi:
3000  case Hexagon::L2_loadrub_pci:
3001  case Hexagon::L2_loadrub_pcr:
3002  case Hexagon::L2_loadbzw2_io:
3003  case Hexagon::L4_loadbzw2_ur:
3004  case Hexagon::L4_loadbzw2_ap:
3005  case Hexagon::L2_loadbzw2_pr:
3006  case Hexagon::L2_loadbzw2_pbr:
3007  case Hexagon::L2_loadbzw2_pi:
3008  case Hexagon::L2_loadbzw2_pci:
3009  case Hexagon::L2_loadbzw2_pcr:
3010  case Hexagon::L2_loadbzw4_io:
3011  case Hexagon::L4_loadbzw4_ur:
3012  case Hexagon::L4_loadbzw4_ap:
3013  case Hexagon::L2_loadbzw4_pr:
3014  case Hexagon::L2_loadbzw4_pbr:
3015  case Hexagon::L2_loadbzw4_pi:
3016  case Hexagon::L2_loadbzw4_pci:
3017  case Hexagon::L2_loadbzw4_pcr:
3018  case Hexagon::L4_loadrub_rr:
3019  case Hexagon::L2_ploadrubt_io:
3020  case Hexagon::L2_ploadrubt_pi:
3021  case Hexagon::L2_ploadrubf_io:
3022  case Hexagon::L2_ploadrubf_pi:
3023  case Hexagon::L2_ploadrubtnew_io:
3024  case Hexagon::L2_ploadrubfnew_io:
3025  case Hexagon::L4_ploadrubt_rr:
3026  case Hexagon::L4_ploadrubf_rr:
3027  case Hexagon::L4_ploadrubtnew_rr:
3028  case Hexagon::L4_ploadrubfnew_rr:
3029  case Hexagon::L2_ploadrubtnew_pi:
3030  case Hexagon::L2_ploadrubfnew_pi:
3031  case Hexagon::L4_ploadrubt_abs:
3032  case Hexagon::L4_ploadrubf_abs:
3033  case Hexagon::L4_ploadrubtnew_abs:
3034  case Hexagon::L4_ploadrubfnew_abs:
3035  case Hexagon::L2_loadrubgp:
3036  // Half
3037  case Hexagon::L2_loadruh_io:
3038  case Hexagon::L4_loadruh_ur:
3039  case Hexagon::L4_loadruh_ap:
3040  case Hexagon::L2_loadruh_pr:
3041  case Hexagon::L2_loadruh_pbr:
3042  case Hexagon::L2_loadruh_pi:
3043  case Hexagon::L2_loadruh_pci:
3044  case Hexagon::L2_loadruh_pcr:
3045  case Hexagon::L4_loadruh_rr:
3046  case Hexagon::L2_ploadruht_io:
3047  case Hexagon::L2_ploadruht_pi:
3048  case Hexagon::L2_ploadruhf_io:
3049  case Hexagon::L2_ploadruhf_pi:
3050  case Hexagon::L2_ploadruhtnew_io:
3051  case Hexagon::L2_ploadruhfnew_io:
3052  case Hexagon::L4_ploadruht_rr:
3053  case Hexagon::L4_ploadruhf_rr:
3054  case Hexagon::L4_ploadruhtnew_rr:
3055  case Hexagon::L4_ploadruhfnew_rr:
3056  case Hexagon::L2_ploadruhtnew_pi:
3057  case Hexagon::L2_ploadruhfnew_pi:
3058  case Hexagon::L4_ploadruht_abs:
3059  case Hexagon::L4_ploadruhf_abs:
3060  case Hexagon::L4_ploadruhtnew_abs:
3061  case Hexagon::L4_ploadruhfnew_abs:
3062  case Hexagon::L2_loadruhgp:
3063  return true;
3064  default:
3065  return false;
3066  }
3067 }
3068 
3069 // Add latency to instruction.
3071  const MachineInstr &MI2) const {
3072  if (isHVXVec(MI1) && isHVXVec(MI2))
3073  if (!isVecUsableNextPacket(MI1, MI2))
3074  return true;
3075  return false;
3076 }
3077 
3078 /// Get the base register and byte offset of a load/store instr.
3081  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
3082  const TargetRegisterInfo *TRI) const {
3083  OffsetIsScalable = false;
3084  const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width);
3085  if (!BaseOp || !BaseOp->isReg())
3086  return false;
3087  BaseOps.push_back(BaseOp);
3088  return true;
3089 }
3090 
3091 /// Can these instructions execute at the same time in a bundle.
3093  const MachineInstr &Second) const {
3094  if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
3095  const MachineOperand &Op = Second.getOperand(0);
3096  if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
3097  return true;
3098  }
3099  if (DisableNVSchedule)
3100  return false;
3101  if (mayBeNewStore(Second)) {
3102  // Make sure the definition of the first instruction is the value being
3103  // stored.
3104  const MachineOperand &Stored =
3105  Second.getOperand(Second.getNumOperands() - 1);
3106  if (!Stored.isReg())
3107  return false;
3108  for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
3109  const MachineOperand &Op = First.getOperand(i);
3110  if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3111  return true;
3112  }
3113  }
3114  return false;
3115 }
3116 
3118  unsigned Opc = CallMI.getOpcode();
3119  return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
3120 }
3121 
3123  for (auto &I : *B)
3124  if (I.isEHLabel())
3125  return true;
3126  return false;
3127 }
3128 
3129 // Returns true if an instruction can be converted into a non-extended
3130 // equivalent instruction.
3132  short NonExtOpcode;
3133  // Check if the instruction has a register form that uses register in place
3134  // of the extended operand, if so return that as the non-extended form.
3135  if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
3136  return true;
3137 
3138  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
3139  // Check addressing mode and retrieve non-ext equivalent instruction.
3140 
3141  switch (getAddrMode(MI)) {
3142  case HexagonII::Absolute:
3143  // Load/store with absolute addressing mode can be converted into
3144  // base+offset mode.
3145  NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
3146  break;
3148  // Load/store with base+offset addressing mode can be converted into
3149  // base+register offset addressing mode. However left shift operand should
3150  // be set to 0.
3151  NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
3152  break;
3154  NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
3155  break;
3156  default:
3157  return false;
3158  }
3159  if (NonExtOpcode < 0)
3160  return false;
3161  return true;
3162  }
3163  return false;
3164 }
3165 
3167  return Hexagon::getRealHWInstr(MI.getOpcode(),
3168  Hexagon::InstrType_Pseudo) >= 0;
3169 }
3170 
3172  const {
3173  MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
3174  while (I != E) {
3175  if (I->isBarrier())
3176  return true;
3177  ++I;
3178  }
3179  return false;
3180 }
3181 
3182 // Returns true, if a LD insn can be promoted to a cur load.
3184  const uint64_t F = MI.getDesc().TSFlags;
3186  Subtarget.hasV60Ops();
3187 }
3188 
3189 // Returns true, if a ST insn can be promoted to a new-value store.
3191  if (MI.mayStore() && !Subtarget.useNewValueStores())
3192  return false;
3193 
3194  const uint64_t F = MI.getDesc().TSFlags;
3196 }
3197 
3199  const MachineInstr &ConsMI) const {
3200  // There is no stall when ProdMI is not a V60 vector.
3201  if (!isHVXVec(ProdMI))
3202  return false;
3203 
3204  // There is no stall when ProdMI and ConsMI are not dependent.
3205  if (!isDependent(ProdMI, ConsMI))
3206  return false;
3207 
3208  // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3209  // are scheduled in consecutive packets.
3210  if (isVecUsableNextPacket(ProdMI, ConsMI))
3211  return false;
3212 
3213  return true;
3214 }
3215 
3218  // There is no stall when I is not a V60 vector.
3219  if (!isHVXVec(MI))
3220  return false;
3221 
3223  MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3224 
3225  if (!MII->isBundle())
3226  return producesStall(*MII, MI);
3227 
3228  for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3229  const MachineInstr &J = *MII;
3230  if (producesStall(J, MI))
3231  return true;
3232  }
3233  return false;
3234 }
3235 
3237  unsigned PredReg) const {
3238  for (const MachineOperand &MO : MI.operands()) {
3239  // Predicate register must be explicitly defined.
3240  if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3241  return false;
3242  if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3243  return false;
3244  }
3245 
3246  // Instruction that produce late predicate cannot be used as sources of
3247  // dot-new.
3248  switch (MI.getOpcode()) {
3249  case Hexagon::A4_addp_c:
3250  case Hexagon::A4_subp_c:
3251  case Hexagon::A4_tlbmatch:
3252  case Hexagon::A5_ACS:
3253  case Hexagon::F2_sfinvsqrta:
3254  case Hexagon::F2_sfrecipa:
3255  case Hexagon::J2_endloop0:
3256  case Hexagon::J2_endloop01:
3257  case Hexagon::J2_ploop1si:
3258  case Hexagon::J2_ploop1sr:
3259  case Hexagon::J2_ploop2si:
3260  case Hexagon::J2_ploop2sr:
3261  case Hexagon::J2_ploop3si:
3262  case Hexagon::J2_ploop3sr:
3263  case Hexagon::S2_cabacdecbin:
3264  case Hexagon::S2_storew_locked:
3265  case Hexagon::S4_stored_locked:
3266  return false;
3267  }
3268  return true;
3269 }
3270 
3271 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3272  return Opcode == Hexagon::J2_jumpt ||
3273  Opcode == Hexagon::J2_jumptpt ||
3274  Opcode == Hexagon::J2_jumpf ||
3275  Opcode == Hexagon::J2_jumpfpt ||
3276  Opcode == Hexagon::J2_jumptnew ||
3277  Opcode == Hexagon::J2_jumpfnew ||
3278  Opcode == Hexagon::J2_jumptnewpt ||
3279  Opcode == Hexagon::J2_jumpfnewpt;
3280 }
3281 
3283  if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3284  return false;
3285  return !isPredicatedTrue(Cond[0].getImm());
3286 }
3287 
3289  const uint64_t F = MI.getDesc().TSFlags;
3291 }
3292 
3293 // Returns the base register in a memory access (load/store). The offset is
3294 // returned in Offset and the access size is returned in AccessSize.
3295 // If the base operand has a subregister or the offset field does not contain
3296 // an immediate value, return nullptr.
3298  int64_t &Offset,
3299  unsigned &AccessSize) const {
3300  // Return if it is not a base+offset type instruction or a MemOp.
3303  !isMemOp(MI) && !isPostIncrement(MI))
3304  return nullptr;
3305 
3306  AccessSize = getMemAccessSize(MI);
3307 
3308  unsigned BasePos = 0, OffsetPos = 0;
3309  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3310  return nullptr;
3311 
3312  // Post increment updates its EA after the mem access,
3313  // so we need to treat its offset as zero.
3314  if (isPostIncrement(MI)) {
3315  Offset = 0;
3316  } else {
3317  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3318  if (!OffsetOp.isImm())
3319  return nullptr;
3320  Offset = OffsetOp.getImm();
3321  }
3322 
3323  const MachineOperand &BaseOp = MI.getOperand(BasePos);
3324  if (BaseOp.getSubReg() != 0)
3325  return nullptr;
3326  return &const_cast<MachineOperand&>(BaseOp);
3327 }
3328 
3329 /// Return the position of the base and offset operands for this instruction.
3331  unsigned &BasePos, unsigned &OffsetPos) const {
3333  return false;
3334 
3335  // Deal with memops first.
3336  if (isMemOp(MI)) {
3337  BasePos = 0;
3338  OffsetPos = 1;
3339  } else if (MI.mayStore()) {
3340  BasePos = 0;
3341  OffsetPos = 1;
3342  } else if (MI.mayLoad()) {
3343  BasePos = 1;
3344  OffsetPos = 2;
3345  } else
3346  return false;
3347 
3348  if (isPredicated(MI)) {
3349  BasePos++;
3350  OffsetPos++;
3351  }
3352  if (isPostIncrement(MI)) {
3353  BasePos++;
3354  OffsetPos++;
3355  }
3356 
3357  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3358  return false;
3359 
3360  return true;
3361 }
3362 
3363 // Inserts branching instructions in reverse order of their occurrence.
3364 // e.g. jump_t t1 (i1)
3365 // jump t2 (i2)
3366 // Jumpers = {i2, i1}
3368  MachineBasicBlock& MBB) const {
3370  // If the block has no terminators, it just falls into the block after it.
3372  if (I == MBB.instr_begin())
3373  return Jumpers;
3374 
3375  // A basic block may looks like this:
3376  //
3377  // [ insn
3378  // EH_LABEL
3379  // insn
3380  // insn
3381  // insn
3382  // EH_LABEL
3383  // insn ]
3384  //
3385  // It has two succs but does not have a terminator
3386  // Don't know how to handle it.
3387  do {
3388  --I;
3389  if (I->isEHLabel())
3390  return Jumpers;
3391  } while (I != MBB.instr_begin());
3392 
3393  I = MBB.instr_end();
3394  --I;
3395 
3396  while (I->isDebugInstr()) {
3397  if (I == MBB.instr_begin())
3398  return Jumpers;
3399  --I;
3400  }
3401  if (!isUnpredicatedTerminator(*I))
3402  return Jumpers;
3403 
3404  // Get the last instruction in the block.
3405  MachineInstr *LastInst = &*I;
3406  Jumpers.push_back(LastInst);
3407  MachineInstr *SecondLastInst = nullptr;
3408  // Find one more terminator if present.
3409  do {
3410  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3411  if (!SecondLastInst) {
3412  SecondLastInst = &*I;
3413  Jumpers.push_back(SecondLastInst);
3414  } else // This is a third branch.
3415  return Jumpers;
3416  }
3417  if (I == MBB.instr_begin())
3418  break;
3419  --I;
3420  } while (true);
3421  return Jumpers;
3422 }
3423 
3424 // Returns Operand Index for the constant extended instruction.
3426  const uint64_t F = MI.getDesc().TSFlags;
3428 }
3429 
3430 // See if instruction could potentially be a duplex candidate.
3431 // If so, return its group. Zero otherwise.
3433  const MachineInstr &MI) const {
3434  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3435 
3436  switch (MI.getOpcode()) {
3437  default:
3438  return HexagonII::HCG_None;
3439  //
3440  // Compound pairs.
3441  // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3442  // "Rd16=#U6 ; jump #r9:2"
3443  // "Rd16=Rs16 ; jump #r9:2"
3444  //
3445  case Hexagon::C2_cmpeq:
3446  case Hexagon::C2_cmpgt:
3447  case Hexagon::C2_cmpgtu:
3448  DstReg = MI.getOperand(0).getReg();
3449  Src1Reg = MI.getOperand(1).getReg();
3450  Src2Reg = MI.getOperand(2).getReg();
3451  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3452  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3453  isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3454  return HexagonII::HCG_A;
3455  break;
3456  case Hexagon::C2_cmpeqi:
3457  case Hexagon::C2_cmpgti:
3458  case Hexagon::C2_cmpgtui:
3459  // P0 = cmp.eq(Rs,#u2)
3460  DstReg = MI.getOperand(0).getReg();
3461  SrcReg = MI.getOperand(1).getReg();
3462  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3463  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3464  isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3465  ((isUInt<5>(MI.getOperand(2).getImm())) ||
3466  (MI.getOperand(2).getImm() == -1)))
3467  return HexagonII::HCG_A;
3468  break;
3469  case Hexagon::A2_tfr:
3470  // Rd = Rs
3471  DstReg = MI.getOperand(0).getReg();
3472  SrcReg = MI.getOperand(1).getReg();
3473  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3474  return HexagonII::HCG_A;
3475  break;
3476  case Hexagon::A2_tfrsi:
3477  // Rd = #u6
3478  // Do not test for #u6 size since the const is getting extended
3479  // regardless and compound could be formed.
3480  DstReg = MI.getOperand(0).getReg();
3481  if (isIntRegForSubInst(DstReg))
3482  return HexagonII::HCG_A;
3483  break;
3484  case Hexagon::S2_tstbit_i:
3485  DstReg = MI.getOperand(0).getReg();
3486  Src1Reg = MI.getOperand(1).getReg();
3487  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3488  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3489  MI.getOperand(2).isImm() &&
3490  isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3491  return HexagonII::HCG_A;
3492  break;
3493  // The fact that .new form is used pretty much guarantees
3494  // that predicate register will match. Nevertheless,
3495  // there could be some false positives without additional
3496  // checking.
3497  case Hexagon::J2_jumptnew:
3498  case Hexagon::J2_jumpfnew:
3499  case Hexagon::J2_jumptnewpt:
3500  case Hexagon::J2_jumpfnewpt:
3501  Src1Reg = MI.getOperand(0).getReg();
3502  if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3503  (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3504  return HexagonII::HCG_B;
3505  break;
3506  // Transfer and jump:
3507  // Rd=#U6 ; jump #r9:2
3508  // Rd=Rs ; jump #r9:2
3509  // Do not test for jump range here.
3510  case Hexagon::J2_jump:
3511  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3512  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3513  return HexagonII::HCG_C;
3514  }
3515 
3516  return HexagonII::HCG_None;
3517 }
3518 
3519 // Returns -1 when there is no opcode found.
3521  const MachineInstr &GB) const {
3524  if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3525  (GB.getOpcode() != Hexagon::J2_jumptnew))
3526  return -1u;
3527  Register DestReg = GA.getOperand(0).getReg();
3528  if (!GB.readsRegister(DestReg))
3529  return -1u;
3530  if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3531  return -1u;
3532  // The value compared against must be either u5 or -1.
3533  const MachineOperand &CmpOp = GA.getOperand(2);
3534  if (!CmpOp.isImm())
3535  return -1u;
3536  int V = CmpOp.getImm();
3537  if (V == -1)
3538  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3539  : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3540  if (!isUInt<5>(V))
3541  return -1u;
3542  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3543  : Hexagon::J4_cmpeqi_tp1_jump_nt;
3544 }
3545 
3546 // Returns -1 if there is no opcode found.
3548  bool ForBigCore) const {
3549  // Static table to switch the opcodes across Tiny Core and Big Core.
3550  // dup_ opcodes are Big core opcodes.
3551  // NOTE: There are special instructions that need to handled later.
3552  // L4_return* instructions, they will only occupy SLOT0 (on big core too).
3553  // PS_jmpret - This pseudo translates to J2_jumpr which occupies only SLOT2.
3554  // The compiler need to base the root instruction to L6_return_map_to_raw
3555  // which can go any slot.
3556  static const std::map<unsigned, unsigned> DupMap = {
3557  {Hexagon::A2_add, Hexagon::dup_A2_add},
3558  {Hexagon::A2_addi, Hexagon::dup_A2_addi},
3559  {Hexagon::A2_andir, Hexagon::dup_A2_andir},
3560  {Hexagon::A2_combineii, Hexagon::dup_A2_combineii},
3561  {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb},
3562  {Hexagon::A2_sxth, Hexagon::dup_A2_sxth},
3563  {Hexagon::A2_tfr, Hexagon::dup_A2_tfr},
3564  {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi},
3565  {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb},
3566  {Hexagon::A2_zxth, Hexagon::dup_A2_zxth},
3567  {Hexagon::A4_combineii, Hexagon::dup_A4_combineii},
3568  {Hexagon::A4_combineir, Hexagon::dup_A4_combineir},
3569  {Hexagon::A4_combineri, Hexagon::dup_A4_combineri},
3570  {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif},
3571  {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit},
3572  {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif},
3573  {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit},
3574  {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi},
3575  {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe},
3576  {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io},
3577  {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io},
3578  {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io},
3579  {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io},
3580  {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io},
3581  {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io},
3582  {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe},
3583  {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io},
3584  {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io},
3585  {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io},
3586  {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io},
3587  {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io},
3588  {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io},
3589  };
3590  unsigned OpNum = MI.getOpcode();
3591  // Conversion to Big core.
3592  if (ForBigCore) {
3593  auto Iter = DupMap.find(OpNum);
3594  if (Iter != DupMap.end())
3595  return Iter->second;
3596  } else { // Conversion to Tiny core.
3597  for (const auto &Iter : DupMap)
3598  if (Iter.second == OpNum)
3599  return Iter.first;
3600  }
3601  return -1;
3602 }
3603 
3604 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3605  enum Hexagon::PredSense inPredSense;
3606  inPredSense = invertPredicate ? Hexagon::PredSense_false :
3607  Hexagon::PredSense_true;
3608  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3609  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3610  return CondOpcode;
3611 
3612  llvm_unreachable("Unexpected predicable instruction");
3613 }
3614 
3615 // Return the cur value instruction for a given store.
3617  switch (MI.getOpcode()) {
3618  default: llvm_unreachable("Unknown .cur type");
3619  case Hexagon::V6_vL32b_pi:
3620  return Hexagon::V6_vL32b_cur_pi;
3621  case Hexagon::V6_vL32b_ai:
3622  return Hexagon::V6_vL32b_cur_ai;
3623  case Hexagon::V6_vL32b_nt_pi:
3624  return Hexagon::V6_vL32b_nt_cur_pi;
3625  case Hexagon::V6_vL32b_nt_ai:
3626  return Hexagon::V6_vL32b_nt_cur_ai;
3627  case Hexagon::V6_vL32b_ppu:
3628  return Hexagon::V6_vL32b_cur_ppu;
3629  case Hexagon::V6_vL32b_nt_ppu:
3630  return Hexagon::V6_vL32b_nt_cur_ppu;
3631  }
3632  return 0;
3633 }
3634 
3635 // Return the regular version of the .cur instruction.
3637  switch (MI.getOpcode()) {
3638  default: llvm_unreachable("Unknown .cur type");
3639  case Hexagon::V6_vL32b_cur_pi:
3640  return Hexagon::V6_vL32b_pi;
3641  case Hexagon::V6_vL32b_cur_ai:
3642  return Hexagon::V6_vL32b_ai;
3643  case Hexagon::V6_vL32b_nt_cur_pi:
3644  return Hexagon::V6_vL32b_nt_pi;
3645  case Hexagon::V6_vL32b_nt_cur_ai:
3646  return Hexagon::V6_vL32b_nt_ai;
3647  case Hexagon::V6_vL32b_cur_ppu:
3648  return Hexagon::V6_vL32b_ppu;
3649  case Hexagon::V6_vL32b_nt_cur_ppu:
3650  return Hexagon::V6_vL32b_nt_ppu;
3651  }
3652  return 0;
3653 }
3654 
3655 // The diagram below shows the steps involved in the conversion of a predicated
3656 // store instruction to its .new predicated new-value form.
3657 //
3658 // Note: It doesn't include conditional new-value stores as they can't be
3659 // converted to .new predicate.
3660 //
3661 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3662 // ^ ^
3663 // / \ (not OK. it will cause new-value store to be
3664 // / X conditional on p0.new while R2 producer is
3665 // / \ on p0)
3666 // / \.
3667 // p.new store p.old NV store
3668 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3669 // ^ ^
3670 // \ /
3671 // \ /
3672 // \ /
3673 // p.old store
3674 // [if (p0)memw(R0+#0)=R2]
3675 //
3676 // The following set of instructions further explains the scenario where
3677 // conditional new-value store becomes invalid when promoted to .new predicate
3678 // form.
3679 //
3680 // { 1) if (p0) r0 = add(r1, r2)
3681 // 2) p0 = cmp.eq(r3, #0) }
3682 //
3683 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3684 // the first two instructions because in instr 1, r0 is conditional on old value
3685 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3686 // is not valid for new-value stores.
3687 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3688 // from the "Conditional Store" list. Because a predicated new value store
3689 // would NOT be promoted to a double dot new store. See diagram below:
3690 // This function returns yes for those stores that are predicated but not
3691 // yet promoted to predicate dot new instructions.
3692 //
3693 // +---------------------+
3694 // /-----| if (p0) memw(..)=r0 |---------\~
3695 // || +---------------------+ ||
3696 // promote || /\ /\ || promote
3697 // || /||\ /||\ ||
3698 // \||/ demote || \||/
3699 // \/ || || \/
3700 // +-------------------------+ || +-------------------------+
3701 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3702 // +-------------------------+ || +-------------------------+
3703 // || || ||
3704 // || demote \||/
3705 // promote || \/ NOT possible
3706 // || || /\~
3707 // \||/ || /||\~
3708 // \/ || ||
3709 // +-----------------------------+
3710 // | if (p0.new) memw(..)=r0.new |
3711 // +-----------------------------+
3712 // Double Dot New Store
3713 //
3714 // Returns the most basic instruction for the .new predicated instructions and
3715 // new-value stores.
3716 // For example, all of the following instructions will be converted back to the
3717 // same instruction:
3718 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3719 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3720 // 3) if (p0.new) memw(R0+#0) = R1 --->
3721 //
3722 // To understand the translation of instruction 1 to its original form, consider
3723 // a packet with 3 instructions.
3724 // { p0 = cmp.eq(R0,R1)
3725 // if (p0.new) R2 = add(R3, R4)
3726 // R5 = add (R3, R1)
3727 // }
3728 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3729 //
3730 // This instruction can be part of the previous packet only if both p0 and R2
3731 // are promoted to .new values. This promotion happens in steps, first
3732 // predicate register is promoted to .new and in the next iteration R2 is
3733 // promoted. Therefore, in case of dependence check failure (due to R5) during
3734 // next iteration, it should be converted back to its most basic form.
3735 
3736 // Return the new value instruction for a given store.
3738  int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3739  if (NVOpcode >= 0) // Valid new-value store instruction.
3740  return NVOpcode;
3741 
3742  switch (MI.getOpcode()) {
3743  default:
3744  report_fatal_error(Twine("Unknown .new type: ") +
3745  std::to_string(MI.getOpcode()));
3746  case Hexagon::S4_storerb_ur:
3747  return Hexagon::S4_storerbnew_ur;
3748 
3749  case Hexagon::S2_storerb_pci:
3750  return Hexagon::S2_storerb_pci;
3751 
3752  case Hexagon::S2_storeri_pci:
3753  return Hexagon::S2_storeri_pci;
3754 
3755  case Hexagon::S2_storerh_pci:
3756  return Hexagon::S2_storerh_pci;
3757 
3758  case Hexagon::S2_storerd_pci:
3759  return Hexagon::S2_storerd_pci;
3760 
3761  case Hexagon::S2_storerf_pci:
3762  return Hexagon::S2_storerf_pci;
3763 
3764  case Hexagon::V6_vS32b_ai:
3765  return Hexagon::V6_vS32b_new_ai;
3766 
3767  case Hexagon::V6_vS32b_pi:
3768  return Hexagon::V6_vS32b_new_pi;
3769  }
3770  return 0;
3771 }
3772 
3773 // Returns the opcode to use when converting MI, which is a conditional jump,
3774 // into a conditional instruction which uses the .new value of the predicate.
3775 // We also use branch probabilities to add a hint to the jump.
3776 // If MBPI is null, all edges will be treated as equally likely for the
3777 // purposes of establishing a predication hint.
3779  const MachineBranchProbabilityInfo *MBPI) const {
3780  // We assume that block can have at most two successors.
3781  const MachineBasicBlock *Src = MI.getParent();
3782  const MachineOperand &BrTarget = MI.getOperand(1);
3783  bool Taken = false;
3784  const BranchProbability OneHalf(1, 2);
3785 
3786  auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3787  const MachineBasicBlock *Dst) {
3788  if (MBPI)
3789  return MBPI->getEdgeProbability(Src, Dst);
3790  return BranchProbability(1, Src->succ_size());
3791  };
3792 
3793  if (BrTarget.isMBB()) {
3794  const MachineBasicBlock *Dst = BrTarget.getMBB();
3795  Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3796  } else {
3797  // The branch target is not a basic block (most likely a function).
3798  // Since BPI only gives probabilities for targets that are basic blocks,
3799  // try to identify another target of this branch (potentially a fall-
3800  // -through) and check the probability of that target.
3801  //
3802  // The only handled branch combinations are:
3803  // - one conditional branch,
3804  // - one conditional branch followed by one unconditional branch.
3805  // Otherwise, assume not-taken.
3806  assert(MI.isConditionalBranch());
3807  const MachineBasicBlock &B = *MI.getParent();
3808  bool SawCond = false, Bad = false;
3809  for (const MachineInstr &I : B) {
3810  if (!I.isBranch())
3811  continue;
3812  if (I.isConditionalBranch()) {
3813  SawCond = true;
3814  if (&I != &MI) {
3815  Bad = true;
3816  break;
3817  }
3818  }
3819  if (I.isUnconditionalBranch() && !SawCond) {
3820  Bad = true;
3821  break;
3822  }
3823  }
3824  if (!Bad) {
3826  MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3827  if (NextIt == B.instr_end()) {
3828  // If this branch is the last, look for the fall-through block.
3829  for (const MachineBasicBlock *SB : B.successors()) {
3830  if (!B.isLayoutSuccessor(SB))
3831  continue;
3832  Taken = getEdgeProbability(Src, SB) < OneHalf;
3833  break;
3834  }
3835  } else {
3836  assert(NextIt->isUnconditionalBranch());
3837  // Find the first MBB operand and assume it's the target.
3838  const MachineBasicBlock *BT = nullptr;
3839  for (const MachineOperand &Op : NextIt->operands()) {
3840  if (!Op.isMBB())
3841  continue;
3842  BT = Op.getMBB();
3843  break;
3844  }
3845  Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3846  }
3847  } // if (!Bad)
3848  }
3849 
3850  // The Taken flag should be set to something reasonable by this point.
3851 
3852  switch (MI.getOpcode()) {
3853  case Hexagon::J2_jumpt:
3854  return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3855  case Hexagon::J2_jumpf:
3856  return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3857 
3858  default:
3859  llvm_unreachable("Unexpected jump instruction.");
3860  }
3861 }
3862 
3863 // Return .new predicate version for an instruction.
3865  const MachineBranchProbabilityInfo *MBPI) const {
3866  switch (MI.getOpcode()) {
3867  // Condtional Jumps
3868  case Hexagon::J2_jumpt:
3869  case Hexagon::J2_jumpf:
3870  return getDotNewPredJumpOp(MI, MBPI);
3871  }
3872 
3873  int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3874  if (NewOpcode >= 0)
3875  return NewOpcode;
3876  return 0;
3877 }
3878 
3880  int NewOp = MI.getOpcode();
3881  if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3882  NewOp = Hexagon::getPredOldOpcode(NewOp);
3883  // All Hexagon architectures have prediction bits on dot-new branches,
3884  // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3885  // to pick the right opcode when converting back to dot-old.
3886  if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3887  switch (NewOp) {
3888  case Hexagon::J2_jumptpt:
3889  NewOp = Hexagon::J2_jumpt;
3890  break;
3891  case Hexagon::J2_jumpfpt:
3892  NewOp = Hexagon::J2_jumpf;
3893  break;
3894  case Hexagon::J2_jumprtpt:
3895  NewOp = Hexagon::J2_jumprt;
3896  break;
3897  case Hexagon::J2_jumprfpt:
3898  NewOp = Hexagon::J2_jumprf;
3899  break;
3900  }
3901  }
3902  assert(NewOp >= 0 &&
3903  "Couldn't change predicate new instruction to its old form.");
3904  }
3905 
3906  if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3907  NewOp = Hexagon::getNonNVStore(NewOp);
3908  assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3909  }
3910 
3911  if (Subtarget.hasV60Ops())
3912  return NewOp;
3913 
3914  // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3915  switch (NewOp) {
3916  case Hexagon::J2_jumpfpt:
3917  return Hexagon::J2_jumpf;
3918  case Hexagon::J2_jumptpt:
3919  return Hexagon::J2_jumpt;
3920  case Hexagon::J2_jumprfpt:
3921  return Hexagon::J2_jumprf;
3922  case Hexagon::J2_jumprtpt:
3923  return Hexagon::J2_jumprt;
3924  }
3925  return NewOp;
3926 }
3927 
3928 // See if instruction could potentially be a duplex candidate.
3929 // If so, return its group. Zero otherwise.
3931  const MachineInstr &MI) const {
3932  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3933  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3934 
3935  switch (MI.getOpcode()) {
3936  default:
3937  return HexagonII::HSIG_None;
3938  //
3939  // Group L1:
3940  //
3941  // Rd = memw(Rs+#u4:2)
3942  // Rd = memub(Rs+#u4:0)
3943  case Hexagon::L2_loadri_io:
3944  case Hexagon::dup_L2_loadri_io:
3945  DstReg = MI.getOperand(0).getReg();
3946  SrcReg = MI.getOperand(1).getReg();
3947  // Special case this one from Group L2.
3948  // Rd = memw(r29+#u5:2)
3949  if (isIntRegForSubInst(DstReg)) {
3950  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3951  HRI.getStackRegister() == SrcReg &&
3952  MI.getOperand(2).isImm() &&
3953  isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3954  return HexagonII::HSIG_L2;
3955  // Rd = memw(Rs+#u4:2)
3956  if (isIntRegForSubInst(SrcReg) &&
3957  (MI.getOperand(2).isImm() &&
3958  isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3959  return HexagonII::HSIG_L1;
3960  }
3961  break;
3962  case Hexagon::L2_loadrub_io:
3963  case Hexagon::dup_L2_loadrub_io:
3964  // Rd = memub(Rs+#u4:0)
3965  DstReg = MI.getOperand(0).getReg();
3966  SrcReg = MI.getOperand(1).getReg();
3967  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3968  MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3969  return HexagonII::HSIG_L1;
3970  break;
3971  //
3972  // Group L2:
3973  //
3974  // Rd = memh/memuh(Rs+#u3:1)
3975  // Rd = memb(Rs+#u3:0)
3976  // Rd = memw(r29+#u5:2) - Handled above.
3977  // Rdd = memd(r29+#u5:3)
3978  // deallocframe
3979  // [if ([!]p0[.new])] dealloc_return
3980  // [if ([!]p0[.new])] jumpr r31
3981  case Hexagon::L2_loadrh_io:
3982  case Hexagon::L2_loadruh_io:
3983  case Hexagon::dup_L2_loadrh_io:
3984  case Hexagon::dup_L2_loadruh_io:
3985  // Rd = memh/memuh(Rs+#u3:1)
3986  DstReg = MI.getOperand(0).getReg();
3987  SrcReg = MI.getOperand(1).getReg();
3988  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3989  MI.getOperand(2).isImm() &&
3990  isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3991  return HexagonII::HSIG_L2;
3992  break;
3993  case Hexagon::L2_loadrb_io:
3994  case Hexagon::dup_L2_loadrb_io:
3995  // Rd = memb(Rs+#u3:0)
3996  DstReg = MI.getOperand(0).getReg();
3997  SrcReg = MI.getOperand(1).getReg();
3998  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3999  MI.getOperand(2).isImm() &&
4000  isUInt<3>(MI.getOperand(2).getImm()))
4001  return HexagonII::HSIG_L2;
4002  break;
4003  case Hexagon::L2_loadrd_io:
4004  case Hexagon::dup_L2_loadrd_io:
4005  // Rdd = memd(r29+#u5:3)
4006  DstReg = MI.getOperand(0).getReg();
4007  SrcReg = MI.getOperand(1).getReg();
4008  if (isDblRegForSubInst(DstReg, HRI) &&
4009  Hexagon::IntRegsRegClass.contains(SrcReg) &&
4010  HRI.getStackRegister() == SrcReg &&
4011  MI.getOperand(2).isImm() &&
4012  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
4013  return HexagonII::HSIG_L2;
4014  break;
4015  // dealloc_return is not documented in Hexagon Manual, but marked
4016  // with A_SUBINSN attribute in iset_v4classic.py.
4017  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
4018  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
4019  case Hexagon::L4_return:
4020  case Hexagon::L2_deallocframe:
4021  case Hexagon::dup_L2_deallocframe:
4022  return HexagonII::HSIG_L2;
4023  case Hexagon::EH_RETURN_JMPR:
4024  case Hexagon::PS_jmpret:
4025  case Hexagon::SL2_jumpr31:
4026  // jumpr r31
4027  // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
4028  DstReg = MI.getOperand(0).getReg();
4029  if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
4030  return HexagonII::HSIG_L2;
4031  break;
4032  case Hexagon::PS_jmprett:
4033  case Hexagon::PS_jmpretf:
4034  case Hexagon::PS_jmprettnewpt:
4035  case Hexagon::PS_jmpretfnewpt:
4036  case Hexagon::PS_jmprettnew:
4037  case Hexagon::PS_jmpretfnew:
4038  case Hexagon::SL2_jumpr31_t:
4039  case Hexagon::SL2_jumpr31_f:
4040  case Hexagon::SL2_jumpr31_tnew:
4041  case Hexagon::SL2_jumpr31_fnew:
4042  DstReg = MI.getOperand(1).getReg();
4043  SrcReg = MI.getOperand(0).getReg();
4044  // [if ([!]p0[.new])] jumpr r31
4045  if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
4046  (Hexagon::P0 == SrcReg)) &&
4047  (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
4048  return HexagonII::HSIG_L2;
4049  break;
4050  case Hexagon::L4_return_t:
4051  case Hexagon::L4_return_f:
4052  case Hexagon::L4_return_tnew_pnt:
4053  case Hexagon::L4_return_fnew_pnt:
4054  case Hexagon::L4_return_tnew_pt:
4055  case Hexagon::L4_return_fnew_pt:
4056  // [if ([!]p0[.new])] dealloc_return
4057  SrcReg = MI.getOperand(0).getReg();
4058  if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
4059  return HexagonII::HSIG_L2;
4060  break;
4061  //
4062  // Group S1:
4063  //
4064  // memw(Rs+#u4:2) = Rt
4065  // memb(Rs+#u4:0) = Rt
4066  case Hexagon::S2_storeri_io:
4067  case Hexagon::dup_S2_storeri_io:
4068  // Special case this one from Group S2.
4069  // memw(r29+#u5:2) = Rt
4070  Src1Reg = MI.getOperand(0).getReg();
4071  Src2Reg = MI.getOperand(2).getReg();
4072  if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4073  isIntRegForSubInst(Src2Reg) &&
4074  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
4075  isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
4076  return HexagonII::HSIG_S2;
4077  // memw(Rs+#u4:2) = Rt
4078  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4079  MI.getOperand(1).isImm() &&
4080  isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
4081  return HexagonII::HSIG_S1;
4082  break;
4083  case Hexagon::S2_storerb_io:
4084  case Hexagon::dup_S2_storerb_io:
4085  // memb(Rs+#u4:0) = Rt
4086  Src1Reg = MI.getOperand(0).getReg();
4087  Src2Reg = MI.getOperand(2).getReg();
4088  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4089  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
4090  return HexagonII::HSIG_S1;
4091  break;
4092  //
4093  // Group S2:
4094  //
4095  // memh(Rs+#u3:1) = Rt
4096  // memw(r29+#u5:2) = Rt
4097  // memd(r29+#s6:3) = Rtt
4098  // memw(Rs+#u4:2) = #U1
4099  // memb(Rs+#u4) = #U1
4100  // allocframe(#u5:3)
4101  case Hexagon::S2_storerh_io:
4102  case Hexagon::dup_S2_storerh_io:
4103  // memh(Rs+#u3:1) = Rt
4104  Src1Reg = MI.getOperand(0).getReg();
4105  Src2Reg = MI.getOperand(2).getReg();
4106  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4107  MI.getOperand(1).isImm() &&
4108  isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
4109  return HexagonII::HSIG_S1;
4110  break;
4111  case Hexagon::S2_storerd_io:
4112  case Hexagon::dup_S2_storerd_io:
4113  // memd(r29+#s6:3) = Rtt
4114  Src1Reg = MI.getOperand(0).getReg();
4115  Src2Reg = MI.getOperand(2).getReg();
4116  if (isDblRegForSubInst(Src2Reg, HRI) &&
4117  Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4118  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
4119  isShiftedInt<6,3>(MI.getOperand(1).getImm()))
4120  return HexagonII::HSIG_S2;
4121  break;
4122  case Hexagon::S4_storeiri_io:
4123  case Hexagon::dup_S4_storeiri_io:
4124  // memw(Rs+#u4:2) = #U1
4125  Src1Reg = MI.getOperand(0).getReg();
4126  if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
4127  isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
4128  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4129  return HexagonII::HSIG_S2;
4130  break;
4131  case Hexagon::S4_storeirb_io:
4132  case Hexagon::dup_S4_storeirb_io:
4133  // memb(Rs+#u4) = #U1
4134  Src1Reg = MI.getOperand(0).getReg();
4135  if (isIntRegForSubInst(Src1Reg) &&
4136  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
4137  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4138  return HexagonII::HSIG_S2;
4139  break;
4140  case Hexagon::S2_allocframe:
4141  case Hexagon::dup_S2_allocframe:
4142  if (MI.getOperand(2).isImm() &&
4143  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
4144  return HexagonII::HSIG_S1;
4145  break;
4146  //
4147  // Group A:
4148  //
4149  // Rx = add(Rx,#s7)
4150  // Rd = Rs
4151  // Rd = #u6
4152  // Rd = #-1
4153  // if ([!]P0[.new]) Rd = #0
4154  // Rd = add(r29,#u6:2)
4155  // Rx = add(Rx,Rs)
4156  // P0 = cmp.eq(Rs,#u2)
4157  // Rdd = combine(#0,Rs)
4158  // Rdd = combine(Rs,#0)
4159  // Rdd = combine(#u2,#U2)
4160  // Rd = add(Rs,#1)
4161  // Rd = add(Rs,#-1)
4162  // Rd = sxth/sxtb/zxtb/zxth(Rs)
4163  // Rd = and(Rs,#1)
4164  case Hexagon::A2_addi:
4165  case Hexagon::dup_A2_addi:
4166  DstReg = MI.getOperand(0).getReg();
4167  SrcReg = MI.getOperand(1).getReg();
4168  if (isIntRegForSubInst(DstReg)) {
4169  // Rd = add(r29,#u6:2)
4170  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
4171  HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
4172  isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
4173  return HexagonII::HSIG_A;
4174  // Rx = add(Rx,#s7)
4175  if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
4176  isInt<7>(MI.getOperand(2).getImm()))
4177  return HexagonII::HSIG_A;
4178  // Rd = add(Rs,#1)
4179  // Rd = add(Rs,#-1)
4180  if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
4181  ((MI.getOperand(2).getImm() == 1) ||
4182  (MI.getOperand(2).getImm() == -1)))
4183  return HexagonII::HSIG_A;
4184  }
4185  break;
4186  case Hexagon::A2_add:
4187  case Hexagon::dup_A2_add:
4188  // Rx = add(Rx,Rs)
4189  DstReg = MI.getOperand(0).getReg();
4190  Src1Reg = MI.getOperand(1).getReg();
4191  Src2Reg = MI.getOperand(2).getReg();
4192  if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
4193  isIntRegForSubInst(Src2Reg))
4194  return HexagonII::HSIG_A;
4195  break;
4196  case Hexagon::A2_andir:
4197  case Hexagon::dup_A2_andir:
4198  // Same as zxtb.
4199  // Rd16=and(Rs16,#255)
4200  // Rd16=and(Rs16,#1)
4201  DstReg = MI.getOperand(0).getReg();
4202  SrcReg = MI.getOperand(1).getReg();
4203  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
4204  MI.getOperand(2).isImm() &&
4205  ((MI.getOperand(2).getImm() == 1) ||
4206  (MI.getOperand(2).getImm() == 255)))
4207  return HexagonII::HSIG_A;
4208  break;
4209  case Hexagon::A2_tfr:
4210  case Hexagon::dup_A2_tfr:
4211  // Rd = Rs
4212  DstReg = MI.getOperand(0).getReg();
4213  SrcReg = MI.getOperand(1).getReg();
4214  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4215  return HexagonII::HSIG_A;
4216  break;
4217  case Hexagon::A2_tfrsi:
4218  case Hexagon::dup_A2_tfrsi:
4219  // Rd = #u6
4220  // Do not test for #u6 size since the const is getting extended
4221  // regardless and compound could be formed.
4222  // Rd = #-1
4223  DstReg = MI.getOperand(0).getReg();
4224  if (isIntRegForSubInst(DstReg))
4225  return HexagonII::HSIG_A;
4226  break;
4227  case Hexagon::C2_cmoveit:
4228  case Hexagon::C2_cmovenewit:
4229  case Hexagon::C2_cmoveif:
4230  case Hexagon::C2_cmovenewif:
4231  case Hexagon::dup_C2_cmoveit:
4232  case Hexagon::dup_C2_cmovenewit:
4233  case Hexagon::dup_C2_cmoveif:
4234  case Hexagon::dup_C2_cmovenewif:
4235  // if ([!]P0[.new]) Rd = #0
4236  // Actual form:
4237  // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
4238  DstReg = MI.getOperand(0).getReg();
4239  SrcReg = MI.getOperand(1).getReg();
4240  if (isIntRegForSubInst(DstReg) &&
4241  Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4242  MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4243  return HexagonII::HSIG_A;
4244  break;
4245  case Hexagon::C2_cmpeqi:
4246  case Hexagon::dup_C2_cmpeqi:
4247  // P0 = cmp.eq(Rs,#u2)
4248  DstReg = MI.getOperand(0).getReg();
4249  SrcReg = MI.getOperand(1).getReg();
4250  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
4251  Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
4252  MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4253  return HexagonII::HSIG_A;
4254  break;
4255  case Hexagon::A2_combineii:
4256  case Hexagon::A4_combineii:
4257  case Hexagon::dup_A2_combineii:
4258  case Hexagon::dup_A4_combineii:
4259  // Rdd = combine(#u2,#U2)
4260  DstReg = MI.getOperand(0).getReg();
4261  if (isDblRegForSubInst(DstReg, HRI) &&
4262  ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4263  (MI.getOperand(1).isGlobal() &&
4264  isUInt<2>(MI.getOperand(1).getOffset()))) &&
4265  ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4266  (MI.getOperand(2).isGlobal() &&
4267  isUInt<2>(MI.getOperand(2).getOffset()))))
4268  return HexagonII::HSIG_A;
4269  break;
4270  case Hexagon::A4_combineri:
4271  case Hexagon::dup_A4_combineri:
4272  // Rdd = combine(Rs,#0)
4273  // Rdd = combine(Rs,#0)
4274  DstReg = MI.getOperand(0).getReg();
4275  SrcReg = MI.getOperand(1).getReg();
4276  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4277  ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4278  (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4279  return HexagonII::HSIG_A;
4280  break;
4281  case Hexagon::A4_combineir:
4282  case Hexagon::dup_A4_combineir:
4283  // Rdd = combine(#0,Rs)
4284  DstReg = MI.getOperand(0).getReg();
4285  SrcReg = MI.getOperand(2).getReg();
4286  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4287  ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4288  (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4289  return HexagonII::HSIG_A;
4290  break;
4291  case Hexagon::A2_sxtb:
4292  case Hexagon::A2_sxth:
4293  case Hexagon::A2_zxtb:
4294  case Hexagon::A2_zxth:
4295  case Hexagon::dup_A2_sxtb:
4296  case Hexagon::dup_A2_sxth:
4297  case Hexagon::dup_A2_zxtb:
4298  case Hexagon::dup_A2_zxth:
4299  // Rd = sxth/sxtb/zxtb/zxth(Rs)
4300  DstReg = MI.getOperand(0).getReg();
4301  SrcReg = MI.getOperand(1).getReg();
4302  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4303  return HexagonII::HSIG_A;
4304  break;
4305  }
4306 
4307  return HexagonII::HSIG_None;
4308 }
4309 
4311  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4312 }
4313 
4315  const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4316  // Default to one cycle for no itinerary. However, an "empty" itinerary may
4317  // still have a MinLatency property, which getStageLatency checks.
4318  if (!ItinData)
4319  return getInstrLatency(ItinData, MI);
4320 
4321  if (MI.isTransient())
4322  return 0;
4323  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4324 }
4325 
4326 /// getOperandLatency - Compute and return the use operand latency of a given
4327 /// pair of def and use.
4328 /// In most cases, the static scheduling itinerary was enough to determine the
4329 /// operand latency. But it may not be possible for instructions with variable
4330 /// number of defs / uses.
4331 ///
4332 /// This is a raw interface to the itinerary that may be directly overriden by
4333 /// a target. Use computeOperandLatency to get the best estimate of latency.
4335  const MachineInstr &DefMI,
4336  unsigned DefIdx,
4337  const MachineInstr &UseMI,
4338  unsigned UseIdx) const {
4339  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4340 
4341  // Get DefIdx and UseIdx for super registers.
4342  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4343 
4344  if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) {
4345  if (DefMO.isImplicit()) {
4346  for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
4347  int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
4348  if (Idx != -1) {
4349  DefIdx = Idx;
4350  break;
4351  }
4352  }
4353  }
4354 
4355  const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4356  if (UseMO.isImplicit()) {
4357  for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
4358  int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
4359  if (Idx != -1) {
4360  UseIdx = Idx;
4361  break;
4362  }
4363  }
4364  }
4365  }
4366 
4367  int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
4368  UseMI, UseIdx);
4369  if (!Latency)
4370  // We should never have 0 cycle latency between two instructions unless
4371  // they can be packetized together. However, this decision can't be made
4372  // here.
4373  Latency = 1;
4374  return Latency;
4375 }
4376 
4377 // inverts the predication logic.
4378 // p -> NotP
4379 // NotP -> P
4382  if (Cond.empty())
4383  return false;
4384  unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4385  Cond[0].setImm(Opc);
4386  return true;
4387 }
4388 
4389 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4390  int InvPredOpcode;
4391  InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4392  : Hexagon::getTruePredOpcode(Opc);
4393  if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4394  return InvPredOpcode;
4395 
4396  llvm_unreachable("Unexpected predicated instruction");
4397 }
4398 
4399 // Returns the max value that doesn't need to be extended.
4401  const uint64_t F = MI.getDesc().TSFlags;
4402  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4404  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4406 
4407  if (isSigned) // if value is signed
4408  return ~(-1U << (bits - 1));
4409  else
4410  return ~(-1U << bits);
4411 }
4412 
4413 
4415  switch (MI.getOpcode()) {
4416  case Hexagon::L2_loadrbgp:
4417  case Hexagon::L2_loadrdgp:
4418  case Hexagon::L2_loadrhgp:
4419  case Hexagon::L2_loadrigp:
4420  case Hexagon::L2_loadrubgp:
4421  case Hexagon::L2_loadruhgp:
4422  case Hexagon::S2_storerbgp:
4423  case Hexagon::S2_storerbnewgp:
4424  case Hexagon::S2_storerhgp:
4425  case Hexagon::S2_storerhnewgp:
4426  case Hexagon::S2_storerigp:
4427  case Hexagon::S2_storerinewgp:
4428  case Hexagon::S2_storerdgp:
4429  case Hexagon::S2_storerfgp:
4430  return true;
4431  }
4432  const uint64_t F = MI.getDesc().TSFlags;
4433  unsigned addrMode =
4435  // Disallow any base+offset instruction. The assembler does not yet reorder
4436  // based up any zero offset instruction.
4437  return (addrMode == HexagonII::BaseRegOffset ||
4438  addrMode == HexagonII::BaseImmOffset ||
4439  addrMode == HexagonII::BaseLongOffset);
4440 }
4441 
4443  // Workaround for the Global Scheduler. Sometimes, it creates
4444  // A4_ext as a Pseudo instruction and calls this function to see if
4445  // it can be added to an existing bundle. Since the instruction doesn't
4446  // belong to any BB yet, we can't use getUnits API.
4447  if (MI.getOpcode() == Hexagon::A4_ext)
4448  return false;
4449 
4450  unsigned FuncUnits = getUnits(MI);
4451  return HexagonFUnits::isSlot0Only(FuncUnits);
4452 }
4453 
4455  const uint64_t F = MI.getDesc().TSFlags;
4456  return ((F >> HexagonII::RestrictNoSlot1StorePos) &
4458 }
4459 
4461  bool ToBigInstrs) const {
4462  int Opcode = -1;
4463  if (ToBigInstrs) { // To BigCore Instr.
4464  // Check if the instruction can form a Duplex.
4465  if (getDuplexCandidateGroup(*MII))
4466  // Get the opcode marked "dup_*" tag.
4467  Opcode = getDuplexOpcode(*MII, ToBigInstrs);
4468  } else // To TinyCore Instr.
4469  Opcode = getDuplexOpcode(*MII, ToBigInstrs);
4470 
4471  // Change the opcode of the instruction.
4472  if (Opcode >= 0)
4473  MII->setDesc(get(Opcode));
4474 }
4475 
4476 // This function is used to translate instructions to facilitate generating
4477 // Duplexes on TinyCore.
4479  bool ToBigInstrs) const {
4480  for (auto &MB : MF)
4481  for (MachineBasicBlock::instr_iterator Instr = MB.instr_begin(),
4482  End = MB.instr_end();
4483  Instr != End; ++Instr)
4484  changeDuplexOpcode(Instr, ToBigInstrs);
4485 }
4486 
4487 // This is a specialized form of above function.
4489  MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const {
4490  MachineBasicBlock *MBB = MII->getParent();
4491  while ((MII != MBB->instr_end()) && MII->isInsideBundle()) {
4492  changeDuplexOpcode(MII, ToBigInstrs);
4493  ++MII;
4494  }
4495 }
4496 
4498  using namespace HexagonII;
4499 
4500  const uint64_t F = MI.getDesc().TSFlags;
4501  unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4502  unsigned Size = getMemAccessSizeInBytes(MemAccessSize(S));
4503  if (Size != 0)
4504  return Size;
4505  // Y2_dcfetchbo is special
4506  if (MI.getOpcode() == Hexagon::Y2_dcfetchbo)
4508 
4509  // Handle vector access sizes.
4510  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4511  switch (S) {
4513  return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4514  default:
4515  llvm_unreachable("Unexpected instruction");
4516  }
4517 }
4518 
4519 // Returns the min value that doesn't need to be extended.
4521  const uint64_t F = MI.getDesc().TSFlags;
4522  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4524  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4526 
4527  if (isSigned) // if value is signed
4528  return -1U << (bits - 1);
4529  else
4530  return 0;
4531 }
4532 
4533 // Returns opcode of the non-extended equivalent instruction.
4535  // Check if the instruction has a register form that uses register in place
4536  // of the extended operand, if so return that as the non-extended form.
4537  short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4538  if (NonExtOpcode >= 0)
4539  return NonExtOpcode;
4540 
4541  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4542  // Check addressing mode and retrieve non-ext equivalent instruction.
4543  switch (getAddrMode(MI)) {
4544  case HexagonII::Absolute:
4545  return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4547  return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4549  return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4550 
4551  default:
4552  return -1;
4553  }
4554  }
4555  return -1;
4556 }
4557 
4559  unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4560  if (Cond.empty())
4561  return false;
4562  assert(Cond.size() == 2);
4563  if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4564  LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4565  return false;
4566  }
4567  PredReg = Cond[1].getReg();
4568  PredRegPos = 1;
4569  // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4570  PredRegFlags = 0;
4571  if (Cond[1].isImplicit())
4572  PredRegFlags = RegState::Implicit;
4573  if (Cond[1].isUndef())
4574  PredRegFlags |= RegState::Undef;
4575  return true;
4576 }
4577 
4579  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4580 }
4581 
4583  return Hexagon::getRegForm(MI.getOpcode());
4584 }
4585 
4586 // Return the number of bytes required to encode the instruction.
4587 // Hexagon instructions are fixed length, 4 bytes, unless they
4588 // use a constant extender, which requires another 4 bytes.
4589 // For debug instructions and prolog labels, return 0.
4591  if (MI.isDebugInstr() || MI.isPosition())
4592  return 0;
4593 
4594  unsigned Size = MI.getDesc().getSize();
4595  if (!Size)
4596  // Assume the default insn size in case it cannot be determined
4597  // for whatever reason.
4598  Size = HEXAGON_INSTR_SIZE;
4599 
4600  if (isConstExtended(MI) || isExtended(MI))
4601  Size += HEXAGON_INSTR_SIZE;
4602 
4603  // Try and compute number of instructions in asm.
4604  if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) {
4605  const MachineBasicBlock &MBB = *MI.getParent();
4606  const MachineFunction *MF = MBB.getParent();
4607  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4608 
4609  // Count the number of register definitions to find the asm string.
4610  unsigned NumDefs = 0;
4611  for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4612  ++NumDefs)
4613  assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4614 
4615  assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4616  // Disassemble the AsmStr and approximate number of instructions.
4617  const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4618  Size = getInlineAsmLength(AsmStr, *MAI);
4619  }
4620 
4621  return Size;
4622 }
4623 
4625  const uint64_t F = MI.getDesc().TSFlags;
4627 }
4628 
4630  const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4631  const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4632 
4633  return IS.getUnits();
4634 }
4635 
4636 // Calculate size of the basic block without debug instructions.
4638  return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4639 }
4640 
4642  MachineBasicBlock::const_iterator BundleHead) const {
4643  assert(BundleHead->isBundle() && "Not a bundle header");
4644  auto MII = BundleHead.getInstrIterator();
4645  // Skip the bundle header.
4646  return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4647 }
4648 
4649 /// immediateExtend - Changes the instruction in place to one using an immediate
4650 /// extender.
4653  "Instruction must be extendable");
4654  // Find which operand is extendable.
4655  short ExtOpNum = getCExtOpNum(MI);
4656  MachineOperand &MO = MI.getOperand(ExtOpNum);
4657  // This needs to be something we understand.
4658  assert((MO.isMBB() || MO.isImm()) &&
4659  "Branch with unknown extendable field type");
4660  // Mark given operand as extended.
4662 }
4663 
4665  MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4666  LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4667  << printMBBReference(*NewTarget);
4668  MI.dump(););
4669  assert(MI.isBranch());
4670  unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4671  int TargetPos = MI.getNumOperands() - 1;
4672  // In general branch target is the last operand,
4673  // but some implicit defs added at the end might change it.
4674  while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4675  --TargetPos;
4676  assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4677  MI.getOperand(TargetPos).setMBB(NewTarget);
4679  NewOpcode = reversePrediction(NewOpcode);
4680  }
4681  MI.setDesc(get(NewOpcode));
4682  return true;
4683 }
4684 
4686  /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4688  MachineBasicBlock &B = *A;
4689  MachineBasicBlock::iterator I = B.begin();
4690  DebugLoc DL = I->getDebugLoc();
4691  MachineInstr *NewMI;
4692 
4693  for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4694  insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4695  NewMI = BuildMI(B, I, DL, get(insn));
4696  LLVM_DEBUG(dbgs() << "\n"
4697  << getName(NewMI->getOpcode())
4698  << " Class: " << NewMI->getDesc().getSchedClass());
4699  NewMI->eraseFromParent();
4700  }
4701  /* --- The code above is used to generate complete set of Hexagon Insn --- */
4702 }
4703 
4704 // inverts the predication logic.
4705 // p -> NotP
4706 // NotP -> P
4708  LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4709  MI.setDesc(get(getInvertedPredicatedOpcode(MI.getOpcode())));
4710  return true;
4711 }
4712 
4713 // Reverse the branch prediction.
4714 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4715  int PredRevOpcode = -1;
4716  if (isPredictedTaken(Opcode))
4717  PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4718  else
4719  PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4720  assert(PredRevOpcode > 0);
4721  return PredRevOpcode;
4722 }
4723 
4724 // TODO: Add more rigorous validation.
4726  const {
4727  return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4728 }
4729 
4730 void HexagonInstrInfo::
4732  assert(MIB->isBundle());
4733  MachineOperand &Operand = MIB->getOperand(0);
4734  if (Operand.isImm())
4735  Operand.setImm(Operand.getImm() | memShufDisabledMask);
4736  else
4737  MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4738 }
4739 
4741  assert(MIB.isBundle());
4742  const MachineOperand &Operand = MIB.getOperand(0);
4743  return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4744 }
4745 
4746 // Addressing mode relations.
4748  return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4749 }
4750 
4752  return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4753 }
4754 
4756  return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4757 }
4758 
4760  return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4761 }
4762 
4764  return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4765 }
4766 
4768  return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4769 }
4770 
4772  return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4773 }
4774 
4776  return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4777 }
4778 
4780  static const MCInst Nop = MCInstBuilder(Hexagon::A2_nop);
4781 
4782  return MCInstBuilder(Hexagon::BUNDLE)
4783  .addImm(0)
4784  .addInst(&Nop);
4785 }
i
i
Definition: README.txt:29
llvm::HexagonInstrInfo::isTailCall
bool isTailCall(const MachineInstr &MI) const override
Definition: HexagonInstrInfo.cpp:2690
llvm::HexagonII::CompoundGroup
CompoundGroup
Definition: HexagonBaseInfo.h:233
llvm::HexagonII::ExtentSignedMask
@ ExtentSignedMask
Definition: HexagonBaseInfo.h:109
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:245
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:62
llvm::HexagonII::HSIG_Compound
@ HSIG_Compound
Definition: HexagonBaseInfo.h:229
llvm::HexagonInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Test if the given instruction should be considered a scheduling boundary.
Definition: HexagonInstrInfo.cpp:1784
llvm::HexagonInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Definition: HexagonInstrInfo.cpp:335
getName
static StringRef getName(Value *V)
Definition: ProvenanceAnalysisEvaluator.cpp:42
llvm::HexagonSubtarget::useNewValueStores
bool useNewValueStores() const
Definition: HexagonSubtarget.h:208
ScheduleDAG.h
llvm::HexagonII::HSIG_S2
@ HSIG_S2
Definition: HexagonBaseInfo.h:227
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131