LLVM 19.0.0git
HexagonInstrInfo.cpp
Go to the documentation of this file.
1//===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Hexagon implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "HexagonInstrInfo.h"
14#include "Hexagon.h"
17#include "HexagonRegisterInfo.h"
18#include "HexagonSubtarget.h"
19#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/StringRef.h"
43#include "llvm/IR/DebugLoc.h"
44#include "llvm/MC/MCAsmInfo.h"
46#include "llvm/MC/MCInstrDesc.h"
51#include "llvm/Support/Debug.h"
56#include <cassert>
57#include <cctype>
58#include <cstdint>
59#include <cstring>
60#include <iterator>
61#include <optional>
62#include <string>
63#include <utility>
64
65using namespace llvm;
66
67#define DEBUG_TYPE "hexagon-instrinfo"
68
69#define GET_INSTRINFO_CTOR_DTOR
70#define GET_INSTRMAP_INFO
72#include "HexagonGenDFAPacketizer.inc"
73#include "HexagonGenInstrInfo.inc"
74
75cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
76 cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
77 "packetization boundary."));
78
79static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
80 cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
81
83 "disable-hexagon-nv-schedule", cl::Hidden,
84 cl::desc("Disable schedule adjustment for new value stores."));
85
87 "enable-timing-class-latency", cl::Hidden, cl::init(false),
88 cl::desc("Enable timing class latency"));
89
91 "enable-alu-forwarding", cl::Hidden, cl::init(true),
92 cl::desc("Enable vec alu forwarding"));
93
95 "enable-acc-forwarding", cl::Hidden, cl::init(true),
96 cl::desc("Enable vec acc forwarding"));
97
98static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
99 cl::init(true), cl::Hidden,
100 cl::desc("branch relax asm"));
101
102static cl::opt<bool>
103 UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden,
104 cl::desc("Use the DFA based hazard recognizer."));
105
106/// Constants for Hexagon instructions.
107const int Hexagon_MEMW_OFFSET_MAX = 4095;
108const int Hexagon_MEMW_OFFSET_MIN = -4096;
109const int Hexagon_MEMD_OFFSET_MAX = 8191;
110const int Hexagon_MEMD_OFFSET_MIN = -8192;
111const int Hexagon_MEMH_OFFSET_MAX = 2047;
112const int Hexagon_MEMH_OFFSET_MIN = -2048;
113const int Hexagon_MEMB_OFFSET_MAX = 1023;
114const int Hexagon_MEMB_OFFSET_MIN = -1024;
115const int Hexagon_ADDI_OFFSET_MAX = 32767;
116const int Hexagon_ADDI_OFFSET_MIN = -32768;
117
118// Pin the vtable to this file.
119void HexagonInstrInfo::anchor() {}
120
122 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
123 Subtarget(ST) {}
124
125namespace llvm {
126namespace HexagonFUnits {
127 bool isSlot0Only(unsigned units);
128}
129}
130
131static bool isIntRegForSubInst(Register Reg) {
132 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
133 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
134}
135
136static bool isDblRegForSubInst(Register Reg, const HexagonRegisterInfo &HRI) {
137 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
138 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
139}
140
141/// Calculate number of instructions excluding the debug instructions.
144 unsigned Count = 0;
145 for (; MIB != MIE; ++MIB) {
146 if (!MIB->isDebugInstr())
147 ++Count;
148 }
149 return Count;
150}
151
152// Check if the A2_tfrsi instruction is cheap or not. If the operand has
153// to be constant-extendend it is not cheap since it occupies two slots
154// in a packet.
156 // Enable the following steps only at Os/Oz
157 if (!(MI.getMF()->getFunction().hasOptSize()))
158 return MI.isAsCheapAsAMove();
159
160 if (MI.getOpcode() == Hexagon::A2_tfrsi) {
161 auto Op = MI.getOperand(1);
162 // If the instruction has a global address as operand, it is not cheap
163 // since the operand will be constant extended.
164 if (Op.isGlobal())
165 return false;
166 // If the instruction has an operand of size > 16bits, its will be
167 // const-extended and hence, it is not cheap.
168 if (Op.isImm()) {
169 int64_t Imm = Op.getImm();
170 if (!isInt<16>(Imm))
171 return false;
172 }
173 }
174 return MI.isAsCheapAsAMove();
175}
176
177// Do not sink floating point instructions that updates USR register.
178// Example:
179// feclearexcept
180// F2_conv_w2sf
181// fetestexcept
182// MachineSink sinks F2_conv_w2sf and we are not able to catch exceptions.
183// TODO: On some of these floating point instructions, USR is marked as Use.
184// In reality, these instructions also Def the USR. If USR is marked as Def,
185// some of the assumptions in assembler packetization are broken.
187 // Assumption: A floating point instruction that reads the USR will write
188 // the USR as well.
189 if (isFloat(MI) && MI.hasRegisterImplicitUseOperand(Hexagon::USR))
190 return false;
191 return true;
192}
193
194/// Find the hardware loop instruction used to set-up the specified loop.
195/// On Hexagon, we have two instructions used to set-up the hardware loop
196/// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
197/// to indicate the end of a loop.
199 unsigned EndLoopOp, MachineBasicBlock *TargetBB,
201 unsigned LOOPi;
202 unsigned LOOPr;
203 if (EndLoopOp == Hexagon::ENDLOOP0) {
204 LOOPi = Hexagon::J2_loop0i;
205 LOOPr = Hexagon::J2_loop0r;
206 } else { // EndLoopOp == Hexagon::EndLOOP1
207 LOOPi = Hexagon::J2_loop1i;
208 LOOPr = Hexagon::J2_loop1r;
209 }
210
211 // The loop set-up instruction will be in a predecessor block
212 for (MachineBasicBlock *PB : BB->predecessors()) {
213 // If this has been visited, already skip it.
214 if (!Visited.insert(PB).second)
215 continue;
216 if (PB == BB)
217 continue;
218 for (MachineInstr &I : llvm::reverse(PB->instrs())) {
219 unsigned Opc = I.getOpcode();
220 if (Opc == LOOPi || Opc == LOOPr)
221 return &I;
222 // We've reached a different loop, which means the loop01 has been
223 // removed.
224 if (Opc == EndLoopOp && I.getOperand(0).getMBB() != TargetBB)
225 return nullptr;
226 }
227 // Check the predecessors for the LOOP instruction.
228 if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
229 return Loop;
230 }
231 return nullptr;
232}
233
234/// Gather register def/uses from MI.
235/// This treats possible (predicated) defs as actually happening ones
236/// (conservatively).
237static inline void parseOperands(const MachineInstr &MI,
239 Defs.clear();
240 Uses.clear();
241
242 for (const MachineOperand &MO : MI.operands()) {
243 if (!MO.isReg())
244 continue;
245
246 Register Reg = MO.getReg();
247 if (!Reg)
248 continue;
249
250 if (MO.isUse())
251 Uses.push_back(MO.getReg());
252
253 if (MO.isDef())
254 Defs.push_back(MO.getReg());
255 }
256}
257
258// Position dependent, so check twice for swap.
259static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
260 switch (Ga) {
262 default:
263 return false;
265 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
267 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
268 Gb == HexagonII::HSIG_A);
270 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
273 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
274 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
275 Gb == HexagonII::HSIG_A);
277 return (Gb == HexagonII::HSIG_A);
279 return (Gb == HexagonII::HSIG_Compound);
280 }
281 return false;
282}
283
284/// isLoadFromStackSlot - If the specified machine instruction is a direct
285/// load from a stack slot, return the virtual or physical register number of
286/// the destination along with the FrameIndex of the loaded stack slot. If
287/// not, return 0. This predicate must return 0 if the instruction has
288/// any side effects other than loading from the stack slot.
290 int &FrameIndex) const {
291 switch (MI.getOpcode()) {
292 default:
293 break;
294 case Hexagon::L2_loadri_io:
295 case Hexagon::L2_loadrd_io:
296 case Hexagon::V6_vL32b_ai:
297 case Hexagon::V6_vL32b_nt_ai:
298 case Hexagon::V6_vL32Ub_ai:
299 case Hexagon::LDriw_pred:
300 case Hexagon::LDriw_ctr:
301 case Hexagon::PS_vloadrq_ai:
302 case Hexagon::PS_vloadrw_ai:
303 case Hexagon::PS_vloadrw_nt_ai: {
304 const MachineOperand OpFI = MI.getOperand(1);
305 if (!OpFI.isFI())
306 return 0;
307 const MachineOperand OpOff = MI.getOperand(2);
308 if (!OpOff.isImm() || OpOff.getImm() != 0)
309 return 0;
310 FrameIndex = OpFI.getIndex();
311 return MI.getOperand(0).getReg();
312 }
313
314 case Hexagon::L2_ploadrit_io:
315 case Hexagon::L2_ploadrif_io:
316 case Hexagon::L2_ploadrdt_io:
317 case Hexagon::L2_ploadrdf_io: {
318 const MachineOperand OpFI = MI.getOperand(2);
319 if (!OpFI.isFI())
320 return 0;
321 const MachineOperand OpOff = MI.getOperand(3);
322 if (!OpOff.isImm() || OpOff.getImm() != 0)
323 return 0;
324 FrameIndex = OpFI.getIndex();
325 return MI.getOperand(0).getReg();
326 }
327 }
328
329 return 0;
330}
331
332/// isStoreToStackSlot - If the specified machine instruction is a direct
333/// store to a stack slot, return the virtual or physical register number of
334/// the source reg along with the FrameIndex of the loaded stack slot. If
335/// not, return 0. This predicate must return 0 if the instruction has
336/// any side effects other than storing to the stack slot.
338 int &FrameIndex) const {
339 switch (MI.getOpcode()) {
340 default:
341 break;
342 case Hexagon::S2_storerb_io:
343 case Hexagon::S2_storerh_io:
344 case Hexagon::S2_storeri_io:
345 case Hexagon::S2_storerd_io:
346 case Hexagon::V6_vS32b_ai:
347 case Hexagon::V6_vS32Ub_ai:
348 case Hexagon::STriw_pred:
349 case Hexagon::STriw_ctr:
350 case Hexagon::PS_vstorerq_ai:
351 case Hexagon::PS_vstorerw_ai: {
352 const MachineOperand &OpFI = MI.getOperand(0);
353 if (!OpFI.isFI())
354 return 0;
355 const MachineOperand &OpOff = MI.getOperand(1);
356 if (!OpOff.isImm() || OpOff.getImm() != 0)
357 return 0;
358 FrameIndex = OpFI.getIndex();
359 return MI.getOperand(2).getReg();
360 }
361
362 case Hexagon::S2_pstorerbt_io:
363 case Hexagon::S2_pstorerbf_io:
364 case Hexagon::S2_pstorerht_io:
365 case Hexagon::S2_pstorerhf_io:
366 case Hexagon::S2_pstorerit_io:
367 case Hexagon::S2_pstorerif_io:
368 case Hexagon::S2_pstorerdt_io:
369 case Hexagon::S2_pstorerdf_io: {
370 const MachineOperand &OpFI = MI.getOperand(1);
371 if (!OpFI.isFI())
372 return 0;
373 const MachineOperand &OpOff = MI.getOperand(2);
374 if (!OpOff.isImm() || OpOff.getImm() != 0)
375 return 0;
376 FrameIndex = OpFI.getIndex();
377 return MI.getOperand(3).getReg();
378 }
379 }
380
381 return 0;
382}
383
384/// This function checks if the instruction or bundle of instructions
385/// has load from stack slot and returns frameindex and machine memory
386/// operand of that instruction if true.
388 const MachineInstr &MI,
390 if (MI.isBundle()) {
391 const MachineBasicBlock *MBB = MI.getParent();
393 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
394 if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
395 return true;
396 return false;
397 }
398
400}
401
402/// This function checks if the instruction or bundle of instructions
403/// has store to stack slot and returns frameindex and machine memory
404/// operand of that instruction if true.
406 const MachineInstr &MI,
408 if (MI.isBundle()) {
409 const MachineBasicBlock *MBB = MI.getParent();
411 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
412 if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
413 return true;
414 return false;
415 }
416
418}
419
420/// This function can analyze one/two way branching only and should (mostly) be
421/// called by target independent side.
422/// First entry is always the opcode of the branching instruction, except when
423/// the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a
424/// BB with only unconditional jump. Subsequent entries depend upon the opcode,
425/// e.g. Jump_c p will have
426/// Cond[0] = Jump_c
427/// Cond[1] = p
428/// HW-loop ENDLOOP:
429/// Cond[0] = ENDLOOP
430/// Cond[1] = MBB
431/// New value jump:
432/// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
433/// Cond[1] = R
434/// Cond[2] = Imm
437 MachineBasicBlock *&FBB,
439 bool AllowModify) const {
440 TBB = nullptr;
441 FBB = nullptr;
442 Cond.clear();
443
444 // If the block has no terminators, it just falls into the block after it.
446 if (I == MBB.instr_begin())
447 return false;
448
449 // A basic block may looks like this:
450 //
451 // [ insn
452 // EH_LABEL
453 // insn
454 // insn
455 // insn
456 // EH_LABEL
457 // insn ]
458 //
459 // It has two succs but does not have a terminator
460 // Don't know how to handle it.
461 do {
462 --I;
463 if (I->isEHLabel())
464 // Don't analyze EH branches.
465 return true;
466 } while (I != MBB.instr_begin());
467
468 I = MBB.instr_end();
469 --I;
470
471 while (I->isDebugInstr()) {
472 if (I == MBB.instr_begin())
473 return false;
474 --I;
475 }
476
477 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
478 I->getOperand(0).isMBB();
479 // Delete the J2_jump if it's equivalent to a fall-through.
480 if (AllowModify && JumpToBlock &&
481 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
482 LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
483 I->eraseFromParent();
484 I = MBB.instr_end();
485 if (I == MBB.instr_begin())
486 return false;
487 --I;
488 }
489 if (!isUnpredicatedTerminator(*I))
490 return false;
491
492 // Get the last instruction in the block.
493 MachineInstr *LastInst = &*I;
494 MachineInstr *SecondLastInst = nullptr;
495 // Find one more terminator if present.
496 while (true) {
497 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
498 if (!SecondLastInst)
499 SecondLastInst = &*I;
500 else
501 // This is a third branch.
502 return true;
503 }
504 if (I == MBB.instr_begin())
505 break;
506 --I;
507 }
508
509 int LastOpcode = LastInst->getOpcode();
510 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
511 // If the branch target is not a basic block, it could be a tail call.
512 // (It is, if the target is a function.)
513 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
514 return true;
515 if (SecLastOpcode == Hexagon::J2_jump &&
516 !SecondLastInst->getOperand(0).isMBB())
517 return true;
518
519 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
520 bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
521
522 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
523 return true;
524
525 // If there is only one terminator instruction, process it.
526 if (LastInst && !SecondLastInst) {
527 if (LastOpcode == Hexagon::J2_jump) {
528 TBB = LastInst->getOperand(0).getMBB();
529 return false;
530 }
531 if (isEndLoopN(LastOpcode)) {
532 TBB = LastInst->getOperand(0).getMBB();
533 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
534 Cond.push_back(LastInst->getOperand(0));
535 return false;
536 }
537 if (LastOpcodeHasJMP_c) {
538 TBB = LastInst->getOperand(1).getMBB();
539 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
540 Cond.push_back(LastInst->getOperand(0));
541 return false;
542 }
543 // Only supporting rr/ri versions of new-value jumps.
544 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
545 TBB = LastInst->getOperand(2).getMBB();
546 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
547 Cond.push_back(LastInst->getOperand(0));
548 Cond.push_back(LastInst->getOperand(1));
549 return false;
550 }
551 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
552 << " with one jump\n";);
553 // Otherwise, don't know what this is.
554 return true;
555 }
556
557 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
558 bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
559 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
560 if (!SecondLastInst->getOperand(1).isMBB())
561 return true;
562 TBB = SecondLastInst->getOperand(1).getMBB();
563 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
564 Cond.push_back(SecondLastInst->getOperand(0));
565 FBB = LastInst->getOperand(0).getMBB();
566 return false;
567 }
568
569 // Only supporting rr/ri versions of new-value jumps.
570 if (SecLastOpcodeHasNVJump &&
571 (SecondLastInst->getNumExplicitOperands() == 3) &&
572 (LastOpcode == Hexagon::J2_jump)) {
573 TBB = SecondLastInst->getOperand(2).getMBB();
574 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
575 Cond.push_back(SecondLastInst->getOperand(0));
576 Cond.push_back(SecondLastInst->getOperand(1));
577 FBB = LastInst->getOperand(0).getMBB();
578 return false;
579 }
580
581 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
582 // executed, so remove it.
583 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
584 TBB = SecondLastInst->getOperand(0).getMBB();
585 I = LastInst->getIterator();
586 if (AllowModify)
587 I->eraseFromParent();
588 return false;
589 }
590
591 // If the block ends with an ENDLOOP, and J2_jump, handle it.
592 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
593 TBB = SecondLastInst->getOperand(0).getMBB();
594 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
595 Cond.push_back(SecondLastInst->getOperand(0));
596 FBB = LastInst->getOperand(0).getMBB();
597 return false;
598 }
599 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
600 << " with two jumps";);
601 // Otherwise, can't handle this.
602 return true;
603}
604
606 int *BytesRemoved) const {
607 assert(!BytesRemoved && "code size not handled");
608
609 LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
611 unsigned Count = 0;
612 while (I != MBB.begin()) {
613 --I;
614 if (I->isDebugInstr())
615 continue;
616 // Only removing branches from end of MBB.
617 if (!I->isBranch())
618 return Count;
619 if (Count && (I->getOpcode() == Hexagon::J2_jump))
620 llvm_unreachable("Malformed basic block: unconditional branch not last");
621 MBB.erase(&MBB.back());
622 I = MBB.end();
623 ++Count;
624 }
625 return Count;
626}
627
632 const DebugLoc &DL,
633 int *BytesAdded) const {
634 unsigned BOpc = Hexagon::J2_jump;
635 unsigned BccOpc = Hexagon::J2_jumpt;
636 assert(validateBranchCond(Cond) && "Invalid branching condition");
637 assert(TBB && "insertBranch must not be told to insert a fallthrough");
638 assert(!BytesAdded && "code size not handled");
639
640 // Check if reverseBranchCondition has asked to reverse this branch
641 // If we want to reverse the branch an odd number of times, we want
642 // J2_jumpf.
643 if (!Cond.empty() && Cond[0].isImm())
644 BccOpc = Cond[0].getImm();
645
646 if (!FBB) {
647 if (Cond.empty()) {
648 // Due to a bug in TailMerging/CFG Optimization, we need to add a
649 // special case handling of a predicated jump followed by an
650 // unconditional jump. If not, Tail Merging and CFG Optimization go
651 // into an infinite loop.
652 MachineBasicBlock *NewTBB, *NewFBB;
654 auto Term = MBB.getFirstTerminator();
655 if (Term != MBB.end() && isPredicated(*Term) &&
656 !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
660 return insertBranch(MBB, TBB, nullptr, Cond, DL);
661 }
662 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
663 } else if (isEndLoopN(Cond[0].getImm())) {
664 int EndLoopOp = Cond[0].getImm();
665 assert(Cond[1].isMBB());
666 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
667 // Check for it, and change the BB target if needed.
669 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
670 VisitedBBs);
671 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
672 Loop->getOperand(0).setMBB(TBB);
673 // Add the ENDLOOP after the finding the LOOP0.
674 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
675 } else if (isNewValueJump(Cond[0].getImm())) {
676 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
677 // New value jump
678 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
679 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
680 unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
681 LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
683 if (Cond[2].isReg()) {
684 unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
685 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
686 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
687 } else if(Cond[2].isImm()) {
688 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
689 addImm(Cond[2].getImm()).addMBB(TBB);
690 } else
691 llvm_unreachable("Invalid condition for branching");
692 } else {
693 assert((Cond.size() == 2) && "Malformed cond vector");
694 const MachineOperand &RO = Cond[1];
695 unsigned Flags = getUndefRegState(RO.isUndef());
696 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
697 }
698 return 1;
699 }
700 assert((!Cond.empty()) &&
701 "Cond. cannot be empty when multiple branchings are required");
702 assert((!isNewValueJump(Cond[0].getImm())) &&
703 "NV-jump cannot be inserted with another branch");
704 // Special case for hardware loops. The condition is a basic block.
705 if (isEndLoopN(Cond[0].getImm())) {
706 int EndLoopOp = Cond[0].getImm();
707 assert(Cond[1].isMBB());
708 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
709 // Check for it, and change the BB target if needed.
711 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
712 VisitedBBs);
713 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
714 Loop->getOperand(0).setMBB(TBB);
715 // Add the ENDLOOP after the finding the LOOP0.
716 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
717 } else {
718 const MachineOperand &RO = Cond[1];
719 unsigned Flags = getUndefRegState(RO.isUndef());
720 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
721 }
722 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
723
724 return 2;
725}
726
727namespace {
728class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
729 MachineInstr *Loop, *EndLoop;
730 MachineFunction *MF;
731 const HexagonInstrInfo *TII;
732 int64_t TripCount;
733 Register LoopCount;
734 DebugLoc DL;
735
736public:
737 HexagonPipelinerLoopInfo(MachineInstr *Loop, MachineInstr *EndLoop)
738 : Loop(Loop), EndLoop(EndLoop), MF(Loop->getParent()->getParent()),
739 TII(MF->getSubtarget<HexagonSubtarget>().getInstrInfo()),
740 DL(Loop->getDebugLoc()) {
741 // Inspect the Loop instruction up-front, as it may be deleted when we call
742 // createTripCountGreaterCondition.
743 TripCount = Loop->getOpcode() == Hexagon::J2_loop0r
744 ? -1
745 : Loop->getOperand(1).getImm();
746 if (TripCount == -1)
747 LoopCount = Loop->getOperand(1).getReg();
748 }
749
750 bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
751 // Only ignore the terminator.
752 return MI == EndLoop;
753 }
754
755 std::optional<bool> createTripCountGreaterCondition(
756 int TC, MachineBasicBlock &MBB,
758 if (TripCount == -1) {
759 // Check if we're done with the loop.
760 Register Done = TII->createVR(MF, MVT::i1);
761 MachineInstr *NewCmp = BuildMI(&MBB, DL,
762 TII->get(Hexagon::C2_cmpgtui), Done)
763 .addReg(LoopCount)
764 .addImm(TC);
765 Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
766 Cond.push_back(NewCmp->getOperand(0));
767 return {};
768 }
769
770 return TripCount > TC;
771 }
772
773 void setPreheader(MachineBasicBlock *NewPreheader) override {
774 NewPreheader->splice(NewPreheader->getFirstTerminator(), Loop->getParent(),
775 Loop);
776 }
777
778 void adjustTripCount(int TripCountAdjust) override {
779 // If the loop trip count is a compile-time value, then just change the
780 // value.
781 if (Loop->getOpcode() == Hexagon::J2_loop0i ||
782 Loop->getOpcode() == Hexagon::J2_loop1i) {
783 int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust;
784 assert(TripCount > 0 && "Can't create an empty or negative loop!");
785 Loop->getOperand(1).setImm(TripCount);
786 return;
787 }
788
789 // The loop trip count is a run-time value. We generate code to subtract
790 // one from the trip count, and update the loop instruction.
791 Register LoopCount = Loop->getOperand(1).getReg();
792 Register NewLoopCount = TII->createVR(MF, MVT::i32);
793 BuildMI(*Loop->getParent(), Loop, Loop->getDebugLoc(),
794 TII->get(Hexagon::A2_addi), NewLoopCount)
795 .addReg(LoopCount)
796 .addImm(TripCountAdjust);
797 Loop->getOperand(1).setReg(NewLoopCount);
798 }
799
800 void disposed() override { Loop->eraseFromParent(); }
801};
802} // namespace
803
804std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
806 // We really "analyze" only hardware loops right now.
808
809 if (I != LoopBB->end() && isEndLoopN(I->getOpcode())) {
811 MachineInstr *LoopInst = findLoopInstr(
812 LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
813 if (LoopInst)
814 return std::make_unique<HexagonPipelinerLoopInfo>(LoopInst, &*I);
815 }
816 return nullptr;
817}
818
820 unsigned NumCycles, unsigned ExtraPredCycles,
821 BranchProbability Probability) const {
822 return nonDbgBBSize(&MBB) <= 3;
823}
824
826 unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
827 unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
828 const {
829 return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
830}
831
833 unsigned NumInstrs, BranchProbability Probability) const {
834 return NumInstrs <= 4;
835}
836
837static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
839 const MachineBasicBlock &B = *MI.getParent();
840 Regs.addLiveIns(B);
841 auto E = MachineBasicBlock::const_iterator(MI.getIterator());
842 for (auto I = B.begin(); I != E; ++I) {
843 Clobbers.clear();
844 Regs.stepForward(*I, Clobbers);
845 }
846}
847
848static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
849 const MachineBasicBlock &B = *MI.getParent();
850 Regs.addLiveOuts(B);
851 auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
852 for (auto I = B.rbegin(); I != E; ++I)
853 Regs.stepBackward(*I);
854}
855
858 const DebugLoc &DL, MCRegister DestReg,
859 MCRegister SrcReg, bool KillSrc) const {
860 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
861 unsigned KillFlag = getKillRegState(KillSrc);
862
863 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
864 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
865 .addReg(SrcReg, KillFlag);
866 return;
867 }
868 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
869 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
870 .addReg(SrcReg, KillFlag);
871 return;
872 }
873 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
874 // Map Pd = Ps to Pd = or(Ps, Ps).
875 BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
876 .addReg(SrcReg).addReg(SrcReg, KillFlag);
877 return;
878 }
879 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
880 Hexagon::IntRegsRegClass.contains(SrcReg)) {
881 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
882 .addReg(SrcReg, KillFlag);
883 return;
884 }
885 if (Hexagon::IntRegsRegClass.contains(DestReg) &&
886 Hexagon::CtrRegsRegClass.contains(SrcReg)) {
887 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
888 .addReg(SrcReg, KillFlag);
889 return;
890 }
891 if (Hexagon::ModRegsRegClass.contains(DestReg) &&
892 Hexagon::IntRegsRegClass.contains(SrcReg)) {
893 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
894 .addReg(SrcReg, KillFlag);
895 return;
896 }
897 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
898 Hexagon::IntRegsRegClass.contains(DestReg)) {
899 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
900 .addReg(SrcReg, KillFlag);
901 return;
902 }
903 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
904 Hexagon::PredRegsRegClass.contains(DestReg)) {
905 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
906 .addReg(SrcReg, KillFlag);
907 return;
908 }
909 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
910 Hexagon::IntRegsRegClass.contains(DestReg)) {
911 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
912 .addReg(SrcReg, KillFlag);
913 return;
914 }
915 if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
916 BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
917 addReg(SrcReg, KillFlag);
918 return;
919 }
920 if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
921 LivePhysRegs LiveAtMI(HRI);
922 getLiveInRegsAt(LiveAtMI, *I);
923 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
924 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
925 unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo));
926 unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi));
927 BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
928 .addReg(SrcHi, KillFlag | UndefHi)
929 .addReg(SrcLo, KillFlag | UndefLo);
930 return;
931 }
932 if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
933 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
934 .addReg(SrcReg)
935 .addReg(SrcReg, KillFlag);
936 return;
937 }
938 if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
939 Hexagon::HvxVRRegClass.contains(DestReg)) {
940 llvm_unreachable("Unimplemented pred to vec");
941 return;
942 }
943 if (Hexagon::HvxQRRegClass.contains(DestReg) &&
944 Hexagon::HvxVRRegClass.contains(SrcReg)) {
945 llvm_unreachable("Unimplemented vec to pred");
946 return;
947 }
948
949#ifndef NDEBUG
950 // Show the invalid registers to ease debugging.
951 dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
952 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
953#endif
954 llvm_unreachable("Unimplemented");
955}
956
959 Register SrcReg, bool isKill, int FI,
960 const TargetRegisterClass *RC,
961 const TargetRegisterInfo *TRI,
962 Register VReg) const {
965 MachineFrameInfo &MFI = MF.getFrameInfo();
966 unsigned KillFlag = getKillRegState(isKill);
967
970 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
971
972 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
973 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
974 .addFrameIndex(FI).addImm(0)
975 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
976 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
977 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
978 .addFrameIndex(FI).addImm(0)
979 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
980 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
981 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
982 .addFrameIndex(FI).addImm(0)
983 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
984 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
985 BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
986 .addFrameIndex(FI).addImm(0)
987 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
988 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
989 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
990 .addFrameIndex(FI).addImm(0)
991 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
992 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
993 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerv_ai))
994 .addFrameIndex(FI).addImm(0)
995 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
996 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
997 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerw_ai))
998 .addFrameIndex(FI).addImm(0)
999 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
1000 } else {
1001 llvm_unreachable("Unimplemented");
1002 }
1003}
1004
1007 Register DestReg, int FI,
1008 const TargetRegisterClass *RC,
1009 const TargetRegisterInfo *TRI,
1010 Register VReg) const {
1012 MachineFunction &MF = *MBB.getParent();
1013 MachineFrameInfo &MFI = MF.getFrameInfo();
1014
1017 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
1018
1019 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
1020 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
1021 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1022 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
1023 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
1024 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1025 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
1026 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
1027 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1028 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
1029 BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
1030 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1031 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
1032 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
1033 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1034 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
1035 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrv_ai), DestReg)
1036 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1037 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1038 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrw_ai), DestReg)
1039 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1040 } else {
1041 llvm_unreachable("Can't store this register to stack slot");
1042 }
1043}
1044
1045/// expandPostRAPseudo - This function is called for all pseudo instructions
1046/// that remain after register allocation. Many pseudo instructions are
1047/// created to help register allocation. This is the place to convert them
1048/// into real instructions. The target can edit MI in place, or it can insert
1049/// new instructions and erase MI. The function should return true if
1050/// anything was changed.
1052 MachineBasicBlock &MBB = *MI.getParent();
1053 MachineFunction &MF = *MBB.getParent();
1055 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1056 LivePhysRegs LiveIn(HRI), LiveOut(HRI);
1057 DebugLoc DL = MI.getDebugLoc();
1058 unsigned Opc = MI.getOpcode();
1059
1060 auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1061 Register Mx = MI.getOperand(MxOp).getReg();
1062 Register CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1063 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1064 .add(MI.getOperand((HasImm ? 5 : 4)));
1065 auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1066 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1067 if (HasImm)
1068 MIB.add(MI.getOperand(4));
1069 MIB.addReg(CSx, RegState::Implicit);
1070 MBB.erase(MI);
1071 return true;
1072 };
1073
1074 auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) {
1075 if (MI.memoperands().empty())
1076 return false;
1077 return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) {
1078 return MMO->getAlign() >= NeedAlign;
1079 });
1080 };
1081
1082 switch (Opc) {
1083 case Hexagon::PS_call_instrprof_custom: {
1084 auto Op0 = MI.getOperand(0);
1085 assert(Op0.isGlobal() &&
1086 "First operand must be a global containing handler name.");
1087 const GlobalValue *NameVar = Op0.getGlobal();
1088 const GlobalVariable *GV = dyn_cast<GlobalVariable>(NameVar);
1089 auto *Arr = cast<ConstantDataArray>(GV->getInitializer());
1090 StringRef NameStr = Arr->isCString() ? Arr->getAsCString() : Arr->getAsString();
1091
1092 MachineOperand &Op1 = MI.getOperand(1);
1093 // Set R0 with the imm value to be passed to the custom profiling handler.
1094 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrsi), Hexagon::R0)
1095 .addImm(Op1.getImm());
1096 // The call to the custom handler is being treated as a special one as the
1097 // callee is responsible for saving and restoring all the registers
1098 // (including caller saved registers) it needs to modify. This is
1099 // done to reduce the impact of instrumentation on the code being
1100 // instrumented/profiled.
1101 // NOTE: R14, R15 and R28 are reserved for PLT handling. These registers
1102 // are in the Def list of the Hexagon::PS_call_instrprof_custom and
1103 // therefore will be handled appropriately duing register allocation.
1104
1105 // TODO: It may be a good idea to add a separate pseudo instruction for
1106 // static relocation which doesn't need to reserve r14, r15 and r28.
1107
1108 auto MIB = BuildMI(MBB, MI, DL, get(Hexagon::J2_call))
1110 .addDef(Hexagon::R29, RegState::ImplicitDefine)
1111 .addDef(Hexagon::R30, RegState::ImplicitDefine)
1112 .addDef(Hexagon::R14, RegState::ImplicitDefine)
1113 .addDef(Hexagon::R15, RegState::ImplicitDefine)
1114 .addDef(Hexagon::R28, RegState::ImplicitDefine);
1115 const char *cstr = MF.createExternalSymbolName(NameStr);
1116 MIB.addExternalSymbol(cstr);
1117 MBB.erase(MI);
1118 return true;
1119 }
1120 case TargetOpcode::COPY: {
1121 MachineOperand &MD = MI.getOperand(0);
1122 MachineOperand &MS = MI.getOperand(1);
1123 MachineBasicBlock::iterator MBBI = MI.getIterator();
1124 if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1125 copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1126 std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1127 }
1128 MBB.erase(MBBI);
1129 return true;
1130 }
1131 case Hexagon::PS_aligna:
1132 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1133 .addReg(HRI.getFrameRegister())
1134 .addImm(-MI.getOperand(1).getImm());
1135 MBB.erase(MI);
1136 return true;
1137 case Hexagon::V6_vassignp: {
1138 Register SrcReg = MI.getOperand(1).getReg();
1139 Register DstReg = MI.getOperand(0).getReg();
1140 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1141 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1142 getLiveInRegsAt(LiveIn, MI);
1143 unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
1144 unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));
1145 unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1146 BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1147 .addReg(SrcHi, UndefHi)
1148 .addReg(SrcLo, Kill | UndefLo);
1149 MBB.erase(MI);
1150 return true;
1151 }
1152 case Hexagon::V6_lo: {
1153 Register SrcReg = MI.getOperand(1).getReg();
1154 Register DstReg = MI.getOperand(0).getReg();
1155 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1156 copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1157 MBB.erase(MI);
1158 MRI.clearKillFlags(SrcSubLo);
1159 return true;
1160 }
1161 case Hexagon::V6_hi: {
1162 Register SrcReg = MI.getOperand(1).getReg();
1163 Register DstReg = MI.getOperand(0).getReg();
1164 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1165 copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1166 MBB.erase(MI);
1167 MRI.clearKillFlags(SrcSubHi);
1168 return true;
1169 }
1170 case Hexagon::PS_vloadrv_ai: {
1171 Register DstReg = MI.getOperand(0).getReg();
1172 const MachineOperand &BaseOp = MI.getOperand(1);
1173 assert(BaseOp.getSubReg() == 0);
1174 int Offset = MI.getOperand(2).getImm();
1175 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1176 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1177 : Hexagon::V6_vL32Ub_ai;
1178 BuildMI(MBB, MI, DL, get(NewOpc), DstReg)
1179 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1180 .addImm(Offset)
1181 .cloneMemRefs(MI);
1182 MBB.erase(MI);
1183 return true;
1184 }
1185 case Hexagon::PS_vloadrw_ai: {
1186 Register DstReg = MI.getOperand(0).getReg();
1187 const MachineOperand &BaseOp = MI.getOperand(1);
1188 assert(BaseOp.getSubReg() == 0);
1189 int Offset = MI.getOperand(2).getImm();
1190 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1191 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1192 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1193 : Hexagon::V6_vL32Ub_ai;
1194 BuildMI(MBB, MI, DL, get(NewOpc),
1195 HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1196 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1197 .addImm(Offset)
1198 .cloneMemRefs(MI);
1199 BuildMI(MBB, MI, DL, get(NewOpc),
1200 HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1201 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1202 .addImm(Offset + VecOffset)
1203 .cloneMemRefs(MI);
1204 MBB.erase(MI);
1205 return true;
1206 }
1207 case Hexagon::PS_vstorerv_ai: {
1208 const MachineOperand &SrcOp = MI.getOperand(2);
1209 assert(SrcOp.getSubReg() == 0);
1210 const MachineOperand &BaseOp = MI.getOperand(0);
1211 assert(BaseOp.getSubReg() == 0);
1212 int Offset = MI.getOperand(1).getImm();
1213 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1214 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1215 : Hexagon::V6_vS32Ub_ai;
1216 BuildMI(MBB, MI, DL, get(NewOpc))
1217 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1218 .addImm(Offset)
1220 .cloneMemRefs(MI);
1221 MBB.erase(MI);
1222 return true;
1223 }
1224 case Hexagon::PS_vstorerw_ai: {
1225 Register SrcReg = MI.getOperand(2).getReg();
1226 const MachineOperand &BaseOp = MI.getOperand(0);
1227 assert(BaseOp.getSubReg() == 0);
1228 int Offset = MI.getOperand(1).getImm();
1229 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1230 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1231 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1232 : Hexagon::V6_vS32Ub_ai;
1233 BuildMI(MBB, MI, DL, get(NewOpc))
1234 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1235 .addImm(Offset)
1236 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo))
1237 .cloneMemRefs(MI);
1238 BuildMI(MBB, MI, DL, get(NewOpc))
1239 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1240 .addImm(Offset + VecOffset)
1241 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi))
1242 .cloneMemRefs(MI);
1243 MBB.erase(MI);
1244 return true;
1245 }
1246 case Hexagon::PS_true: {
1247 Register Reg = MI.getOperand(0).getReg();
1248 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1249 .addReg(Reg, RegState::Undef)
1250 .addReg(Reg, RegState::Undef);
1251 MBB.erase(MI);
1252 return true;
1253 }
1254 case Hexagon::PS_false: {
1255 Register Reg = MI.getOperand(0).getReg();
1256 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1257 .addReg(Reg, RegState::Undef)
1258 .addReg(Reg, RegState::Undef);
1259 MBB.erase(MI);
1260 return true;
1261 }
1262 case Hexagon::PS_qtrue: {
1263 BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1264 .addReg(Hexagon::V0, RegState::Undef)
1265 .addReg(Hexagon::V0, RegState::Undef);
1266 MBB.erase(MI);
1267 return true;
1268 }
1269 case Hexagon::PS_qfalse: {
1270 BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1271 .addReg(Hexagon::V0, RegState::Undef)
1272 .addReg(Hexagon::V0, RegState::Undef);
1273 MBB.erase(MI);
1274 return true;
1275 }
1276 case Hexagon::PS_vdd0: {
1277 Register Vd = MI.getOperand(0).getReg();
1278 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1280 .addReg(Vd, RegState::Undef);
1281 MBB.erase(MI);
1282 return true;
1283 }
1284 case Hexagon::PS_vmulw: {
1285 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1286 Register DstReg = MI.getOperand(0).getReg();
1287 Register Src1Reg = MI.getOperand(1).getReg();
1288 Register Src2Reg = MI.getOperand(2).getReg();
1289 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1290 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1291 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1292 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1293 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1294 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1295 .addReg(Src1SubHi)
1296 .addReg(Src2SubHi);
1297 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1298 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1299 .addReg(Src1SubLo)
1300 .addReg(Src2SubLo);
1301 MBB.erase(MI);
1302 MRI.clearKillFlags(Src1SubHi);
1303 MRI.clearKillFlags(Src1SubLo);
1304 MRI.clearKillFlags(Src2SubHi);
1305 MRI.clearKillFlags(Src2SubLo);
1306 return true;
1307 }
1308 case Hexagon::PS_vmulw_acc: {
1309 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1310 Register DstReg = MI.getOperand(0).getReg();
1311 Register Src1Reg = MI.getOperand(1).getReg();
1312 Register Src2Reg = MI.getOperand(2).getReg();
1313 Register Src3Reg = MI.getOperand(3).getReg();
1314 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1315 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1316 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1317 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1318 Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1319 Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1320 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1321 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1322 .addReg(Src1SubHi)
1323 .addReg(Src2SubHi)
1324 .addReg(Src3SubHi);
1325 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1326 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1327 .addReg(Src1SubLo)
1328 .addReg(Src2SubLo)
1329 .addReg(Src3SubLo);
1330 MBB.erase(MI);
1331 MRI.clearKillFlags(Src1SubHi);
1332 MRI.clearKillFlags(Src1SubLo);
1333 MRI.clearKillFlags(Src2SubHi);
1334 MRI.clearKillFlags(Src2SubLo);
1335 MRI.clearKillFlags(Src3SubHi);
1336 MRI.clearKillFlags(Src3SubLo);
1337 return true;
1338 }
1339 case Hexagon::PS_pselect: {
1340 const MachineOperand &Op0 = MI.getOperand(0);
1341 const MachineOperand &Op1 = MI.getOperand(1);
1342 const MachineOperand &Op2 = MI.getOperand(2);
1343 const MachineOperand &Op3 = MI.getOperand(3);
1344 Register Rd = Op0.getReg();
1345 Register Pu = Op1.getReg();
1346 Register Rs = Op2.getReg();
1347 Register Rt = Op3.getReg();
1348 DebugLoc DL = MI.getDebugLoc();
1349 unsigned K1 = getKillRegState(Op1.isKill());
1350 unsigned K2 = getKillRegState(Op2.isKill());
1351 unsigned K3 = getKillRegState(Op3.isKill());
1352 if (Rd != Rs)
1353 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1354 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1355 .addReg(Rs, K2);
1356 if (Rd != Rt)
1357 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1358 .addReg(Pu, K1)
1359 .addReg(Rt, K3);
1360 MBB.erase(MI);
1361 return true;
1362 }
1363 case Hexagon::PS_vselect: {
1364 const MachineOperand &Op0 = MI.getOperand(0);
1365 const MachineOperand &Op1 = MI.getOperand(1);
1366 const MachineOperand &Op2 = MI.getOperand(2);
1367 const MachineOperand &Op3 = MI.getOperand(3);
1368 getLiveOutRegsAt(LiveOut, MI);
1369 bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
1370 Register PReg = Op1.getReg();
1371 assert(Op1.getSubReg() == 0);
1372 unsigned PState = getRegState(Op1);
1373
1374 if (Op0.getReg() != Op2.getReg()) {
1375 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1376 : PState;
1377 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1378 .add(Op0)
1379 .addReg(PReg, S)
1380 .add(Op2);
1381 if (IsDestLive)
1382 T.addReg(Op0.getReg(), RegState::Implicit);
1383 IsDestLive = true;
1384 }
1385 if (Op0.getReg() != Op3.getReg()) {
1386 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1387 .add(Op0)
1388 .addReg(PReg, PState)
1389 .add(Op3);
1390 if (IsDestLive)
1391 T.addReg(Op0.getReg(), RegState::Implicit);
1392 }
1393 MBB.erase(MI);
1394 return true;
1395 }
1396 case Hexagon::PS_wselect: {
1397 MachineOperand &Op0 = MI.getOperand(0);
1398 MachineOperand &Op1 = MI.getOperand(1);
1399 MachineOperand &Op2 = MI.getOperand(2);
1400 MachineOperand &Op3 = MI.getOperand(3);
1401 getLiveOutRegsAt(LiveOut, MI);
1402 bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
1403 Register PReg = Op1.getReg();
1404 assert(Op1.getSubReg() == 0);
1405 unsigned PState = getRegState(Op1);
1406
1407 if (Op0.getReg() != Op2.getReg()) {
1408 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1409 : PState;
1410 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1411 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1412 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1413 .add(Op0)
1414 .addReg(PReg, S)
1415 .addReg(SrcHi)
1416 .addReg(SrcLo);
1417 if (IsDestLive)
1418 T.addReg(Op0.getReg(), RegState::Implicit);
1419 IsDestLive = true;
1420 }
1421 if (Op0.getReg() != Op3.getReg()) {
1422 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1423 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1424 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1425 .add(Op0)
1426 .addReg(PReg, PState)
1427 .addReg(SrcHi)
1428 .addReg(SrcLo);
1429 if (IsDestLive)
1430 T.addReg(Op0.getReg(), RegState::Implicit);
1431 }
1432 MBB.erase(MI);
1433 return true;
1434 }
1435
1436 case Hexagon::PS_crash: {
1437 // Generate a misaligned load that is guaranteed to cause a crash.
1438 class CrashPseudoSourceValue : public PseudoSourceValue {
1439 public:
1440 CrashPseudoSourceValue(const TargetMachine &TM)
1441 : PseudoSourceValue(TargetCustom, TM) {}
1442
1443 bool isConstant(const MachineFrameInfo *) const override {
1444 return false;
1445 }
1446 bool isAliased(const MachineFrameInfo *) const override {
1447 return false;
1448 }
1449 bool mayAlias(const MachineFrameInfo *) const override {
1450 return false;
1451 }
1452 void printCustom(raw_ostream &OS) const override {
1453 OS << "MisalignedCrash";
1454 }
1455 };
1456
1457 static const CrashPseudoSourceValue CrashPSV(MF.getTarget());
1459 MachinePointerInfo(&CrashPSV),
1461 Align(1));
1462 BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
1463 .addImm(0xBADC0FEE) // Misaligned load.
1464 .addMemOperand(MMO);
1465 MBB.erase(MI);
1466 return true;
1467 }
1468
1469 case Hexagon::PS_tailcall_i:
1470 MI.setDesc(get(Hexagon::J2_jump));
1471 return true;
1472 case Hexagon::PS_tailcall_r:
1473 case Hexagon::PS_jmpret:
1474 MI.setDesc(get(Hexagon::J2_jumpr));
1475 return true;
1476 case Hexagon::PS_jmprett:
1477 MI.setDesc(get(Hexagon::J2_jumprt));
1478 return true;
1479 case Hexagon::PS_jmpretf:
1480 MI.setDesc(get(Hexagon::J2_jumprf));
1481 return true;
1482 case Hexagon::PS_jmprettnewpt:
1483 MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1484 return true;
1485 case Hexagon::PS_jmpretfnewpt:
1486 MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1487 return true;
1488 case Hexagon::PS_jmprettnew:
1489 MI.setDesc(get(Hexagon::J2_jumprtnew));
1490 return true;
1491 case Hexagon::PS_jmpretfnew:
1492 MI.setDesc(get(Hexagon::J2_jumprfnew));
1493 return true;
1494
1495 case Hexagon::PS_loadrub_pci:
1496 return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1497 case Hexagon::PS_loadrb_pci:
1498 return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1499 case Hexagon::PS_loadruh_pci:
1500 return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1501 case Hexagon::PS_loadrh_pci:
1502 return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1503 case Hexagon::PS_loadri_pci:
1504 return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1505 case Hexagon::PS_loadrd_pci:
1506 return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1507 case Hexagon::PS_loadrub_pcr:
1508 return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1509 case Hexagon::PS_loadrb_pcr:
1510 return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1511 case Hexagon::PS_loadruh_pcr:
1512 return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1513 case Hexagon::PS_loadrh_pcr:
1514 return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1515 case Hexagon::PS_loadri_pcr:
1516 return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1517 case Hexagon::PS_loadrd_pcr:
1518 return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1519 case Hexagon::PS_storerb_pci:
1520 return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1521 case Hexagon::PS_storerh_pci:
1522 return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1523 case Hexagon::PS_storerf_pci:
1524 return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1525 case Hexagon::PS_storeri_pci:
1526 return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1527 case Hexagon::PS_storerd_pci:
1528 return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1529 case Hexagon::PS_storerb_pcr:
1530 return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1531 case Hexagon::PS_storerh_pcr:
1532 return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1533 case Hexagon::PS_storerf_pcr:
1534 return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1535 case Hexagon::PS_storeri_pcr:
1536 return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1537 case Hexagon::PS_storerd_pcr:
1538 return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1539 }
1540
1541 return false;
1542}
1543
1546 MachineBasicBlock &MBB = *MI.getParent();
1547 const DebugLoc &DL = MI.getDebugLoc();
1548 unsigned Opc = MI.getOpcode();
1550
1551 switch (Opc) {
1552 case Hexagon::V6_vgathermh_pseudo:
1553 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1554 .add(MI.getOperand(2))
1555 .add(MI.getOperand(3))
1556 .add(MI.getOperand(4));
1557 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1558 .add(MI.getOperand(0))
1559 .addImm(MI.getOperand(1).getImm())
1560 .addReg(Hexagon::VTMP);
1561 MBB.erase(MI);
1562 return First.getInstrIterator();
1563
1564 case Hexagon::V6_vgathermw_pseudo:
1565 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1566 .add(MI.getOperand(2))
1567 .add(MI.getOperand(3))
1568 .add(MI.getOperand(4));
1569 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1570 .add(MI.getOperand(0))
1571 .addImm(MI.getOperand(1).getImm())
1572 .addReg(Hexagon::VTMP);
1573 MBB.erase(MI);
1574 return First.getInstrIterator();
1575
1576 case Hexagon::V6_vgathermhw_pseudo:
1577 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1578 .add(MI.getOperand(2))
1579 .add(MI.getOperand(3))
1580 .add(MI.getOperand(4));
1581 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1582 .add(MI.getOperand(0))
1583 .addImm(MI.getOperand(1).getImm())
1584 .addReg(Hexagon::VTMP);
1585 MBB.erase(MI);
1586 return First.getInstrIterator();
1587
1588 case Hexagon::V6_vgathermhq_pseudo:
1589 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1590 .add(MI.getOperand(2))
1591 .add(MI.getOperand(3))
1592 .add(MI.getOperand(4))
1593 .add(MI.getOperand(5));
1594 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1595 .add(MI.getOperand(0))
1596 .addImm(MI.getOperand(1).getImm())
1597 .addReg(Hexagon::VTMP);
1598 MBB.erase(MI);
1599 return First.getInstrIterator();
1600
1601 case Hexagon::V6_vgathermwq_pseudo:
1602 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1603 .add(MI.getOperand(2))
1604 .add(MI.getOperand(3))
1605 .add(MI.getOperand(4))
1606 .add(MI.getOperand(5));
1607 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1608 .add(MI.getOperand(0))
1609 .addImm(MI.getOperand(1).getImm())
1610 .addReg(Hexagon::VTMP);
1611 MBB.erase(MI);
1612 return First.getInstrIterator();
1613
1614 case Hexagon::V6_vgathermhwq_pseudo:
1615 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1616 .add(MI.getOperand(2))
1617 .add(MI.getOperand(3))
1618 .add(MI.getOperand(4))
1619 .add(MI.getOperand(5));
1620 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1621 .add(MI.getOperand(0))
1622 .addImm(MI.getOperand(1).getImm())
1623 .addReg(Hexagon::VTMP);
1624 MBB.erase(MI);
1625 return First.getInstrIterator();
1626 }
1627
1628 return MI.getIterator();
1629}
1630
1631// We indicate that we want to reverse the branch by
1632// inserting the reversed branching opcode.
1635 if (Cond.empty())
1636 return true;
1637 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1638 unsigned opcode = Cond[0].getImm();
1639 //unsigned temp;
1640 assert(get(opcode).isBranch() && "Should be a branching condition.");
1641 if (isEndLoopN(opcode))
1642 return true;
1643 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1644 Cond[0].setImm(NewOpcode);
1645 return false;
1646}
1647
1650 DebugLoc DL;
1651 BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1652}
1653
1656}
1657
1658// Returns true if an instruction is predicated irrespective of the predicate
1659// sense. For example, all of the following will return true.
1660// if (p0) R1 = add(R2, R3)
1661// if (!p0) R1 = add(R2, R3)
1662// if (p0.new) R1 = add(R2, R3)
1663// if (!p0.new) R1 = add(R2, R3)
1664// Note: New-value stores are not included here as in the current
1665// implementation, we don't need to check their predicate sense.
1667 const uint64_t F = MI.getDesc().TSFlags;
1669}
1670
1673 if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1674 isEndLoopN(Cond[0].getImm())) {
1675 LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1676 return false;
1677 }
1678 int Opc = MI.getOpcode();
1679 assert (isPredicable(MI) && "Expected predicable instruction");
1680 bool invertJump = predOpcodeHasNot(Cond);
1681
1682 // We have to predicate MI "in place", i.e. after this function returns,
1683 // MI will need to be transformed into a predicated form. To avoid com-
1684 // plicated manipulations with the operands (handling tied operands,
1685 // etc.), build a new temporary instruction, then overwrite MI with it.
1686
1687 MachineBasicBlock &B = *MI.getParent();
1688 DebugLoc DL = MI.getDebugLoc();
1689 unsigned PredOpc = getCondOpcode(Opc, invertJump);
1690 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1691 unsigned NOp = 0, NumOps = MI.getNumOperands();
1692 while (NOp < NumOps) {
1693 MachineOperand &Op = MI.getOperand(NOp);
1694 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1695 break;
1696 T.add(Op);
1697 NOp++;
1698 }
1699
1700 Register PredReg;
1701 unsigned PredRegPos, PredRegFlags;
1702 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1703 (void)GotPredReg;
1704 assert(GotPredReg);
1705 T.addReg(PredReg, PredRegFlags);
1706 while (NOp < NumOps)
1707 T.add(MI.getOperand(NOp++));
1708
1709 MI.setDesc(get(PredOpc));
1710 while (unsigned n = MI.getNumOperands())
1711 MI.removeOperand(n-1);
1712 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1713 MI.addOperand(T->getOperand(i));
1714
1715 MachineBasicBlock::instr_iterator TI = T->getIterator();
1716 B.erase(TI);
1717
1718 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1719 MRI.clearKillFlags(PredReg);
1720 return true;
1721}
1722
1724 ArrayRef<MachineOperand> Pred2) const {
1725 // TODO: Fix this
1726 return false;
1727}
1728
1730 std::vector<MachineOperand> &Pred,
1731 bool SkipDead) const {
1732 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1733
1734 for (const MachineOperand &MO : MI.operands()) {
1735 if (MO.isReg()) {
1736 if (!MO.isDef())
1737 continue;
1738 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1739 if (RC == &Hexagon::PredRegsRegClass) {
1740 Pred.push_back(MO);
1741 return true;
1742 }
1743 continue;
1744 } else if (MO.isRegMask()) {
1745 for (Register PR : Hexagon::PredRegsRegClass) {
1746 if (!MI.modifiesRegister(PR, &HRI))
1747 continue;
1748 Pred.push_back(MO);
1749 return true;
1750 }
1751 }
1752 }
1753 return false;
1754}
1755
1757 if (!MI.getDesc().isPredicable())
1758 return false;
1759
1760 if (MI.isCall() || isTailCall(MI)) {
1761 if (!Subtarget.usePredicatedCalls())
1762 return false;
1763 }
1764
1765 // HVX loads are not predicable on v60, but are on v62.
1766 if (!Subtarget.hasV62Ops()) {
1767 switch (MI.getOpcode()) {
1768 case Hexagon::V6_vL32b_ai:
1769 case Hexagon::V6_vL32b_pi:
1770 case Hexagon::V6_vL32b_ppu:
1771 case Hexagon::V6_vL32b_cur_ai:
1772 case Hexagon::V6_vL32b_cur_pi:
1773 case Hexagon::V6_vL32b_cur_ppu:
1774 case Hexagon::V6_vL32b_nt_ai:
1775 case Hexagon::V6_vL32b_nt_pi:
1776 case Hexagon::V6_vL32b_nt_ppu:
1777 case Hexagon::V6_vL32b_tmp_ai:
1778 case Hexagon::V6_vL32b_tmp_pi:
1779 case Hexagon::V6_vL32b_tmp_ppu:
1780 case Hexagon::V6_vL32b_nt_cur_ai:
1781 case Hexagon::V6_vL32b_nt_cur_pi:
1782 case Hexagon::V6_vL32b_nt_cur_ppu:
1783 case Hexagon::V6_vL32b_nt_tmp_ai:
1784 case Hexagon::V6_vL32b_nt_tmp_pi:
1785 case Hexagon::V6_vL32b_nt_tmp_ppu:
1786 return false;
1787 }
1788 }
1789 return true;
1790}
1791
1793 const MachineBasicBlock *MBB,
1794 const MachineFunction &MF) const {
1795 // Debug info is never a scheduling boundary. It's necessary to be explicit
1796 // due to the special treatment of IT instructions below, otherwise a
1797 // dbg_value followed by an IT will result in the IT instruction being
1798 // considered a scheduling hazard, which is wrong. It should be the actual
1799 // instruction preceding the dbg_value instruction(s), just like it is
1800 // when debug info is not present.
1801 if (MI.isDebugInstr())
1802 return false;
1803
1804 // Throwing call is a boundary.
1805 if (MI.isCall()) {
1806 // Don't mess around with no return calls.
1807 if (doesNotReturn(MI))
1808 return true;
1809 // If any of the block's successors is a landing pad, this could be a
1810 // throwing call.
1811 for (auto *I : MBB->successors())
1812 if (I->isEHPad())
1813 return true;
1814 }
1815
1816 // Terminators and labels can't be scheduled around.
1817 if (MI.getDesc().isTerminator() || MI.isPosition())
1818 return true;
1819
1820 // INLINEASM_BR can jump to another block
1821 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1822 return true;
1823
1824 if (MI.isInlineAsm() && !ScheduleInlineAsm)
1825 return true;
1826
1827 return false;
1828}
1829
1830/// Measure the specified inline asm to determine an approximation of its
1831/// length.
1832/// Comments (which run till the next SeparatorString or newline) do not
1833/// count as an instruction.
1834/// Any other non-whitespace text is considered an instruction, with
1835/// multiple instructions separated by SeparatorString or newlines.
1836/// Variable-length instructions are not handled here; this function
1837/// may be overloaded in the target code to do that.
1838/// Hexagon counts the number of ##'s and adjust for that many
1839/// constant exenders.
1841 const MCAsmInfo &MAI,
1842 const TargetSubtargetInfo *STI) const {
1843 StringRef AStr(Str);
1844 // Count the number of instructions in the asm.
1845 bool atInsnStart = true;
1846 unsigned Length = 0;
1847 const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
1848 for (; *Str; ++Str) {
1849 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1850 strlen(MAI.getSeparatorString())) == 0)
1851 atInsnStart = true;
1852 if (atInsnStart && !isSpace(static_cast<unsigned char>(*Str))) {
1853 Length += MaxInstLength;
1854 atInsnStart = false;
1855 }
1856 if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1857 MAI.getCommentString().size()) == 0)
1858 atInsnStart = false;
1859 }
1860
1861 // Add to size number of constant extenders seen * 4.
1862 StringRef Occ("##");
1863 Length += AStr.count(Occ)*4;
1864 return Length;
1865}
1866
1869 const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1870 if (UseDFAHazardRec)
1871 return new HexagonHazardRecognizer(II, this, Subtarget);
1873}
1874
1875/// For a comparison instruction, return the source registers in
1876/// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1877/// compares against in CmpValue. Return true if the comparison instruction
1878/// can be analyzed.
1880 Register &SrcReg2, int64_t &Mask,
1881 int64_t &Value) const {
1882 unsigned Opc = MI.getOpcode();
1883
1884 // Set mask and the first source register.
1885 switch (Opc) {
1886 case Hexagon::C2_cmpeq:
1887 case Hexagon::C2_cmpeqp:
1888 case Hexagon::C2_cmpgt:
1889 case Hexagon::C2_cmpgtp:
1890 case Hexagon::C2_cmpgtu:
1891 case Hexagon::C2_cmpgtup:
1892 case Hexagon::C4_cmpneq:
1893 case Hexagon::C4_cmplte:
1894 case Hexagon::C4_cmplteu:
1895 case Hexagon::C2_cmpeqi:
1896 case Hexagon::C2_cmpgti:
1897 case Hexagon::C2_cmpgtui:
1898 case Hexagon::C4_cmpneqi:
1899 case Hexagon::C4_cmplteui:
1900 case Hexagon::C4_cmpltei:
1901 SrcReg = MI.getOperand(1).getReg();
1902 Mask = ~0;
1903 break;
1904 case Hexagon::A4_cmpbeq:
1905 case Hexagon::A4_cmpbgt:
1906 case Hexagon::A4_cmpbgtu:
1907 case Hexagon::A4_cmpbeqi:
1908 case Hexagon::A4_cmpbgti:
1909 case Hexagon::A4_cmpbgtui:
1910 SrcReg = MI.getOperand(1).getReg();
1911 Mask = 0xFF;
1912 break;
1913 case Hexagon::A4_cmpheq:
1914 case Hexagon::A4_cmphgt:
1915 case Hexagon::A4_cmphgtu:
1916 case Hexagon::A4_cmpheqi:
1917 case Hexagon::A4_cmphgti:
1918 case Hexagon::A4_cmphgtui:
1919 SrcReg = MI.getOperand(1).getReg();
1920 Mask = 0xFFFF;
1921 break;
1922 }
1923
1924 // Set the value/second source register.
1925 switch (Opc) {
1926 case Hexagon::C2_cmpeq:
1927 case Hexagon::C2_cmpeqp:
1928 case Hexagon::C2_cmpgt:
1929 case Hexagon::C2_cmpgtp:
1930 case Hexagon::C2_cmpgtu:
1931 case Hexagon::C2_cmpgtup:
1932 case Hexagon::A4_cmpbeq:
1933 case Hexagon::A4_cmpbgt:
1934 case Hexagon::A4_cmpbgtu:
1935 case Hexagon::A4_cmpheq:
1936 case Hexagon::A4_cmphgt:
1937 case Hexagon::A4_cmphgtu:
1938 case Hexagon::C4_cmpneq:
1939 case Hexagon::C4_cmplte:
1940 case Hexagon::C4_cmplteu:
1941 SrcReg2 = MI.getOperand(2).getReg();
1942 Value = 0;
1943 return true;
1944
1945 case Hexagon::C2_cmpeqi:
1946 case Hexagon::C2_cmpgtui:
1947 case Hexagon::C2_cmpgti:
1948 case Hexagon::C4_cmpneqi:
1949 case Hexagon::C4_cmplteui:
1950 case Hexagon::C4_cmpltei:
1951 case Hexagon::A4_cmpbeqi:
1952 case Hexagon::A4_cmpbgti:
1953 case Hexagon::A4_cmpbgtui:
1954 case Hexagon::A4_cmpheqi:
1955 case Hexagon::A4_cmphgti:
1956 case Hexagon::A4_cmphgtui: {
1957 SrcReg2 = 0;
1958 const MachineOperand &Op2 = MI.getOperand(2);
1959 if (!Op2.isImm())
1960 return false;
1961 Value = MI.getOperand(2).getImm();
1962 return true;
1963 }
1964 }
1965
1966 return false;
1967}
1968
1970 const MachineInstr &MI,
1971 unsigned *PredCost) const {
1972 return getInstrTimingClassLatency(ItinData, MI);
1973}
1974
1976 const TargetSubtargetInfo &STI) const {
1977 const InstrItineraryData *II = STI.getInstrItineraryData();
1978 return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1979}
1980
1981// Inspired by this pair:
1982// %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1983// S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1984// Currently AA considers the addresses in these instructions to be aliasing.
1986 const MachineInstr &MIa, const MachineInstr &MIb) const {
1989 return false;
1990
1991 // Instructions that are pure loads, not loads and stores like memops are not
1992 // dependent.
1993 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1994 return true;
1995
1996 // Get the base register in MIa.
1997 unsigned BasePosA, OffsetPosA;
1998 if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1999 return false;
2000 const MachineOperand &BaseA = MIa.getOperand(BasePosA);
2001 Register BaseRegA = BaseA.getReg();
2002 unsigned BaseSubA = BaseA.getSubReg();
2003
2004 // Get the base register in MIb.
2005 unsigned BasePosB, OffsetPosB;
2006 if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
2007 return false;
2008 const MachineOperand &BaseB = MIb.getOperand(BasePosB);
2009 Register BaseRegB = BaseB.getReg();
2010 unsigned BaseSubB = BaseB.getSubReg();
2011
2012 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
2013 return false;
2014
2015 // Get the access sizes.
2016 unsigned SizeA = getMemAccessSize(MIa);
2017 unsigned SizeB = getMemAccessSize(MIb);
2018
2019 // Get the offsets. Handle immediates only for now.
2020 const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
2021 const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
2022 if (!MIa.getOperand(OffsetPosA).isImm() ||
2023 !MIb.getOperand(OffsetPosB).isImm())
2024 return false;
2025 int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
2026 int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
2027
2028 // This is a mem access with the same base register and known offsets from it.
2029 // Reason about it.
2030 if (OffsetA > OffsetB) {
2031 uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
2032 return SizeB <= OffDiff;
2033 }
2034 if (OffsetA < OffsetB) {
2035 uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
2036 return SizeA <= OffDiff;
2037 }
2038
2039 return false;
2040}
2041
2042/// If the instruction is an increment of a constant value, return the amount.
2044 int &Value) const {
2045 if (isPostIncrement(MI)) {
2046 unsigned BasePos = 0, OffsetPos = 0;
2047 if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
2048 return false;
2049 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
2050 if (OffsetOp.isImm()) {
2051 Value = OffsetOp.getImm();
2052 return true;
2053 }
2054 } else if (MI.getOpcode() == Hexagon::A2_addi) {
2055 const MachineOperand &AddOp = MI.getOperand(2);
2056 if (AddOp.isImm()) {
2057 Value = AddOp.getImm();
2058 return true;
2059 }
2060 }
2061
2062 return false;
2063}
2064
2065std::pair<unsigned, unsigned>
2067 return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
2069}
2070
2073 using namespace HexagonII;
2074
2075 static const std::pair<unsigned, const char*> Flags[] = {
2076 {MO_PCREL, "hexagon-pcrel"},
2077 {MO_GOT, "hexagon-got"},
2078 {MO_LO16, "hexagon-lo16"},
2079 {MO_HI16, "hexagon-hi16"},
2080 {MO_GPREL, "hexagon-gprel"},
2081 {MO_GDGOT, "hexagon-gdgot"},
2082 {MO_GDPLT, "hexagon-gdplt"},
2083 {MO_IE, "hexagon-ie"},
2084 {MO_IEGOT, "hexagon-iegot"},
2085 {MO_TPREL, "hexagon-tprel"}
2086 };
2087 return ArrayRef(Flags);
2088}
2089
2092 using namespace HexagonII;
2093
2094 static const std::pair<unsigned, const char*> Flags[] = {
2095 {HMOTF_ConstExtended, "hexagon-ext"}
2096 };
2097 return ArrayRef(Flags);
2098}
2099
2102 const TargetRegisterClass *TRC;
2103 if (VT == MVT::i1) {
2104 TRC = &Hexagon::PredRegsRegClass;
2105 } else if (VT == MVT::i32 || VT == MVT::f32) {
2106 TRC = &Hexagon::IntRegsRegClass;
2107 } else if (VT == MVT::i64 || VT == MVT::f64) {
2108 TRC = &Hexagon::DoubleRegsRegClass;
2109 } else {
2110 llvm_unreachable("Cannot handle this register class");
2111 }
2112
2113 Register NewReg = MRI.createVirtualRegister(TRC);
2114 return NewReg;
2115}
2116
2119}
2120
2122 const uint64_t F = MI.getDesc().TSFlags;
2124}
2125
2128}
2129
2131 return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
2132 !MI.getDesc().mayStore() &&
2133 MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2134 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2135 !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
2136}
2137
2138// Return true if the instruction is a compound branch instruction.
2140 return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
2141}
2142
2143// TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
2144// isFPImm and later getFPImm as well.
2146 const uint64_t F = MI.getDesc().TSFlags;
2148 if (isExtended) // Instruction must be extended.
2149 return true;
2150
2151 unsigned isExtendable =
2153 if (!isExtendable)
2154 return false;
2155
2156 if (MI.isCall())
2157 return false;
2158
2159 short ExtOpNum = getCExtOpNum(MI);
2160 const MachineOperand &MO = MI.getOperand(ExtOpNum);
2161 // Use MO operand flags to determine if MO
2162 // has the HMOTF_ConstExtended flag set.
2164 return true;
2165 // If this is a Machine BB address we are talking about, and it is
2166 // not marked as extended, say so.
2167 if (MO.isMBB())
2168 return false;
2169
2170 // We could be using an instruction with an extendable immediate and shoehorn
2171 // a global address into it. If it is a global address it will be constant
2172 // extended. We do this for COMBINE.
2173 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2174 MO.isJTI() || MO.isCPI() || MO.isFPImm())
2175 return true;
2176
2177 // If the extendable operand is not 'Immediate' type, the instruction should
2178 // have 'isExtended' flag set.
2179 assert(MO.isImm() && "Extendable operand must be Immediate type");
2180
2181 int64_t Value = MO.getImm();
2183 int32_t SValue = Value;
2184 int32_t MinValue = getMinValue(MI);
2185 int32_t MaxValue = getMaxValue(MI);
2186 return SValue < MinValue || SValue > MaxValue;
2187 }
2188 uint32_t UValue = Value;
2189 uint32_t MinValue = getMinValue(MI);
2190 uint32_t MaxValue = getMaxValue(MI);
2191 return UValue < MinValue || UValue > MaxValue;
2192}
2193
2195 switch (MI.getOpcode()) {
2196 case Hexagon::L4_return:
2197 case Hexagon::L4_return_t:
2198 case Hexagon::L4_return_f:
2199 case Hexagon::L4_return_tnew_pnt:
2200 case Hexagon::L4_return_fnew_pnt:
2201 case Hexagon::L4_return_tnew_pt:
2202 case Hexagon::L4_return_fnew_pt:
2203 return true;
2204 }
2205 return false;
2206}
2207
2208// Return true when ConsMI uses a register defined by ProdMI.
2210 const MachineInstr &ConsMI) const {
2211 if (!ProdMI.getDesc().getNumDefs())
2212 return false;
2213 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2214
2219
2220 parseOperands(ProdMI, DefsA, UsesA);
2221 parseOperands(ConsMI, DefsB, UsesB);
2222
2223 for (auto &RegA : DefsA)
2224 for (auto &RegB : UsesB) {
2225 // True data dependency.
2226 if (RegA == RegB)
2227 return true;
2228
2229 if (RegA.isPhysical() && llvm::is_contained(HRI.subregs(RegA), RegB))
2230 return true;
2231
2232 if (RegB.isPhysical() && llvm::is_contained(HRI.subregs(RegB), RegA))
2233 return true;
2234 }
2235
2236 return false;
2237}
2238
2239// Returns true if the instruction is alread a .cur.
2241 switch (MI.getOpcode()) {
2242 case Hexagon::V6_vL32b_cur_pi:
2243 case Hexagon::V6_vL32b_cur_ai:
2244 return true;
2245 }
2246 return false;
2247}
2248
2249// Returns true, if any one of the operands is a dot new
2250// insn, whether it is predicated dot new or register dot new.
2253 return true;
2254
2255 return false;
2256}
2257
2258/// Symmetrical. See if these two instructions are fit for duplex pair.
2260 const MachineInstr &MIb) const {
2263 return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2264}
2265
2266bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2267 return (Opcode == Hexagon::ENDLOOP0 ||
2268 Opcode == Hexagon::ENDLOOP1);
2269}
2270
2271bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2272 switch(OpType) {
2279 return true;
2280 default:
2281 return false;
2282 }
2283}
2284
2286 const MCInstrDesc &MID = MI.getDesc();
2287 const uint64_t F = MID.TSFlags;
2289 return true;
2290
2291 // TODO: This is largely obsolete now. Will need to be removed
2292 // in consecutive patches.
2293 switch (MI.getOpcode()) {
2294 // PS_fi and PS_fia remain special cases.
2295 case Hexagon::PS_fi:
2296 case Hexagon::PS_fia:
2297 return true;
2298 default:
2299 return false;
2300 }
2301 return false;
2302}
2303
2304// This returns true in two cases:
2305// - The OP code itself indicates that this is an extended instruction.
2306// - One of MOs has been marked with HMOTF_ConstExtended flag.
2308 // First check if this is permanently extended op code.
2309 const uint64_t F = MI.getDesc().TSFlags;
2311 return true;
2312 // Use MO operand flags to determine if one of MI's operands
2313 // has HMOTF_ConstExtended flag set.
2314 for (const MachineOperand &MO : MI.operands())
2315 if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2316 return true;
2317 return false;
2318}
2319
2321 unsigned Opcode = MI.getOpcode();
2322 const uint64_t F = get(Opcode).TSFlags;
2323 return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2324}
2325
2326// No V60 HVX VMEM with A_INDIRECT.
2328 const MachineInstr &J) const {
2329 if (!isHVXVec(I))
2330 return false;
2331 if (!I.mayLoad() && !I.mayStore())
2332 return false;
2333 return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2334}
2335
2337 switch (MI.getOpcode()) {
2338 case Hexagon::J2_callr:
2339 case Hexagon::J2_callrf:
2340 case Hexagon::J2_callrt:
2341 case Hexagon::PS_call_nr:
2342 return true;
2343 }
2344 return false;
2345}
2346
2348 switch (MI.getOpcode()) {
2349 case Hexagon::L4_return:
2350 case Hexagon::L4_return_t:
2351 case Hexagon::L4_return_f:
2352 case Hexagon::L4_return_fnew_pnt:
2353 case Hexagon::L4_return_fnew_pt:
2354 case Hexagon::L4_return_tnew_pnt:
2355 case Hexagon::L4_return_tnew_pt:
2356 return true;
2357 }
2358 return false;
2359}
2360
2362 switch (MI.getOpcode()) {
2363 case Hexagon::J2_jumpr:
2364 case Hexagon::J2_jumprt:
2365 case Hexagon::J2_jumprf:
2366 case Hexagon::J2_jumprtnewpt:
2367 case Hexagon::J2_jumprfnewpt:
2368 case Hexagon::J2_jumprtnew:
2369 case Hexagon::J2_jumprfnew:
2370 return true;
2371 }
2372 return false;
2373}
2374
2375// Return true if a given MI can accommodate given offset.
2376// Use abs estimate as oppose to the exact number.
2377// TODO: This will need to be changed to use MC level
2378// definition of instruction extendable field size.
2380 unsigned offset) const {
2381 // This selection of jump instructions matches to that what
2382 // analyzeBranch can parse, plus NVJ.
2383 if (isNewValueJump(MI)) // r9:2
2384 return isInt<11>(offset);
2385
2386 switch (MI.getOpcode()) {
2387 // Still missing Jump to address condition on register value.
2388 default:
2389 return false;
2390 case Hexagon::J2_jump: // bits<24> dst; // r22:2
2391 case Hexagon::J2_call:
2392 case Hexagon::PS_call_nr:
2393 return isInt<24>(offset);
2394 case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2395 case Hexagon::J2_jumpf:
2396 case Hexagon::J2_jumptnew:
2397 case Hexagon::J2_jumptnewpt:
2398 case Hexagon::J2_jumpfnew:
2399 case Hexagon::J2_jumpfnewpt:
2400 case Hexagon::J2_callt:
2401 case Hexagon::J2_callf:
2402 return isInt<17>(offset);
2403 case Hexagon::J2_loop0i:
2404 case Hexagon::J2_loop0iext:
2405 case Hexagon::J2_loop0r:
2406 case Hexagon::J2_loop0rext:
2407 case Hexagon::J2_loop1i:
2408 case Hexagon::J2_loop1iext:
2409 case Hexagon::J2_loop1r:
2410 case Hexagon::J2_loop1rext:
2411 return isInt<9>(offset);
2412 // TODO: Add all the compound branches here. Can we do this in Relation model?
2413 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2414 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2415 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2416 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2417 return isInt<11>(offset);
2418 }
2419}
2420
2422 // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2423 // resource, but all operands can be received late like an ALU instruction.
2425}
2426
2428 unsigned Opcode = MI.getOpcode();
2429 return Opcode == Hexagon::J2_loop0i ||
2430 Opcode == Hexagon::J2_loop0r ||
2431 Opcode == Hexagon::J2_loop0iext ||
2432 Opcode == Hexagon::J2_loop0rext ||
2433 Opcode == Hexagon::J2_loop1i ||
2434 Opcode == Hexagon::J2_loop1r ||
2435 Opcode == Hexagon::J2_loop1iext ||
2436 Opcode == Hexagon::J2_loop1rext;
2437}
2438
2440 switch (MI.getOpcode()) {
2441 default: return false;
2442 case Hexagon::L4_iadd_memopw_io:
2443 case Hexagon::L4_isub_memopw_io:
2444 case Hexagon::L4_add_memopw_io:
2445 case Hexagon::L4_sub_memopw_io:
2446 case Hexagon::L4_and_memopw_io:
2447 case Hexagon::L4_or_memopw_io:
2448 case Hexagon::L4_iadd_memoph_io:
2449 case Hexagon::L4_isub_memoph_io:
2450 case Hexagon::L4_add_memoph_io:
2451 case Hexagon::L4_sub_memoph_io:
2452 case Hexagon::L4_and_memoph_io:
2453 case Hexagon::L4_or_memoph_io:
2454 case Hexagon::L4_iadd_memopb_io:
2455 case Hexagon::L4_isub_memopb_io:
2456 case Hexagon::L4_add_memopb_io:
2457 case Hexagon::L4_sub_memopb_io:
2458 case Hexagon::L4_and_memopb_io:
2459 case Hexagon::L4_or_memopb_io:
2460 case Hexagon::L4_ior_memopb_io:
2461 case Hexagon::L4_ior_memoph_io:
2462 case Hexagon::L4_ior_memopw_io:
2463 case Hexagon::L4_iand_memopb_io:
2464 case Hexagon::L4_iand_memoph_io:
2465 case Hexagon::L4_iand_memopw_io:
2466 return true;
2467 }
2468 return false;
2469}
2470
2472 const uint64_t F = MI.getDesc().TSFlags;
2474}
2475
2476bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2477 const uint64_t F = get(Opcode).TSFlags;
2479}
2480
2482 return isNewValueJump(MI) || isNewValueStore(MI);
2483}
2484
2486 return isNewValue(MI) && MI.isBranch();
2487}
2488
2489bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2490 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2491}
2492
2494 const uint64_t F = MI.getDesc().TSFlags;
2496}
2497
2498bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2499 const uint64_t F = get(Opcode).TSFlags;
2501}
2502
2503// Returns true if a particular operand is extendable for an instruction.
2505 unsigned OperandNum) const {
2506 const uint64_t F = MI.getDesc().TSFlags;
2508 == OperandNum;
2509}
2510
2512 const uint64_t F = MI.getDesc().TSFlags;
2515}
2516
2517bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2518 const uint64_t F = get(Opcode).TSFlags;
2519 assert(isPredicated(Opcode));
2521}
2522
2524 const uint64_t F = MI.getDesc().TSFlags;
2525 return !((F >> HexagonII::PredicatedFalsePos) &
2527}
2528
2529bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2530 const uint64_t F = get(Opcode).TSFlags;
2531 // Make sure that the instruction is predicated.
2533 return !((F >> HexagonII::PredicatedFalsePos) &
2535}
2536
2537bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2538 const uint64_t F = get(Opcode).TSFlags;
2540}
2541
2542bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2543 const uint64_t F = get(Opcode).TSFlags;
2545}
2546
2547bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2548 const uint64_t F = get(Opcode).TSFlags;
2549 assert(get(Opcode).isBranch() &&
2550 (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2552}
2553
2555 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2556 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2557 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2558 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2559}
2560
2562 switch (MI.getOpcode()) {
2563 // Byte
2564 case Hexagon::L2_loadrb_io:
2565 case Hexagon::L4_loadrb_ur:
2566 case Hexagon::L4_loadrb_ap:
2567 case Hexagon::L2_loadrb_pr:
2568 case Hexagon::L2_loadrb_pbr:
2569 case Hexagon::L2_loadrb_pi:
2570 case Hexagon::L2_loadrb_pci:
2571 case Hexagon::L2_loadrb_pcr:
2572 case Hexagon::L2_loadbsw2_io:
2573 case Hexagon::L4_loadbsw2_ur:
2574 case Hexagon::L4_loadbsw2_ap:
2575 case Hexagon::L2_loadbsw2_pr:
2576 case Hexagon::L2_loadbsw2_pbr:
2577 case Hexagon::L2_loadbsw2_pi:
2578 case Hexagon::L2_loadbsw2_pci:
2579 case Hexagon::L2_loadbsw2_pcr:
2580 case Hexagon::L2_loadbsw4_io:
2581 case Hexagon::L4_loadbsw4_ur:
2582 case Hexagon::L4_loadbsw4_ap:
2583 case Hexagon::L2_loadbsw4_pr:
2584 case Hexagon::L2_loadbsw4_pbr:
2585 case Hexagon::L2_loadbsw4_pi:
2586 case Hexagon::L2_loadbsw4_pci:
2587 case Hexagon::L2_loadbsw4_pcr:
2588 case Hexagon::L4_loadrb_rr:
2589 case Hexagon::L2_ploadrbt_io:
2590 case Hexagon::L2_ploadrbt_pi:
2591 case Hexagon::L2_ploadrbf_io:
2592 case Hexagon::L2_ploadrbf_pi:
2593 case Hexagon::L2_ploadrbtnew_io:
2594 case Hexagon::L2_ploadrbfnew_io:
2595 case Hexagon::L4_ploadrbt_rr:
2596 case Hexagon::L4_ploadrbf_rr:
2597 case Hexagon::L4_ploadrbtnew_rr:
2598 case Hexagon::L4_ploadrbfnew_rr:
2599 case Hexagon::L2_ploadrbtnew_pi:
2600 case Hexagon::L2_ploadrbfnew_pi:
2601 case Hexagon::L4_ploadrbt_abs:
2602 case Hexagon::L4_ploadrbf_abs:
2603 case Hexagon::L4_ploadrbtnew_abs:
2604 case Hexagon::L4_ploadrbfnew_abs:
2605 case Hexagon::L2_loadrbgp:
2606 // Half
2607 case Hexagon::L2_loadrh_io:
2608 case Hexagon::L4_loadrh_ur:
2609 case Hexagon::L4_loadrh_ap:
2610 case Hexagon::L2_loadrh_pr:
2611 case Hexagon::L2_loadrh_pbr:
2612 case Hexagon::L2_loadrh_pi:
2613 case Hexagon::L2_loadrh_pci:
2614 case Hexagon::L2_loadrh_pcr:
2615 case Hexagon::L4_loadrh_rr:
2616 case Hexagon::L2_ploadrht_io:
2617 case Hexagon::L2_ploadrht_pi:
2618 case Hexagon::L2_ploadrhf_io:
2619 case Hexagon::L2_ploadrhf_pi:
2620 case Hexagon::L2_ploadrhtnew_io:
2621 case Hexagon::L2_ploadrhfnew_io:
2622 case Hexagon::L4_ploadrht_rr:
2623 case Hexagon::L4_ploadrhf_rr:
2624 case Hexagon::L4_ploadrhtnew_rr:
2625 case Hexagon::L4_ploadrhfnew_rr:
2626 case Hexagon::L2_ploadrhtnew_pi:
2627 case Hexagon::L2_ploadrhfnew_pi:
2628 case Hexagon::L4_ploadrht_abs:
2629 case Hexagon::L4_ploadrhf_abs:
2630 case Hexagon::L4_ploadrhtnew_abs:
2631 case Hexagon::L4_ploadrhfnew_abs:
2632 case Hexagon::L2_loadrhgp:
2633 return true;
2634 default:
2635 return false;
2636 }
2637}
2638
2640 const uint64_t F = MI.getDesc().TSFlags;
2642}
2643
2645 switch (MI.getOpcode()) {
2646 case Hexagon::STriw_pred:
2647 case Hexagon::LDriw_pred:
2648 return true;
2649 default:
2650 return false;
2651 }
2652}
2653
2655 if (!MI.isBranch())
2656 return false;
2657
2658 for (auto &Op : MI.operands())
2659 if (Op.isGlobal() || Op.isSymbol())
2660 return true;
2661 return false;
2662}
2663
2664// Returns true when SU has a timing class TC1.
2666 unsigned SchedClass = MI.getDesc().getSchedClass();
2667 return is_TC1(SchedClass);
2668}
2669
2671 unsigned SchedClass = MI.getDesc().getSchedClass();
2672 return is_TC2(SchedClass);
2673}
2674
2676 unsigned SchedClass = MI.getDesc().getSchedClass();
2677 return is_TC2early(SchedClass);
2678}
2679
2681 unsigned SchedClass = MI.getDesc().getSchedClass();
2682 return is_TC4x(SchedClass);
2683}
2684
2685// Schedule this ASAP.
2687 const MachineInstr &MI2) const {
2688 if (mayBeCurLoad(MI1)) {
2689 // if (result of SU is used in Next) return true;
2690 Register DstReg = MI1.getOperand(0).getReg();
2691 int N = MI2.getNumOperands();
2692 for (int I = 0; I < N; I++)
2693 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2694 return true;
2695 }
2696 if (mayBeNewStore(MI2))
2697 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2698 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2699 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2700 return true;
2701 return false;
2702}
2703
2705 const uint64_t V = getType(MI);
2707}
2708
2709// Check if the Offset is a valid auto-inc imm by Load/Store Type.
2711 int Size = VT.getSizeInBits() / 8;
2712 if (Offset % Size != 0)
2713 return false;
2714 int Count = Offset / Size;
2715
2716 switch (VT.getSimpleVT().SimpleTy) {
2717 // For scalars the auto-inc is s4
2718 case MVT::i8:
2719 case MVT::i16:
2720 case MVT::i32:
2721 case MVT::i64:
2722 case MVT::f32:
2723 case MVT::f64:
2724 case MVT::v2i16:
2725 case MVT::v2i32:
2726 case MVT::v4i8:
2727 case MVT::v4i16:
2728 case MVT::v8i8:
2729 return isInt<4>(Count);
2730 // For HVX vectors the auto-inc is s3
2731 case MVT::v64i8:
2732 case MVT::v32i16:
2733 case MVT::v16i32:
2734 case MVT::v8i64:
2735 case MVT::v128i8:
2736 case MVT::v64i16:
2737 case MVT::v32i32:
2738 case MVT::v16i64:
2739 return isInt<3>(Count);
2740 default:
2741 break;
2742 }
2743
2744 llvm_unreachable("Not an valid type!");
2745}
2746
2747bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2748 const TargetRegisterInfo *TRI, bool Extend) const {
2749 // This function is to check whether the "Offset" is in the correct range of
2750 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2751 // inserted to calculate the final address. Due to this reason, the function
2752 // assumes that the "Offset" has correct alignment.
2753 // We used to assert if the offset was not properly aligned, however,
2754 // there are cases where a misaligned pointer recast can cause this
2755 // problem, and we need to allow for it. The front end warns of such
2756 // misaligns with respect to load size.
2757 switch (Opcode) {
2758 case Hexagon::PS_vstorerq_ai:
2759 case Hexagon::PS_vstorerv_ai:
2760 case Hexagon::PS_vstorerw_ai:
2761 case Hexagon::PS_vstorerw_nt_ai:
2762 case Hexagon::PS_vloadrq_ai:
2763 case Hexagon::PS_vloadrv_ai:
2764 case Hexagon::PS_vloadrw_ai:
2765 case Hexagon::PS_vloadrw_nt_ai:
2766 case Hexagon::V6_vL32b_ai:
2767 case Hexagon::V6_vS32b_ai:
2768 case Hexagon::V6_vS32b_pred_ai:
2769 case Hexagon::V6_vS32b_npred_ai:
2770 case Hexagon::V6_vS32b_qpred_ai:
2771 case Hexagon::V6_vS32b_nqpred_ai:
2772 case Hexagon::V6_vS32b_new_ai:
2773 case Hexagon::V6_vS32b_new_pred_ai:
2774 case Hexagon::V6_vS32b_new_npred_ai:
2775 case Hexagon::V6_vS32b_nt_pred_ai:
2776 case Hexagon::V6_vS32b_nt_npred_ai:
2777 case Hexagon::V6_vS32b_nt_new_ai:
2778 case Hexagon::V6_vS32b_nt_new_pred_ai:
2779 case Hexagon::V6_vS32b_nt_new_npred_ai:
2780 case Hexagon::V6_vS32b_nt_qpred_ai:
2781 case Hexagon::V6_vS32b_nt_nqpred_ai:
2782 case Hexagon::V6_vL32b_nt_ai:
2783 case Hexagon::V6_vS32b_nt_ai:
2784 case Hexagon::V6_vL32Ub_ai:
2785 case Hexagon::V6_vS32Ub_ai:
2786 case Hexagon::V6_vL32b_cur_ai:
2787 case Hexagon::V6_vL32b_tmp_ai:
2788 case Hexagon::V6_vL32b_pred_ai:
2789 case Hexagon::V6_vL32b_npred_ai:
2790 case Hexagon::V6_vL32b_cur_pred_ai:
2791 case Hexagon::V6_vL32b_cur_npred_ai:
2792 case Hexagon::V6_vL32b_tmp_pred_ai:
2793 case Hexagon::V6_vL32b_tmp_npred_ai:
2794 case Hexagon::V6_vL32b_nt_cur_ai:
2795 case Hexagon::V6_vL32b_nt_tmp_ai:
2796 case Hexagon::V6_vL32b_nt_pred_ai:
2797 case Hexagon::V6_vL32b_nt_npred_ai:
2798 case Hexagon::V6_vL32b_nt_cur_pred_ai:
2799 case Hexagon::V6_vL32b_nt_cur_npred_ai:
2800 case Hexagon::V6_vL32b_nt_tmp_pred_ai:
2801 case Hexagon::V6_vL32b_nt_tmp_npred_ai:
2802 case Hexagon::V6_vgathermh_pseudo:
2803 case Hexagon::V6_vgathermw_pseudo:
2804 case Hexagon::V6_vgathermhw_pseudo:
2805 case Hexagon::V6_vgathermhq_pseudo:
2806 case Hexagon::V6_vgathermwq_pseudo:
2807 case Hexagon::V6_vgathermhwq_pseudo: {
2808 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2809 assert(isPowerOf2_32(VectorSize));
2810 if (Offset & (VectorSize-1))
2811 return false;
2812 return isInt<4>(Offset >> Log2_32(VectorSize));
2813 }
2814
2815 case Hexagon::J2_loop0i:
2816 case Hexagon::J2_loop1i:
2817 return isUInt<10>(Offset);
2818
2819 case Hexagon::S4_storeirb_io:
2820 case Hexagon::S4_storeirbt_io:
2821 case Hexagon::S4_storeirbf_io:
2822 return isUInt<6>(Offset);
2823
2824 case Hexagon::S4_storeirh_io:
2825 case Hexagon::S4_storeirht_io:
2826 case Hexagon::S4_storeirhf_io:
2827 return isShiftedUInt<6,1>(Offset);
2828
2829 case Hexagon::S4_storeiri_io:
2830 case Hexagon::S4_storeirit_io:
2831 case Hexagon::S4_storeirif_io:
2832 return isShiftedUInt<6,2>(Offset);
2833 // Handle these two compare instructions that are not extendable.
2834 case Hexagon::A4_cmpbeqi:
2835 return isUInt<8>(Offset);
2836 case Hexagon::A4_cmpbgti:
2837 return isInt<8>(Offset);
2838 }
2839
2840 if (Extend)
2841 return true;
2842
2843 switch (Opcode) {
2844 case Hexagon::L2_loadri_io:
2845 case Hexagon::S2_storeri_io:
2846 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2848
2849 case Hexagon::L2_loadrd_io:
2850 case Hexagon::S2_storerd_io:
2851 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2853
2854 case Hexagon::L2_loadrh_io:
2855 case Hexagon::L2_loadruh_io:
2856 case Hexagon::S2_storerh_io:
2857 case Hexagon::S2_storerf_io:
2858 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2860
2861 case Hexagon::L2_loadrb_io:
2862 case Hexagon::L2_loadrub_io:
2863 case Hexagon::S2_storerb_io:
2864 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2866
2867 case Hexagon::A2_addi:
2868 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2870
2871 case Hexagon::L4_iadd_memopw_io:
2872 case Hexagon::L4_isub_memopw_io:
2873 case Hexagon::L4_add_memopw_io:
2874 case Hexagon::L4_sub_memopw_io:
2875 case Hexagon::L4_iand_memopw_io:
2876 case Hexagon::L4_ior_memopw_io:
2877 case Hexagon::L4_and_memopw_io:
2878 case Hexagon::L4_or_memopw_io:
2879 return (0 <= Offset && Offset <= 255);
2880
2881 case Hexagon::L4_iadd_memoph_io:
2882 case Hexagon::L4_isub_memoph_io:
2883 case Hexagon::L4_add_memoph_io:
2884 case Hexagon::L4_sub_memoph_io:
2885 case Hexagon::L4_iand_memoph_io:
2886 case Hexagon::L4_ior_memoph_io:
2887 case Hexagon::L4_and_memoph_io:
2888 case Hexagon::L4_or_memoph_io:
2889 return (0 <= Offset && Offset <= 127);
2890
2891 case Hexagon::L4_iadd_memopb_io:
2892 case Hexagon::L4_isub_memopb_io:
2893 case Hexagon::L4_add_memopb_io:
2894 case Hexagon::L4_sub_memopb_io:
2895 case Hexagon::L4_iand_memopb_io:
2896 case Hexagon::L4_ior_memopb_io:
2897 case Hexagon::L4_and_memopb_io:
2898 case Hexagon::L4_or_memopb_io:
2899 return (0 <= Offset && Offset <= 63);
2900
2901 // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2902 // any size. Later pass knows how to handle it.
2903 case Hexagon::STriw_pred:
2904 case Hexagon::LDriw_pred:
2905 case Hexagon::STriw_ctr:
2906 case Hexagon::LDriw_ctr:
2907 return true;
2908
2909 case Hexagon::PS_fi:
2910 case Hexagon::PS_fia:
2911 case Hexagon::INLINEASM:
2912 return true;
2913
2914 case Hexagon::L2_ploadrbt_io:
2915 case Hexagon::L2_ploadrbf_io:
2916 case Hexagon::L2_ploadrubt_io:
2917 case Hexagon::L2_ploadrubf_io:
2918 case Hexagon::S2_pstorerbt_io:
2919 case Hexagon::S2_pstorerbf_io:
2920 return isUInt<6>(Offset);
2921
2922 case Hexagon::L2_ploadrht_io:
2923 case Hexagon::L2_ploadrhf_io:
2924 case Hexagon::L2_ploadruht_io:
2925 case Hexagon::L2_ploadruhf_io:
2926 case Hexagon::S2_pstorerht_io:
2927 case Hexagon::S2_pstorerhf_io:
2928 return isShiftedUInt<6,1>(Offset);
2929
2930 case Hexagon::L2_ploadrit_io:
2931 case Hexagon::L2_ploadrif_io:
2932 case Hexagon::S2_pstorerit_io:
2933 case Hexagon::S2_pstorerif_io:
2934 return isShiftedUInt<6,2>(Offset);
2935
2936 case Hexagon::L2_ploadrdt_io:
2937 case Hexagon::L2_ploadrdf_io:
2938 case Hexagon::S2_pstorerdt_io:
2939 case Hexagon::S2_pstorerdf_io:
2940 return isShiftedUInt<6,3>(Offset);
2941
2942 case Hexagon::L2_loadbsw2_io:
2943 case Hexagon::L2_loadbzw2_io:
2944 return isShiftedInt<11,1>(Offset);
2945
2946 case Hexagon::L2_loadbsw4_io:
2947 case Hexagon::L2_loadbzw4_io:
2948 return isShiftedInt<11,2>(Offset);
2949 } // switch
2950
2951 dbgs() << "Failed Opcode is : " << Opcode << " (" << getName(Opcode)
2952 << ")\n";
2953 llvm_unreachable("No offset range is defined for this opcode. "
2954 "Please define it in the above switch statement!");
2955}
2956
2958 return isHVXVec(MI) && isAccumulator(MI);
2959}
2960
2962 const uint64_t F = get(MI.getOpcode()).TSFlags;
2964 return
2965 V == HexagonII::TypeCVI_VA ||
2967}
2968
2970 const MachineInstr &ConsMI) const {
2971 if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2972 return true;
2973
2974 if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2975 return true;
2976
2977 if (mayBeNewStore(ConsMI))
2978 return true;
2979
2980 return false;
2981}
2982
2984 switch (MI.getOpcode()) {
2985 // Byte
2986 case Hexagon::L2_loadrub_io:
2987 case Hexagon::L4_loadrub_ur:
2988 case Hexagon::L4_loadrub_ap:
2989 case Hexagon::L2_loadrub_pr:
2990 case Hexagon::L2_loadrub_pbr:
2991 case Hexagon::L2_loadrub_pi:
2992 case Hexagon::L2_loadrub_pci:
2993 case Hexagon::L2_loadrub_pcr:
2994 case Hexagon::L2_loadbzw2_io:
2995 case Hexagon::L4_loadbzw2_ur:
2996 case Hexagon::L4_loadbzw2_ap:
2997 case Hexagon::L2_loadbzw2_pr:
2998 case Hexagon::L2_loadbzw2_pbr:
2999 case Hexagon::L2_loadbzw2_pi:
3000 case Hexagon::L2_loadbzw2_pci:
3001 case Hexagon::L2_loadbzw2_pcr:
3002 case Hexagon::L2_loadbzw4_io:
3003 case Hexagon::L4_loadbzw4_ur:
3004 case Hexagon::L4_loadbzw4_ap:
3005 case Hexagon::L2_loadbzw4_pr:
3006 case Hexagon::L2_loadbzw4_pbr:
3007 case Hexagon::L2_loadbzw4_pi:
3008 case Hexagon::L2_loadbzw4_pci:
3009 case Hexagon::L2_loadbzw4_pcr:
3010 case Hexagon::L4_loadrub_rr:
3011 case Hexagon::L2_ploadrubt_io:
3012 case Hexagon::L2_ploadrubt_pi:
3013 case Hexagon::L2_ploadrubf_io:
3014 case Hexagon::L2_ploadrubf_pi:
3015 case Hexagon::L2_ploadrubtnew_io:
3016 case Hexagon::L2_ploadrubfnew_io:
3017 case Hexagon::L4_ploadrubt_rr:
3018 case Hexagon::L4_ploadrubf_rr:
3019 case Hexagon::L4_ploadrubtnew_rr:
3020 case Hexagon::L4_ploadrubfnew_rr:
3021 case Hexagon::L2_ploadrubtnew_pi:
3022 case Hexagon::L2_ploadrubfnew_pi:
3023 case Hexagon::L4_ploadrubt_abs:
3024 case Hexagon::L4_ploadrubf_abs:
3025 case Hexagon::L4_ploadrubtnew_abs:
3026 case Hexagon::L4_ploadrubfnew_abs:
3027 case Hexagon::L2_loadrubgp:
3028 // Half
3029 case Hexagon::L2_loadruh_io:
3030 case Hexagon::L4_loadruh_ur:
3031 case Hexagon::L4_loadruh_ap:
3032 case Hexagon::L2_loadruh_pr:
3033 case Hexagon::L2_loadruh_pbr:
3034 case Hexagon::L2_loadruh_pi:
3035 case Hexagon::L2_loadruh_pci:
3036 case Hexagon::L2_loadruh_pcr:
3037 case Hexagon::L4_loadruh_rr:
3038 case Hexagon::L2_ploadruht_io:
3039 case Hexagon::L2_ploadruht_pi:
3040 case Hexagon::L2_ploadruhf_io:
3041 case Hexagon::L2_ploadruhf_pi:
3042 case Hexagon::L2_ploadruhtnew_io:
3043 case Hexagon::L2_ploadruhfnew_io:
3044 case Hexagon::L4_ploadruht_rr:
3045 case Hexagon::L4_ploadruhf_rr:
3046 case Hexagon::L4_ploadruhtnew_rr:
3047 case Hexagon::L4_ploadruhfnew_rr:
3048 case Hexagon::L2_ploadruhtnew_pi:
3049 case Hexagon::L2_ploadruhfnew_pi:
3050 case Hexagon::L4_ploadruht_abs:
3051 case Hexagon::L4_ploadruhf_abs:
3052 case Hexagon::L4_ploadruhtnew_abs:
3053 case Hexagon::L4_ploadruhfnew_abs:
3054 case Hexagon::L2_loadruhgp:
3055 return true;
3056 default:
3057 return false;
3058 }
3059}
3060
3061// Add latency to instruction.
3063 const MachineInstr &MI2) const {
3064 if (isHVXVec(MI1) && isHVXVec(MI2))
3065 if (!isVecUsableNextPacket(MI1, MI2))
3066 return true;
3067 return false;
3068}
3069
3070/// Get the base register and byte offset of a load/store instr.
3073 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
3074 const TargetRegisterInfo *TRI) const {
3075 OffsetIsScalable = false;
3076 const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width);
3077 if (!BaseOp || !BaseOp->isReg())
3078 return false;
3079 BaseOps.push_back(BaseOp);
3080 return true;
3081}
3082
3083/// Can these instructions execute at the same time in a bundle.
3085 const MachineInstr &Second) const {
3086 if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
3087 const MachineOperand &Op = Second.getOperand(0);
3088 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
3089 return true;
3090 }
3092 return false;
3093 if (mayBeNewStore(Second)) {
3094 // Make sure the definition of the first instruction is the value being
3095 // stored.
3096 const MachineOperand &Stored =
3097 Second.getOperand(Second.getNumOperands() - 1);
3098 if (!Stored.isReg())
3099 return false;
3100 for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
3101 const MachineOperand &Op = First.getOperand(i);
3102 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3103 return true;
3104 }
3105 }
3106 return false;
3107}
3108
3110 unsigned Opc = CallMI.getOpcode();
3111 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
3112}
3113
3115 for (auto &I : *B)
3116 if (I.isEHLabel())
3117 return true;
3118 return false;
3119}
3120
3121// Returns true if an instruction can be converted into a non-extended
3122// equivalent instruction.
3124 short NonExtOpcode;
3125 // Check if the instruction has a register form that uses register in place
3126 // of the extended operand, if so return that as the non-extended form.
3127 if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
3128 return true;
3129
3130 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
3131 // Check addressing mode and retrieve non-ext equivalent instruction.
3132
3133 switch (getAddrMode(MI)) {
3135 // Load/store with absolute addressing mode can be converted into
3136 // base+offset mode.
3137 NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
3138 break;
3140 // Load/store with base+offset addressing mode can be converted into
3141 // base+register offset addressing mode. However left shift operand should
3142 // be set to 0.
3143 NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
3144 break;
3146 NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
3147 break;
3148 default:
3149 return false;
3150 }
3151 if (NonExtOpcode < 0)
3152 return false;
3153 return true;
3154 }
3155 return false;
3156}
3157
3159 return Hexagon::getRealHWInstr(MI.getOpcode(),
3160 Hexagon::InstrType_Pseudo) >= 0;
3161}
3162
3164 const {
3165 MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
3166 while (I != E) {
3167 if (I->isBarrier())
3168 return true;
3169 ++I;
3170 }
3171 return false;
3172}
3173
3174// Returns true, if a LD insn can be promoted to a cur load.
3176 const uint64_t F = MI.getDesc().TSFlags;
3178 Subtarget.hasV60Ops();
3179}
3180
3181// Returns true, if a ST insn can be promoted to a new-value store.
3183 if (MI.mayStore() && !Subtarget.useNewValueStores())
3184 return false;
3185
3186 const uint64_t F = MI.getDesc().TSFlags;
3188}
3189
3191 const MachineInstr &ConsMI) const {
3192 // There is no stall when ProdMI is not a V60 vector.
3193 if (!isHVXVec(ProdMI))
3194 return false;
3195
3196 // There is no stall when ProdMI and ConsMI are not dependent.
3197 if (!isDependent(ProdMI, ConsMI))
3198 return false;
3199
3200 // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3201 // are scheduled in consecutive packets.
3202 if (isVecUsableNextPacket(ProdMI, ConsMI))
3203 return false;
3204
3205 return true;
3206}
3207
3210 // There is no stall when I is not a V60 vector.
3211 if (!isHVXVec(MI))
3212 return false;
3213
3215 MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3216
3217 if (!MII->isBundle())
3218 return producesStall(*MII, MI);
3219
3220 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3221 const MachineInstr &J = *MII;
3222 if (producesStall(J, MI))
3223 return true;
3224 }
3225 return false;
3226}
3227
3229 Register PredReg) const {
3230 for (const MachineOperand &MO : MI.operands()) {
3231 // Predicate register must be explicitly defined.
3232 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3233 return false;
3234 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3235 return false;
3236 }
3237
3238 // Instruction that produce late predicate cannot be used as sources of
3239 // dot-new.
3240 switch (MI.getOpcode()) {
3241 case Hexagon::A4_addp_c:
3242 case Hexagon::A4_subp_c:
3243 case Hexagon::A4_tlbmatch:
3244 case Hexagon::A5_ACS:
3245 case Hexagon::F2_sfinvsqrta:
3246 case Hexagon::F2_sfrecipa:
3247 case Hexagon::J2_endloop0:
3248 case Hexagon::J2_endloop01:
3249 case Hexagon::J2_ploop1si:
3250 case Hexagon::J2_ploop1sr:
3251 case Hexagon::J2_ploop2si:
3252 case Hexagon::J2_ploop2sr:
3253 case Hexagon::J2_ploop3si:
3254 case Hexagon::J2_ploop3sr:
3255 case Hexagon::S2_cabacdecbin:
3256 case Hexagon::S2_storew_locked:
3257 case Hexagon::S4_stored_locked:
3258 return false;
3259 }
3260 return true;
3261}
3262
3263bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3264 return Opcode == Hexagon::J2_jumpt ||
3265 Opcode == Hexagon::J2_jumptpt ||
3266 Opcode == Hexagon::J2_jumpf ||
3267 Opcode == Hexagon::J2_jumpfpt ||
3268 Opcode == Hexagon::J2_jumptnew ||
3269 Opcode == Hexagon::J2_jumpfnew ||
3270 Opcode == Hexagon::J2_jumptnewpt ||
3271 Opcode == Hexagon::J2_jumpfnewpt;
3272}
3273
3275 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3276 return false;
3277 return !isPredicatedTrue(Cond[0].getImm());
3278}
3279
3281 const uint64_t F = MI.getDesc().TSFlags;
3283}
3284
3285// Returns the base register in a memory access (load/store). The offset is
3286// returned in Offset and the access size is returned in AccessSize.
3287// If the base operand has a subregister or the offset field does not contain
3288// an immediate value, return nullptr.
3291 LocationSize &AccessSize) const {
3292 // Return if it is not a base+offset type instruction or a MemOp.
3296 return nullptr;
3297
3298 AccessSize = getMemAccessSize(MI);
3299
3300 unsigned BasePos = 0, OffsetPos = 0;
3301 if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3302 return nullptr;
3303
3304 // Post increment updates its EA after the mem access,
3305 // so we need to treat its offset as zero.
3306 if (isPostIncrement(MI)) {
3307 Offset = 0;
3308 } else {
3309 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3310 if (!OffsetOp.isImm())
3311 return nullptr;
3312 Offset = OffsetOp.getImm();
3313 }
3314
3315 const MachineOperand &BaseOp = MI.getOperand(BasePos);
3316 if (BaseOp.getSubReg() != 0)
3317 return nullptr;
3318 return &const_cast<MachineOperand&>(BaseOp);
3319}
3320
3321/// Return the position of the base and offset operands for this instruction.
3323 unsigned &BasePos, unsigned &OffsetPos) const {
3325 return false;
3326
3327 // Deal with memops first.
3328 if (isMemOp(MI)) {
3329 BasePos = 0;
3330 OffsetPos = 1;
3331 } else if (MI.mayStore()) {
3332 BasePos = 0;
3333 OffsetPos = 1;
3334 } else if (MI.mayLoad()) {
3335 BasePos = 1;
3336 OffsetPos = 2;
3337 } else
3338 return false;
3339
3340 if (isPredicated(MI)) {
3341 BasePos++;
3342 OffsetPos++;
3343 }
3344 if (isPostIncrement(MI)) {
3345 BasePos++;
3346 OffsetPos++;
3347 }
3348
3349 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3350 return false;
3351
3352 return true;
3353}
3354
3355// Inserts branching instructions in reverse order of their occurrence.
3356// e.g. jump_t t1 (i1)
3357// jump t2 (i2)
3358// Jumpers = {i2, i1}
3360 MachineBasicBlock& MBB) const {
3362 // If the block has no terminators, it just falls into the block after it.
3364 if (I == MBB.instr_begin())
3365 return Jumpers;
3366
3367 // A basic block may looks like this:
3368 //
3369 // [ insn
3370 // EH_LABEL
3371 // insn
3372 // insn
3373 // insn
3374 // EH_LABEL
3375 // insn ]
3376 //
3377 // It has two succs but does not have a terminator
3378 // Don't know how to handle it.
3379 do {
3380 --I;
3381 if (I->isEHLabel())
3382 return Jumpers;
3383 } while (I != MBB.instr_begin());
3384
3385 I = MBB.instr_end();
3386 --I;
3387
3388 while (I->isDebugInstr()) {
3389 if (I == MBB.instr_begin())
3390 return Jumpers;
3391 --I;
3392 }
3393 if (!isUnpredicatedTerminator(*I))
3394 return Jumpers;
3395
3396 // Get the last instruction in the block.
3397 MachineInstr *LastInst = &*I;
3398 Jumpers.push_back(LastInst);
3399 MachineInstr *SecondLastInst = nullptr;
3400 // Find one more terminator if present.
3401 do {
3402 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3403 if (!SecondLastInst) {
3404 SecondLastInst = &*I;
3405 Jumpers.push_back(SecondLastInst);
3406 } else // This is a third branch.
3407 return Jumpers;
3408 }
3409 if (I == MBB.instr_begin())
3410 break;
3411 --I;
3412 } while (true);
3413 return Jumpers;
3414}
3415
3416// Returns Operand Index for the constant extended instruction.
3418 const uint64_t F = MI.getDesc().TSFlags;
3420}
3421
3422// See if instruction could potentially be a duplex candidate.
3423// If so, return its group. Zero otherwise.
3425 const MachineInstr &MI) const {
3426 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3427
3428 switch (MI.getOpcode()) {
3429 default:
3430 return HexagonII::HCG_None;
3431 //
3432 // Compound pairs.
3433 // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3434 // "Rd16=#U6 ; jump #r9:2"
3435 // "Rd16=Rs16 ; jump #r9:2"
3436 //
3437 case Hexagon::C2_cmpeq:
3438 case Hexagon::C2_cmpgt:
3439 case Hexagon::C2_cmpgtu:
3440 DstReg = MI.getOperand(0).getReg();
3441 Src1Reg = MI.getOperand(1).getReg();
3442 Src2Reg = MI.getOperand(2).getReg();
3443 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3444 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3445 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3446 return HexagonII::HCG_A;
3447 break;
3448 case Hexagon::C2_cmpeqi:
3449 case Hexagon::C2_cmpgti:
3450 case Hexagon::C2_cmpgtui:
3451 // P0 = cmp.eq(Rs,#u2)
3452 DstReg = MI.getOperand(0).getReg();
3453 SrcReg = MI.getOperand(1).getReg();
3454 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3455 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3456 isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3457 ((isUInt<5>(MI.getOperand(2).getImm())) ||
3458 (MI.getOperand(2).getImm() == -1)))
3459 return HexagonII::HCG_A;
3460 break;
3461 case Hexagon::A2_tfr:
3462 // Rd = Rs
3463 DstReg = MI.getOperand(0).getReg();
3464 SrcReg = MI.getOperand(1).getReg();
3465 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3466 return HexagonII::HCG_A;
3467 break;
3468 case Hexagon::A2_tfrsi:
3469 // Rd = #u6
3470 // Do not test for #u6 size since the const is getting extended
3471 // regardless and compound could be formed.
3472 DstReg = MI.getOperand(0).getReg();
3473 if (isIntRegForSubInst(DstReg))
3474 return HexagonII::HCG_A;
3475 break;
3476 case Hexagon::S2_tstbit_i:
3477 DstReg = MI.getOperand(0).getReg();
3478 Src1Reg = MI.getOperand(1).getReg();
3479 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3480 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3481 MI.getOperand(2).isImm() &&
3482 isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3483 return HexagonII::HCG_A;
3484 break;
3485 // The fact that .new form is used pretty much guarantees
3486 // that predicate register will match. Nevertheless,
3487 // there could be some false positives without additional
3488 // checking.
3489 case Hexagon::J2_jumptnew:
3490 case Hexagon::J2_jumpfnew:
3491 case Hexagon::J2_jumptnewpt:
3492 case Hexagon::J2_jumpfnewpt:
3493 Src1Reg = MI.getOperand(0).getReg();
3494 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3495 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3496 return HexagonII::HCG_B;
3497 break;
3498 // Transfer and jump:
3499 // Rd=#U6 ; jump #r9:2
3500 // Rd=Rs ; jump #r9:2
3501 // Do not test for jump range here.
3502 case Hexagon::J2_jump:
3503 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3504 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3505 return HexagonII::HCG_C;
3506 }
3507
3508 return HexagonII::HCG_None;
3509}
3510
3511// Returns -1 when there is no opcode found.
3513 const MachineInstr &GB) const {
3516 if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3517 (GB.getOpcode() != Hexagon::J2_jumptnew))
3518 return -1u;
3519 Register DestReg = GA.getOperand(0).getReg();
3520 if (!GB.readsRegister(DestReg))
3521 return -1u;
3522 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3523 return -1u;
3524 // The value compared against must be either u5 or -1.
3525 const MachineOperand &CmpOp = GA.getOperand(2);
3526 if (!CmpOp.isImm())
3527 return -1u;
3528 int V = CmpOp.getImm();
3529 if (V == -1)
3530 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3531 : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3532 if (!isUInt<5>(V))
3533 return -1u;
3534 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3535 : Hexagon::J4_cmpeqi_tp1_jump_nt;
3536}
3537
3538// Returns -1 if there is no opcode found.
3540 bool ForBigCore) const {
3541 // Static table to switch the opcodes across Tiny Core and Big Core.
3542 // dup_ opcodes are Big core opcodes.
3543 // NOTE: There are special instructions that need to handled later.
3544 // L4_return* instructions, they will only occupy SLOT0 (on big core too).
3545 // PS_jmpret - This pseudo translates to J2_jumpr which occupies only SLOT2.
3546 // The compiler need to base the root instruction to L6_return_map_to_raw
3547 // which can go any slot.
3548 static const std::map<unsigned, unsigned> DupMap = {
3549 {Hexagon::A2_add, Hexagon::dup_A2_add},
3550 {Hexagon::A2_addi, Hexagon::dup_A2_addi},
3551 {Hexagon::A2_andir, Hexagon::dup_A2_andir},
3552 {Hexagon::A2_combineii, Hexagon::dup_A2_combineii},
3553 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb},
3554 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth},
3555 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr},
3556 {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi},
3557 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb},
3558 {Hexagon::A2_zxth, Hexagon::dup_A2_zxth},
3559 {Hexagon::A4_combineii, Hexagon::dup_A4_combineii},
3560 {Hexagon::A4_combineir, Hexagon::dup_A4_combineir},
3561 {Hexagon::A4_combineri, Hexagon::dup_A4_combineri},
3562 {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif},
3563 {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit},
3564 {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif},
3565 {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit},
3566 {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi},
3567 {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe},
3568 {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io},
3569 {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io},
3570 {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io},
3571 {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io},
3572 {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io},
3573 {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io},
3574 {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe},
3575 {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io},
3576 {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io},
3577 {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io},
3578 {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io},
3579 {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io},
3580 {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io},
3581 };
3582 unsigned OpNum = MI.getOpcode();
3583 // Conversion to Big core.
3584 if (ForBigCore) {
3585 auto Iter = DupMap.find(OpNum);
3586 if (Iter != DupMap.end())
3587 return Iter->second;
3588 } else { // Conversion to Tiny core.
3589 for (const auto &Iter : DupMap)
3590 if (Iter.second == OpNum)
3591 return Iter.first;
3592 }
3593 return -1;
3594}
3595
3596int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3597 enum Hexagon::PredSense inPredSense;
3598 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3599 Hexagon::PredSense_true;
3600 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3601 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3602 return CondOpcode;
3603
3604 llvm_unreachable("Unexpected predicable instruction");
3605}
3606
3607// Return the cur value instruction for a given store.
3609 switch (MI.getOpcode()) {
3610 default: llvm_unreachable("Unknown .cur type");
3611 case Hexagon::V6_vL32b_pi:
3612 return Hexagon::V6_vL32b_cur_pi;
3613 case Hexagon::V6_vL32b_ai:
3614 return Hexagon::V6_vL32b_cur_ai;
3615 case Hexagon::V6_vL32b_nt_pi:
3616 return Hexagon::V6_vL32b_nt_cur_pi;
3617 case Hexagon::V6_vL32b_nt_ai:
3618 return Hexagon::V6_vL32b_nt_cur_ai;
3619 case Hexagon::V6_vL32b_ppu:
3620 return Hexagon::V6_vL32b_cur_ppu;
3621 case Hexagon::V6_vL32b_nt_ppu:
3622 return Hexagon::V6_vL32b_nt_cur_ppu;
3623 }
3624 return 0;
3625}
3626
3627// Return the regular version of the .cur instruction.
3629 switch (MI.getOpcode()) {
3630 default: llvm_unreachable("Unknown .cur type");
3631 case Hexagon::V6_vL32b_cur_pi:
3632 return Hexagon::V6_vL32b_pi;
3633 case Hexagon::V6_vL32b_cur_ai:
3634 return Hexagon::V6_vL32b_ai;
3635 case Hexagon::V6_vL32b_nt_cur_pi:
3636 return Hexagon::V6_vL32b_nt_pi;
3637 case Hexagon::V6_vL32b_nt_cur_ai:
3638 return Hexagon::V6_vL32b_nt_ai;
3639 case Hexagon::V6_vL32b_cur_ppu:
3640 return Hexagon::V6_vL32b_ppu;
3641 case Hexagon::V6_vL32b_nt_cur_ppu:
3642 return Hexagon::V6_vL32b_nt_ppu;
3643 }
3644 return 0;
3645}
3646
3647// The diagram below shows the steps involved in the conversion of a predicated
3648// store instruction to its .new predicated new-value form.
3649//
3650// Note: It doesn't include conditional new-value stores as they can't be
3651// converted to .new predicate.
3652//
3653// p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3654// ^ ^
3655// / \ (not OK. it will cause new-value store to be
3656// / X conditional on p0.new while R2 producer is
3657// / \ on p0)
3658// / \.
3659// p.new store p.old NV store
3660// [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3661// ^ ^
3662// \ /
3663// \ /
3664// \ /
3665// p.old store
3666// [if (p0)memw(R0+#0)=R2]
3667//
3668// The following set of instructions further explains the scenario where
3669// conditional new-value store becomes invalid when promoted to .new predicate
3670// form.
3671//
3672// { 1) if (p0) r0 = add(r1, r2)
3673// 2) p0 = cmp.eq(r3, #0) }
3674//
3675// 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3676// the first two instructions because in instr 1, r0 is conditional on old value
3677// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3678// is not valid for new-value stores.
3679// Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3680// from the "Conditional Store" list. Because a predicated new value store
3681// would NOT be promoted to a double dot new store. See diagram below:
3682// This function returns yes for those stores that are predicated but not
3683// yet promoted to predicate dot new instructions.
3684//
3685// +---------------------+
3686// /-----| if (p0) memw(..)=r0 |---------\~
3687// || +---------------------+ ||
3688// promote || /\ /\ || promote
3689// || /||\ /||\ ||
3690// \||/ demote || \||/
3691// \/ || || \/
3692// +-------------------------+ || +-------------------------+
3693// | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3694// +-------------------------+ || +-------------------------+
3695// || || ||
3696// || demote \||/
3697// promote || \/ NOT possible
3698// || || /\~
3699// \||/ || /||\~
3700// \/ || ||
3701// +-----------------------------+
3702// | if (p0.new) memw(..)=r0.new |
3703// +-----------------------------+
3704// Double Dot New Store
3705//
3706// Returns the most basic instruction for the .new predicated instructions and
3707// new-value stores.
3708// For example, all of the following instructions will be converted back to the
3709// same instruction:
3710// 1) if (p0.new) memw(R0+#0) = R1.new --->
3711// 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3712// 3) if (p0.new) memw(R0+#0) = R1 --->
3713//
3714// To understand the translation of instruction 1 to its original form, consider
3715// a packet with 3 instructions.
3716// { p0 = cmp.eq(R0,R1)
3717// if (p0.new) R2 = add(R3, R4)
3718// R5 = add (R3, R1)
3719// }
3720// if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3721//
3722// This instruction can be part of the previous packet only if both p0 and R2
3723// are promoted to .new values. This promotion happens in steps, first
3724// predicate register is promoted to .new and in the next iteration R2 is
3725// promoted. Therefore, in case of dependence check failure (due to R5) during
3726// next iteration, it should be converted back to its most basic form.
3727
3728// Return the new value instruction for a given store.
3730 int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3731 if (NVOpcode >= 0) // Valid new-value store instruction.
3732 return NVOpcode;
3733
3734 switch (MI.getOpcode()) {
3735 default:
3736 report_fatal_error(Twine("Unknown .new type: ") +
3737 std::to_string(MI.getOpcode()));
3738 case Hexagon::S4_storerb_ur:
3739 return Hexagon::S4_storerbnew_ur;
3740
3741 case Hexagon::S2_storerb_pci:
3742 return Hexagon::S2_storerb_pci;
3743
3744 case Hexagon::S2_storeri_pci:
3745 return Hexagon::S2_storeri_pci;
3746
3747 case Hexagon::S2_storerh_pci:
3748 return Hexagon::S2_storerh_pci;
3749
3750 case Hexagon::S2_storerd_pci:
3751 return Hexagon::S2_storerd_pci;
3752
3753 case Hexagon::S2_storerf_pci:
3754 return Hexagon::S2_storerf_pci;
3755
3756 case Hexagon::V6_vS32b_ai:
3757 return Hexagon::V6_vS32b_new_ai;
3758
3759 case Hexagon::V6_vS32b_pi:
3760 return Hexagon::V6_vS32b_new_pi;
3761 }
3762 return 0;
3763}
3764
3765// Returns the opcode to use when converting MI, which is a conditional jump,
3766// into a conditional instruction which uses the .new value of the predicate.
3767// We also use branch probabilities to add a hint to the jump.
3768// If MBPI is null, all edges will be treated as equally likely for the
3769// purposes of establishing a predication hint.
3771 const MachineBranchProbabilityInfo *MBPI) const {
3772 // We assume that block can have at most two successors.
3773 const MachineBasicBlock *Src = MI.getParent();
3774 const MachineOperand &BrTarget = MI.getOperand(1);
3775 bool Taken = false;
3776 const BranchProbability OneHalf(1, 2);
3777
3778 auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3779 const MachineBasicBlock *Dst) {
3780 if (MBPI)
3781 return MBPI->getEdgeProbability(Src, Dst);
3782 return BranchProbability(1, Src->succ_size());
3783 };
3784
3785 if (BrTarget.isMBB()) {
3786 const MachineBasicBlock *Dst = BrTarget.getMBB();
3787 Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3788 } else {
3789 // The branch target is not a basic block (most likely a function).
3790 // Since BPI only gives probabilities for targets that are basic blocks,
3791 // try to identify another target of this branch (potentially a fall-
3792 // -through) and check the probability of that target.
3793 //
3794 // The only handled branch combinations are:
3795 // - one conditional branch,
3796 // - one conditional branch followed by one unconditional branch.
3797 // Otherwise, assume not-taken.
3798 assert(MI.isConditionalBranch());
3799 const MachineBasicBlock &B = *MI.getParent();
3800 bool SawCond = false, Bad = false;
3801 for (const MachineInstr &I : B) {
3802 if (!I.isBranch())
3803 continue;
3804 if (I.isConditionalBranch()) {
3805 SawCond = true;
3806 if (&I != &MI) {
3807 Bad = true;
3808 break;
3809 }
3810 }
3811 if (I.isUnconditionalBranch() && !SawCond) {
3812 Bad = true;
3813 break;
3814 }
3815 }
3816 if (!Bad) {
3818 MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3819 if (NextIt == B.instr_end()) {
3820 // If this branch is the last, look for the fall-through block.
3821 for (const MachineBasicBlock *SB : B.successors()) {
3822 if (!B.isLayoutSuccessor(SB))
3823 continue;
3824 Taken = getEdgeProbability(Src, SB) < OneHalf;
3825 break;
3826 }
3827 } else {
3828 assert(NextIt->isUnconditionalBranch());
3829 // Find the first MBB operand and assume it's the target.
3830 const MachineBasicBlock *BT = nullptr;
3831 for (const MachineOperand &Op : NextIt->operands()) {
3832 if (!Op.isMBB())
3833 continue;
3834 BT = Op.getMBB();
3835 break;
3836 }
3837 Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3838 }
3839 } // if (!Bad)
3840 }
3841
3842 // The Taken flag should be set to something reasonable by this point.
3843
3844 switch (MI.getOpcode()) {
3845 case Hexagon::J2_jumpt:
3846 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3847 case Hexagon::J2_jumpf:
3848 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3849
3850 default:
3851 llvm_unreachable("Unexpected jump instruction.");
3852 }
3853}
3854
3855// Return .new predicate version for an instruction.
3857 const MachineBranchProbabilityInfo *MBPI) const {
3858 switch (MI.getOpcode()) {
3859 // Condtional Jumps
3860 case Hexagon::J2_jumpt:
3861 case Hexagon::J2_jumpf:
3862 return getDotNewPredJumpOp(MI, MBPI);
3863 }
3864
3865 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3866 if (NewOpcode >= 0)
3867 return NewOpcode;
3868 return 0;
3869}
3870
3872 int NewOp = MI.getOpcode();
3873 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3874 NewOp = Hexagon::getPredOldOpcode(NewOp);
3875 // All Hexagon architectures have prediction bits on dot-new branches,
3876 // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3877 // to pick the right opcode when converting back to dot-old.
3878 if (!Subtarget.hasFeature(Hexagon::ArchV60)) {
3879 switch (NewOp) {
3880 case Hexagon::J2_jumptpt:
3881 NewOp = Hexagon::J2_jumpt;
3882 break;
3883 case Hexagon::J2_jumpfpt:
3884 NewOp = Hexagon::J2_jumpf;
3885 break;
3886 case Hexagon::J2_jumprtpt:
3887 NewOp = Hexagon::J2_jumprt;
3888 break;
3889 case Hexagon::J2_jumprfpt:
3890 NewOp = Hexagon::J2_jumprf;
3891 break;
3892 }
3893 }
3894 assert(NewOp >= 0 &&
3895 "Couldn't change predicate new instruction to its old form.");
3896 }
3897
3898 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3899 NewOp = Hexagon::getNonNVStore(NewOp);
3900 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3901 }
3902
3903 if (Subtarget.hasV60Ops())
3904 return NewOp;
3905
3906 // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3907 switch (NewOp) {
3908 case Hexagon::J2_jumpfpt:
3909 return Hexagon::J2_jumpf;
3910 case Hexagon::J2_jumptpt:
3911 return Hexagon::J2_jumpt;
3912 case Hexagon::J2_jumprfpt:
3913 return Hexagon::J2_jumprf;
3914 case Hexagon::J2_jumprtpt:
3915 return Hexagon::J2_jumprt;
3916 }
3917 return NewOp;
3918}
3919
3920// See if instruction could potentially be a duplex candidate.
3921// If so, return its group. Zero otherwise.
3923 const MachineInstr &MI) const {
3924 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3925 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3926
3927 switch (MI.getOpcode()) {
3928 default:
3929 return HexagonII::HSIG_None;
3930 //
3931 // Group L1:
3932 //
3933 // Rd = memw(Rs+#u4:2)
3934 // Rd = memub(Rs+#u4:0)
3935 case Hexagon::L2_loadri_io:
3936 case Hexagon::dup_L2_loadri_io:
3937 DstReg = MI.getOperand(0).getReg();
3938 SrcReg = MI.getOperand(1).getReg();
3939 // Special case this one from Group L2.
3940 // Rd = memw(r29+#u5:2)
3941 if (isIntRegForSubInst(DstReg)) {
3942 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3943 HRI.getStackRegister() == SrcReg &&
3944 MI.getOperand(2).isImm() &&
3945 isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3946 return HexagonII::HSIG_L2;
3947 // Rd = memw(Rs+#u4:2)
3948 if (isIntRegForSubInst(SrcReg) &&
3949 (MI.getOperand(2).isImm() &&
3950 isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3951 return HexagonII::HSIG_L1;
3952 }
3953 break;
3954 case Hexagon::L2_loadrub_io:
3955 case Hexagon::dup_L2_loadrub_io:
3956 // Rd = memub(Rs+#u4:0)
3957 DstReg = MI.getOperand(0).getReg();
3958 SrcReg = MI.getOperand(1).getReg();
3959 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3960 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3961 return HexagonII::HSIG_L1;
3962 break;
3963 //
3964 // Group L2:
3965 //
3966 // Rd = memh/memuh(Rs+#u3:1)
3967 // Rd = memb(Rs+#u3:0)
3968 // Rd = memw(r29+#u5:2) - Handled above.
3969 // Rdd = memd(r29+#u5:3)
3970 // deallocframe
3971 // [if ([!]p0[.new])] dealloc_return
3972 // [if ([!]p0[.new])] jumpr r31
3973 case Hexagon::L2_loadrh_io:
3974 case Hexagon::L2_loadruh_io:
3975 case Hexagon::dup_L2_loadrh_io:
3976 case Hexagon::dup_L2_loadruh_io:
3977 // Rd = memh/memuh(Rs+#u3:1)
3978 DstReg = MI.getOperand(0).getReg();
3979 SrcReg = MI.getOperand(1).getReg();
3980 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3981 MI.getOperand(2).isImm() &&
3982 isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3983 return HexagonII::HSIG_L2;
3984 break;
3985 case Hexagon::L2_loadrb_io:
3986 case Hexagon::dup_L2_loadrb_io:
3987 // Rd = memb(Rs+#u3:0)
3988 DstReg = MI.getOperand(0).getReg();
3989 SrcReg = MI.getOperand(1).getReg();
3990 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3991 MI.getOperand(2).isImm() &&
3992 isUInt<3>(MI.getOperand(2).getImm()))
3993 return HexagonII::HSIG_L2;
3994 break;
3995 case Hexagon::L2_loadrd_io:
3996 case Hexagon::dup_L2_loadrd_io:
3997 // Rdd = memd(r29+#u5:3)
3998 DstReg = MI.getOperand(0).getReg();
3999 SrcReg = MI.getOperand(1).getReg();
4000 if (isDblRegForSubInst(DstReg, HRI) &&
4001 Hexagon::IntRegsRegClass.contains(SrcReg) &&
4002 HRI.getStackRegister() == SrcReg &&
4003 MI.getOperand(2).isImm() &&
4004 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
4005 return HexagonII::HSIG_L2;
4006 break;
4007 // dealloc_return is not documented in Hexagon Manual, but marked
4008 // with A_SUBINSN attribute in iset_v4classic.py.
4009 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
4010 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
4011 case Hexagon::L4_return:
4012 case Hexagon::L2_deallocframe:
4013 case Hexagon::dup_L2_deallocframe:
4014 return HexagonII::HSIG_L2;
4015 case Hexagon::EH_RETURN_JMPR:
4016 case Hexagon::PS_jmpret:
4017 case Hexagon::SL2_jumpr31:
4018 // jumpr r31
4019 // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
4020 DstReg = MI.getOperand(0).getReg();
4021 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
4022 return HexagonII::HSIG_L2;
4023 break;
4024 case Hexagon::PS_jmprett:
4025 case Hexagon::PS_jmpretf:
4026 case Hexagon::PS_jmprettnewpt:
4027 case Hexagon::PS_jmpretfnewpt:
4028 case Hexagon::PS_jmprettnew:
4029 case Hexagon::PS_jmpretfnew:
4030 case Hexagon::SL2_jumpr31_t:
4031 case Hexagon::SL2_jumpr31_f:
4032 case Hexagon::SL2_jumpr31_tnew:
4033 case Hexagon::SL2_jumpr31_fnew:
4034 DstReg = MI.getOperand(1).getReg();
4035 SrcReg = MI.getOperand(0).getReg();
4036 // [if ([!]p0[.new])] jumpr r31
4037 if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
4038 (Hexagon::P0 == SrcReg)) &&
4039 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
4040 return HexagonII::HSIG_L2;
4041 break;
4042 case Hexagon::L4_return_t:
4043 case Hexagon::L4_return_f:
4044 case Hexagon::L4_return_tnew_pnt:
4045 case Hexagon::L4_return_fnew_pnt:
4046 case Hexagon::L4_return_tnew_pt:
4047 case Hexagon::L4_return_fnew_pt:
4048 // [if ([!]p0[.new])] dealloc_return
4049 SrcReg = MI.getOperand(0).getReg();
4050 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
4051 return HexagonII::HSIG_L2;
4052 break;
4053 //
4054 // Group S1:
4055 //
4056 // memw(Rs+#u4:2) = Rt
4057 // memb(Rs+#u4:0) = Rt
4058 case Hexagon::S2_storeri_io:
4059 case Hexagon::dup_S2_storeri_io:
4060 // Special case this one from Group S2.
4061 // memw(r29+#u5:2) = Rt
4062 Src1Reg = MI.getOperand(0).getReg();
4063 Src2Reg = MI.getOperand(2).getReg();
4064 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4065 isIntRegForSubInst(Src2Reg) &&
4066 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
4067 isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
4068 return HexagonII::HSIG_S2;
4069 // memw(Rs+#u4:2) = Rt
4070 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4071 MI.getOperand(1).isImm() &&
4072 isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
4073 return HexagonII::HSIG_S1;
4074 break;
4075 case Hexagon::S2_storerb_io:
4076 case Hexagon::dup_S2_storerb_io:
4077 // memb(Rs+#u4:0) = Rt
4078 Src1Reg = MI.getOperand(0).getReg();
4079 Src2Reg = MI.getOperand(2).getReg();
4080 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4081 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
4082 return HexagonII::HSIG_S1;
4083 break;
4084 //
4085 // Group S2:
4086 //
4087 // memh(Rs+#u3:1) = Rt
4088 // memw(r29+#u5:2) = Rt
4089 // memd(r29+#s6:3) = Rtt
4090 // memw(Rs+#u4:2) = #U1
4091 // memb(Rs+#u4) = #U1
4092 // allocframe(#u5:3)
4093 case Hexagon::S2_storerh_io:
4094 case Hexagon::dup_S2_storerh_io:
4095 // memh(Rs+#u3:1) = Rt
4096 Src1Reg = MI.getOperand(0).getReg();
4097 Src2Reg = MI.getOperand(2).getReg();
4098 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4099 MI.getOperand(1).isImm() &&
4100 isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
4101 return HexagonII::HSIG_S1;
4102 break;
4103 case Hexagon::S2_storerd_io:
4104 case Hexagon::dup_S2_storerd_io:
4105 // memd(r29+#s6:3) = Rtt
4106 Src1Reg = MI.getOperand(0).getReg();
4107 Src2Reg = MI.getOperand(2).getReg();
4108 if (isDblRegForSubInst(Src2Reg, HRI) &&
4109 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4110 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
4111 isShiftedInt<6,3>(MI.getOperand(1).getImm()))
4112 return HexagonII::HSIG_S2;
4113 break;
4114 case Hexagon::S4_storeiri_io:
4115 case Hexagon::dup_S4_storeiri_io:
4116 // memw(Rs+#u4:2) = #U1
4117 Src1Reg = MI.getOperand(0).getReg();
4118 if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
4119 isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
4120 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4121 return HexagonII::HSIG_S2;
4122 break;
4123 case Hexagon::S4_storeirb_io:
4124 case Hexagon::dup_S4_storeirb_io:
4125 // memb(Rs+#u4) = #U1
4126 Src1Reg = MI.getOperand(0).getReg();
4127 if (isIntRegForSubInst(Src1Reg) &&
4128 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
4129 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4130 return HexagonII::HSIG_S2;
4131 break;
4132 case Hexagon::S2_allocframe:
4133 case Hexagon::dup_S2_allocframe:
4134 if (MI.getOperand(2).isImm() &&
4135 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
4136 return HexagonII::HSIG_S1;
4137 break;
4138 //
4139 // Group A:
4140 //
4141 // Rx = add(Rx,#s7)
4142 // Rd = Rs
4143 // Rd = #u6
4144 // Rd = #-1
4145 // if ([!]P0[.new]) Rd = #0
4146 // Rd = add(r29,#u6:2)
4147 // Rx = add(Rx,Rs)
4148 // P0 = cmp.eq(Rs,#u2)
4149 // Rdd = combine(#0,Rs)
4150 // Rdd = combine(Rs,#0)
4151 // Rdd = combine(#u2,#U2)
4152 // Rd = add(Rs,#1)
4153 // Rd = add(Rs,#-1)
4154 // Rd = sxth/sxtb/zxtb/zxth(Rs)
4155 // Rd = and(Rs,#1)
4156 case Hexagon::A2_addi:
4157 case Hexagon::dup_A2_addi:
4158 DstReg = MI.getOperand(0).getReg();
4159 SrcReg = MI.getOperand(1).getReg();
4160 if (isIntRegForSubInst(DstReg)) {
4161 // Rd = add(r29,#u6:2)
4162 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
4163 HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
4164 isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
4165 return HexagonII::HSIG_A;
4166 // Rx = add(Rx,#s7)
4167 if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
4168 isInt<7>(MI.getOperand(2).getImm()))
4169 return HexagonII::HSIG_A;
4170 // Rd = add(Rs,#1)
4171 // Rd = add(Rs,#-1)
4172 if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
4173 ((MI.getOperand(2).getImm() == 1) ||
4174 (MI.getOperand(2).getImm() == -1)))
4175 return HexagonII::HSIG_A;
4176 }
4177 break;
4178 case Hexagon::A2_add:
4179 case Hexagon::dup_A2_add:
4180 // Rx = add(Rx,Rs)
4181 DstReg = MI.getOperand(0).getReg();
4182 Src1Reg = MI.getOperand(1).getReg();
4183 Src2Reg = MI.getOperand(2).getReg();
4184 if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
4185 isIntRegForSubInst(Src2Reg))
4186 return HexagonII::HSIG_A;
4187 break;
4188 case Hexagon::A2_andir:
4189 case Hexagon::dup_A2_andir:
4190 // Same as zxtb.
4191 // Rd16=and(Rs16,#255)
4192 // Rd16=and(Rs16,#1)
4193 DstReg = MI.getOperand(0).getReg();
4194 SrcReg = MI.getOperand(1).getReg();
4195 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
4196 MI.getOperand(2).isImm() &&
4197 ((MI.getOperand(2).getImm() == 1) ||
4198 (MI.getOperand(2).getImm() == 255)))
4199 return HexagonII::HSIG_A;
4200 break;
4201 case Hexagon::A2_tfr:
4202 case Hexagon::dup_A2_tfr:
4203 // Rd = Rs
4204 DstReg = MI.getOperand(0).getReg();
4205 SrcReg = MI.getOperand(1).getReg();
4206 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4207 return HexagonII::HSIG_A;
4208 break;
4209 case Hexagon::A2_tfrsi:
4210 case Hexagon::dup_A2_tfrsi:
4211 // Rd = #u6
4212 // Do not test for #u6 size since the const is getting extended
4213 // regardless and compound could be formed.
4214 // Rd = #-1
4215 DstReg = MI.getOperand(0).getReg();
4216 if (isIntRegForSubInst(DstReg))
4217 return HexagonII::HSIG_A;
4218 break;
4219 case Hexagon::C2_cmoveit:
4220 case Hexagon::C2_cmovenewit:
4221 case Hexagon::C2_cmoveif:
4222 case Hexagon::C2_cmovenewif:
4223 case Hexagon::dup_C2_cmoveit:
4224 case Hexagon::dup_C2_cmovenewit:
4225 case Hexagon::dup_C2_cmoveif:
4226 case Hexagon::dup_C2_cmovenewif:
4227 // if ([!]P0[.new]) Rd = #0
4228 // Actual form:
4229 // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
4230 DstReg = MI.getOperand(0).getReg();
4231 SrcReg = MI.getOperand(1).getReg();
4232 if (isIntRegForSubInst(DstReg) &&
4233 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4234 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4235 return HexagonII::HSIG_A;
4236 break;
4237 case Hexagon::C2_cmpeqi:
4238 case Hexagon::dup_C2_cmpeqi:
4239 // P0 = cmp.eq(Rs,#u2)
4240 DstReg = MI.getOperand(0).getReg();
4241 SrcReg = MI.getOperand(1).getReg();
4242 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
4243 Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
4244 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4245 return HexagonII::HSIG_A;
4246 break;
4247 case Hexagon::A2_combineii:
4248 case Hexagon::A4_combineii:
4249 case Hexagon::dup_A2_combineii:
4250 case Hexagon::dup_A4_combineii:
4251 // Rdd = combine(#u2,#U2)
4252 DstReg = MI.getOperand(0).getReg();
4253 if (isDblRegForSubInst(DstReg, HRI) &&
4254 ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4255 (MI.getOperand(1).isGlobal() &&
4256 isUInt<2>(MI.getOperand(1).getOffset()))) &&
4257 ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4258 (MI.getOperand(2).isGlobal() &&
4259 isUInt<2>(MI.getOperand(2).getOffset()))))
4260 return HexagonII::HSIG_A;
4261 break;
4262 case Hexagon::A4_combineri:
4263 case Hexagon::dup_A4_combineri:
4264 // Rdd = combine(Rs,#0)
4265 // Rdd = combine(Rs,#0)
4266 DstReg = MI.getOperand(0).getReg();
4267 SrcReg = MI.getOperand(1).getReg();
4268 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4269 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4270 (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4271 return HexagonII::HSIG_A;
4272 break;
4273 case Hexagon::A4_combineir:
4274 case Hexagon::dup_A4_combineir:
4275 // Rdd = combine(#0,Rs)
4276 DstReg = MI.getOperand(0).getReg();
4277 SrcReg = MI.getOperand(2).getReg();
4278 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4279 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4280 (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4281 return HexagonII::HSIG_A;
4282 break;
4283 case Hexagon::A2_sxtb:
4284 case Hexagon::A2_sxth:
4285 case Hexagon::A2_zxtb:
4286 case Hexagon::A2_zxth:
4287 case Hexagon::dup_A2_sxtb:
4288 case Hexagon::dup_A2_sxth:
4289 case Hexagon::dup_A2_zxtb:
4290 case Hexagon::dup_A2_zxth:
4291 // Rd = sxth/sxtb/zxtb/zxth(Rs)
4292 DstReg = MI.getOperand(0).getReg();
4293 SrcReg = MI.getOperand(1).getReg();
4294 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4295 return HexagonII::HSIG_A;
4296 break;
4297 }
4298
4299 return HexagonII::HSIG_None;
4300}
4301
4303 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4304}
4305
4307 const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4308 // Default to one cycle for no itinerary. However, an "empty" itinerary may
4309 // still have a MinLatency property, which getStageLatency checks.
4310 if (!ItinData)
4311 return getInstrLatency(ItinData, MI);
4312
4313 if (MI.isTransient())
4314 return 0;
4315 return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4316}
4317
4318/// getOperandLatency - Compute and return the use operand latency of a given
4319/// pair of def and use.
4320/// In most cases, the static scheduling itinerary was enough to determine the
4321/// operand latency. But it may not be possible for instructions with variable
4322/// number of defs / uses.
4323///
4324/// This is a raw interface to the itinerary that may be directly overriden by
4325/// a target. Use computeOperandLatency to get the best estimate of latency.
4327 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4328 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {
4329 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4330
4331 // Get DefIdx and UseIdx for super registers.
4332 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4333
4334 if (DefMO.isReg() && DefMO.getReg().isPhysical()) {
4335 if (DefMO.isImplicit()) {
4336 for (MCPhysReg SR : HRI.superregs(DefMO.getReg())) {
4337 int Idx = DefMI.findRegisterDefOperandIdx(SR, false, false, &HRI);
4338 if (Idx != -1) {
4339 DefIdx = Idx;
4340 break;
4341 }
4342 }
4343 }
4344
4345 const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4346 if (UseMO.isImplicit()) {
4347 for (MCPhysReg SR : HRI.superregs(UseMO.getReg())) {
4348 int Idx = UseMI.findRegisterUseOperandIdx(SR, false, &HRI);
4349 if (Idx != -1) {
4350 UseIdx = Idx;
4351 break;
4352 }
4353 }
4354 }
4355 }
4356
4357 std::optional<unsigned> Latency = TargetInstrInfo::getOperandLatency(
4358 ItinData, DefMI, DefIdx, UseMI, UseIdx);
4359 if (Latency == 0)
4360 // We should never have 0 cycle latency between two instructions unless
4361 // they can be packetized together. However, this decision can't be made
4362 // here.
4363 Latency = 1;
4364 return Latency;
4365}
4366
4367// inverts the predication logic.
4368// p -> NotP
4369// NotP -> P
4372 if (Cond.empty())
4373 return false;
4374 unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4375 Cond[0].setImm(Opc);
4376 return true;
4377}
4378
4380 int InvPredOpcode;
4381 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4382 : Hexagon::getTruePredOpcode(Opc);
4383 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4384 return InvPredOpcode;
4385
4386 llvm_unreachable("Unexpected predicated instruction");
4387}
4388
4389// Returns the max value that doesn't need to be extended.
4391 const uint64_t F = MI.getDesc().TSFlags;
4392 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4394 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4396
4397 if (isSigned) // if value is signed
4398 return ~(-1U << (bits - 1));
4399 else
4400 return ~(-1U << bits);
4401}
4402
4403
4405 switch (MI.getOpcode()) {
4406 case Hexagon::L2_loadrbgp:
4407 case Hexagon::L2_loadrdgp:
4408 case Hexagon::L2_loadrhgp:
4409 case Hexagon::L2_loadrigp:
4410 case Hexagon::L2_loadrubgp:
4411 case Hexagon::L2_loadruhgp:
4412 case Hexagon::S2_storerbgp:
4413 case Hexagon::S2_storerbnewgp:
4414 case Hexagon::S2_storerhgp:
4415 case Hexagon::S2_storerhnewgp:
4416 case Hexagon::S2_storerigp:
4417 case Hexagon::S2_storerinewgp:
4418 case Hexagon::S2_storerdgp:
4419 case Hexagon::S2_storerfgp:
4420 return true;
4421 }
4422 const uint64_t F = MI.getDesc().TSFlags;
4423 unsigned addrMode =
4425 // Disallow any base+offset instruction. The assembler does not yet reorder
4426 // based up any zero offset instruction.
4427 return (addrMode == HexagonII::BaseRegOffset ||
4428 addrMode == HexagonII::BaseImmOffset ||
4429 addrMode == HexagonII::BaseLongOffset);
4430}
4431
4433 // Workaround for the Global Scheduler. Sometimes, it creates
4434 // A4_ext as a Pseudo instruction and calls this function to see if
4435 // it can be added to an existing bundle. Since the instruction doesn't
4436 // belong to any BB yet, we can't use getUnits API.
4437 if (MI.getOpcode() == Hexagon::A4_ext)
4438 return false;
4439
4440 unsigned FuncUnits = getUnits(MI);
4441 return HexagonFUnits::isSlot0Only(FuncUnits);
4442}
4443
4445 const uint64_t F = MI.getDesc().TSFlags;
4448}
4449
4451 bool ToBigInstrs) const {
4452 int Opcode = -1;
4453 if (ToBigInstrs) { // To BigCore Instr.
4454 // Check if the instruction can form a Duplex.
4455 if (getDuplexCandidateGroup(*MII))
4456 // Get the opcode marked "dup_*" tag.
4457 Opcode = getDuplexOpcode(*MII, ToBigInstrs);
4458 } else // To TinyCore Instr.
4459 Opcode = getDuplexOpcode(*MII, ToBigInstrs);
4460
4461 // Change the opcode of the instruction.
4462 if (Opcode >= 0)
4463 MII->setDesc(get(Opcode));
4464}
4465
4466// This function is used to translate instructions to facilitate generating
4467// Duplexes on TinyCore.
4469 bool ToBigInstrs) const {
4470 for (auto &MB : MF)
4471 for (MachineBasicBlock::instr_iterator Instr = MB.instr_begin(),
4472 End = MB.instr_end();
4473 Instr != End; ++Instr)
4474 changeDuplexOpcode(Instr, ToBigInstrs);
4475}
4476
4477// This is a specialized form of above function.
4479 MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const {
4481 while ((MII != MBB->instr_end()) && MII->isInsideBundle()) {
4482 changeDuplexOpcode(MII, ToBigInstrs);
4483 ++MII;
4484 }
4485}
4486
4488 using namespace HexagonII;
4489
4490 const uint64_t F = MI.getDesc().TSFlags;
4491 unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4492 unsigned Size = getMemAccessSizeInBytes(MemAccessSize(S));
4493 if (Size != 0)
4494 return Size;
4495 // Y2_dcfetchbo is special
4496 if (MI.getOpcode() == Hexagon::Y2_dcfetchbo)
4498
4499 // Handle vector access sizes.
4500 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4501 switch (S) {
4503 return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4504 default:
4505 llvm_unreachable("Unexpected instruction");
4506 }
4507}
4508
4509// Returns the min value that doesn't need to be extended.
4511 const uint64_t F = MI.getDesc().TSFlags;
4512 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4514 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4516
4517 if (isSigned) // if value is signed
4518 return -1U << (bits - 1);
4519 else
4520 return 0;
4521}
4522
4523// Returns opcode of the non-extended equivalent instruction.
4525 // Check if the instruction has a register form that uses register in place
4526 // of the extended operand, if so return that as the non-extended form.
4527 short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4528 if (NonExtOpcode >= 0)
4529 return NonExtOpcode;
4530
4531 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4532 // Check addressing mode and retrieve non-ext equivalent instruction.
4533 switch (getAddrMode(MI)) {
4535 return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4537 return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4539 return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4540
4541 default:
4542 return -1;
4543 }
4544 }
4545 return -1;
4546}
4547
4549 Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4550 if (Cond.empty())
4551 return false;
4552 assert(Cond.size() == 2);
4553 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4554 LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4555 return false;
4556 }
4557 PredReg = Cond[1].getReg();
4558 PredRegPos = 1;
4559 // See IfConversi