LLVM  13.0.0git
HexagonInstrInfo.cpp
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1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonInstrInfo.h"
14 #include "Hexagon.h"
15 #include "HexagonFrameLowering.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCInstrDesc.h"
45 #include "llvm/MC/MCRegisterInfo.h"
48 #include "llvm/Support/Debug.h"
54 #include <cassert>
55 #include <cctype>
56 #include <cstdint>
57 #include <cstring>
58 #include <iterator>
59 #include <string>
60 #include <utility>
61 
62 using namespace llvm;
63 
64 #define DEBUG_TYPE "hexagon-instrinfo"
65 
66 #define GET_INSTRINFO_CTOR_DTOR
67 #define GET_INSTRMAP_INFO
69 #include "HexagonGenDFAPacketizer.inc"
70 #include "HexagonGenInstrInfo.inc"
71 
72 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
73  cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
74  "packetization boundary."));
75 
76 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
77  cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
78 
79 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
81  cl::desc("Disable schedule adjustment for new value stores."));
82 
84  "enable-timing-class-latency", cl::Hidden, cl::init(false),
85  cl::desc("Enable timing class latency"));
86 
88  "enable-alu-forwarding", cl::Hidden, cl::init(true),
89  cl::desc("Enable vec alu forwarding"));
90 
92  "enable-acc-forwarding", cl::Hidden, cl::init(true),
93  cl::desc("Enable vec acc forwarding"));
94 
95 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
96  cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
97 
98 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
100  cl::desc("Use the DFA based hazard recognizer."));
101 
102 /// Constants for Hexagon instructions.
103 const int Hexagon_MEMW_OFFSET_MAX = 4095;
104 const int Hexagon_MEMW_OFFSET_MIN = -4096;
105 const int Hexagon_MEMD_OFFSET_MAX = 8191;
106 const int Hexagon_MEMD_OFFSET_MIN = -8192;
107 const int Hexagon_MEMH_OFFSET_MAX = 2047;
108 const int Hexagon_MEMH_OFFSET_MIN = -2048;
109 const int Hexagon_MEMB_OFFSET_MAX = 1023;
110 const int Hexagon_MEMB_OFFSET_MIN = -1024;
111 const int Hexagon_ADDI_OFFSET_MAX = 32767;
112 const int Hexagon_ADDI_OFFSET_MIN = -32768;
113 
114 // Pin the vtable to this file.
115 void HexagonInstrInfo::anchor() {}
116 
118  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
119  Subtarget(ST) {}
120 
121 namespace llvm {
122 namespace HexagonFUnits {
123  bool isSlot0Only(unsigned units);
124 }
125 }
126 
127 static bool isIntRegForSubInst(unsigned Reg) {
128  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
129  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
130 }
131 
132 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
133  return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
134  isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
135 }
136 
137 /// Calculate number of instructions excluding the debug instructions.
140  unsigned Count = 0;
141  for (; MIB != MIE; ++MIB) {
142  if (!MIB->isDebugInstr())
143  ++Count;
144  }
145  return Count;
146 }
147 
148 /// Find the hardware loop instruction used to set-up the specified loop.
149 /// On Hexagon, we have two instructions used to set-up the hardware loop
150 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
151 /// to indicate the end of a loop.
153  unsigned EndLoopOp, MachineBasicBlock *TargetBB,
154  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
155  unsigned LOOPi;
156  unsigned LOOPr;
157  if (EndLoopOp == Hexagon::ENDLOOP0) {
158  LOOPi = Hexagon::J2_loop0i;
159  LOOPr = Hexagon::J2_loop0r;
160  } else { // EndLoopOp == Hexagon::EndLOOP1
161  LOOPi = Hexagon::J2_loop1i;
162  LOOPr = Hexagon::J2_loop1r;
163  }
164 
165  // The loop set-up instruction will be in a predecessor block
166  for (MachineBasicBlock *PB : BB->predecessors()) {
167  // If this has been visited, already skip it.
168  if (!Visited.insert(PB).second)
169  continue;
170  if (PB == BB)
171  continue;
172  for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
173  unsigned Opc = I->getOpcode();
174  if (Opc == LOOPi || Opc == LOOPr)
175  return &*I;
176  // We've reached a different loop, which means the loop01 has been
177  // removed.
178  if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
179  return nullptr;
180  }
181  // Check the predecessors for the LOOP instruction.
182  if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
183  return Loop;
184  }
185  return nullptr;
186 }
187 
188 /// Gather register def/uses from MI.
189 /// This treats possible (predicated) defs as actually happening ones
190 /// (conservatively).
191 static inline void parseOperands(const MachineInstr &MI,
193  Defs.clear();
194  Uses.clear();
195 
196  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
197  const MachineOperand &MO = MI.getOperand(i);
198 
199  if (!MO.isReg())
200  continue;
201 
202  Register Reg = MO.getReg();
203  if (!Reg)
204  continue;
205 
206  if (MO.isUse())
207  Uses.push_back(MO.getReg());
208 
209  if (MO.isDef())
210  Defs.push_back(MO.getReg());
211  }
212 }
213 
214 // Position dependent, so check twice for swap.
215 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
216  switch (Ga) {
218  default:
219  return false;
220  case HexagonII::HSIG_L1:
221  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
222  case HexagonII::HSIG_L2:
223  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
224  Gb == HexagonII::HSIG_A);
225  case HexagonII::HSIG_S1:
226  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
227  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
228  case HexagonII::HSIG_S2:
229  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
230  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
231  Gb == HexagonII::HSIG_A);
232  case HexagonII::HSIG_A:
233  return (Gb == HexagonII::HSIG_A);
235  return (Gb == HexagonII::HSIG_Compound);
236  }
237  return false;
238 }
239 
240 /// isLoadFromStackSlot - If the specified machine instruction is a direct
241 /// load from a stack slot, return the virtual or physical register number of
242 /// the destination along with the FrameIndex of the loaded stack slot. If
243 /// not, return 0. This predicate must return 0 if the instruction has
244 /// any side effects other than loading from the stack slot.
246  int &FrameIndex) const {
247  switch (MI.getOpcode()) {
248  default:
249  break;
250  case Hexagon::L2_loadri_io:
251  case Hexagon::L2_loadrd_io:
252  case Hexagon::V6_vL32b_ai:
253  case Hexagon::V6_vL32b_nt_ai:
254  case Hexagon::V6_vL32Ub_ai:
255  case Hexagon::LDriw_pred:
256  case Hexagon::LDriw_ctr:
257  case Hexagon::PS_vloadrq_ai:
258  case Hexagon::PS_vloadrw_ai:
259  case Hexagon::PS_vloadrw_nt_ai: {
260  const MachineOperand OpFI = MI.getOperand(1);
261  if (!OpFI.isFI())
262  return 0;
263  const MachineOperand OpOff = MI.getOperand(2);
264  if (!OpOff.isImm() || OpOff.getImm() != 0)
265  return 0;
266  FrameIndex = OpFI.getIndex();
267  return MI.getOperand(0).getReg();
268  }
269 
270  case Hexagon::L2_ploadrit_io:
271  case Hexagon::L2_ploadrif_io:
272  case Hexagon::L2_ploadrdt_io:
273  case Hexagon::L2_ploadrdf_io: {
274  const MachineOperand OpFI = MI.getOperand(2);
275  if (!OpFI.isFI())
276  return 0;
277  const MachineOperand OpOff = MI.getOperand(3);
278  if (!OpOff.isImm() || OpOff.getImm() != 0)
279  return 0;
280  FrameIndex = OpFI.getIndex();
281  return MI.getOperand(0).getReg();
282  }
283  }
284 
285  return 0;
286 }
287 
288 /// isStoreToStackSlot - If the specified machine instruction is a direct
289 /// store to a stack slot, return the virtual or physical register number of
290 /// the source reg along with the FrameIndex of the loaded stack slot. If
291 /// not, return 0. This predicate must return 0 if the instruction has
292 /// any side effects other than storing to the stack slot.
294  int &FrameIndex) const {
295  switch (MI.getOpcode()) {
296  default:
297  break;
298  case Hexagon::S2_storerb_io:
299  case Hexagon::S2_storerh_io:
300  case Hexagon::S2_storeri_io:
301  case Hexagon::S2_storerd_io:
302  case Hexagon::V6_vS32b_ai:
303  case Hexagon::V6_vS32Ub_ai:
304  case Hexagon::STriw_pred:
305  case Hexagon::STriw_ctr:
306  case Hexagon::PS_vstorerq_ai:
307  case Hexagon::PS_vstorerw_ai: {
308  const MachineOperand &OpFI = MI.getOperand(0);
309  if (!OpFI.isFI())
310  return 0;
311  const MachineOperand &OpOff = MI.getOperand(1);
312  if (!OpOff.isImm() || OpOff.getImm() != 0)
313  return 0;
314  FrameIndex = OpFI.getIndex();
315  return MI.getOperand(2).getReg();
316  }
317 
318  case Hexagon::S2_pstorerbt_io:
319  case Hexagon::S2_pstorerbf_io:
320  case Hexagon::S2_pstorerht_io:
321  case Hexagon::S2_pstorerhf_io:
322  case Hexagon::S2_pstorerit_io:
323  case Hexagon::S2_pstorerif_io:
324  case Hexagon::S2_pstorerdt_io:
325  case Hexagon::S2_pstorerdf_io: {
326  const MachineOperand &OpFI = MI.getOperand(1);
327  if (!OpFI.isFI())
328  return 0;
329  const MachineOperand &OpOff = MI.getOperand(2);
330  if (!OpOff.isImm() || OpOff.getImm() != 0)
331  return 0;
332  FrameIndex = OpFI.getIndex();
333  return MI.getOperand(3).getReg();
334  }
335  }
336 
337  return 0;
338 }
339 
340 /// This function checks if the instruction or bundle of instructions
341 /// has load from stack slot and returns frameindex and machine memory
342 /// operand of that instruction if true.
344  const MachineInstr &MI,
346  if (MI.isBundle()) {
347  const MachineBasicBlock *MBB = MI.getParent();
348  MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
349  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
350  if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
351  return true;
352  return false;
353  }
354 
355  return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
356 }
357 
358 /// This function checks if the instruction or bundle of instructions
359 /// has store to stack slot and returns frameindex and machine memory
360 /// operand of that instruction if true.
362  const MachineInstr &MI,
364  if (MI.isBundle()) {
365  const MachineBasicBlock *MBB = MI.getParent();
366  MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
367  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
368  if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
369  return true;
370  return false;
371  }
372 
373  return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
374 }
375 
376 /// This function can analyze one/two way branching only and should (mostly) be
377 /// called by target independent side.
378 /// First entry is always the opcode of the branching instruction, except when
379 /// the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a
380 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
381 /// e.g. Jump_c p will have
382 /// Cond[0] = Jump_c
383 /// Cond[1] = p
384 /// HW-loop ENDLOOP:
385 /// Cond[0] = ENDLOOP
386 /// Cond[1] = MBB
387 /// New value jump:
388 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
389 /// Cond[1] = R
390 /// Cond[2] = Imm
392  MachineBasicBlock *&TBB,
393  MachineBasicBlock *&FBB,
395  bool AllowModify) const {
396  TBB = nullptr;
397  FBB = nullptr;
398  Cond.clear();
399 
400  // If the block has no terminators, it just falls into the block after it.
402  if (I == MBB.instr_begin())
403  return false;
404 
405  // A basic block may looks like this:
406  //
407  // [ insn
408  // EH_LABEL
409  // insn
410  // insn
411  // insn
412  // EH_LABEL
413  // insn ]
414  //
415  // It has two succs but does not have a terminator
416  // Don't know how to handle it.
417  do {
418  --I;
419  if (I->isEHLabel())
420  // Don't analyze EH branches.
421  return true;
422  } while (I != MBB.instr_begin());
423 
424  I = MBB.instr_end();
425  --I;
426 
427  while (I->isDebugInstr()) {
428  if (I == MBB.instr_begin())
429  return false;
430  --I;
431  }
432 
433  bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
434  I->getOperand(0).isMBB();
435  // Delete the J2_jump if it's equivalent to a fall-through.
436  if (AllowModify && JumpToBlock &&
437  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
438  LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
439  I->eraseFromParent();
440  I = MBB.instr_end();
441  if (I == MBB.instr_begin())
442  return false;
443  --I;
444  }
445  if (!isUnpredicatedTerminator(*I))
446  return false;
447 
448  // Get the last instruction in the block.
449  MachineInstr *LastInst = &*I;
450  MachineInstr *SecondLastInst = nullptr;
451  // Find one more terminator if present.
452  while (true) {
453  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
454  if (!SecondLastInst)
455  SecondLastInst = &*I;
456  else
457  // This is a third branch.
458  return true;
459  }
460  if (I == MBB.instr_begin())
461  break;
462  --I;
463  }
464 
465  int LastOpcode = LastInst->getOpcode();
466  int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
467  // If the branch target is not a basic block, it could be a tail call.
468  // (It is, if the target is a function.)
469  if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
470  return true;
471  if (SecLastOpcode == Hexagon::J2_jump &&
472  !SecondLastInst->getOperand(0).isMBB())
473  return true;
474 
475  bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
476  bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
477 
478  if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
479  return true;
480 
481  // If there is only one terminator instruction, process it.
482  if (LastInst && !SecondLastInst) {
483  if (LastOpcode == Hexagon::J2_jump) {
484  TBB = LastInst->getOperand(0).getMBB();
485  return false;
486  }
487  if (isEndLoopN(LastOpcode)) {
488  TBB = LastInst->getOperand(0).getMBB();
489  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
490  Cond.push_back(LastInst->getOperand(0));
491  return false;
492  }
493  if (LastOpcodeHasJMP_c) {
494  TBB = LastInst->getOperand(1).getMBB();
495  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
496  Cond.push_back(LastInst->getOperand(0));
497  return false;
498  }
499  // Only supporting rr/ri versions of new-value jumps.
500  if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
501  TBB = LastInst->getOperand(2).getMBB();
502  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
503  Cond.push_back(LastInst->getOperand(0));
504  Cond.push_back(LastInst->getOperand(1));
505  return false;
506  }
507  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
508  << " with one jump\n";);
509  // Otherwise, don't know what this is.
510  return true;
511  }
512 
513  bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
514  bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
515  if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
516  if (!SecondLastInst->getOperand(1).isMBB())
517  return true;
518  TBB = SecondLastInst->getOperand(1).getMBB();
519  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
520  Cond.push_back(SecondLastInst->getOperand(0));
521  FBB = LastInst->getOperand(0).getMBB();
522  return false;
523  }
524 
525  // Only supporting rr/ri versions of new-value jumps.
526  if (SecLastOpcodeHasNVJump &&
527  (SecondLastInst->getNumExplicitOperands() == 3) &&
528  (LastOpcode == Hexagon::J2_jump)) {
529  TBB = SecondLastInst->getOperand(2).getMBB();
530  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
531  Cond.push_back(SecondLastInst->getOperand(0));
532  Cond.push_back(SecondLastInst->getOperand(1));
533  FBB = LastInst->getOperand(0).getMBB();
534  return false;
535  }
536 
537  // If the block ends with two Hexagon:JMPs, handle it. The second one is not
538  // executed, so remove it.
539  if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
540  TBB = SecondLastInst->getOperand(0).getMBB();
541  I = LastInst->getIterator();
542  if (AllowModify)
543  I->eraseFromParent();
544  return false;
545  }
546 
547  // If the block ends with an ENDLOOP, and J2_jump, handle it.
548  if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
549  TBB = SecondLastInst->getOperand(0).getMBB();
550  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
551  Cond.push_back(SecondLastInst->getOperand(0));
552  FBB = LastInst->getOperand(0).getMBB();
553  return false;
554  }
555  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
556  << " with two jumps";);
557  // Otherwise, can't handle this.
558  return true;
559 }
560 
562  int *BytesRemoved) const {
563  assert(!BytesRemoved && "code size not handled");
564 
565  LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
567  unsigned Count = 0;
568  while (I != MBB.begin()) {
569  --I;
570  if (I->isDebugInstr())
571  continue;
572  // Only removing branches from end of MBB.
573  if (!I->isBranch())
574  return Count;
575  if (Count && (I->getOpcode() == Hexagon::J2_jump))
576  llvm_unreachable("Malformed basic block: unconditional branch not last");
577  MBB.erase(&MBB.back());
578  I = MBB.end();
579  ++Count;
580  }
581  return Count;
582 }
583 
585  MachineBasicBlock *TBB,
586  MachineBasicBlock *FBB,
588  const DebugLoc &DL,
589  int *BytesAdded) const {
590  unsigned BOpc = Hexagon::J2_jump;
591  unsigned BccOpc = Hexagon::J2_jumpt;
592  assert(validateBranchCond(Cond) && "Invalid branching condition");
593  assert(TBB && "insertBranch must not be told to insert a fallthrough");
594  assert(!BytesAdded && "code size not handled");
595 
596  // Check if reverseBranchCondition has asked to reverse this branch
597  // If we want to reverse the branch an odd number of times, we want
598  // J2_jumpf.
599  if (!Cond.empty() && Cond[0].isImm())
600  BccOpc = Cond[0].getImm();
601 
602  if (!FBB) {
603  if (Cond.empty()) {
604  // Due to a bug in TailMerging/CFG Optimization, we need to add a
605  // special case handling of a predicated jump followed by an
606  // unconditional jump. If not, Tail Merging and CFG Optimization go
607  // into an infinite loop.
608  MachineBasicBlock *NewTBB, *NewFBB;
610  auto Term = MBB.getFirstTerminator();
611  if (Term != MBB.end() && isPredicated(*Term) &&
612  !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
613  MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
615  removeBranch(MBB);
616  return insertBranch(MBB, TBB, nullptr, Cond, DL);
617  }
618  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
619  } else if (isEndLoopN(Cond[0].getImm())) {
620  int EndLoopOp = Cond[0].getImm();
621  assert(Cond[1].isMBB());
622  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
623  // Check for it, and change the BB target if needed.
625  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
626  VisitedBBs);
627  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
628  Loop->getOperand(0).setMBB(TBB);
629  // Add the ENDLOOP after the finding the LOOP0.
630  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
631  } else if (isNewValueJump(Cond[0].getImm())) {
632  assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
633  // New value jump
634  // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
635  // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
636  unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
637  LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
638  << printMBBReference(MBB););
639  if (Cond[2].isReg()) {
640  unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
641  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
642  addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
643  } else if(Cond[2].isImm()) {
644  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
645  addImm(Cond[2].getImm()).addMBB(TBB);
646  } else
647  llvm_unreachable("Invalid condition for branching");
648  } else {
649  assert((Cond.size() == 2) && "Malformed cond vector");
650  const MachineOperand &RO = Cond[1];
651  unsigned Flags = getUndefRegState(RO.isUndef());
652  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
653  }
654  return 1;
655  }
656  assert((!Cond.empty()) &&
657  "Cond. cannot be empty when multiple branchings are required");
658  assert((!isNewValueJump(Cond[0].getImm())) &&
659  "NV-jump cannot be inserted with another branch");
660  // Special case for hardware loops. The condition is a basic block.
661  if (isEndLoopN(Cond[0].getImm())) {
662  int EndLoopOp = Cond[0].getImm();
663  assert(Cond[1].isMBB());
664  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
665  // Check for it, and change the BB target if needed.
667  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
668  VisitedBBs);
669  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
670  Loop->getOperand(0).setMBB(TBB);
671  // Add the ENDLOOP after the finding the LOOP0.
672  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
673  } else {
674  const MachineOperand &RO = Cond[1];
675  unsigned Flags = getUndefRegState(RO.isUndef());
676  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
677  }
678  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
679 
680  return 2;
681 }
682 
683 namespace {
684 class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
685  MachineInstr *Loop, *EndLoop;
686  MachineFunction *MF;
687  const HexagonInstrInfo *TII;
688  int64_t TripCount;
689  Register LoopCount;
690  DebugLoc DL;
691 
692 public:
693  HexagonPipelinerLoopInfo(MachineInstr *Loop, MachineInstr *EndLoop)
694  : Loop(Loop), EndLoop(EndLoop), MF(Loop->getParent()->getParent()),
695  TII(MF->getSubtarget<HexagonSubtarget>().getInstrInfo()),
696  DL(Loop->getDebugLoc()) {
697  // Inspect the Loop instruction up-front, as it may be deleted when we call
698  // createTripCountGreaterCondition.
699  TripCount = Loop->getOpcode() == Hexagon::J2_loop0r
700  ? -1
701  : Loop->getOperand(1).getImm();
702  if (TripCount == -1)
703  LoopCount = Loop->getOperand(1).getReg();
704  }
705 
706  bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
707  // Only ignore the terminator.
708  return MI == EndLoop;
709  }
710 
712  createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
714  if (TripCount == -1) {
715  // Check if we're done with the loop.
716  unsigned Done = TII->createVR(MF, MVT::i1);
717  MachineInstr *NewCmp = BuildMI(&MBB, DL,
718  TII->get(Hexagon::C2_cmpgtui), Done)
719  .addReg(LoopCount)
720  .addImm(TC);
721  Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
722  Cond.push_back(NewCmp->getOperand(0));
723  return {};
724  }
725 
726  return TripCount > TC;
727  }
728 
729  void setPreheader(MachineBasicBlock *NewPreheader) override {
730  NewPreheader->splice(NewPreheader->getFirstTerminator(), Loop->getParent(),
731  Loop);
732  }
733 
734  void adjustTripCount(int TripCountAdjust) override {
735  // If the loop trip count is a compile-time value, then just change the
736  // value.
737  if (Loop->getOpcode() == Hexagon::J2_loop0i ||
738  Loop->getOpcode() == Hexagon::J2_loop1i) {
739  int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust;
740  assert(TripCount > 0 && "Can't create an empty or negative loop!");
741  Loop->getOperand(1).setImm(TripCount);
742  return;
743  }
744 
745  // The loop trip count is a run-time value. We generate code to subtract
746  // one from the trip count, and update the loop instruction.
747  Register LoopCount = Loop->getOperand(1).getReg();
748  Register NewLoopCount = TII->createVR(MF, MVT::i32);
749  BuildMI(*Loop->getParent(), Loop, Loop->getDebugLoc(),
750  TII->get(Hexagon::A2_addi), NewLoopCount)
751  .addReg(LoopCount)
752  .addImm(TripCountAdjust);
753  Loop->getOperand(1).setReg(NewLoopCount);
754  }
755 
756  void disposed() override { Loop->eraseFromParent(); }
757 };
758 } // namespace
759 
760 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
762  // We really "analyze" only hardware loops right now.
764 
765  if (I != LoopBB->end() && isEndLoopN(I->getOpcode())) {
767  MachineInstr *LoopInst = findLoopInstr(
768  LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
769  if (LoopInst)
770  return std::make_unique<HexagonPipelinerLoopInfo>(LoopInst, &*I);
771  }
772  return nullptr;
773 }
774 
776  unsigned NumCycles, unsigned ExtraPredCycles,
777  BranchProbability Probability) const {
778  return nonDbgBBSize(&MBB) <= 3;
779 }
780 
782  unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
783  unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
784  const {
785  return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
786 }
787 
789  unsigned NumInstrs, BranchProbability Probability) const {
790  return NumInstrs <= 4;
791 }
792 
793 static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
795  const MachineBasicBlock &B = *MI.getParent();
796  Regs.addLiveIns(B);
797  auto E = MachineBasicBlock::const_iterator(MI.getIterator());
798  for (auto I = B.begin(); I != E; ++I) {
799  Clobbers.clear();
800  Regs.stepForward(*I, Clobbers);
801  }
802 }
803 
804 static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
805  const MachineBasicBlock &B = *MI.getParent();
806  Regs.addLiveOuts(B);
807  auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
808  for (auto I = B.rbegin(); I != E; ++I)
809  Regs.stepBackward(*I);
810 }
811 
814  const DebugLoc &DL, MCRegister DestReg,
815  MCRegister SrcReg, bool KillSrc) const {
816  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
817  unsigned KillFlag = getKillRegState(KillSrc);
818 
819  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
820  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
821  .addReg(SrcReg, KillFlag);
822  return;
823  }
824  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
825  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
826  .addReg(SrcReg, KillFlag);
827  return;
828  }
829  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
830  // Map Pd = Ps to Pd = or(Ps, Ps).
831  BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
832  .addReg(SrcReg).addReg(SrcReg, KillFlag);
833  return;
834  }
835  if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
836  Hexagon::IntRegsRegClass.contains(SrcReg)) {
837  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
838  .addReg(SrcReg, KillFlag);
839  return;
840  }
841  if (Hexagon::IntRegsRegClass.contains(DestReg) &&
842  Hexagon::CtrRegsRegClass.contains(SrcReg)) {
843  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
844  .addReg(SrcReg, KillFlag);
845  return;
846  }
847  if (Hexagon::ModRegsRegClass.contains(DestReg) &&
848  Hexagon::IntRegsRegClass.contains(SrcReg)) {
849  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
850  .addReg(SrcReg, KillFlag);
851  return;
852  }
853  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
854  Hexagon::IntRegsRegClass.contains(DestReg)) {
855  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
856  .addReg(SrcReg, KillFlag);
857  return;
858  }
859  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
860  Hexagon::PredRegsRegClass.contains(DestReg)) {
861  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
862  .addReg(SrcReg, KillFlag);
863  return;
864  }
865  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
866  Hexagon::IntRegsRegClass.contains(DestReg)) {
867  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
868  .addReg(SrcReg, KillFlag);
869  return;
870  }
871  if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
872  BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
873  addReg(SrcReg, KillFlag);
874  return;
875  }
876  if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
877  LivePhysRegs LiveAtMI(HRI);
878  getLiveInRegsAt(LiveAtMI, *I);
879  Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
880  Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
881  unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo));
882  unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi));
883  BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
884  .addReg(SrcHi, KillFlag | UndefHi)
885  .addReg(SrcLo, KillFlag | UndefLo);
886  return;
887  }
888  if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
889  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
890  .addReg(SrcReg)
891  .addReg(SrcReg, KillFlag);
892  return;
893  }
894  if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
895  Hexagon::HvxVRRegClass.contains(DestReg)) {
896  llvm_unreachable("Unimplemented pred to vec");
897  return;
898  }
899  if (Hexagon::HvxQRRegClass.contains(DestReg) &&
900  Hexagon::HvxVRRegClass.contains(SrcReg)) {
901  llvm_unreachable("Unimplemented vec to pred");
902  return;
903  }
904 
905 #ifndef NDEBUG
906  // Show the invalid registers to ease debugging.
907  dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
908  << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
909 #endif
910  llvm_unreachable("Unimplemented");
911 }
912 
914  MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI,
915  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
917  MachineFunction &MF = *MBB.getParent();
918  MachineFrameInfo &MFI = MF.getFrameInfo();
919  unsigned KillFlag = getKillRegState(isKill);
920 
923  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
924 
925  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
926  BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
927  .addFrameIndex(FI).addImm(0)
928  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
929  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
930  BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
931  .addFrameIndex(FI).addImm(0)
932  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
933  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
934  BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
935  .addFrameIndex(FI).addImm(0)
936  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
937  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
938  BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
939  .addFrameIndex(FI).addImm(0)
940  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
941  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
942  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
943  .addFrameIndex(FI).addImm(0)
944  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
945  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
946  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerv_ai))
947  .addFrameIndex(FI).addImm(0)
948  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
949  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
950  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerw_ai))
951  .addFrameIndex(FI).addImm(0)
952  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
953  } else {
954  llvm_unreachable("Unimplemented");
955  }
956 }
957 
960  int FI, const TargetRegisterClass *RC,
961  const TargetRegisterInfo *TRI) const {
963  MachineFunction &MF = *MBB.getParent();
964  MachineFrameInfo &MFI = MF.getFrameInfo();
965 
968  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
969 
970  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
971  BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
972  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
973  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
974  BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
975  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
976  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
977  BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
978  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
979  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
980  BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
981  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
982  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
983  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
984  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
985  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
986  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrv_ai), DestReg)
987  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
988  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
989  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrw_ai), DestReg)
990  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
991  } else {
992  llvm_unreachable("Can't store this register to stack slot");
993  }
994 }
995 
996 /// expandPostRAPseudo - This function is called for all pseudo instructions
997 /// that remain after register allocation. Many pseudo instructions are
998 /// created to help register allocation. This is the place to convert them
999 /// into real instructions. The target can edit MI in place, or it can insert
1000 /// new instructions and erase MI. The function should return true if
1001 /// anything was changed.
1003  MachineBasicBlock &MBB = *MI.getParent();
1004  MachineFunction &MF = *MBB.getParent();
1006  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1007  LivePhysRegs LiveIn(HRI), LiveOut(HRI);
1008  DebugLoc DL = MI.getDebugLoc();
1009  unsigned Opc = MI.getOpcode();
1010 
1011  auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1012  Register Mx = MI.getOperand(MxOp).getReg();
1013  unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1014  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1015  .add(MI.getOperand((HasImm ? 5 : 4)));
1016  auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1017  .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1018  if (HasImm)
1019  MIB.add(MI.getOperand(4));
1020  MIB.addReg(CSx, RegState::Implicit);
1021  MBB.erase(MI);
1022  return true;
1023  };
1024 
1025  auto UseAligned = [&] (const MachineInstr &MI, unsigned NeedAlign) {
1026  if (MI.memoperands().empty())
1027  return false;
1028  return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) {
1029  return MMO->getAlign() >= NeedAlign;
1030  });
1031  };
1032 
1033  switch (Opc) {
1034  case TargetOpcode::COPY: {
1035  MachineOperand &MD = MI.getOperand(0);
1036  MachineOperand &MS = MI.getOperand(1);
1037  MachineBasicBlock::iterator MBBI = MI.getIterator();
1038  if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1039  copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1040  std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1041  }
1042  MBB.erase(MBBI);
1043  return true;
1044  }
1045  case Hexagon::PS_aligna:
1046  BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1047  .addReg(HRI.getFrameRegister())
1048  .addImm(-MI.getOperand(1).getImm());
1049  MBB.erase(MI);
1050  return true;
1051  case Hexagon::V6_vassignp: {
1052  Register SrcReg = MI.getOperand(1).getReg();
1053  Register DstReg = MI.getOperand(0).getReg();
1054  Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1055  Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1056  getLiveInRegsAt(LiveIn, MI);
1057  unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
1058  unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));
1059  unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1060  BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1061  .addReg(SrcHi, UndefHi)
1062  .addReg(SrcLo, Kill | UndefLo);
1063  MBB.erase(MI);
1064  return true;
1065  }
1066  case Hexagon::V6_lo: {
1067  Register SrcReg = MI.getOperand(1).getReg();
1068  Register DstReg = MI.getOperand(0).getReg();
1069  Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1070  copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1071  MBB.erase(MI);
1072  MRI.clearKillFlags(SrcSubLo);
1073  return true;
1074  }
1075  case Hexagon::V6_hi: {
1076  Register SrcReg = MI.getOperand(1).getReg();
1077  Register DstReg = MI.getOperand(0).getReg();
1078  Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1079  copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1080  MBB.erase(MI);
1081  MRI.clearKillFlags(SrcSubHi);
1082  return true;
1083  }
1084  case Hexagon::PS_vloadrv_ai: {
1085  Register DstReg = MI.getOperand(0).getReg();
1086  const MachineOperand &BaseOp = MI.getOperand(1);
1087  assert(BaseOp.getSubReg() == 0);
1088  int Offset = MI.getOperand(2).getImm();
1089  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1090  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1091  : Hexagon::V6_vL32Ub_ai;
1092  BuildMI(MBB, MI, DL, get(NewOpc), DstReg)
1093  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1094  .addImm(Offset)
1095  .cloneMemRefs(MI);
1096  MBB.erase(MI);
1097  return true;
1098  }
1099  case Hexagon::PS_vloadrw_ai: {
1100  Register DstReg = MI.getOperand(0).getReg();
1101  const MachineOperand &BaseOp = MI.getOperand(1);
1102  assert(BaseOp.getSubReg() == 0);
1103  int Offset = MI.getOperand(2).getImm();
1104  unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1105  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1106  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1107  : Hexagon::V6_vL32Ub_ai;
1108  BuildMI(MBB, MI, DL, get(NewOpc),
1109  HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1110  .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1111  .addImm(Offset)
1112  .cloneMemRefs(MI);
1113  BuildMI(MBB, MI, DL, get(NewOpc),
1114  HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1115  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1116  .addImm(Offset + VecOffset)
1117  .cloneMemRefs(MI);
1118  MBB.erase(MI);
1119  return true;
1120  }
1121  case Hexagon::PS_vstorerv_ai: {
1122  const MachineOperand &SrcOp = MI.getOperand(2);
1123  assert(SrcOp.getSubReg() == 0);
1124  const MachineOperand &BaseOp = MI.getOperand(0);
1125  assert(BaseOp.getSubReg() == 0);
1126  int Offset = MI.getOperand(1).getImm();
1127  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1128  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1129  : Hexagon::V6_vS32Ub_ai;
1130  BuildMI(MBB, MI, DL, get(NewOpc))
1131  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1132  .addImm(Offset)
1134  .cloneMemRefs(MI);
1135  MBB.erase(MI);
1136  return true;
1137  }
1138  case Hexagon::PS_vstorerw_ai: {
1139  Register SrcReg = MI.getOperand(2).getReg();
1140  const MachineOperand &BaseOp = MI.getOperand(0);
1141  assert(BaseOp.getSubReg() == 0);
1142  int Offset = MI.getOperand(1).getImm();
1143  unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1144  unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1145  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1146  : Hexagon::V6_vS32Ub_ai;
1147  BuildMI(MBB, MI, DL, get(NewOpc))
1148  .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1149  .addImm(Offset)
1150  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo))
1151  .cloneMemRefs(MI);
1152  BuildMI(MBB, MI, DL, get(NewOpc))
1153  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1154  .addImm(Offset + VecOffset)
1155  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi))
1156  .cloneMemRefs(MI);
1157  MBB.erase(MI);
1158  return true;
1159  }
1160  case Hexagon::PS_true: {
1161  Register Reg = MI.getOperand(0).getReg();
1162  BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1165  MBB.erase(MI);
1166  return true;
1167  }
1168  case Hexagon::PS_false: {
1169  Register Reg = MI.getOperand(0).getReg();
1170  BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1173  MBB.erase(MI);
1174  return true;
1175  }
1176  case Hexagon::PS_qtrue: {
1177  BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1178  .addReg(Hexagon::V0, RegState::Undef)
1179  .addReg(Hexagon::V0, RegState::Undef);
1180  MBB.erase(MI);
1181  return true;
1182  }
1183  case Hexagon::PS_qfalse: {
1184  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1185  .addReg(Hexagon::V0, RegState::Undef)
1186  .addReg(Hexagon::V0, RegState::Undef);
1187  MBB.erase(MI);
1188  return true;
1189  }
1190  case Hexagon::PS_vdd0: {
1191  Register Vd = MI.getOperand(0).getReg();
1192  BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1193  .addReg(Vd, RegState::Undef)
1194  .addReg(Vd, RegState::Undef);
1195  MBB.erase(MI);
1196  return true;
1197  }
1198  case Hexagon::PS_vmulw: {
1199  // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1200  Register DstReg = MI.getOperand(0).getReg();
1201  Register Src1Reg = MI.getOperand(1).getReg();
1202  Register Src2Reg = MI.getOperand(2).getReg();
1203  Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1204  Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1205  Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1206  Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1207  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1208  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1209  .addReg(Src1SubHi)
1210  .addReg(Src2SubHi);
1211  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1212  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1213  .addReg(Src1SubLo)
1214  .addReg(Src2SubLo);
1215  MBB.erase(MI);
1216  MRI.clearKillFlags(Src1SubHi);
1217  MRI.clearKillFlags(Src1SubLo);
1218  MRI.clearKillFlags(Src2SubHi);
1219  MRI.clearKillFlags(Src2SubLo);
1220  return true;
1221  }
1222  case Hexagon::PS_vmulw_acc: {
1223  // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1224  Register DstReg = MI.getOperand(0).getReg();
1225  Register Src1Reg = MI.getOperand(1).getReg();
1226  Register Src2Reg = MI.getOperand(2).getReg();
1227  Register Src3Reg = MI.getOperand(3).getReg();
1228  Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1229  Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1230  Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1231  Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1232  Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1233  Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1234  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1235  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1236  .addReg(Src1SubHi)
1237  .addReg(Src2SubHi)
1238  .addReg(Src3SubHi);
1239  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1240  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1241  .addReg(Src1SubLo)
1242  .addReg(Src2SubLo)
1243  .addReg(Src3SubLo);
1244  MBB.erase(MI);
1245  MRI.clearKillFlags(Src1SubHi);
1246  MRI.clearKillFlags(Src1SubLo);
1247  MRI.clearKillFlags(Src2SubHi);
1248  MRI.clearKillFlags(Src2SubLo);
1249  MRI.clearKillFlags(Src3SubHi);
1250  MRI.clearKillFlags(Src3SubLo);
1251  return true;
1252  }
1253  case Hexagon::PS_pselect: {
1254  const MachineOperand &Op0 = MI.getOperand(0);
1255  const MachineOperand &Op1 = MI.getOperand(1);
1256  const MachineOperand &Op2 = MI.getOperand(2);
1257  const MachineOperand &Op3 = MI.getOperand(3);
1258  Register Rd = Op0.getReg();
1259  Register Pu = Op1.getReg();
1260  Register Rs = Op2.getReg();
1261  Register Rt = Op3.getReg();
1262  DebugLoc DL = MI.getDebugLoc();
1263  unsigned K1 = getKillRegState(Op1.isKill());
1264  unsigned K2 = getKillRegState(Op2.isKill());
1265  unsigned K3 = getKillRegState(Op3.isKill());
1266  if (Rd != Rs)
1267  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1268  .addReg(Pu, (Rd == Rt) ? K1 : 0)
1269  .addReg(Rs, K2);
1270  if (Rd != Rt)
1271  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1272  .addReg(Pu, K1)
1273  .addReg(Rt, K3);
1274  MBB.erase(MI);
1275  return true;
1276  }
1277  case Hexagon::PS_vselect: {
1278  const MachineOperand &Op0 = MI.getOperand(0);
1279  const MachineOperand &Op1 = MI.getOperand(1);
1280  const MachineOperand &Op2 = MI.getOperand(2);
1281  const MachineOperand &Op3 = MI.getOperand(3);
1282  getLiveOutRegsAt(LiveOut, MI);
1283  bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
1284  Register PReg = Op1.getReg();
1285  assert(Op1.getSubReg() == 0);
1286  unsigned PState = getRegState(Op1);
1287 
1288  if (Op0.getReg() != Op2.getReg()) {
1289  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1290  : PState;
1291  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1292  .add(Op0)
1293  .addReg(PReg, S)
1294  .add(Op2);
1295  if (IsDestLive)
1296  T.addReg(Op0.getReg(), RegState::Implicit);
1297  IsDestLive = true;
1298  }
1299  if (Op0.getReg() != Op3.getReg()) {
1300  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1301  .add(Op0)
1302  .addReg(PReg, PState)
1303  .add(Op3);
1304  if (IsDestLive)
1305  T.addReg(Op0.getReg(), RegState::Implicit);
1306  }
1307  MBB.erase(MI);
1308  return true;
1309  }
1310  case Hexagon::PS_wselect: {
1311  MachineOperand &Op0 = MI.getOperand(0);
1312  MachineOperand &Op1 = MI.getOperand(1);
1313  MachineOperand &Op2 = MI.getOperand(2);
1314  MachineOperand &Op3 = MI.getOperand(3);
1315  getLiveOutRegsAt(LiveOut, MI);
1316  bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
1317  Register PReg = Op1.getReg();
1318  assert(Op1.getSubReg() == 0);
1319  unsigned PState = getRegState(Op1);
1320 
1321  if (Op0.getReg() != Op2.getReg()) {
1322  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1323  : PState;
1324  Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1325  Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1326  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1327  .add(Op0)
1328  .addReg(PReg, S)
1329  .addReg(SrcHi)
1330  .addReg(SrcLo);
1331  if (IsDestLive)
1332  T.addReg(Op0.getReg(), RegState::Implicit);
1333  IsDestLive = true;
1334  }
1335  if (Op0.getReg() != Op3.getReg()) {
1336  Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1337  Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1338  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1339  .add(Op0)
1340  .addReg(PReg, PState)
1341  .addReg(SrcHi)
1342  .addReg(SrcLo);
1343  if (IsDestLive)
1344  T.addReg(Op0.getReg(), RegState::Implicit);
1345  }
1346  MBB.erase(MI);
1347  return true;
1348  }
1349 
1350  case Hexagon::PS_crash: {
1351  // Generate a misaligned load that is guaranteed to cause a crash.
1352  class CrashPseudoSourceValue : public PseudoSourceValue {
1353  public:
1354  CrashPseudoSourceValue(const TargetInstrInfo &TII)
1355  : PseudoSourceValue(TargetCustom, TII) {}
1356 
1357  bool isConstant(const MachineFrameInfo *) const override {
1358  return false;
1359  }
1360  bool isAliased(const MachineFrameInfo *) const override {
1361  return false;
1362  }
1363  bool mayAlias(const MachineFrameInfo *) const override {
1364  return false;
1365  }
1366  void printCustom(raw_ostream &OS) const override {
1367  OS << "MisalignedCrash";
1368  }
1369  };
1370 
1371  static const CrashPseudoSourceValue CrashPSV(*this);
1373  MachinePointerInfo(&CrashPSV),
1375  Align(1));
1376  BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
1377  .addImm(0xBADC0FEE) // Misaligned load.
1378  .addMemOperand(MMO);
1379  MBB.erase(MI);
1380  return true;
1381  }
1382 
1383  case Hexagon::PS_tailcall_i:
1384  MI.setDesc(get(Hexagon::J2_jump));
1385  return true;
1386  case Hexagon::PS_tailcall_r:
1387  case Hexagon::PS_jmpret:
1388  MI.setDesc(get(Hexagon::J2_jumpr));
1389  return true;
1390  case Hexagon::PS_jmprett:
1391  MI.setDesc(get(Hexagon::J2_jumprt));
1392  return true;
1393  case Hexagon::PS_jmpretf:
1394  MI.setDesc(get(Hexagon::J2_jumprf));
1395  return true;
1396  case Hexagon::PS_jmprettnewpt:
1397  MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1398  return true;
1399  case Hexagon::PS_jmpretfnewpt:
1400  MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1401  return true;
1402  case Hexagon::PS_jmprettnew:
1403  MI.setDesc(get(Hexagon::J2_jumprtnew));
1404  return true;
1405  case Hexagon::PS_jmpretfnew:
1406  MI.setDesc(get(Hexagon::J2_jumprfnew));
1407  return true;
1408 
1409  case Hexagon::PS_loadrub_pci:
1410  return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1411  case Hexagon::PS_loadrb_pci:
1412  return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1413  case Hexagon::PS_loadruh_pci:
1414  return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1415  case Hexagon::PS_loadrh_pci:
1416  return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1417  case Hexagon::PS_loadri_pci:
1418  return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1419  case Hexagon::PS_loadrd_pci:
1420  return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1421  case Hexagon::PS_loadrub_pcr:
1422  return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1423  case Hexagon::PS_loadrb_pcr:
1424  return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1425  case Hexagon::PS_loadruh_pcr:
1426  return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1427  case Hexagon::PS_loadrh_pcr:
1428  return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1429  case Hexagon::PS_loadri_pcr:
1430  return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1431  case Hexagon::PS_loadrd_pcr:
1432  return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1433  case Hexagon::PS_storerb_pci:
1434  return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1435  case Hexagon::PS_storerh_pci:
1436  return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1437  case Hexagon::PS_storerf_pci:
1438  return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1439  case Hexagon::PS_storeri_pci:
1440  return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1441  case Hexagon::PS_storerd_pci:
1442  return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1443  case Hexagon::PS_storerb_pcr:
1444  return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1445  case Hexagon::PS_storerh_pcr:
1446  return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1447  case Hexagon::PS_storerf_pcr:
1448  return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1449  case Hexagon::PS_storeri_pcr:
1450  return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1451  case Hexagon::PS_storerd_pcr:
1452  return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1453  }
1454 
1455  return false;
1456 }
1457 
1460  MachineBasicBlock &MBB = *MI.getParent();
1461  const DebugLoc &DL = MI.getDebugLoc();
1462  unsigned Opc = MI.getOpcode();
1464 
1465  switch (Opc) {
1466  case Hexagon::V6_vgathermh_pseudo:
1467  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1468  .add(MI.getOperand(1))
1469  .add(MI.getOperand(2))
1470  .add(MI.getOperand(3));
1471  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1472  .add(MI.getOperand(0))
1473  .addImm(0)
1474  .addReg(Hexagon::VTMP);
1475  MBB.erase(MI);
1476  return First.getInstrIterator();
1477 
1478  case Hexagon::V6_vgathermw_pseudo:
1479  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1480  .add(MI.getOperand(1))
1481  .add(MI.getOperand(2))
1482  .add(MI.getOperand(3));
1483  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1484  .add(MI.getOperand(0))
1485  .addImm(0)
1486  .addReg(Hexagon::VTMP);
1487  MBB.erase(MI);
1488  return First.getInstrIterator();
1489 
1490  case Hexagon::V6_vgathermhw_pseudo:
1491  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1492  .add(MI.getOperand(1))
1493  .add(MI.getOperand(2))
1494  .add(MI.getOperand(3));
1495  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1496  .add(MI.getOperand(0))
1497  .addImm(0)
1498  .addReg(Hexagon::VTMP);
1499  MBB.erase(MI);
1500  return First.getInstrIterator();
1501 
1502  case Hexagon::V6_vgathermhq_pseudo:
1503  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1504  .add(MI.getOperand(1))
1505  .add(MI.getOperand(2))
1506  .add(MI.getOperand(3))
1507  .add(MI.getOperand(4));
1508  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1509  .add(MI.getOperand(0))
1510  .addImm(0)
1511  .addReg(Hexagon::VTMP);
1512  MBB.erase(MI);
1513  return First.getInstrIterator();
1514 
1515  case Hexagon::V6_vgathermwq_pseudo:
1516  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1517  .add(MI.getOperand(1))
1518  .add(MI.getOperand(2))
1519  .add(MI.getOperand(3))
1520  .add(MI.getOperand(4));
1521  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1522  .add(MI.getOperand(0))
1523  .addImm(0)
1524  .addReg(Hexagon::VTMP);
1525  MBB.erase(MI);
1526  return First.getInstrIterator();
1527 
1528  case Hexagon::V6_vgathermhwq_pseudo:
1529  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1530  .add(MI.getOperand(1))
1531  .add(MI.getOperand(2))
1532  .add(MI.getOperand(3))
1533  .add(MI.getOperand(4));
1534  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1535  .add(MI.getOperand(0))
1536  .addImm(0)
1537  .addReg(Hexagon::VTMP);
1538  MBB.erase(MI);
1539  return First.getInstrIterator();
1540  }
1541 
1542  return MI.getIterator();
1543 }
1544 
1545 // We indicate that we want to reverse the branch by
1546 // inserting the reversed branching opcode.
1549  if (Cond.empty())
1550  return true;
1551  assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1552  unsigned opcode = Cond[0].getImm();
1553  //unsigned temp;
1554  assert(get(opcode).isBranch() && "Should be a branching condition.");
1555  if (isEndLoopN(opcode))
1556  return true;
1557  unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1558  Cond[0].setImm(NewOpcode);
1559  return false;
1560 }
1561 
1564  DebugLoc DL;
1565  BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1566 }
1567 
1569  return getAddrMode(MI) == HexagonII::PostInc;
1570 }
1571 
1572 // Returns true if an instruction is predicated irrespective of the predicate
1573 // sense. For example, all of the following will return true.
1574 // if (p0) R1 = add(R2, R3)
1575 // if (!p0) R1 = add(R2, R3)
1576 // if (p0.new) R1 = add(R2, R3)
1577 // if (!p0.new) R1 = add(R2, R3)
1578 // Note: New-value stores are not included here as in the current
1579 // implementation, we don't need to check their predicate sense.
1581  const uint64_t F = MI.getDesc().TSFlags;
1583 }
1584 
1587  if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1588  isEndLoopN(Cond[0].getImm())) {
1589  LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1590  return false;
1591  }
1592  int Opc = MI.getOpcode();
1593  assert (isPredicable(MI) && "Expected predicable instruction");
1594  bool invertJump = predOpcodeHasNot(Cond);
1595 
1596  // We have to predicate MI "in place", i.e. after this function returns,
1597  // MI will need to be transformed into a predicated form. To avoid com-
1598  // plicated manipulations with the operands (handling tied operands,
1599  // etc.), build a new temporary instruction, then overwrite MI with it.
1600 
1601  MachineBasicBlock &B = *MI.getParent();
1602  DebugLoc DL = MI.getDebugLoc();
1603  unsigned PredOpc = getCondOpcode(Opc, invertJump);
1604  MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1605  unsigned NOp = 0, NumOps = MI.getNumOperands();
1606  while (NOp < NumOps) {
1607  MachineOperand &Op = MI.getOperand(NOp);
1608  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1609  break;
1610  T.add(Op);
1611  NOp++;
1612  }
1613 
1614  unsigned PredReg, PredRegPos, PredRegFlags;
1615  bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1616  (void)GotPredReg;
1617  assert(GotPredReg);
1618  T.addReg(PredReg, PredRegFlags);
1619  while (NOp < NumOps)
1620  T.add(MI.getOperand(NOp++));
1621 
1622  MI.setDesc(get(PredOpc));
1623  while (unsigned n = MI.getNumOperands())
1624  MI.RemoveOperand(n-1);
1625  for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1626  MI.addOperand(T->getOperand(i));
1627 
1628  MachineBasicBlock::instr_iterator TI = T->getIterator();
1629  B.erase(TI);
1630 
1631  MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1632  MRI.clearKillFlags(PredReg);
1633  return true;
1634 }
1635 
1637  ArrayRef<MachineOperand> Pred2) const {
1638  // TODO: Fix this
1639  return false;
1640 }
1641 
1643  std::vector<MachineOperand> &Pred,
1644  bool SkipDead) const {
1645  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1646 
1647  for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1648  MachineOperand MO = MI.getOperand(oper);
1649  if (MO.isReg()) {
1650  if (!MO.isDef())
1651  continue;
1652  const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1653  if (RC == &Hexagon::PredRegsRegClass) {
1654  Pred.push_back(MO);
1655  return true;
1656  }
1657  continue;
1658  } else if (MO.isRegMask()) {
1659  for (unsigned PR : Hexagon::PredRegsRegClass) {
1660  if (!MI.modifiesRegister(PR, &HRI))
1661  continue;
1662  Pred.push_back(MO);
1663  return true;
1664  }
1665  }
1666  }
1667  return false;
1668 }
1669 
1671  if (!MI.getDesc().isPredicable())
1672  return false;
1673 
1674  if (MI.isCall() || isTailCall(MI)) {
1675  if (!Subtarget.usePredicatedCalls())
1676  return false;
1677  }
1678 
1679  // HVX loads are not predicable on v60, but are on v62.
1680  if (!Subtarget.hasV62Ops()) {
1681  switch (MI.getOpcode()) {
1682  case Hexagon::V6_vL32b_ai:
1683  case Hexagon::V6_vL32b_pi:
1684  case Hexagon::V6_vL32b_ppu:
1685  case Hexagon::V6_vL32b_cur_ai:
1686  case Hexagon::V6_vL32b_cur_pi:
1687  case Hexagon::V6_vL32b_cur_ppu:
1688  case Hexagon::V6_vL32b_nt_ai:
1689  case Hexagon::V6_vL32b_nt_pi:
1690  case Hexagon::V6_vL32b_nt_ppu:
1691  case Hexagon::V6_vL32b_tmp_ai:
1692  case Hexagon::V6_vL32b_tmp_pi:
1693  case Hexagon::V6_vL32b_tmp_ppu:
1694  case Hexagon::V6_vL32b_nt_cur_ai:
1695  case Hexagon::V6_vL32b_nt_cur_pi:
1696  case Hexagon::V6_vL32b_nt_cur_ppu:
1697  case Hexagon::V6_vL32b_nt_tmp_ai:
1698  case Hexagon::V6_vL32b_nt_tmp_pi:
1699  case Hexagon::V6_vL32b_nt_tmp_ppu:
1700  return false;
1701  }
1702  }
1703  return true;
1704 }
1705 
1707  const MachineBasicBlock *MBB,
1708  const MachineFunction &MF) const {
1709  // Debug info is never a scheduling boundary. It's necessary to be explicit
1710  // due to the special treatment of IT instructions below, otherwise a
1711  // dbg_value followed by an IT will result in the IT instruction being
1712  // considered a scheduling hazard, which is wrong. It should be the actual
1713  // instruction preceding the dbg_value instruction(s), just like it is
1714  // when debug info is not present.
1715  if (MI.isDebugInstr())
1716  return false;
1717 
1718  // Throwing call is a boundary.
1719  if (MI.isCall()) {
1720  // Don't mess around with no return calls.
1721  if (doesNotReturn(MI))
1722  return true;
1723  // If any of the block's successors is a landing pad, this could be a
1724  // throwing call.
1725  for (auto I : MBB->successors())
1726  if (I->isEHPad())
1727  return true;
1728  }
1729 
1730  // Terminators and labels can't be scheduled around.
1731  if (MI.getDesc().isTerminator() || MI.isPosition())
1732  return true;
1733 
1734  // INLINEASM_BR can jump to another block
1735  if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1736  return true;
1737 
1738  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1739  return true;
1740 
1741  return false;
1742 }
1743 
1744 /// Measure the specified inline asm to determine an approximation of its
1745 /// length.
1746 /// Comments (which run till the next SeparatorString or newline) do not
1747 /// count as an instruction.
1748 /// Any other non-whitespace text is considered an instruction, with
1749 /// multiple instructions separated by SeparatorString or newlines.
1750 /// Variable-length instructions are not handled here; this function
1751 /// may be overloaded in the target code to do that.
1752 /// Hexagon counts the number of ##'s and adjust for that many
1753 /// constant exenders.
1754 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1755  const MCAsmInfo &MAI,
1756  const TargetSubtargetInfo *STI) const {
1757  StringRef AStr(Str);
1758  // Count the number of instructions in the asm.
1759  bool atInsnStart = true;
1760  unsigned Length = 0;
1761  const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
1762  for (; *Str; ++Str) {
1763  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1764  strlen(MAI.getSeparatorString())) == 0)
1765  atInsnStart = true;
1766  if (atInsnStart && !isSpace(static_cast<unsigned char>(*Str))) {
1767  Length += MaxInstLength;
1768  atInsnStart = false;
1769  }
1770  if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1771  MAI.getCommentString().size()) == 0)
1772  atInsnStart = false;
1773  }
1774 
1775  // Add to size number of constant extenders seen * 4.
1776  StringRef Occ("##");
1777  Length += AStr.count(Occ)*4;
1778  return Length;
1779 }
1780 
1783  const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1784  if (UseDFAHazardRec)
1785  return new HexagonHazardRecognizer(II, this, Subtarget);
1787 }
1788 
1789 /// For a comparison instruction, return the source registers in
1790 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1791 /// compares against in CmpValue. Return true if the comparison instruction
1792 /// can be analyzed.
1794  Register &SrcReg2, int &Mask,
1795  int &Value) const {
1796  unsigned Opc = MI.getOpcode();
1797 
1798  // Set mask and the first source register.
1799  switch (Opc) {
1800  case Hexagon::C2_cmpeq:
1801  case Hexagon::C2_cmpeqp:
1802  case Hexagon::C2_cmpgt:
1803  case Hexagon::C2_cmpgtp:
1804  case Hexagon::C2_cmpgtu:
1805  case Hexagon::C2_cmpgtup:
1806  case Hexagon::C4_cmpneq:
1807  case Hexagon::C4_cmplte:
1808  case Hexagon::C4_cmplteu:
1809  case Hexagon::C2_cmpeqi:
1810  case Hexagon::C2_cmpgti:
1811  case Hexagon::C2_cmpgtui:
1812  case Hexagon::C4_cmpneqi:
1813  case Hexagon::C4_cmplteui:
1814  case Hexagon::C4_cmpltei:
1815  SrcReg = MI.getOperand(1).getReg();
1816  Mask = ~0;
1817  break;
1818  case Hexagon::A4_cmpbeq:
1819  case Hexagon::A4_cmpbgt:
1820  case Hexagon::A4_cmpbgtu:
1821  case Hexagon::A4_cmpbeqi:
1822  case Hexagon::A4_cmpbgti:
1823  case Hexagon::A4_cmpbgtui:
1824  SrcReg = MI.getOperand(1).getReg();
1825  Mask = 0xFF;
1826  break;
1827  case Hexagon::A4_cmpheq:
1828  case Hexagon::A4_cmphgt:
1829  case Hexagon::A4_cmphgtu:
1830  case Hexagon::A4_cmpheqi:
1831  case Hexagon::A4_cmphgti:
1832  case Hexagon::A4_cmphgtui:
1833  SrcReg = MI.getOperand(1).getReg();
1834  Mask = 0xFFFF;
1835  break;
1836  }
1837 
1838  // Set the value/second source register.
1839  switch (Opc) {
1840  case Hexagon::C2_cmpeq:
1841  case Hexagon::C2_cmpeqp:
1842  case Hexagon::C2_cmpgt:
1843  case Hexagon::C2_cmpgtp:
1844  case Hexagon::C2_cmpgtu:
1845  case Hexagon::C2_cmpgtup:
1846  case Hexagon::A4_cmpbeq:
1847  case Hexagon::A4_cmpbgt:
1848  case Hexagon::A4_cmpbgtu:
1849  case Hexagon::A4_cmpheq:
1850  case Hexagon::A4_cmphgt:
1851  case Hexagon::A4_cmphgtu:
1852  case Hexagon::C4_cmpneq:
1853  case Hexagon::C4_cmplte:
1854  case Hexagon::C4_cmplteu:
1855  SrcReg2 = MI.getOperand(2).getReg();
1856  return true;
1857 
1858  case Hexagon::C2_cmpeqi:
1859  case Hexagon::C2_cmpgtui:
1860  case Hexagon::C2_cmpgti:
1861  case Hexagon::C4_cmpneqi:
1862  case Hexagon::C4_cmplteui:
1863  case Hexagon::C4_cmpltei:
1864  case Hexagon::A4_cmpbeqi:
1865  case Hexagon::A4_cmpbgti:
1866  case Hexagon::A4_cmpbgtui:
1867  case Hexagon::A4_cmpheqi:
1868  case Hexagon::A4_cmphgti:
1869  case Hexagon::A4_cmphgtui: {
1870  SrcReg2 = 0;
1871  const MachineOperand &Op2 = MI.getOperand(2);
1872  if (!Op2.isImm())
1873  return false;
1874  Value = MI.getOperand(2).getImm();
1875  return true;
1876  }
1877  }
1878 
1879  return false;
1880 }
1881 
1883  const MachineInstr &MI,
1884  unsigned *PredCost) const {
1885  return getInstrTimingClassLatency(ItinData, MI);
1886 }
1887 
1889  const TargetSubtargetInfo &STI) const {
1890  const InstrItineraryData *II = STI.getInstrItineraryData();
1891  return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1892 }
1893 
1894 // Inspired by this pair:
1895 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1896 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1897 // Currently AA considers the addresses in these instructions to be aliasing.
1899  const MachineInstr &MIa, const MachineInstr &MIb) const {
1900  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1902  return false;
1903 
1904  // Instructions that are pure loads, not loads and stores like memops are not
1905  // dependent.
1906  if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1907  return true;
1908 
1909  // Get the base register in MIa.
1910  unsigned BasePosA, OffsetPosA;
1911  if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1912  return false;
1913  const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1914  Register BaseRegA = BaseA.getReg();
1915  unsigned BaseSubA = BaseA.getSubReg();
1916 
1917  // Get the base register in MIb.
1918  unsigned BasePosB, OffsetPosB;
1919  if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1920  return false;
1921  const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1922  Register BaseRegB = BaseB.getReg();
1923  unsigned BaseSubB = BaseB.getSubReg();
1924 
1925  if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
1926  return false;
1927 
1928  // Get the access sizes.
1929  unsigned SizeA = getMemAccessSize(MIa);
1930  unsigned SizeB = getMemAccessSize(MIb);
1931 
1932  // Get the offsets. Handle immediates only for now.
1933  const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1934  const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1935  if (!MIa.getOperand(OffsetPosA).isImm() ||
1936  !MIb.getOperand(OffsetPosB).isImm())
1937  return false;
1938  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
1939  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
1940 
1941  // This is a mem access with the same base register and known offsets from it.
1942  // Reason about it.
1943  if (OffsetA > OffsetB) {
1944  uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1945  return SizeB <= OffDiff;
1946  }
1947  if (OffsetA < OffsetB) {
1948  uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1949  return SizeA <= OffDiff;
1950  }
1951 
1952  return false;
1953 }
1954 
1955 /// If the instruction is an increment of a constant value, return the amount.
1957  int &Value) const {
1958  if (isPostIncrement(MI)) {
1959  unsigned BasePos = 0, OffsetPos = 0;
1960  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
1961  return false;
1962  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
1963  if (OffsetOp.isImm()) {
1964  Value = OffsetOp.getImm();
1965  return true;
1966  }
1967  } else if (MI.getOpcode() == Hexagon::A2_addi) {
1968  const MachineOperand &AddOp = MI.getOperand(2);
1969  if (AddOp.isImm()) {
1970  Value = AddOp.getImm();
1971  return true;
1972  }
1973  }
1974 
1975  return false;
1976 }
1977 
1978 std::pair<unsigned, unsigned>
1980  return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
1981  TF & HexagonII::MO_Bitmasks);
1982 }
1983 
1986  using namespace HexagonII;
1987 
1988  static const std::pair<unsigned, const char*> Flags[] = {
1989  {MO_PCREL, "hexagon-pcrel"},
1990  {MO_GOT, "hexagon-got"},
1991  {MO_LO16, "hexagon-lo16"},
1992  {MO_HI16, "hexagon-hi16"},
1993  {MO_GPREL, "hexagon-gprel"},
1994  {MO_GDGOT, "hexagon-gdgot"},
1995  {MO_GDPLT, "hexagon-gdplt"},
1996  {MO_IE, "hexagon-ie"},
1997  {MO_IEGOT, "hexagon-iegot"},
1998  {MO_TPREL, "hexagon-tprel"}
1999  };
2000  return makeArrayRef(Flags);
2001 }
2002 
2005  using namespace HexagonII;
2006 
2007  static const std::pair<unsigned, const char*> Flags[] = {
2008  {HMOTF_ConstExtended, "hexagon-ext"}
2009  };
2010  return makeArrayRef(Flags);
2011 }
2012 
2015  const TargetRegisterClass *TRC;
2016  if (VT == MVT::i1) {
2017  TRC = &Hexagon::PredRegsRegClass;
2018  } else if (VT == MVT::i32 || VT == MVT::f32) {
2019  TRC = &Hexagon::IntRegsRegClass;
2020  } else if (VT == MVT::i64 || VT == MVT::f64) {
2021  TRC = &Hexagon::DoubleRegsRegClass;
2022  } else {
2023  llvm_unreachable("Cannot handle this register class");
2024  }
2025 
2026  Register NewReg = MRI.createVirtualRegister(TRC);
2027  return NewReg;
2028 }
2029 
2031  return (getAddrMode(MI) == HexagonII::AbsoluteSet);
2032 }
2033 
2035  const uint64_t F = MI.getDesc().TSFlags;
2037 }
2038 
2041 }
2042 
2044  return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
2045  !MI.getDesc().mayStore() &&
2046  MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2047  MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2048  !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
2049 }
2050 
2051 // Return true if the instruction is a compund branch instruction.
2053  return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
2054 }
2055 
2056 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
2057 // isFPImm and later getFPImm as well.
2059  const uint64_t F = MI.getDesc().TSFlags;
2061  if (isExtended) // Instruction must be extended.
2062  return true;
2063 
2064  unsigned isExtendable =
2066  if (!isExtendable)
2067  return false;
2068 
2069  if (MI.isCall())
2070  return false;
2071 
2072  short ExtOpNum = getCExtOpNum(MI);
2073  const MachineOperand &MO = MI.getOperand(ExtOpNum);
2074  // Use MO operand flags to determine if MO
2075  // has the HMOTF_ConstExtended flag set.
2077  return true;
2078  // If this is a Machine BB address we are talking about, and it is
2079  // not marked as extended, say so.
2080  if (MO.isMBB())
2081  return false;
2082 
2083  // We could be using an instruction with an extendable immediate and shoehorn
2084  // a global address into it. If it is a global address it will be constant
2085  // extended. We do this for COMBINE.
2086  if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2087  MO.isJTI() || MO.isCPI() || MO.isFPImm())
2088  return true;
2089 
2090  // If the extendable operand is not 'Immediate' type, the instruction should
2091  // have 'isExtended' flag set.
2092  assert(MO.isImm() && "Extendable operand must be Immediate type");
2093 
2094  int MinValue = getMinValue(MI);
2095  int MaxValue = getMaxValue(MI);
2096  int ImmValue = MO.getImm();
2097 
2098  return (ImmValue < MinValue || ImmValue > MaxValue);
2099 }
2100 
2102  switch (MI.getOpcode()) {
2103  case Hexagon::L4_return:
2104  case Hexagon::L4_return_t:
2105  case Hexagon::L4_return_f:
2106  case Hexagon::L4_return_tnew_pnt:
2107  case Hexagon::L4_return_fnew_pnt:
2108  case Hexagon::L4_return_tnew_pt:
2109  case Hexagon::L4_return_fnew_pt:
2110  return true;
2111  }
2112  return false;
2113 }
2114 
2115 // Return true when ConsMI uses a register defined by ProdMI.
2117  const MachineInstr &ConsMI) const {
2118  if (!ProdMI.getDesc().getNumDefs())
2119  return false;
2120  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2121 
2126 
2127  parseOperands(ProdMI, DefsA, UsesA);
2128  parseOperands(ConsMI, DefsB, UsesB);
2129 
2130  for (auto &RegA : DefsA)
2131  for (auto &RegB : UsesB) {
2132  // True data dependency.
2133  if (RegA == RegB)
2134  return true;
2135 
2136  if (Register::isPhysicalRegister(RegA))
2137  for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
2138  if (RegB == *SubRegs)
2139  return true;
2140 
2141  if (Register::isPhysicalRegister(RegB))
2142  for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
2143  if (RegA == *SubRegs)
2144  return true;
2145  }
2146 
2147  return false;
2148 }
2149 
2150 // Returns true if the instruction is alread a .cur.
2152  switch (MI.getOpcode()) {
2153  case Hexagon::V6_vL32b_cur_pi:
2154  case Hexagon::V6_vL32b_cur_ai:
2155  return true;
2156  }
2157  return false;
2158 }
2159 
2160 // Returns true, if any one of the operands is a dot new
2161 // insn, whether it is predicated dot new or register dot new.
2164  return true;
2165 
2166  return false;
2167 }
2168 
2169 /// Symmetrical. See if these two instructions are fit for duplex pair.
2171  const MachineInstr &MIb) const {
2174  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2175 }
2176 
2178  if (MI.mayLoadOrStore() || MI.isCompare())
2179  return true;
2180 
2181  // Multiply
2182  unsigned SchedClass = MI.getDesc().getSchedClass();
2183  return is_TC4x(SchedClass) || is_TC3x(SchedClass);
2184 }
2185 
2186 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2187  return (Opcode == Hexagon::ENDLOOP0 ||
2188  Opcode == Hexagon::ENDLOOP1);
2189 }
2190 
2191 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2192  switch(OpType) {
2199  return true;
2200  default:
2201  return false;
2202  }
2203 }
2204 
2206  const MCInstrDesc &MID = MI.getDesc();
2207  const uint64_t F = MID.TSFlags;
2209  return true;
2210 
2211  // TODO: This is largely obsolete now. Will need to be removed
2212  // in consecutive patches.
2213  switch (MI.getOpcode()) {
2214  // PS_fi and PS_fia remain special cases.
2215  case Hexagon::PS_fi:
2216  case Hexagon::PS_fia:
2217  return true;
2218  default:
2219  return false;
2220  }
2221  return false;
2222 }
2223 
2224 // This returns true in two cases:
2225 // - The OP code itself indicates that this is an extended instruction.
2226 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2228  // First check if this is permanently extended op code.
2229  const uint64_t F = MI.getDesc().TSFlags;
2231  return true;
2232  // Use MO operand flags to determine if one of MI's operands
2233  // has HMOTF_ConstExtended flag set.
2234  for (const MachineOperand &MO : MI.operands())
2235  if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2236  return true;
2237  return false;
2238 }
2239 
2241  unsigned Opcode = MI.getOpcode();
2242  const uint64_t F = get(Opcode).TSFlags;
2243  return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2244 }
2245 
2246 // No V60 HVX VMEM with A_INDIRECT.
2248  const MachineInstr &J) const {
2249  if (!isHVXVec(I))
2250  return false;
2251  if (!I.mayLoad() && !I.mayStore())
2252  return false;
2253  return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2254 }
2255 
2257  switch (MI.getOpcode()) {
2258  case Hexagon::J2_callr:
2259  case Hexagon::J2_callrf:
2260  case Hexagon::J2_callrt:
2261  case Hexagon::PS_call_nr:
2262  return true;
2263  }
2264  return false;
2265 }
2266 
2268  switch (MI.getOpcode()) {
2269  case Hexagon::L4_return:
2270  case Hexagon::L4_return_t:
2271  case Hexagon::L4_return_f:
2272  case Hexagon::L4_return_fnew_pnt:
2273  case Hexagon::L4_return_fnew_pt:
2274  case Hexagon::L4_return_tnew_pnt:
2275  case Hexagon::L4_return_tnew_pt:
2276  return true;
2277  }
2278  return false;
2279 }
2280 
2282  switch (MI.getOpcode()) {
2283  case Hexagon::J2_jumpr:
2284  case Hexagon::J2_jumprt:
2285  case Hexagon::J2_jumprf:
2286  case Hexagon::J2_jumprtnewpt:
2287  case Hexagon::J2_jumprfnewpt:
2288  case Hexagon::J2_jumprtnew:
2289  case Hexagon::J2_jumprfnew:
2290  return true;
2291  }
2292  return false;
2293 }
2294 
2295 // Return true if a given MI can accommodate given offset.
2296 // Use abs estimate as oppose to the exact number.
2297 // TODO: This will need to be changed to use MC level
2298 // definition of instruction extendable field size.
2300  unsigned offset) const {
2301  // This selection of jump instructions matches to that what
2302  // analyzeBranch can parse, plus NVJ.
2303  if (isNewValueJump(MI)) // r9:2
2304  return isInt<11>(offset);
2305 
2306  switch (MI.getOpcode()) {
2307  // Still missing Jump to address condition on register value.
2308  default:
2309  return false;
2310  case Hexagon::J2_jump: // bits<24> dst; // r22:2
2311  case Hexagon::J2_call:
2312  case Hexagon::PS_call_nr:
2313  return isInt<24>(offset);
2314  case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2315  case Hexagon::J2_jumpf:
2316  case Hexagon::J2_jumptnew:
2317  case Hexagon::J2_jumptnewpt:
2318  case Hexagon::J2_jumpfnew:
2319  case Hexagon::J2_jumpfnewpt:
2320  case Hexagon::J2_callt:
2321  case Hexagon::J2_callf:
2322  return isInt<17>(offset);
2323  case Hexagon::J2_loop0i:
2324  case Hexagon::J2_loop0iext:
2325  case Hexagon::J2_loop0r:
2326  case Hexagon::J2_loop0rext:
2327  case Hexagon::J2_loop1i:
2328  case Hexagon::J2_loop1iext:
2329  case Hexagon::J2_loop1r:
2330  case Hexagon::J2_loop1rext:
2331  return isInt<9>(offset);
2332  // TODO: Add all the compound branches here. Can we do this in Relation model?
2333  case Hexagon::J4_cmpeqi_tp0_jump_nt:
2334  case Hexagon::J4_cmpeqi_tp1_jump_nt:
2335  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2336  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2337  return isInt<11>(offset);
2338  }
2339 }
2340 
2342  const MachineInstr &ESMI) const {
2343  bool isLate = isLateResultInstr(LRMI);
2344  bool isEarly = isEarlySourceInstr(ESMI);
2345 
2346  LLVM_DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2347  LLVM_DEBUG(LRMI.dump());
2348  LLVM_DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2349  LLVM_DEBUG(ESMI.dump());
2350 
2351  if (isLate && isEarly) {
2352  LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2353  return true;
2354  }
2355 
2356  return false;
2357 }
2358 
2360  switch (MI.getOpcode()) {
2361  case TargetOpcode::EXTRACT_SUBREG:
2362  case TargetOpcode::INSERT_SUBREG:
2363  case TargetOpcode::SUBREG_TO_REG:
2364  case TargetOpcode::REG_SEQUENCE:
2365  case TargetOpcode::IMPLICIT_DEF:
2366  case TargetOpcode::COPY:
2368  case TargetOpcode::PHI:
2369  return false;
2370  default:
2371  break;
2372  }
2373 
2374  unsigned SchedClass = MI.getDesc().getSchedClass();
2375  return !is_TC1(SchedClass);
2376 }
2377 
2379  // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2380  // resource, but all operands can be received late like an ALU instruction.
2382 }
2383 
2385  unsigned Opcode = MI.getOpcode();
2386  return Opcode == Hexagon::J2_loop0i ||
2387  Opcode == Hexagon::J2_loop0r ||
2388  Opcode == Hexagon::J2_loop0iext ||
2389  Opcode == Hexagon::J2_loop0rext ||
2390  Opcode == Hexagon::J2_loop1i ||
2391  Opcode == Hexagon::J2_loop1r ||
2392  Opcode == Hexagon::J2_loop1iext ||
2393  Opcode == Hexagon::J2_loop1rext;
2394 }
2395 
2397  switch (MI.getOpcode()) {
2398  default: return false;
2399  case Hexagon::L4_iadd_memopw_io:
2400  case Hexagon::L4_isub_memopw_io:
2401  case Hexagon::L4_add_memopw_io:
2402  case Hexagon::L4_sub_memopw_io:
2403  case Hexagon::L4_and_memopw_io:
2404  case Hexagon::L4_or_memopw_io:
2405  case Hexagon::L4_iadd_memoph_io:
2406  case Hexagon::L4_isub_memoph_io:
2407  case Hexagon::L4_add_memoph_io:
2408  case Hexagon::L4_sub_memoph_io:
2409  case Hexagon::L4_and_memoph_io:
2410  case Hexagon::L4_or_memoph_io:
2411  case Hexagon::L4_iadd_memopb_io:
2412  case Hexagon::L4_isub_memopb_io:
2413  case Hexagon::L4_add_memopb_io:
2414  case Hexagon::L4_sub_memopb_io:
2415  case Hexagon::L4_and_memopb_io:
2416  case Hexagon::L4_or_memopb_io:
2417  case Hexagon::L4_ior_memopb_io:
2418  case Hexagon::L4_ior_memoph_io:
2419  case Hexagon::L4_ior_memopw_io:
2420  case Hexagon::L4_iand_memopb_io:
2421  case Hexagon::L4_iand_memoph_io:
2422  case Hexagon::L4_iand_memopw_io:
2423  return true;
2424  }
2425  return false;
2426 }
2427 
2429  const uint64_t F = MI.getDesc().TSFlags;
2431 }
2432 
2433 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2434  const uint64_t F = get(Opcode).TSFlags;
2436 }
2437 
2439  return isNewValueJump(MI) || isNewValueStore(MI);
2440 }
2441 
2443  return isNewValue(MI) && MI.isBranch();
2444 }
2445 
2446 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2447  return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2448 }
2449 
2451  const uint64_t F = MI.getDesc().TSFlags;
2453 }
2454 
2455 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2456  const uint64_t F = get(Opcode).TSFlags;
2458 }
2459 
2460 // Returns true if a particular operand is extendable for an instruction.
2462  unsigned OperandNum) const {
2463  const uint64_t F = MI.getDesc().TSFlags;
2465  == OperandNum;
2466 }
2467 
2469  const uint64_t F = MI.getDesc().TSFlags;
2472 }
2473 
2474 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2475  const uint64_t F = get(Opcode).TSFlags;
2476  assert(isPredicated(Opcode));
2478 }
2479 
2481  const uint64_t F = MI.getDesc().TSFlags;
2482  return !((F >> HexagonII::PredicatedFalsePos) &
2484 }
2485 
2486 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2487  const uint64_t F = get(Opcode).TSFlags;
2488  // Make sure that the instruction is predicated.
2490  return !((F >> HexagonII::PredicatedFalsePos) &
2492 }
2493 
2494 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2495  const uint64_t F = get(Opcode).TSFlags;
2497 }
2498 
2499 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2500  const uint64_t F = get(Opcode).TSFlags;
2502 }
2503 
2504 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2505  const uint64_t F = get(Opcode).TSFlags;
2506  assert(get(Opcode).isBranch() &&
2507  (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2509 }
2510 
2512  return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2513  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2514  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2515  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2516 }
2517 
2519  switch (MI.getOpcode()) {
2520  // Byte
2521  case Hexagon::L2_loadrb_io:
2522  case Hexagon::L4_loadrb_ur:
2523  case Hexagon::L4_loadrb_ap:
2524  case Hexagon::L2_loadrb_pr:
2525  case Hexagon::L2_loadrb_pbr:
2526  case Hexagon::L2_loadrb_pi:
2527  case Hexagon::L2_loadrb_pci:
2528  case Hexagon::L2_loadrb_pcr:
2529  case Hexagon::L2_loadbsw2_io:
2530  case Hexagon::L4_loadbsw2_ur:
2531  case Hexagon::L4_loadbsw2_ap:
2532  case Hexagon::L2_loadbsw2_pr:
2533  case Hexagon::L2_loadbsw2_pbr:
2534  case Hexagon::L2_loadbsw2_pi:
2535  case Hexagon::L2_loadbsw2_pci:
2536  case Hexagon::L2_loadbsw2_pcr:
2537  case Hexagon::L2_loadbsw4_io:
2538  case Hexagon::L4_loadbsw4_ur:
2539  case Hexagon::L4_loadbsw4_ap:
2540  case Hexagon::L2_loadbsw4_pr:
2541  case Hexagon::L2_loadbsw4_pbr:
2542  case Hexagon::L2_loadbsw4_pi:
2543  case Hexagon::L2_loadbsw4_pci:
2544  case Hexagon::L2_loadbsw4_pcr:
2545  case Hexagon::L4_loadrb_rr:
2546  case Hexagon::L2_ploadrbt_io:
2547  case Hexagon::L2_ploadrbt_pi:
2548  case Hexagon::L2_ploadrbf_io:
2549  case Hexagon::L2_ploadrbf_pi:
2550  case Hexagon::L2_ploadrbtnew_io:
2551  case Hexagon::L2_ploadrbfnew_io:
2552  case Hexagon::L4_ploadrbt_rr:
2553  case Hexagon::L4_ploadrbf_rr:
2554  case Hexagon::L4_ploadrbtnew_rr:
2555  case Hexagon::L4_ploadrbfnew_rr:
2556  case Hexagon::L2_ploadrbtnew_pi:
2557  case Hexagon::L2_ploadrbfnew_pi:
2558  case Hexagon::L4_ploadrbt_abs:
2559  case Hexagon::L4_ploadrbf_abs:
2560  case Hexagon::L4_ploadrbtnew_abs:
2561  case Hexagon::L4_ploadrbfnew_abs:
2562  case Hexagon::L2_loadrbgp:
2563  // Half
2564  case Hexagon::L2_loadrh_io:
2565  case Hexagon::L4_loadrh_ur:
2566  case Hexagon::L4_loadrh_ap:
2567  case Hexagon::L2_loadrh_pr:
2568  case Hexagon::L2_loadrh_pbr:
2569  case Hexagon::L2_loadrh_pi:
2570  case Hexagon::L2_loadrh_pci:
2571  case Hexagon::L2_loadrh_pcr:
2572  case Hexagon::L4_loadrh_rr:
2573  case Hexagon::L2_ploadrht_io:
2574  case Hexagon::L2_ploadrht_pi:
2575  case Hexagon::L2_ploadrhf_io:
2576  case Hexagon::L2_ploadrhf_pi:
2577  case Hexagon::L2_ploadrhtnew_io:
2578  case Hexagon::L2_ploadrhfnew_io:
2579  case Hexagon::L4_ploadrht_rr:
2580  case Hexagon::L4_ploadrhf_rr:
2581  case Hexagon::L4_ploadrhtnew_rr:
2582  case Hexagon::L4_ploadrhfnew_rr:
2583  case Hexagon::L2_ploadrhtnew_pi:
2584  case Hexagon::L2_ploadrhfnew_pi:
2585  case Hexagon::L4_ploadrht_abs:
2586  case Hexagon::L4_ploadrhf_abs:
2587  case Hexagon::L4_ploadrhtnew_abs:
2588  case Hexagon::L4_ploadrhfnew_abs:
2589  case Hexagon::L2_loadrhgp:
2590  return true;
2591  default:
2592  return false;
2593  }
2594 }
2595 
2597  const uint64_t F = MI.getDesc().TSFlags;
2599 }
2600 
2602  switch (MI.getOpcode()) {
2603  case Hexagon::STriw_pred:
2604  case Hexagon::LDriw_pred:
2605  return true;
2606  default:
2607  return false;
2608  }
2609 }
2610 
2612  if (!MI.isBranch())
2613  return false;
2614 
2615  for (auto &Op : MI.operands())
2616  if (Op.isGlobal() || Op.isSymbol())
2617  return true;
2618  return false;
2619 }
2620 
2621 // Returns true when SU has a timing class TC1.
2623  unsigned SchedClass = MI.getDesc().getSchedClass();
2624  return is_TC1(SchedClass);
2625 }
2626 
2628  unsigned SchedClass = MI.getDesc().getSchedClass();
2629  return is_TC2(SchedClass);
2630 }
2631 
2633  unsigned SchedClass = MI.getDesc().getSchedClass();
2634  return is_TC2early(SchedClass);
2635 }
2636 
2638  unsigned SchedClass = MI.getDesc().getSchedClass();
2639  return is_TC4x(SchedClass);
2640 }
2641 
2642 // Schedule this ASAP.
2644  const MachineInstr &MI2) const {
2645  if (mayBeCurLoad(MI1)) {
2646  // if (result of SU is used in Next) return true;
2647  Register DstReg = MI1.getOperand(0).getReg();
2648  int N = MI2.getNumOperands();
2649  for (int I = 0; I < N; I++)
2650  if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2651  return true;
2652  }
2653  if (mayBeNewStore(MI2))
2654  if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2655  if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2656  MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2657  return true;
2658  return false;
2659 }
2660 
2662  const uint64_t V = getType(MI);
2664 }
2665 
2666 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2668  int Size = VT.getSizeInBits() / 8;
2669  if (Offset % Size != 0)
2670  return false;
2671  int Count = Offset / Size;
2672 
2673  switch (VT.getSimpleVT().SimpleTy) {
2674  // For scalars the auto-inc is s4
2675  case MVT::i8:
2676  case MVT::i16:
2677  case MVT::i32:
2678  case MVT::i64:
2679  case MVT::f32:
2680  case MVT::f64:
2681  case MVT::v2i16:
2682  case MVT::v2i32:
2683  case MVT::v4i8:
2684  case MVT::v4i16:
2685  case MVT::v8i8:
2686  return isInt<4>(Count);
2687  // For HVX vectors the auto-inc is s3
2688  case MVT::v64i8:
2689  case MVT::v32i16:
2690  case MVT::v16i32:
2691  case MVT::v8i64:
2692  case MVT::v128i8:
2693  case MVT::v64i16:
2694  case MVT::v32i32:
2695  case MVT::v16i64:
2696  return isInt<3>(Count);
2697  default:
2698  break;
2699  }
2700 
2701  llvm_unreachable("Not an valid type!");
2702 }
2703 
2704 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2705  const TargetRegisterInfo *TRI, bool Extend) const {
2706  // This function is to check whether the "Offset" is in the correct range of
2707  // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2708  // inserted to calculate the final address. Due to this reason, the function
2709  // assumes that the "Offset" has correct alignment.
2710  // We used to assert if the offset was not properly aligned, however,
2711  // there are cases where a misaligned pointer recast can cause this
2712  // problem, and we need to allow for it. The front end warns of such
2713  // misaligns with respect to load size.
2714  switch (Opcode) {
2715  case Hexagon::PS_vstorerq_ai:
2716  case Hexagon::PS_vstorerv_ai:
2717  case Hexagon::PS_vstorerw_ai:
2718  case Hexagon::PS_vstorerw_nt_ai:
2719  case Hexagon::PS_vloadrq_ai:
2720  case Hexagon::PS_vloadrv_ai:
2721  case Hexagon::PS_vloadrw_ai:
2722  case Hexagon::PS_vloadrw_nt_ai:
2723  case Hexagon::V6_vL32b_ai:
2724  case Hexagon::V6_vS32b_ai:
2725  case Hexagon::V6_vS32b_qpred_ai:
2726  case Hexagon::V6_vS32b_nqpred_ai:
2727  case Hexagon::V6_vL32b_nt_ai:
2728  case Hexagon::V6_vS32b_nt_ai:
2729  case Hexagon::V6_vL32Ub_ai:
2730  case Hexagon::V6_vS32Ub_ai: {
2731  unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2732  assert(isPowerOf2_32(VectorSize));
2733  if (Offset & (VectorSize-1))
2734  return false;
2735  return isInt<4>(Offset >> Log2_32(VectorSize));
2736  }
2737 
2738  case Hexagon::J2_loop0i:
2739  case Hexagon::J2_loop1i:
2740  return isUInt<10>(Offset);
2741 
2742  case Hexagon::S4_storeirb_io:
2743  case Hexagon::S4_storeirbt_io:
2744  case Hexagon::S4_storeirbf_io:
2745  return isUInt<6>(Offset);
2746 
2747  case Hexagon::S4_storeirh_io:
2748  case Hexagon::S4_storeirht_io:
2749  case Hexagon::S4_storeirhf_io:
2750  return isShiftedUInt<6,1>(Offset);
2751 
2752  case Hexagon::S4_storeiri_io:
2753  case Hexagon::S4_storeirit_io:
2754  case Hexagon::S4_storeirif_io:
2755  return isShiftedUInt<6,2>(Offset);
2756  }
2757 
2758  if (Extend)
2759  return true;
2760 
2761  switch (Opcode) {
2762  case Hexagon::L2_loadri_io:
2763  case Hexagon::S2_storeri_io:
2764  return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2766 
2767  case Hexagon::L2_loadrd_io:
2768  case Hexagon::S2_storerd_io:
2769  return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2771 
2772  case Hexagon::L2_loadrh_io:
2773  case Hexagon::L2_loadruh_io:
2774  case Hexagon::S2_storerh_io:
2775  case Hexagon::S2_storerf_io:
2776  return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2778 
2779  case Hexagon::L2_loadrb_io:
2780  case Hexagon::L2_loadrub_io:
2781  case Hexagon::S2_storerb_io:
2782  return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2784 
2785  case Hexagon::A2_addi:
2786  return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2788 
2789  case Hexagon::L4_iadd_memopw_io:
2790  case Hexagon::L4_isub_memopw_io:
2791  case Hexagon::L4_add_memopw_io:
2792  case Hexagon::L4_sub_memopw_io:
2793  case Hexagon::L4_and_memopw_io:
2794  case Hexagon::L4_or_memopw_io:
2795  return (0 <= Offset && Offset <= 255);
2796 
2797  case Hexagon::L4_iadd_memoph_io:
2798  case Hexagon::L4_isub_memoph_io:
2799  case Hexagon::L4_add_memoph_io:
2800  case Hexagon::L4_sub_memoph_io:
2801  case Hexagon::L4_and_memoph_io:
2802  case Hexagon::L4_or_memoph_io:
2803  return (0 <= Offset && Offset <= 127);
2804 
2805  case Hexagon::L4_iadd_memopb_io:
2806  case Hexagon::L4_isub_memopb_io:
2807  case Hexagon::L4_add_memopb_io:
2808  case Hexagon::L4_sub_memopb_io:
2809  case Hexagon::L4_and_memopb_io:
2810  case Hexagon::L4_or_memopb_io:
2811  return (0 <= Offset && Offset <= 63);
2812 
2813  // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2814  // any size. Later pass knows how to handle it.
2815  case Hexagon::STriw_pred:
2816  case Hexagon::LDriw_pred:
2817  case Hexagon::STriw_ctr:
2818  case Hexagon::LDriw_ctr:
2819  return true;
2820 
2821  case Hexagon::PS_fi:
2822  case Hexagon::PS_fia:
2823  case Hexagon::INLINEASM:
2824  return true;
2825 
2826  case Hexagon::L2_ploadrbt_io:
2827  case Hexagon::L2_ploadrbf_io:
2828  case Hexagon::L2_ploadrubt_io:
2829  case Hexagon::L2_ploadrubf_io:
2830  case Hexagon::S2_pstorerbt_io:
2831  case Hexagon::S2_pstorerbf_io:
2832  return isUInt<6>(Offset);
2833 
2834  case Hexagon::L2_ploadrht_io:
2835  case Hexagon::L2_ploadrhf_io:
2836  case Hexagon::L2_ploadruht_io:
2837  case Hexagon::L2_ploadruhf_io:
2838  case Hexagon::S2_pstorerht_io:
2839  case Hexagon::S2_pstorerhf_io:
2840  return isShiftedUInt<6,1>(Offset);
2841 
2842  case Hexagon::L2_ploadrit_io:
2843  case Hexagon::L2_ploadrif_io:
2844  case Hexagon::S2_pstorerit_io:
2845  case Hexagon::S2_pstorerif_io:
2846  return isShiftedUInt<6,2>(Offset);
2847 
2848  case Hexagon::L2_ploadrdt_io:
2849  case Hexagon::L2_ploadrdf_io:
2850  case Hexagon::S2_pstorerdt_io:
2851  case Hexagon::S2_pstorerdf_io:
2852  return isShiftedUInt<6,3>(Offset);
2853  } // switch
2854 
2855  llvm_unreachable("No offset range is defined for this opcode. "
2856  "Please define it in the above switch statement!");
2857 }
2858 
2860  return isHVXVec(MI) && isAccumulator(MI);
2861 }
2862 
2864  const uint64_t F = get(MI.getOpcode()).TSFlags;
2865  const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2866  return
2867  V == HexagonII::TypeCVI_VA ||
2869 }
2870 
2872  const MachineInstr &ConsMI) const {
2873  if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2874  return true;
2875 
2876  if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2877  return true;
2878 
2879  if (mayBeNewStore(ConsMI))
2880  return true;
2881 
2882  return false;
2883 }
2884 
2886  switch (MI.getOpcode()) {
2887  // Byte
2888  case Hexagon::L2_loadrub_io:
2889  case Hexagon::L4_loadrub_ur:
2890  case Hexagon::L4_loadrub_ap:
2891  case Hexagon::L2_loadrub_pr:
2892  case Hexagon::L2_loadrub_pbr:
2893  case Hexagon::L2_loadrub_pi:
2894  case Hexagon::L2_loadrub_pci:
2895  case Hexagon::L2_loadrub_pcr:
2896  case Hexagon::L2_loadbzw2_io:
2897  case Hexagon::L4_loadbzw2_ur:
2898  case Hexagon::L4_loadbzw2_ap:
2899  case Hexagon::L2_loadbzw2_pr:
2900  case Hexagon::L2_loadbzw2_pbr:
2901  case Hexagon::L2_loadbzw2_pi:
2902  case Hexagon::L2_loadbzw2_pci:
2903  case Hexagon::L2_loadbzw2_pcr:
2904  case Hexagon::L2_loadbzw4_io:
2905  case Hexagon::L4_loadbzw4_ur:
2906  case Hexagon::L4_loadbzw4_ap:
2907  case Hexagon::L2_loadbzw4_pr:
2908  case Hexagon::L2_loadbzw4_pbr:
2909  case Hexagon::L2_loadbzw4_pi:
2910  case Hexagon::L2_loadbzw4_pci:
2911  case Hexagon::L2_loadbzw4_pcr:
2912  case Hexagon::L4_loadrub_rr:
2913  case Hexagon::L2_ploadrubt_io:
2914  case Hexagon::L2_ploadrubt_pi:
2915  case Hexagon::L2_ploadrubf_io:
2916  case Hexagon::L2_ploadrubf_pi:
2917  case Hexagon::L2_ploadrubtnew_io:
2918  case Hexagon::L2_ploadrubfnew_io:
2919  case Hexagon::L4_ploadrubt_rr:
2920  case Hexagon::L4_ploadrubf_rr:
2921  case Hexagon::L4_ploadrubtnew_rr:
2922  case Hexagon::L4_ploadrubfnew_rr:
2923  case Hexagon::L2_ploadrubtnew_pi:
2924  case Hexagon::L2_ploadrubfnew_pi:
2925  case Hexagon::L4_ploadrubt_abs:
2926  case Hexagon::L4_ploadrubf_abs:
2927  case Hexagon::L4_ploadrubtnew_abs:
2928  case Hexagon::L4_ploadrubfnew_abs:
2929  case Hexagon::L2_loadrubgp:
2930  // Half
2931  case Hexagon::L2_loadruh_io:
2932  case Hexagon::L4_loadruh_ur:
2933  case Hexagon::L4_loadruh_ap:
2934  case Hexagon::L2_loadruh_pr:
2935  case Hexagon::L2_loadruh_pbr:
2936  case Hexagon::L2_loadruh_pi:
2937  case Hexagon::L2_loadruh_pci:
2938  case Hexagon::L2_loadruh_pcr:
2939  case Hexagon::L4_loadruh_rr:
2940  case Hexagon::L2_ploadruht_io:
2941  case Hexagon::L2_ploadruht_pi:
2942  case Hexagon::L2_ploadruhf_io:
2943  case Hexagon::L2_ploadruhf_pi:
2944  case Hexagon::L2_ploadruhtnew_io:
2945  case Hexagon::L2_ploadruhfnew_io:
2946  case Hexagon::L4_ploadruht_rr:
2947  case Hexagon::L4_ploadruhf_rr:
2948  case Hexagon::L4_ploadruhtnew_rr:
2949  case Hexagon::L4_ploadruhfnew_rr:
2950  case Hexagon::L2_ploadruhtnew_pi:
2951  case Hexagon::L2_ploadruhfnew_pi:
2952  case Hexagon::L4_ploadruht_abs:
2953  case Hexagon::L4_ploadruhf_abs:
2954  case Hexagon::L4_ploadruhtnew_abs:
2955  case Hexagon::L4_ploadruhfnew_abs:
2956  case Hexagon::L2_loadruhgp:
2957  return true;
2958  default:
2959  return false;
2960  }
2961 }
2962 
2963 // Add latency to instruction.
2965  const MachineInstr &MI2) const {
2966  if (isHVXVec(MI1) && isHVXVec(MI2))
2967  if (!isVecUsableNextPacket(MI1, MI2))
2968  return true;
2969  return false;
2970 }
2971 
2972 /// Get the base register and byte offset of a load/store instr.
2975  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
2976  const TargetRegisterInfo *TRI) const {
2977  OffsetIsScalable = false;
2978  const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width);
2979  if (!BaseOp || !BaseOp->isReg())
2980  return false;
2981  BaseOps.push_back(BaseOp);
2982  return true;
2983 }
2984 
2985 /// Can these instructions execute at the same time in a bundle.
2987  const MachineInstr &Second) const {
2988  if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
2989  const MachineOperand &Op = Second.getOperand(0);
2990  if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2991  return true;
2992  }
2993  if (DisableNVSchedule)
2994  return false;
2995  if (mayBeNewStore(Second)) {
2996  // Make sure the definition of the first instruction is the value being
2997  // stored.
2998  const MachineOperand &Stored =
2999  Second.getOperand(Second.getNumOperands() - 1);
3000  if (!Stored.isReg())
3001  return false;
3002  for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
3003  const MachineOperand &Op = First.getOperand(i);
3004  if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3005  return true;
3006  }
3007  }
3008  return false;
3009 }
3010 
3012  unsigned Opc = CallMI.getOpcode();
3013  return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
3014 }
3015 
3017  for (auto &I : *B)
3018  if (I.isEHLabel())
3019  return true;
3020  return false;
3021 }
3022 
3023 // Returns true if an instruction can be converted into a non-extended
3024 // equivalent instruction.
3026  short NonExtOpcode;
3027  // Check if the instruction has a register form that uses register in place
3028  // of the extended operand, if so return that as the non-extended form.
3029  if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
3030  return true;
3031 
3032  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
3033  // Check addressing mode and retrieve non-ext equivalent instruction.
3034 
3035  switch (getAddrMode(MI)) {
3036  case HexagonII::Absolute:
3037  // Load/store with absolute addressing mode can be converted into
3038  // base+offset mode.
3039  NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
3040  break;
3042  // Load/store with base+offset addressing mode can be converted into
3043  // base+register offset addressing mode. However left shift operand should
3044  // be set to 0.
3045  NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
3046  break;
3048  NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
3049  break;
3050  default:
3051  return false;
3052  }
3053  if (NonExtOpcode < 0)
3054  return false;
3055  return true;
3056  }
3057  return false;
3058 }
3059 
3061  return Hexagon::getRealHWInstr(MI.getOpcode(),
3062  Hexagon::InstrType_Pseudo) >= 0;
3063 }
3064 
3066  const {
3067  MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
3068  while (I != E) {
3069  if (I->isBarrier())
3070  return true;
3071  ++I;
3072  }
3073  return false;
3074 }
3075 
3076 // Returns true, if a LD insn can be promoted to a cur load.
3078  const uint64_t F = MI.getDesc().TSFlags;
3080  Subtarget.hasV60Ops();
3081 }
3082 
3083 // Returns true, if a ST insn can be promoted to a new-value store.
3085  if (MI.mayStore() && !Subtarget.useNewValueStores())
3086  return false;
3087 
3088  const uint64_t F = MI.getDesc().TSFlags;
3090 }
3091 
3093  const MachineInstr &ConsMI) const {
3094  // There is no stall when ProdMI is not a V60 vector.
3095  if (!isHVXVec(ProdMI))
3096  return false;
3097 
3098  // There is no stall when ProdMI and ConsMI are not dependent.
3099  if (!isDependent(ProdMI, ConsMI))
3100  return false;
3101 
3102  // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3103  // are scheduled in consecutive packets.
3104  if (isVecUsableNextPacket(ProdMI, ConsMI))
3105  return false;
3106 
3107  return true;
3108 }
3109 
3112  // There is no stall when I is not a V60 vector.
3113  if (!isHVXVec(MI))
3114  return false;
3115 
3117  MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3118 
3119  if (!MII->isBundle())
3120  return producesStall(*MII, MI);
3121 
3122  for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3123  const MachineInstr &J = *MII;
3124  if (producesStall(J, MI))
3125  return true;
3126  }
3127  return false;
3128 }
3129 
3131  unsigned PredReg) const {
3132  for (const MachineOperand &MO : MI.operands()) {
3133  // Predicate register must be explicitly defined.
3134  if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3135  return false;
3136  if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3137  return false;
3138  }
3139 
3140  // Instruction that produce late predicate cannot be used as sources of
3141  // dot-new.
3142  switch (MI.getOpcode()) {
3143  case Hexagon::A4_addp_c:
3144  case Hexagon::A4_subp_c:
3145  case Hexagon::A4_tlbmatch:
3146  case Hexagon::A5_ACS:
3147  case Hexagon::F2_sfinvsqrta:
3148  case Hexagon::F2_sfrecipa:
3149  case Hexagon::J2_endloop0:
3150  case Hexagon::J2_endloop01:
3151  case Hexagon::J2_ploop1si:
3152  case Hexagon::J2_ploop1sr:
3153  case Hexagon::J2_ploop2si:
3154  case Hexagon::J2_ploop2sr:
3155  case Hexagon::J2_ploop3si:
3156  case Hexagon::J2_ploop3sr:
3157  case Hexagon::S2_cabacdecbin:
3158  case Hexagon::S2_storew_locked:
3159  case Hexagon::S4_stored_locked:
3160  return false;
3161  }
3162  return true;
3163 }
3164 
3165 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3166  return Opcode == Hexagon::J2_jumpt ||
3167  Opcode == Hexagon::J2_jumptpt ||
3168  Opcode == Hexagon::J2_jumpf ||
3169  Opcode == Hexagon::J2_jumpfpt ||
3170  Opcode == Hexagon::J2_jumptnew ||
3171  Opcode == Hexagon::J2_jumpfnew ||
3172  Opcode == Hexagon::J2_jumptnewpt ||
3173  Opcode == Hexagon::J2_jumpfnewpt;
3174 }
3175 
3177  if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3178  return false;
3179  return !isPredicatedTrue(Cond[0].getImm());
3180 }
3181 
3183  const uint64_t F = MI.getDesc().TSFlags;
3185 }
3186 
3187 // Returns the base register in a memory access (load/store). The offset is
3188 // returned in Offset and the access size is returned in AccessSize.
3189 // If the base operand has a subregister or the offset field does not contain
3190 // an immediate value, return nullptr.
3192  int64_t &Offset,
3193  unsigned &AccessSize) const {
3194  // Return if it is not a base+offset type instruction or a MemOp.
3197  !isMemOp(MI) && !isPostIncrement(MI))
3198  return nullptr;
3199 
3200  AccessSize = getMemAccessSize(MI);
3201 
3202  unsigned BasePos = 0, OffsetPos = 0;
3203  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3204  return nullptr;
3205 
3206  // Post increment updates its EA after the mem access,
3207  // so we need to treat its offset as zero.
3208  if (isPostIncrement(MI)) {
3209  Offset = 0;
3210  } else {
3211  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3212  if (!OffsetOp.isImm())
3213  return nullptr;
3214  Offset = OffsetOp.getImm();
3215  }
3216 
3217  const MachineOperand &BaseOp = MI.getOperand(BasePos);
3218  if (BaseOp.getSubReg() != 0)
3219  return nullptr;
3220  return &const_cast<MachineOperand&>(BaseOp);
3221 }
3222 
3223 /// Return the position of the base and offset operands for this instruction.
3225  unsigned &BasePos, unsigned &OffsetPos) const {
3227  return false;
3228 
3229  // Deal with memops first.
3230  if (isMemOp(MI)) {
3231  BasePos = 0;
3232  OffsetPos = 1;
3233  } else if (MI.mayStore()) {
3234  BasePos = 0;
3235  OffsetPos = 1;
3236  } else if (MI.mayLoad()) {
3237  BasePos = 1;
3238  OffsetPos = 2;
3239  } else
3240  return false;
3241 
3242  if (isPredicated(MI)) {
3243  BasePos++;
3244  OffsetPos++;
3245  }
3246  if (isPostIncrement(MI)) {
3247  BasePos++;
3248  OffsetPos++;
3249  }
3250 
3251  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3252  return false;
3253 
3254  return true;
3255 }
3256 
3257 // Inserts branching instructions in reverse order of their occurrence.
3258 // e.g. jump_t t1 (i1)
3259 // jump t2 (i2)
3260 // Jumpers = {i2, i1}
3262  MachineBasicBlock& MBB) const {
3264  // If the block has no terminators, it just falls into the block after it.
3266  if (I == MBB.instr_begin())
3267  return Jumpers;
3268 
3269  // A basic block may looks like this:
3270  //
3271  // [ insn
3272  // EH_LABEL
3273  // insn
3274  // insn
3275  // insn
3276  // EH_LABEL
3277  // insn ]
3278  //
3279  // It has two succs but does not have a terminator
3280  // Don't know how to handle it.
3281  do {
3282  --I;
3283  if (I->isEHLabel())
3284  return Jumpers;
3285  } while (I != MBB.instr_begin());
3286 
3287  I = MBB.instr_end();
3288  --I;
3289 
3290  while (I->isDebugInstr()) {
3291  if (I == MBB.instr_begin())
3292  return Jumpers;
3293  --I;
3294  }
3295  if (!isUnpredicatedTerminator(*I))
3296  return Jumpers;
3297 
3298  // Get the last instruction in the block.
3299  MachineInstr *LastInst = &*I;
3300  Jumpers.push_back(LastInst);
3301  MachineInstr *SecondLastInst = nullptr;
3302  // Find one more terminator if present.
3303  do {
3304  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3305  if (!SecondLastInst) {
3306  SecondLastInst = &*I;
3307  Jumpers.push_back(SecondLastInst);
3308  } else // This is a third branch.
3309  return Jumpers;
3310  }
3311  if (I == MBB.instr_begin())
3312  break;
3313  --I;
3314  } while (true);
3315  return Jumpers;
3316 }
3317 
3318 // Returns Operand Index for the constant extended instruction.
3320  const uint64_t F = MI.getDesc().TSFlags;
3322 }
3323 
3324 // See if instruction could potentially be a duplex candidate.
3325 // If so, return its group. Zero otherwise.
3327  const MachineInstr &MI) const {
3328  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3329 
3330  switch (MI.getOpcode()) {
3331  default:
3332  return HexagonII::HCG_None;
3333  //
3334  // Compound pairs.
3335  // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3336  // "Rd16=#U6 ; jump #r9:2"
3337  // "Rd16=Rs16 ; jump #r9:2"
3338  //
3339  case Hexagon::C2_cmpeq:
3340  case Hexagon::C2_cmpgt:
3341  case Hexagon::C2_cmpgtu:
3342  DstReg = MI.getOperand(0).getReg();
3343  Src1Reg = MI.getOperand(1).getReg();
3344  Src2Reg = MI.getOperand(2).getReg();
3345  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3346  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3347  isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3348  return HexagonII::HCG_A;
3349  break;
3350  case Hexagon::C2_cmpeqi:
3351  case Hexagon::C2_cmpgti:
3352  case Hexagon::C2_cmpgtui:
3353  // P0 = cmp.eq(Rs,#u2)
3354  DstReg = MI.getOperand(0).getReg();
3355  SrcReg = MI.getOperand(1).getReg();
3356  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3357  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3358  isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3359  ((isUInt<5>(MI.getOperand(2).getImm())) ||
3360  (MI.getOperand(2).getImm() == -1)))
3361  return HexagonII::HCG_A;
3362  break;
3363  case Hexagon::A2_tfr:
3364  // Rd = Rs
3365  DstReg = MI.getOperand(0).getReg();
3366  SrcReg = MI.getOperand(1).getReg();
3367  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3368  return HexagonII::HCG_A;
3369  break;
3370  case Hexagon::A2_tfrsi:
3371  // Rd = #u6
3372  // Do not test for #u6 size since the const is getting extended
3373  // regardless and compound could be formed.
3374  DstReg = MI.getOperand(0).getReg();
3375  if (isIntRegForSubInst(DstReg))
3376  return HexagonII::HCG_A;
3377  break;
3378  case Hexagon::S2_tstbit_i:
3379  DstReg = MI.getOperand(0).getReg();
3380  Src1Reg = MI.getOperand(1).getReg();
3381  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3382  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3383  MI.getOperand(2).isImm() &&
3384  isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3385  return HexagonII::HCG_A;
3386  break;
3387  // The fact that .new form is used pretty much guarantees
3388  // that predicate register will match. Nevertheless,
3389  // there could be some false positives without additional
3390  // checking.
3391  case Hexagon::J2_jumptnew:
3392  case Hexagon::J2_jumpfnew:
3393  case Hexagon::J2_jumptnewpt:
3394  case Hexagon::J2_jumpfnewpt:
3395  Src1Reg = MI.getOperand(0).getReg();
3396  if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3397  (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3398  return HexagonII::HCG_B;
3399  break;
3400  // Transfer and jump:
3401  // Rd=#U6 ; jump #r9:2
3402  // Rd=Rs ; jump #r9:2
3403  // Do not test for jump range here.
3404  case Hexagon::J2_jump:
3405  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3406  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3407  return HexagonII::HCG_C;
3408  }
3409 
3410  return HexagonII::HCG_None;
3411 }
3412 
3413 // Returns -1 when there is no opcode found.
3415  const MachineInstr &GB) const {
3418  if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3419  (GB.getOpcode() != Hexagon::J2_jumptnew))
3420  return -1u;
3421  Register DestReg = GA.getOperand(0).getReg();
3422  if (!GB.readsRegister(DestReg))
3423  return -1u;
3424  if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3425  return -1u;
3426  // The value compared against must be either u5 or -1.
3427  const MachineOperand &CmpOp = GA.getOperand(2);
3428  if (!CmpOp.isImm())
3429  return -1u;
3430  int V = CmpOp.getImm();
3431  if (V == -1)
3432  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3433  : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3434  if (!isUInt<5>(V))
3435  return -1u;
3436  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3437  : Hexagon::J4_cmpeqi_tp1_jump_nt;
3438 }
3439 
3440 // Returns -1 if there is no opcode found.
3442  bool ForBigCore) const {
3443  // Static table to switch the opcodes across Tiny Core and Big Core.
3444  // dup_ opcodes are Big core opcodes.
3445  // NOTE: There are special instructions that need to handled later.
3446  // L4_return* instructions, they will only occupy SLOT0 (on big core too).
3447  // PS_jmpret - This pseudo translates to J2_jumpr which occupies only SLOT2.
3448  // The compiler need to base the root instruction to L6_return_map_to_raw
3449  // which can go any slot.
3450  static const std::map<unsigned, unsigned> DupMap = {
3451  {Hexagon::A2_add, Hexagon::dup_A2_add},
3452  {Hexagon::A2_addi, Hexagon::dup_A2_addi},
3453  {Hexagon::A2_andir, Hexagon::dup_A2_andir},
3454  {Hexagon::A2_combineii, Hexagon::dup_A2_combineii},
3455  {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb},
3456  {Hexagon::A2_sxth, Hexagon::dup_A2_sxth},
3457  {Hexagon::A2_tfr, Hexagon::dup_A2_tfr},
3458  {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi},
3459  {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb},
3460  {Hexagon::A2_zxth, Hexagon::dup_A2_zxth},
3461  {Hexagon::A4_combineii, Hexagon::dup_A4_combineii},
3462  {Hexagon::A4_combineir, Hexagon::dup_A4_combineir},
3463  {Hexagon::A4_combineri, Hexagon::dup_A4_combineri},
3464  {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif},
3465  {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit},
3466  {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif},
3467  {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit},
3468  {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi},
3469  {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe},
3470  {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io},
3471  {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io},
3472  {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io},
3473  {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io},
3474  {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io},
3475  {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io},
3476  {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe},
3477  {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io},
3478  {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io},
3479  {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io},
3480  {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io},
3481  {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io},
3482  {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io},
3483  };
3484  unsigned OpNum = MI.getOpcode();
3485  // Conversion to Big core.
3486  if (ForBigCore) {
3487  auto Iter = DupMap.find(OpNum);
3488  if (Iter != DupMap.end())
3489  return Iter->second;
3490  } else { // Conversion to Tiny core.
3491  for (auto Iter = DupMap.begin(), End = DupMap.end(); Iter != End; ++Iter)
3492  if (Iter->second == OpNum)
3493  return Iter->first;
3494  }
3495  return -1;
3496 }
3497 
3498 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3499  enum Hexagon::PredSense inPredSense;
3500  inPredSense = invertPredicate ? Hexagon::PredSense_false :
3501  Hexagon::PredSense_true;
3502  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3503  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3504  return CondOpcode;
3505 
3506  llvm_unreachable("Unexpected predicable instruction");
3507 }
3508 
3509 // Return the cur value instruction for a given store.
3511  switch (MI.getOpcode()) {
3512  default: llvm_unreachable("Unknown .cur type");
3513  case Hexagon::V6_vL32b_pi:
3514  return Hexagon::V6_vL32b_cur_pi;
3515  case Hexagon::V6_vL32b_ai:
3516  return Hexagon::V6_vL32b_cur_ai;
3517  case Hexagon::V6_vL32b_nt_pi:
3518  return Hexagon::V6_vL32b_nt_cur_pi;
3519  case Hexagon::V6_vL32b_nt_ai:
3520  return Hexagon::V6_vL32b_nt_cur_ai;
3521  }
3522  return 0;
3523 }
3524 
3525 // Return the regular version of the .cur instruction.
3527  switch (MI.getOpcode()) {
3528  default: llvm_unreachable("Unknown .cur type");
3529  case Hexagon::V6_vL32b_cur_pi:
3530  return Hexagon::V6_vL32b_pi;
3531  case Hexagon::V6_vL32b_cur_ai:
3532  return Hexagon::V6_vL32b_ai;
3533  case Hexagon::V6_vL32b_nt_cur_pi:
3534  return Hexagon::V6_vL32b_nt_pi;
3535  case Hexagon::V6_vL32b_nt_cur_ai:
3536  return Hexagon::V6_vL32b_nt_ai;
3537  }
3538  return 0;
3539 }
3540 
3541 // The diagram below shows the steps involved in the conversion of a predicated
3542 // store instruction to its .new predicated new-value form.
3543 //
3544 // Note: It doesn't include conditional new-value stores as they can't be
3545 // converted to .new predicate.
3546 //
3547 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3548 // ^ ^
3549 // / \ (not OK. it will cause new-value store to be
3550 // / X conditional on p0.new while R2 producer is
3551 // / \ on p0)
3552 // / \.
3553 // p.new store p.old NV store
3554 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3555 // ^ ^
3556 // \ /
3557 // \ /
3558 // \ /
3559 // p.old store
3560 // [if (p0)memw(R0+#0)=R2]
3561 //
3562 // The following set of instructions further explains the scenario where
3563 // conditional new-value store becomes invalid when promoted to .new predicate
3564 // form.
3565 //
3566 // { 1) if (p0) r0 = add(r1, r2)
3567 // 2) p0 = cmp.eq(r3, #0) }
3568 //
3569 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3570 // the first two instructions because in instr 1, r0 is conditional on old value
3571 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3572 // is not valid for new-value stores.
3573 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3574 // from the "Conditional Store" list. Because a predicated new value store
3575 // would NOT be promoted to a double dot new store. See diagram below:
3576 // This function returns yes for those stores that are predicated but not
3577 // yet promoted to predicate dot new instructions.
3578 //
3579 // +---------------------+
3580 // /-----| if (p0) memw(..)=r0 |---------\~
3581 // || +---------------------+ ||
3582 // promote || /\ /\ || promote
3583 // || /||\ /||\ ||
3584 // \||/ demote || \||/
3585 // \/ || || \/
3586 // +-------------------------+ || +-------------------------+
3587 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3588 // +-------------------------+ || +-------------------------+
3589 // || || ||
3590 // || demote \||/
3591 // promote || \/ NOT possible
3592 // || || /\~
3593 // \||/ || /||\~
3594 // \/ || ||
3595 // +-----------------------------+
3596 // | if (p0.new) memw(..)=r0.new |
3597 // +-----------------------------+
3598 // Double Dot New Store
3599 //
3600 // Returns the most basic instruction for the .new predicated instructions and
3601 // new-value stores.
3602 // For example, all of the following instructions will be converted back to the
3603 // same instruction:
3604 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3605 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3606 // 3) if (p0.new) memw(R0+#0) = R1 --->
3607 //
3608 // To understand the translation of instruction 1 to its original form, consider
3609 // a packet with 3 instructions.
3610 // { p0 = cmp.eq(R0,R1)
3611 // if (p0.new) R2 = add(R3, R4)
3612 // R5 = add (R3, R1)
3613 // }
3614 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3615 //
3616 // This instruction can be part of the previous packet only if both p0 and R2
3617 // are promoted to .new values. This promotion happens in steps, first
3618 // predicate register is promoted to .new and in the next iteration R2 is
3619 // promoted. Therefore, in case of dependence check failure (due to R5) during
3620 // next iteration, it should be converted back to its most basic form.
3621 
3622 // Return the new value instruction for a given store.
3624  int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3625  if (NVOpcode >= 0) // Valid new-value store instruction.
3626  return NVOpcode;
3627 
3628  switch (MI.getOpcode()) {
3629  default:
3630  report_fatal_error(std::string("Unknown .new type: ") +
3631  std::to_string(MI.getOpcode()));
3632  case Hexagon::S4_storerb_ur:
3633  return Hexagon::S4_storerbnew_ur;
3634 
3635  case Hexagon::S2_storerb_pci:
3636  return Hexagon::S2_storerb_pci;
3637 
3638  case Hexagon::S2_storeri_pci:
3639  return Hexagon::S2_storeri_pci;
3640 
3641  case Hexagon::S2_storerh_pci:
3642  return Hexagon::S2_storerh_pci;
3643 
3644  case Hexagon::S2_storerd_pci:
3645  return Hexagon::S2_storerd_pci;
3646 
3647  case Hexagon::S2_storerf_pci:
3648  return Hexagon::S2_storerf_pci;
3649 
3650  case Hexagon::V6_vS32b_ai:
3651  return Hexagon::V6_vS32b_new_ai;
3652 
3653  case Hexagon::V6_vS32b_pi:
3654  return Hexagon::V6_vS32b_new_pi;
3655  }
3656  return 0;
3657 }
3658 
3659 // Returns the opcode to use when converting MI, which is a conditional jump,
3660 // into a conditional instruction which uses the .new value of the predicate.
3661 // We also use branch probabilities to add a hint to the jump.
3662 // If MBPI is null, all edges will be treated as equally likely for the
3663 // purposes of establishing a predication hint.
3665  const MachineBranchProbabilityInfo *MBPI) const {
3666  // We assume that block can have at most two successors.
3667  const MachineBasicBlock *Src = MI.getParent();
3668  const MachineOperand &BrTarget = MI.getOperand(1);
3669  bool Taken = false;
3670  const BranchProbability OneHalf(1, 2);
3671 
3672  auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3673  const MachineBasicBlock *Dst) {
3674  if (MBPI)
3675  return MBPI->getEdgeProbability(Src, Dst);
3676  return BranchProbability(1, Src->succ_size());
3677  };
3678 
3679  if (BrTarget.isMBB()) {
3680  const MachineBasicBlock *Dst = BrTarget.getMBB();
3681  Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3682  } else {
3683  // The branch target is not a basic block (most likely a function).
3684  // Since BPI only gives probabilities for targets that are basic blocks,
3685  // try to identify another target of this branch (potentially a fall-
3686  // -through) and check the probability of that target.
3687  //
3688  // The only handled branch combinations are:
3689  // - one conditional branch,
3690  // - one conditional branch followed by one unconditional branch.
3691  // Otherwise, assume not-taken.
3692  assert(MI.isConditionalBranch());
3693  const MachineBasicBlock &B = *MI.getParent();
3694  bool SawCond = false, Bad = false;
3695  for (const MachineInstr &I : B) {
3696  if (!I.isBranch())
3697  continue;
3698  if (I.isConditionalBranch()) {
3699  SawCond = true;
3700  if (&I != &MI) {
3701  Bad = true;
3702  break;
3703  }
3704  }
3705  if (I.isUnconditionalBranch() && !SawCond) {
3706  Bad = true;
3707  break;
3708  }
3709  }
3710  if (!Bad) {
3712  MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3713  if (NextIt == B.instr_end()) {
3714  // If this branch is the last, look for the fall-through block.
3715  for (const MachineBasicBlock *SB : B.successors()) {
3716  if (!B.isLayoutSuccessor(SB))
3717  continue;
3718  Taken = getEdgeProbability(Src, SB) < OneHalf;
3719  break;
3720  }
3721  } else {
3722  assert(NextIt->isUnconditionalBranch());
3723  // Find the first MBB operand and assume it's the target.
3724  const MachineBasicBlock *BT = nullptr;
3725  for (const MachineOperand &Op : NextIt->operands()) {
3726  if (!Op.isMBB())
3727  continue;
3728  BT = Op.getMBB();
3729  break;
3730  }
3731  Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3732  }
3733  } // if (!Bad)
3734  }
3735 
3736  // The Taken flag should be set to something reasonable by this point.
3737 
3738  switch (MI.getOpcode()) {
3739  case Hexagon::J2_jumpt:
3740  return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3741  case Hexagon::J2_jumpf:
3742  return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3743 
3744  default:
3745  llvm_unreachable("Unexpected jump instruction.");
3746  }
3747 }
3748 
3749 // Return .new predicate version for an instruction.
3751  const MachineBranchProbabilityInfo *MBPI) const {
3752  switch (MI.getOpcode()) {
3753  // Condtional Jumps
3754  case Hexagon::J2_jumpt:
3755  case Hexagon::J2_jumpf:
3756  return getDotNewPredJumpOp(MI, MBPI);
3757  }
3758 
3759  int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3760  if (NewOpcode >= 0)
3761  return NewOpcode;
3762  return 0;
3763 }
3764 
3766  int NewOp = MI.getOpcode();
3767  if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3768  NewOp = Hexagon::getPredOldOpcode(NewOp);
3769  // All Hexagon architectures have prediction bits on dot-new branches,
3770  // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3771  // to pick the right opcode when converting back to dot-old.
3772  if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3773  switch (NewOp) {
3774  case Hexagon::J2_jumptpt:
3775  NewOp = Hexagon::J2_jumpt;
3776  break;
3777  case Hexagon::J2_jumpfpt:
3778  NewOp = Hexagon::J2_jumpf;
3779  break;
3780  case Hexagon::J2_jumprtpt:
3781  NewOp = Hexagon::J2_jumprt;
3782  break;
3783  case Hexagon::J2_jumprfpt:
3784  NewOp = Hexagon::J2_jumprf;
3785  break;
3786  }
3787  }
3788  assert(NewOp >= 0 &&
3789  "Couldn't change predicate new instruction to its old form.");
3790  }
3791 
3792  if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3793  NewOp = Hexagon::getNonNVStore(NewOp);
3794  assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3795  }
3796 
3797  if (Subtarget.hasV60Ops())
3798  return NewOp;
3799 
3800  // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3801  switch (NewOp) {
3802  case Hexagon::J2_jumpfpt:
3803  return Hexagon::J2_jumpf;
3804  case Hexagon::J2_jumptpt:
3805  return Hexagon::J2_jumpt;
3806  case Hexagon::J2_jumprfpt:
3807  return Hexagon::J2_jumprf;
3808  case Hexagon::J2_jumprtpt:
3809  return Hexagon::J2_jumprt;
3810  }
3811  return NewOp;
3812 }
3813 
3814 // See if instruction could potentially be a duplex candidate.
3815 // If so, return its group. Zero otherwise.
3817  const MachineInstr &MI) const {
3818  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3819  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3820 
3821  switch (MI.getOpcode()) {
3822  default:
3823  return HexagonII::HSIG_None;
3824  //
3825  // Group L1:
3826  //
3827  // Rd = memw(Rs+#u4:2)
3828  // Rd = memub(Rs+#u4:0)
3829  case Hexagon::L2_loadri_io:
3830  case Hexagon::dup_L2_loadri_io:
3831  DstReg = MI.getOperand(0).getReg();
3832  SrcReg = MI.getOperand(1).getReg();
3833  // Special case this one from Group L2.
3834  // Rd = memw(r29+#u5:2)
3835  if (isIntRegForSubInst(DstReg)) {
3836  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3837  HRI.getStackRegister() == SrcReg &&
3838  MI.getOperand(2).isImm() &&
3839  isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3840  return HexagonII::HSIG_L2;
3841  // Rd = memw(Rs+#u4:2)
3842  if (isIntRegForSubInst(SrcReg) &&
3843  (MI.getOperand(2).isImm() &&
3844  isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3845  return HexagonII::HSIG_L1;
3846  }
3847  break;
3848  case Hexagon::L2_loadrub_io:
3849  case Hexagon::dup_L2_loadrub_io:
3850  // Rd = memub(Rs+#u4:0)
3851  DstReg = MI.getOperand(0).getReg();
3852  SrcReg = MI.getOperand(1).getReg();
3853  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3854  MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3855  return HexagonII::HSIG_L1;
3856  break;
3857  //
3858  // Group L2:
3859  //
3860  // Rd = memh/memuh(Rs+#u3:1)
3861  // Rd = memb(Rs+#u3:0)
3862  // Rd = memw(r29+#u5:2) - Handled above.
3863  // Rdd = memd(r29+#u5:3)
3864  // deallocframe
3865  // [if ([!]p0[.new])] dealloc_return
3866  // [if ([!]p0[.new])] jumpr r31
3867  case Hexagon::L2_loadrh_io:
3868  case Hexagon::L2_loadruh_io:
3869  case Hexagon::dup_L2_loadrh_io:
3870  case Hexagon::dup_L2_loadruh_io:
3871  // Rd = memh/memuh(Rs+#u3:1)
3872  DstReg = MI.getOperand(0).getReg();
3873  SrcReg = MI.getOperand(1).getReg();
3874  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3875  MI.getOperand(2).isImm() &&
3876  isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3877  return HexagonII::HSIG_L2;
3878  break;
3879  case Hexagon::L2_loadrb_io:
3880  case Hexagon::dup_L2_loadrb_io:
3881  // Rd = memb(Rs+#u3:0)
3882  DstReg = MI.getOperand(0).getReg();
3883  SrcReg = MI.getOperand(1).getReg();
3884  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3885  MI.getOperand(2).isImm() &&
3886  isUInt<3>(MI.getOperand(2).getImm()))
3887  return HexagonII::HSIG_L2;
3888  break;
3889  case Hexagon::L2_loadrd_io:
3890  case Hexagon::dup_L2_loadrd_io:
3891  // Rdd = memd(r29+#u5:3)
3892  DstReg = MI.getOperand(0).getReg();
3893  SrcReg = MI.getOperand(1).getReg();
3894  if (isDblRegForSubInst(DstReg, HRI) &&
3895  Hexagon::IntRegsRegClass.contains(SrcReg) &&
3896  HRI.getStackRegister() == SrcReg &&
3897  MI.getOperand(2).isImm() &&
3898  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3899  return HexagonII::HSIG_L2;
3900  break;
3901  // dealloc_return is not documented in Hexagon Manual, but marked
3902  // with A_SUBINSN attribute in iset_v4classic.py.
3903  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3904  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3905  case Hexagon::L4_return:
3906  case Hexagon::L2_deallocframe:
3907  case Hexagon::dup_L2_deallocframe:
3908  return HexagonII::HSIG_L2;
3909  case Hexagon::EH_RETURN_JMPR:
3910  case Hexagon::PS_jmpret:
3911  case Hexagon::SL2_jumpr31:
3912  // jumpr r31
3913  // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
3914  DstReg = MI.getOperand(0).getReg();
3915  if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3916  return HexagonII::HSIG_L2;
3917  break;
3918  case Hexagon::PS_jmprett:
3919  case Hexagon::PS_jmpretf:
3920  case Hexagon::PS_jmprettnewpt:
3921  case Hexagon::PS_jmpretfnewpt:
3922  case Hexagon::PS_jmprettnew:
3923  case Hexagon::PS_jmpretfnew:
3924  case Hexagon::SL2_jumpr31_t:
3925  case Hexagon::SL2_jumpr31_f:
3926  case Hexagon::SL2_jumpr31_tnew:
3927  case Hexagon::SL2_jumpr31_fnew:
3928  DstReg = MI.getOperand(1).getReg();
3929  SrcReg = MI.getOperand(0).getReg();
3930  // [if ([!]p0[.new])] jumpr r31
3931  if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3932  (Hexagon::P0 == SrcReg)) &&
3933  (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3934  return HexagonII::HSIG_L2;
3935  break;
3936  case Hexagon::L4_return_t:
3937  case Hexagon::L4_return_f:
3938  case Hexagon::L4_return_tnew_pnt:
3939  case Hexagon::L4_return_fnew_pnt:
3940  case Hexagon::L4_return_tnew_pt:
3941  case Hexagon::L4_return_fnew_pt:
3942  // [if ([!]p0[.new])] dealloc_return
3943  SrcReg = MI.getOperand(0).getReg();
3944  if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3945  return HexagonII::HSIG_L2;
3946  break;
3947  //
3948  // Group S1:
3949  //
3950  // memw(Rs+#u4:2) = Rt
3951  // memb(Rs+#u4:0) = Rt
3952  case Hexagon::S2_storeri_io:
3953  case Hexagon::dup_S2_storeri_io:
3954  // Special case this one from Group S2.
3955  // memw(r29+#u5:2) = Rt
3956  Src1Reg = MI.getOperand(0).getReg();
3957  Src2Reg = MI.getOperand(2).getReg();
3958  if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3959  isIntRegForSubInst(Src2Reg) &&
3960  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3961  isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3962  return HexagonII::HSIG_S2;
3963  // memw(Rs+#u4:2) = Rt
3964  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3965  MI.getOperand(1).isImm() &&
3966  isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3967  return HexagonII::HSIG_S1;
3968  break;
3969  case Hexagon::S2_storerb_io:
3970  case Hexagon::dup_S2_storerb_io:
3971  // memb(Rs+#u4:0) = Rt
3972  Src1Reg = MI.getOperand(0).getReg();
3973  Src2Reg = MI.getOperand(2).getReg();
3974  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3975  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3976  return HexagonII::HSIG_S1;
3977  break;
3978  //
3979  // Group S2:
3980  //
3981  // memh(Rs+#u3:1) = Rt
3982  // memw(r29+#u5:2) = Rt
3983  // memd(r29+#s6:3) = Rtt
3984  // memw(Rs+#u4:2) = #U1
3985  // memb(Rs+#u4) = #U1
3986  // allocframe(#u5:3)
3987  case Hexagon::S2_storerh_io:
3988  case Hexagon::dup_S2_storerh_io:
3989  // memh(Rs+#u3:1) = Rt
3990  Src1Reg = MI.getOperand(0).getReg();
3991  Src2Reg = MI.getOperand(2).getReg();
3992  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3993  MI.getOperand(1).isImm() &&
3994  isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3995  return HexagonII::HSIG_S1;
3996  break;
3997  case Hexagon::S2_storerd_io:
3998  case Hexagon::dup_S2_storerd_io:
3999  // memd(r29+#s6:3) = Rtt
4000  Src1Reg = MI.getOperand(0).getReg();
4001  Src2Reg = MI.getOperand(2).getReg();
4002  if (isDblRegForSubInst(Src2Reg, HRI) &&
4003  Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4004  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
4005  isShiftedInt<6,3>(MI.getOperand(1).getImm()))
4006  return HexagonII::HSIG_S2;
4007  break;
4008  case Hexagon::S4_storeiri_io:
4009  case Hexagon::dup_S4_storeiri_io:
4010  // memw(Rs+#u4:2) = #U1
4011  Src1Reg = MI.getOperand(0).getReg();
4012  if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
4013  isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
4014  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4015  return HexagonII::HSIG_S2;
4016  break;
4017  case Hexagon::S4_storeirb_io:
4018  case Hexagon::dup_S4_storeirb_io:
4019  // memb(Rs+#u4) = #U1
4020  Src1Reg = MI.getOperand(0).getReg();
4021  if (isIntRegForSubInst(Src1Reg) &&
4022  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
4023  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4024  return HexagonII::HSIG_S2;
4025  break;
4026  case Hexagon::S2_allocframe:
4027  case Hexagon::dup_S2_allocframe:
4028  if (MI.getOperand(2).isImm() &&
4029  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
4030  return HexagonII::HSIG_S1;
4031  break;
4032  //
4033  // Group A:
4034  //
4035  // Rx = add(Rx,#s7)
4036  // Rd = Rs
4037  // Rd = #u6
4038  // Rd = #-1
4039  // if ([!]P0[.new]) Rd = #0
4040  // Rd = add(r29,#u6:2)
4041  // Rx = add(Rx,Rs)
4042  // P0 = cmp.eq(Rs,#u2)
4043  // Rdd = combine(#0,Rs)
4044  // Rdd = combine(Rs,#0)
4045  // Rdd = combine(#u2,#U2)
4046  // Rd = add(Rs,#1)
4047  // Rd = add(Rs,#-1)
4048  // Rd = sxth/sxtb/zxtb/zxth(Rs)
4049  // Rd = and(Rs,#1)
4050  case Hexagon::A2_addi:
4051  case Hexagon::dup_A2_addi:
4052  DstReg = MI.getOperand(0).getReg();
4053  SrcReg = MI.getOperand(1).getReg();
4054  if (isIntRegForSubInst(DstReg)) {
4055  // Rd = add(r29,#u6:2)
4056  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
4057  HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
4058  isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
4059  return HexagonII::HSIG_A;
4060  // Rx = add(Rx,#s7)
4061  if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
4062  isInt<7>(MI.getOperand(2).getImm()))
4063  return HexagonII::HSIG_A;
4064  // Rd = add(Rs,#1)
4065  // Rd = add(Rs,#-1)
4066  if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
4067  ((MI.getOperand(2).getImm() == 1) ||
4068  (MI.getOperand(2).getImm() == -1)))
4069  return HexagonII::HSIG_A;
4070  }
4071  break;
4072  case Hexagon::A2_add:
4073  case Hexagon::dup_A2_add:
4074  // Rx = add(Rx,Rs)
4075  DstReg = MI.getOperand(0).getReg();
4076  Src1Reg = MI.getOperand(1).getReg();
4077  Src2Reg = MI.getOperand(2).getReg();
4078  if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
4079  isIntRegForSubInst(Src2Reg))
4080  return HexagonII::HSIG_A;
4081  break;
4082  case Hexagon::A2_andir:
4083  case Hexagon::dup_A2_andir:
4084  // Same as zxtb.
4085  // Rd16=and(Rs16,#255)
4086  // Rd16=and(Rs16,#1)
4087  DstReg = MI.getOperand(0).getReg();
4088  SrcReg = MI.getOperand(1).getReg();
4089  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
4090  MI.getOperand(2).isImm() &&
4091  ((MI.getOperand(2).getImm() == 1) ||
4092  (MI.getOperand(2).getImm() == 255)))
4093  return HexagonII::HSIG_A;
4094  break;
4095  case Hexagon::A2_tfr:
4096  case Hexagon::dup_A2_tfr:
4097  // Rd = Rs
4098  DstReg = MI.getOperand(0).getReg();
4099  SrcReg = MI.getOperand(1).getReg();
4100  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4101  return HexagonII::HSIG_A;
4102  break;
4103  case Hexagon::A2_tfrsi:
4104  case Hexagon::dup_A2_tfrsi:
4105  // Rd = #u6
4106  // Do not test for #u6 size since the const is getting extended
4107  // regardless and compound could be formed.
4108  // Rd = #-1
4109  DstReg = MI.getOperand(0).getReg();
4110  if (isIntRegForSubInst(DstReg))
4111  return HexagonII::HSIG_A;
4112  break;
4113  case Hexagon::C2_cmoveit:
4114  case Hexagon::C2_cmovenewit:
4115  case Hexagon::C2_cmoveif:
4116  case Hexagon::C2_cmovenewif:
4117  case Hexagon::dup_C2_cmoveit:
4118  case Hexagon::dup_C2_cmovenewit:
4119  case Hexagon::dup_C2_cmoveif:
4120  case Hexagon::dup_C2_cmovenewif:
4121  // if ([!]P0[.new]) Rd = #0
4122  // Actual form:
4123  // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
4124  DstReg = MI.getOperand(0).getReg();
4125  SrcReg = MI.getOperand(1).getReg();
4126  if (isIntRegForSubInst(DstReg) &&
4127  Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4128  MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4129  return HexagonII::HSIG_A;
4130  break;
4131  case Hexagon::C2_cmpeqi:
4132  case Hexagon::dup_C2_cmpeqi:
4133  // P0 = cmp.eq(Rs,#u2)
4134  DstReg = MI.getOperand(0).getReg();
4135  SrcReg = MI.getOperand(1).getReg();
4136  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
4137  Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
4138  MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4139  return HexagonII::HSIG_A;
4140  break;
4141  case Hexagon::A2_combineii:
4142  case Hexagon::A4_combineii:
4143  case Hexagon::dup_A2_combineii:
4144  case Hexagon::dup_A4_combineii:
4145  // Rdd = combine(#u2,#U2)
4146  DstReg = MI.getOperand(0).getReg();
4147  if (isDblRegForSubInst(DstReg, HRI) &&
4148  ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4149  (MI.getOperand(1).isGlobal() &&
4150  isUInt<2>(MI.getOperand(1).getOffset()))) &&
4151  ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4152  (MI.getOperand(2).isGlobal() &&
4153  isUInt<2>(MI.getOperand(2).getOffset()))))
4154  return HexagonII::HSIG_A;
4155  break;
4156  case Hexagon::A4_combineri:
4157  case Hexagon::dup_A4_combineri:
4158  // Rdd = combine(Rs,#0)
4159  // Rdd = combine(Rs,#0)
4160  DstReg = MI.getOperand(0).getReg();
4161  SrcReg = MI.getOperand(1).getReg();
4162  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4163  ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4164  (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4165  return HexagonII::HSIG_A;
4166  break;
4167  case Hexagon::A4_combineir:
4168  case Hexagon::dup_A4_combineir:
4169  // Rdd = combine(#0,Rs)
4170  DstReg = MI.getOperand(0).getReg();
4171  SrcReg = MI.getOperand(2).getReg();
4172  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4173  ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4174  (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4175  return HexagonII::HSIG_A;
4176  break;
4177  case Hexagon::A2_sxtb:
4178  case Hexagon::A2_sxth:
4179  case Hexagon::A2_zxtb:
4180  case Hexagon::A2_zxth:
4181  case Hexagon::dup_A2_sxtb:
4182  case Hexagon::dup_A2_sxth:
4183  case Hexagon::dup_A2_zxtb:
4184  case Hexagon::dup_A2_zxth:
4185  // Rd = sxth/sxtb/zxtb/zxth(Rs)
4186  DstReg = MI.getOperand(0).getReg();
4187  SrcReg = MI.getOperand(1).getReg();
4188  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4189  return HexagonII::HSIG_A;
4190  break;
4191  }
4192 
4193  return HexagonII::HSIG_None;
4194 }
4195 
4197  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4198 }
4199 
4201  const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4202  // Default to one cycle for no itinerary. However, an "empty" itinerary may
4203  // still have a MinLatency property, which getStageLatency checks.
4204  if (!ItinData)
4205  return getInstrLatency(ItinData, MI);
4206 
4207  if (MI.isTransient())
4208  return 0;
4209  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4210 }
4211 
4212 /// getOperandLatency - Compute and return the use operand latency of a given
4213 /// pair of def and use.
4214 /// In most cases, the static scheduling itinerary was enough to determine the
4215 /// operand latency. But it may not be possible for instructions with variable
4216 /// number of defs / uses.
4217 ///
4218 /// This is a raw interface to the itinerary that may be directly overriden by
4219 /// a target. Use computeOperandLatency to get the best estimate of latency.
4221  const MachineInstr &DefMI,
4222  unsigned DefIdx,
4223  const MachineInstr &UseMI,
4224  unsigned UseIdx) const {
4225  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4226 
4227  // Get DefIdx and UseIdx for super registers.
4228  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4229 
4230  if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) {
4231  if (DefMO.isImplicit()) {
4232  for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
4233  int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
4234  if (Idx != -1) {
4235  DefIdx = Idx;
4236  break;
4237  }
4238  }
4239  }
4240 
4241  const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4242  if (UseMO.isImplicit()) {
4243  for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
4244  int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
4245  if (Idx != -1) {
4246  UseIdx = Idx;
4247  break;
4248  }
4249  }
4250  }
4251  }
4252 
4253  int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
4254  UseMI, UseIdx);
4255  if (!Latency)
4256  // We should never have 0 cycle latency between two instructions unless
4257  // they can be packetized together. However, this decision can't be made
4258  // here.
4259  Latency = 1;
4260  return Latency;
4261 }
4262 
4263 // inverts the predication logic.
4264 // p -> NotP
4265 // NotP -> P
4268  if (Cond.empty())
4269  return false;
4270  unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4271  Cond[0].setImm(Opc);
4272  return true;
4273 }
4274 
4275 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4276  int InvPredOpcode;
4277  InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4278  : Hexagon::getTruePredOpcode(Opc);
4279  if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4280  return InvPredOpcode;
4281 
4282  llvm_unreachable("Unexpected predicated instruction");
4283 }
4284 
4285 // Returns the max value that doesn't need to be extended.
4287  const uint64_t F = MI.getDesc().TSFlags;
4288  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4290  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4292 
4293  if (isSigned) // if value is signed
4294  return ~(-1U << (bits - 1));
4295  else
4296  return ~(-1U << bits);
4297 }
4298 
4299 
4301  switch (MI.getOpcode()) {
4302  case Hexagon::L2_loadrbgp:
4303  case Hexagon::L2_loadrdgp:
4304  case Hexagon::L2_loadrhgp:
4305  case Hexagon::L2_loadrigp:
4306  case Hexagon::L2_loadrubgp:
4307  case Hexagon::L2_loadruhgp:
4308  case Hexagon::S2_storerbgp:
4309  case Hexagon::S2_storerbnewgp:
4310  case Hexagon::S2_storerhgp:
4311  case Hexagon::S2_storerhnewgp:
4312  case Hexagon::S2_storerigp:
4313  case Hexagon::S2_storerinewgp:
4314  case Hexagon::S2_storerdgp:
4315  case Hexagon::S2_storerfgp:
4316  return true;
4317  }
4318  const uint64_t F = MI.getDesc().TSFlags;
4319  unsigned addrMode =
4321  // Disallow any base+offset instruction. The assembler does not yet reorder
4322  // based up any zero offset instruction.
4323  return (addrMode == HexagonII::BaseRegOffset ||
4324  addrMode == HexagonII::BaseImmOffset ||
4325  addrMode == HexagonII::BaseLongOffset);
4326 }
4327 
4329  // Workaround for the Global Scheduler. Sometimes, it creates
4330  // A4_ext as a Pseudo instruction and calls this function to see if
4331  // it can be added to an existing bundle. Since the instruction doesn't
4332  // belong to any BB yet, we can't use getUnits API.
4333  if (MI.getOpcode() == Hexagon::A4_ext)
4334  return false;
4335 
4336  unsigned FuncUnits = getUnits(MI);
4337  return HexagonFUnits::isSlot0Only(FuncUnits);
4338 }
4339 
4341  const uint64_t F = MI.getDesc().TSFlags;
4342  return ((F >> HexagonII::RestrictNoSlot1StorePos) &
4344 }
4345 
4347  bool ToBigInstrs) const {
4348  int Opcode = -1;
4349  if (ToBigInstrs) { // To BigCore Instr.
4350  // Check if the instruction can form a Duplex.
4351  if (getDuplexCandidateGroup(*MII))
4352  // Get the opcode marked "dup_*" tag.
4353  Opcode = getDuplexOpcode(*MII, ToBigInstrs);
4354  } else // To TinyCore Instr.
4355  Opcode = getDuplexOpcode(*MII, ToBigInstrs);
4356 
4357  // Change the opcode of the instruction.
4358  if (Opcode >= 0)
4359  MII->setDesc(get(Opcode));
4360 }
4361 
4362 // This function is used to translate instructions to facilitate generating
4363 // Duplexes on TinyCore.
4365  bool ToBigInstrs) const {
4366  for (auto &MB : MF)
4367  for (MachineBasicBlock::instr_iterator Instr = MB.instr_begin(),
4368  End = MB.instr_end();
4369  Instr != End; ++Instr)
4370  changeDuplexOpcode(Instr, ToBigInstrs);
4371 }
4372 
4373 // This is a specialized form of above function.
4375  MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const {
4376  MachineBasicBlock *MBB = MII->getParent();
4377  while ((MII != MBB->instr_end()) && MII->isInsideBundle()) {
4378  changeDuplexOpcode(MII, ToBigInstrs);
4379  ++MII;
4380  }
4381 }
4382 
4384  using namespace HexagonII;
4385 
4386  const uint64_t F = MI.getDesc().TSFlags;
4387  unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4389  if (Size != 0)
4390  return Size;
4391 
4392  // Handle vector access sizes.
4393  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4394  switch (S) {
4396  return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4397  default:
4398  llvm_unreachable("Unexpected instruction");
4399  }
4400 }
4401 
4402 // Returns the min value that doesn't need to be extended.
4404  const uint64_t F = MI.getDesc().TSFlags;
4405  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4407  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4409 
4410  if (isSigned) // if value is signed
4411  return -1U << (bits - 1);
4412  else
4413  return 0;
4414 }
4415 
4416 // Returns opcode of the non-extended equivalent instruction.
4418  // Check if the instruction has a register form that uses register in place
4419  // of the extended operand, if so return that as the non-extended form.
4420  short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4421  if (NonExtOpcode >= 0)
4422  return NonExtOpcode;
4423 
4424  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4425  // Check addressing mode and retrieve non-ext equivalent instruction.
4426  switch (getAddrMode(MI)) {
4427  case HexagonII::Absolute:
4428  return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4430  return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4432  return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4433 
4434  default:
4435  return -1;
4436  }
4437  }
4438  return -1;
4439 }
4440 
4442  unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4443  if (Cond.empty())
4444  return false;
4445  assert(Cond.size() == 2);
4446  if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4447  LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4448  return false;
4449  }
4450  PredReg = Cond[1].getReg();
4451  PredRegPos = 1;
4452  // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4453  PredRegFlags = 0;
4454  if (Cond[1].isImplicit())
4455  PredRegFlags = RegState::Implicit;
4456  if (Cond[1].isUndef())
4457  PredRegFlags |= RegState::Undef;
4458  return true;
4459 }
4460 
4462  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4463 }
4464 
4466  return Hexagon::getRegForm(MI.getOpcode());
4467 }
4468 
4469 // Return the number of bytes required to encode the instruction.
4470 // Hexagon instructions are fixed length, 4 bytes, unless they
4471 // use a constant extender, which requires another 4 bytes.
4472 // For debug instructions and prolog labels, return 0.
4474  if (MI.isDebugInstr() || MI.isPosition())
4475  return 0;
4476 
4477  unsigned Size = MI.getDesc().getSize();
4478  if (!Size)
4479  // Assume the default insn size in case it cannot be determined
4480  // for whatever reason.
4482 
4483  if (isConstExtended(MI) || isExtended(MI))
4485 
4486  // Try and compute number of instructions in asm.
4487  if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) {
4488  const MachineBasicBlock &MBB = *MI.getParent();
4489  const MachineFunction *MF = MBB.getParent();
4490  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4491 
4492  // Count the number of register definitions to find the asm string.
4493  unsigned NumDefs = 0;
4494  for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4495  ++NumDefs)
4496  assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4497 
4498  assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4499  // Disassemble the AsmStr and approximate number of instructions.
4500  const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4501  Size = getInlineAsmLength(AsmStr, *MAI);
4502  }
4503 
4504  return Size;
4505 }
4506 
4508  const uint64_t F = MI.getDesc().TSFlags;
4510 }
4511 
4513  const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4514  const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4515 
4516  return IS.getUnits();
4517 }
4518 
4519 // Calculate size of the basic block without debug instructions.
4521  return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4522 }
4523 
4525  MachineBasicBlock::const_iterator BundleHead) const {
4526  assert(BundleHead->isBundle() && "Not a bundle header");
4527  auto MII = BundleHead.getInstrIterator();
4528  // Skip the bundle header.
4529  return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4530 }
4531 
4532 /// immediateExtend - Changes the instruction in place to one using an immediate
4533 /// extender.
4536  "Instruction must be extendable");
4537  // Find which operand is extendable.
4538  short ExtOpNum = getCExtOpNum(MI);
4539  MachineOperand &MO = MI.getOperand(ExtOpNum);
4540  // This needs to be something we understand.
4541  assert((MO.isMBB() || MO.isImm()) &&
4542  "Branch with unknown extendable field type");
4543  // Mark given operand as extended.
4545 }
4546 
4548  MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4549  LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4550  << printMBBReference(*NewTarget);
4551  MI.dump(););
4552  assert(MI.isBranch());
4553  unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4554  int TargetPos = MI.getNumOperands() - 1;
4555  // In general branch target is the last operand,
4556  // but some implicit defs added at the end might change it.
4557  while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4558  --TargetPos;
4559  assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4560  MI.getOperand(TargetPos).setMBB(NewTarget);
4562  NewOpcode = reversePrediction(NewOpcode);
4563  }
4564  MI.setDesc(get(NewOpcode));
4565  return true;
4566 }
4567 
4569  /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4571  MachineBasicBlock &B = *A;
4572  MachineBasicBlock::iterator I = B.begin();
4573  DebugLoc DL = I->getDebugLoc();
4574  MachineInstr *NewMI;
4575 
4576  for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4577  insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4578  NewMI = BuildMI(B, I, DL, get(insn));
4579  LLVM_DEBUG(dbgs() << "\n"
4580  << getName(NewMI->getOpcode())
4581  << " Class: " << NewMI->getDesc().getSchedClass());
4582  NewMI->eraseFromParent();
4583  }
4584  /* --- The code above is used to generate complete set of Hexagon Insn --- */
4585 }
4586 
4587 // inverts the predication logic.
4588 // p -> NotP
4589 // NotP -> P
4591  LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4592  MI.setDesc(get(getInvertedPredicatedOpcode(MI.getOpcode())));
4593  return true;
4594 }
4595 
4596 // Reverse the branch prediction.
4597 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4598  int PredRevOpcode = -1;
4599  if (isPredictedTaken(Opcode))
4600  PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4601  else
4602  PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4603  assert(PredRevOpcode > 0);
4604  return PredRevOpcode;
4605 }
4606 
4607 // TODO: Add more rigorous validation.
4609  const {
4610  return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4611 }
4612 
4613 void HexagonInstrInfo::
4615  assert(MIB->isBundle());
4616  MachineOperand &Operand = MIB->getOperand(0);
4617  if (Operand.isImm())
4618  Operand.setImm(Operand.getImm() | memShufDisabledMask);
4619  else
4620  MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4621 }
4622 
4624  assert(MIB.isBundle());
4625  const MachineOperand &Operand = MIB.getOperand(0);
4626  return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4627 }
4628 
4629 // Addressing mode relations.
4631  return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4632 }
4633 
4635  return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4636 }
4637 
4639  return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4640 }
4641 
4643  return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4644 }
4645 
4647  return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4648 }
4649 
4651  return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4652 }
4653 
4655  return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4656 }
4657 
4659  return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4660 }
llvm::HexagonII::mayNVStoreMask
@ mayNVStoreMask
Definition: HexagonBaseInfo.h:87
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::HexagonII::SoloPos
@ SoloPos
Definition: HexagonBaseInfo.h:57
i
i
Definition: README.txt:29
llvm::HexagonInstrInfo::isTailCall
bool isTailCall(const MachineInstr &MI) const override
Definition: HexagonInstrInfo.cpp:2611
llvm::HexagonII::CompoundGroup
CompoundGroup
Definition: HexagonBaseInfo.h:234
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:244
llvm::HexagonII::ExtendableOpMask
@ ExtendableOpMask
Definition: HexagonBaseInfo.h:106
llvm::HexagonII::TakenMask
@ TakenMask
Definition: HexagonBaseInfo.h:136
llvm::MachineBasicBlock::succ_size
unsigned succ_size() const
Definition: MachineBasicBlock.h:344
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:63
llvm::HexagonII::HSIG_Compound
@ HSIG_Compound
Definition: HexagonBaseInfo.h:230
llvm::HexagonInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Test if the given instruction should be considered a scheduling boundary.
Definition: HexagonInstrInfo.cpp:1706
llvm::HexagonInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Definition: HexagonInstrInfo.cpp:293
getName
static StringRef getName(Value *V)
Definition: ProvenanceAnalysisEvaluator.cpp:42
llvm::HexagonSubtarget::useNewValueStores
bool useNewValueStores() const
Definition: HexagonSubtarget.h:195
llvm::HexagonII::AccumulatorPos
@ AccumulatorPos
Definition: HexagonBaseInfo.h:150
ScheduleDAG.h
llvm::HexagonII::HSIG_S2
@ HSIG_S2
Definition: HexagonBaseInfo.h:228
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:132
llvm::HexagonII::PredicateLateMask
@ PredicateLateMask
Definition: HexagonBaseInfo.h:74
llvm
Definition: AllocatorList.h:23
llvm::MCAsmInfo::getCommentString
StringRef getCommentString() const
Definition: MCAsmInfo.h:574
llvm::HexagonInstrInfo::nonDbgBBSize
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
Definition: HexagonInstrInfo.cpp:4520
llvm::ARMII::MO_HI16
@ MO_HI16
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address.
Definition: ARMBaseInfo.h:250
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::HexagonInstrInfo::HexagonInstrInfo
HexagonInstrInfo(HexagonSubtarget &ST)
Definition: HexagonInstrInfo.cpp:117
llvm::M68kBeads::Term
@ Term
Definition: M68kBaseInfo.h:71
llvm::MachineOperand::isBlockAddress
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Definition: MachineOperand.h:340
llvm::MCAsmInfo::getSeparatorString
const char * getSeparatorString() const
Definition: MCAsmInfo.h:568
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:100
llvm::HexagonII::TakenPos
@ TakenPos
Definition: HexagonBaseInfo.h:135
llvm::MachineInstr::isIndirectBranch
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:850
llvm::HexagonInstrInfo::isAbsoluteSet
bool isAbsoluteSet(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2030
llvm::HexagonInstrInfo::changeAddrMode_io_rr
short changeAddrMode_io_rr(short Opc) const
Definition: HexagonInstrInfo.cpp:4642
llvm::StringRef::count
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Definition: StringRef.h:490
llvm::HexagonInstrInfo::getUnits
InstrStage::FuncUnits getUnits(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4512
llvm::HexagonInstrInfo::getCompoundCandidateGroup
HexagonII::CompoundGroup getCompoundCandidateGroup(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3326
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::HexagonII::ExtendedPos
@ ExtendedPos
Definition: HexagonBaseInfo.h:102
llvm::HexagonII::MO_GDGOT
@ MO_GDGOT
Definition: HexagonBaseInfo.h:195
llvm::HexagonII::HCG_C
@ HCG_C
Definition: HexagonBaseInfo.h:238
llvm::is_TC2
bool is_TC2(unsigned SchedClass)
Definition: HexagonDepTimingClasses.h:66
llvm::HexagonInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
Definition: HexagonInstrInfo.cpp:561
llvm::Latency
@ Latency
Definition: SIMachineScheduler.h:32
MCInstrDesc.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstr::getNumExplicitOperands
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Definition: MachineInstr.cpp:726
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:225
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
StringRef.h
llvm::HexagonInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition: HexagonInstrInfo.cpp:391
llvm::HexagonInstrInfo::isJumpR
bool isJumpR(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2281
llvm::HexagonII::AddrModePos
@ AddrModePos
Definition: HexagonBaseInfo.h:128
llvm::HexagonInstrInfo::hasPseudoInstrPair
bool hasPseudoInstrPair(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3060
llvm::HexagonInstrInfo::isJumpWithinBranchRange
bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const
Definition: HexagonInstrInfo.cpp:2299
llvm::HexagonInstrInfo::isSpillPredRegOp
bool isSpillPredRegOp(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2601
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:994
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::HexagonInstrInfo::isZeroExtendingLoad
bool isZeroExtendingLoad(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2885
HEXAGON_INSTR_SIZE
#define HEXAGON_INSTR_SIZE
Definition: HexagonMCTargetDesc.h:33
llvm::SmallVector< unsigned, 4 >
llvm::HexagonInstrInfo::getNonDotCurOp
int getNonDotCurOp(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3526
llvm::MCInstrDesc::getSchedClass
unsigned getS