65 #define DEBUG_TYPE "hexagon-instrinfo"
67 #define GET_INSTRINFO_CTOR_DTOR
68 #define GET_INSTRMAP_INFO
70 #include "HexagonGenDFAPacketizer.inc"
71 #include "HexagonGenInstrInfo.inc"
75 "packetization boundary."));
82 cl::desc(
"Disable schedule adjustment for new value stores."));
86 cl::desc(
"Enable timing class latency"));
90 cl::desc(
"Enable vec alu forwarding"));
94 cl::desc(
"Enable vec acc forwarding"));
102 cl::desc(
"Use the DFA based hazard recognizer."));
117 void HexagonInstrInfo::anchor() {}
124 namespace HexagonFUnits {
130 return (
Reg >= Hexagon::R0 &&
Reg <= Hexagon::R7) ||
131 (
Reg >= Hexagon::R16 &&
Reg <= Hexagon::R23);
143 for (; MIB != MIE; ++MIB) {
144 if (!MIB->isDebugInstr())
155 if (!(
MI.getMF()->getFunction().hasOptSize()))
156 return MI.isAsCheapAsAMove();
158 if (
MI.getOpcode() == Hexagon::A2_tfrsi) {
159 auto Op =
MI.getOperand(1);
167 int64_t
Imm =
Op.getImm();
172 return MI.isAsCheapAsAMove();
187 if (
isFloat(
MI) &&
MI.hasRegisterImplicitUseOperand(Hexagon::USR))
201 if (EndLoopOp == Hexagon::ENDLOOP0) {
202 LOOPi = Hexagon::J2_loop0i;
203 LOOPr = Hexagon::J2_loop0r;
205 LOOPi = Hexagon::J2_loop1i;
206 LOOPr = Hexagon::J2_loop1r;
217 unsigned Opc =
I.getOpcode();
218 if (Opc == LOOPi || Opc == LOOPr)
222 if (Opc == EndLoopOp &&
I.getOperand(0).getMBB() != TargetBB)
249 Uses.push_back(MO.getReg());
252 Defs.push_back(MO.getReg());
289 switch (
MI.getOpcode()) {
292 case Hexagon::L2_loadri_io:
293 case Hexagon::L2_loadrd_io:
294 case Hexagon::V6_vL32b_ai:
295 case Hexagon::V6_vL32b_nt_ai:
296 case Hexagon::V6_vL32Ub_ai:
297 case Hexagon::LDriw_pred:
298 case Hexagon::LDriw_ctr:
299 case Hexagon::PS_vloadrq_ai:
300 case Hexagon::PS_vloadrw_ai:
301 case Hexagon::PS_vloadrw_nt_ai: {
309 return MI.getOperand(0).getReg();
312 case Hexagon::L2_ploadrit_io:
313 case Hexagon::L2_ploadrif_io:
314 case Hexagon::L2_ploadrdt_io:
315 case Hexagon::L2_ploadrdf_io: {
323 return MI.getOperand(0).getReg();
337 switch (
MI.getOpcode()) {
340 case Hexagon::S2_storerb_io:
341 case Hexagon::S2_storerh_io:
342 case Hexagon::S2_storeri_io:
343 case Hexagon::S2_storerd_io:
344 case Hexagon::V6_vS32b_ai:
345 case Hexagon::V6_vS32Ub_ai:
346 case Hexagon::STriw_pred:
347 case Hexagon::STriw_ctr:
348 case Hexagon::PS_vstorerq_ai:
349 case Hexagon::PS_vstorerw_ai: {
357 return MI.getOperand(2).getReg();
360 case Hexagon::S2_pstorerbt_io:
361 case Hexagon::S2_pstorerbf_io:
362 case Hexagon::S2_pstorerht_io:
363 case Hexagon::S2_pstorerhf_io:
364 case Hexagon::S2_pstorerit_io:
365 case Hexagon::S2_pstorerif_io:
366 case Hexagon::S2_pstorerdt_io:
367 case Hexagon::S2_pstorerdf_io: {
375 return MI.getOperand(3).getReg();
391 for (++MII; MII !=
MBB->
instr_end() && MII->isInsideBundle(); ++MII)
409 for (++MII; MII !=
MBB->
instr_end() && MII->isInsideBundle(); ++MII)
437 bool AllowModify)
const {
469 while (
I->isDebugInstr()) {
475 bool JumpToBlock =
I->getOpcode() == Hexagon::J2_jump &&
476 I->getOperand(0).isMBB();
478 if (AllowModify && JumpToBlock &&
481 I->eraseFromParent();
487 if (!isUnpredicatedTerminator(*
I))
495 if (&*
I != LastInst && !
I->isBundle() && isUnpredicatedTerminator(*
I)) {
497 SecondLastInst = &*
I;
508 int SecLastOpcode = SecondLastInst ? SecondLastInst->
getOpcode() : 0;
511 if (LastOpcode == Hexagon::J2_jump && !LastInst->
getOperand(0).
isMBB())
513 if (SecLastOpcode == Hexagon::J2_jump &&
524 if (LastInst && !SecondLastInst) {
525 if (LastOpcode == Hexagon::J2_jump) {
535 if (LastOpcodeHasJMP_c) {
550 <<
" with one jump\n";);
557 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
568 if (SecLastOpcodeHasNVJump &&
570 (LastOpcode == Hexagon::J2_jump)) {
581 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
585 I->eraseFromParent();
590 if (
isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
598 <<
" with two jumps";);
604 int *BytesRemoved)
const {
605 assert(!BytesRemoved &&
"code size not handled");
612 if (
I->isDebugInstr())
617 if (Count && (
I->getOpcode() == Hexagon::J2_jump))
631 int *BytesAdded)
const {
632 unsigned BOpc = Hexagon::J2_jump;
633 unsigned BccOpc = Hexagon::J2_jumpt;
635 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
636 assert(!BytesAdded &&
"code size not handled");
641 if (!
Cond.empty() &&
Cond[0].isImm())
642 BccOpc =
Cond[0].getImm();
662 int EndLoopOp =
Cond[0].getImm();
669 assert(
Loop !=
nullptr &&
"Inserting an ENDLOOP without a LOOP");
670 Loop->getOperand(0).setMBB(TBB);
674 assert((
Cond.size() == 3) &&
"Only supporting rr/ri version of nvjump");
691 assert((
Cond.size() == 2) &&
"Malformed cond vector");
699 "Cond. cannot be empty when multiple branchings are required");
701 "NV-jump cannot be inserted with another branch");
704 int EndLoopOp =
Cond[0].getImm();
711 assert(
Loop !=
nullptr &&
"Inserting an ENDLOOP without a LOOP");
712 Loop->getOperand(0).setMBB(TBB);
741 TripCount =
Loop->getOpcode() == Hexagon::J2_loop0r
743 :
Loop->getOperand(1).getImm();
745 LoopCount =
Loop->getOperand(1).getReg();
748 bool shouldIgnoreForPipelining(
const MachineInstr *
MI)
const override {
750 return MI == EndLoop;
756 if (TripCount == -1) {
760 TII->get(Hexagon::C2_cmpgtui), Done)
768 return TripCount > TC;
776 void adjustTripCount(
int TripCountAdjust)
override {
779 if (
Loop->getOpcode() == Hexagon::J2_loop0i ||
780 Loop->getOpcode() == Hexagon::J2_loop1i) {
781 int64_t TripCount =
Loop->getOperand(1).getImm() + TripCountAdjust;
782 assert(TripCount > 0 &&
"Can't create an empty or negative loop!");
783 Loop->getOperand(1).setImm(TripCount);
792 TII->get(Hexagon::A2_addi), NewLoopCount)
795 Loop->getOperand(1).setReg(NewLoopCount);
798 void disposed()
override {
Loop->eraseFromParent(); }
802 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
810 LoopBB,
I->getOpcode(),
I->getOperand(0).getMBB(), VisitedBBs);
812 return std::make_unique<HexagonPipelinerLoopInfo>(LoopInst, &*
I);
818 unsigned NumCycles,
unsigned ExtraPredCycles,
832 return NumInstrs <= 4;
840 for (
auto I =
B.begin();
I !=
E; ++
I) {
850 for (
auto I =
B.rbegin();
I !=
E; ++
I)
861 if (Hexagon::IntRegsRegClass.
contains(SrcReg, DestReg)) {
863 .
addReg(SrcReg, KillFlag);
866 if (Hexagon::DoubleRegsRegClass.
contains(SrcReg, DestReg)) {
868 .
addReg(SrcReg, KillFlag);
871 if (Hexagon::PredRegsRegClass.
contains(SrcReg, DestReg)) {
877 if (Hexagon::CtrRegsRegClass.
contains(DestReg) &&
878 Hexagon::IntRegsRegClass.
contains(SrcReg)) {
880 .
addReg(SrcReg, KillFlag);
883 if (Hexagon::IntRegsRegClass.
contains(DestReg) &&
884 Hexagon::CtrRegsRegClass.
contains(SrcReg)) {
886 .
addReg(SrcReg, KillFlag);
889 if (Hexagon::ModRegsRegClass.
contains(DestReg) &&
890 Hexagon::IntRegsRegClass.
contains(SrcReg)) {
892 .
addReg(SrcReg, KillFlag);
895 if (Hexagon::PredRegsRegClass.
contains(SrcReg) &&
896 Hexagon::IntRegsRegClass.
contains(DestReg)) {
898 .
addReg(SrcReg, KillFlag);
901 if (Hexagon::IntRegsRegClass.
contains(SrcReg) &&
902 Hexagon::PredRegsRegClass.
contains(DestReg)) {
904 .
addReg(SrcReg, KillFlag);
907 if (Hexagon::PredRegsRegClass.
contains(SrcReg) &&
908 Hexagon::IntRegsRegClass.
contains(DestReg)) {
910 .
addReg(SrcReg, KillFlag);
913 if (Hexagon::HvxVRRegClass.
contains(SrcReg, DestReg)) {
915 addReg(SrcReg, KillFlag);
918 if (Hexagon::HvxWRRegClass.
contains(SrcReg, DestReg)) {
921 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
922 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
926 .
addReg(SrcHi, KillFlag | UndefHi)
927 .
addReg(SrcLo, KillFlag | UndefLo);
930 if (Hexagon::HvxQRRegClass.
contains(SrcReg, DestReg)) {
933 .
addReg(SrcReg, KillFlag);
936 if (Hexagon::HvxQRRegClass.
contains(SrcReg) &&
937 Hexagon::HvxVRRegClass.
contains(DestReg)) {
941 if (Hexagon::HvxQRRegClass.
contains(DestReg) &&
942 Hexagon::HvxVRRegClass.
contains(SrcReg)) {
967 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
971 }
else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
975 }
else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
979 }
else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
983 }
else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
987 }
else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
991 }
else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1012 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
1015 }
else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
1018 }
else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
1021 }
else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
1024 }
else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
1027 }
else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
1030 }
else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1051 unsigned Opc =
MI.getOpcode();
1053 auto RealCirc = [&](
unsigned Opc,
bool HasImm,
unsigned MxOp) {
1055 unsigned CSx = (Mx ==
Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1057 .
add(
MI.getOperand((HasImm ? 5 : 4)));
1061 MIB.
add(
MI.getOperand(4));
1068 if (
MI.memoperands().empty())
1071 return MMO->getAlign() >= NeedAlign;
1076 case Hexagon::PS_call_instrprof_custom: {
1077 auto Op0 =
MI.getOperand(0);
1079 "First operand must be a global containing handler name.");
1083 StringRef NameStr = Arr->isCString() ? Arr->getAsCString() : Arr->getAsString();
1109 MIB.addExternalSymbol(cstr);
1113 case TargetOpcode::COPY: {
1124 case Hexagon::PS_aligna:
1127 .
addImm(-
MI.getOperand(1).getImm());
1130 case Hexagon::V6_vassignp: {
1133 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1134 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1145 case Hexagon::V6_lo: {
1148 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1154 case Hexagon::V6_hi: {
1157 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1163 case Hexagon::PS_vloadrv_ai: {
1167 int Offset =
MI.getOperand(2).getImm();
1168 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1169 unsigned NewOpc = UseAligned(
MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1170 : Hexagon::V6_vL32Ub_ai;
1178 case Hexagon::PS_vloadrw_ai: {
1182 int Offset =
MI.getOperand(2).getImm();
1183 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1184 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1185 unsigned NewOpc = UseAligned(
MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1186 : Hexagon::V6_vL32Ub_ai;
1188 HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1193 HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1195 .
addImm(Offset + VecOffset)
1200 case Hexagon::PS_vstorerv_ai: {
1205 int Offset =
MI.getOperand(1).getImm();
1206 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1207 unsigned NewOpc = UseAligned(
MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1208 : Hexagon::V6_vS32Ub_ai;
1217 case Hexagon::PS_vstorerw_ai: {
1221 int Offset =
MI.getOperand(1).getImm();
1222 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1223 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1224 unsigned NewOpc = UseAligned(
MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1225 : Hexagon::V6_vS32Ub_ai;
1229 .
addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo))
1233 .
addImm(Offset + VecOffset)
1234 .
addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi))
1239 case Hexagon::PS_true: {
1247 case Hexagon::PS_false: {
1255 case Hexagon::PS_qtrue: {
1262 case Hexagon::PS_qfalse: {
1269 case Hexagon::PS_vdd0: {
1277 case Hexagon::PS_vmulw: {
1280 Register Src1Reg =
MI.getOperand(1).getReg();
1281 Register Src2Reg =
MI.getOperand(2).getReg();
1282 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1283 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1284 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1285 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1287 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1291 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1301 case Hexagon::PS_vmulw_acc: {
1304 Register Src1Reg =
MI.getOperand(1).getReg();
1305 Register Src2Reg =
MI.getOperand(2).getReg();
1306 Register Src3Reg =
MI.getOperand(3).getReg();
1307 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1308 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1309 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1310 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1311 Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1312 Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1314 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1319 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1332 case Hexagon::PS_pselect: {
1347 .
addReg(Pu, (Rd == Rt) ? K1 : 0)
1356 case Hexagon::PS_vselect: {
1389 case Hexagon::PS_wselect: {
1429 case Hexagon::PS_crash: {
1445 void printCustom(
raw_ostream &OS)
const override {
1446 OS <<
"MisalignedCrash";
1450 static const CrashPseudoSourceValue CrashPSV(MF.
getTarget());
1462 case Hexagon::PS_tailcall_i:
1463 MI.setDesc(
get(Hexagon::J2_jump));
1465 case Hexagon::PS_tailcall_r:
1466 case Hexagon::PS_jmpret:
1467 MI.setDesc(
get(Hexagon::J2_jumpr));
1469 case Hexagon::PS_jmprett:
1470 MI.setDesc(
get(Hexagon::J2_jumprt));
1472 case Hexagon::PS_jmpretf:
1473 MI.setDesc(
get(Hexagon::J2_jumprf));
1475 case Hexagon::PS_jmprettnewpt:
1476 MI.setDesc(
get(Hexagon::J2_jumprtnewpt));
1478 case Hexagon::PS_jmpretfnewpt:
1479 MI.setDesc(
get(Hexagon::J2_jumprfnewpt));
1481 case Hexagon::PS_jmprettnew:
1482 MI.setDesc(
get(Hexagon::J2_jumprtnew));
1484 case Hexagon::PS_jmpretfnew:
1485 MI.setDesc(
get(Hexagon::J2_jumprfnew));
1488 case Hexagon::PS_loadrub_pci:
1489 return RealCirc(Hexagon::L2_loadrub_pci,
true, 4);
1490 case Hexagon::PS_loadrb_pci:
1491 return RealCirc(Hexagon::L2_loadrb_pci,
true, 4);
1492 case Hexagon::PS_loadruh_pci:
1493 return RealCirc(Hexagon::L2_loadruh_pci,
true, 4);
1494 case Hexagon::PS_loadrh_pci:
1495 return RealCirc(Hexagon::L2_loadrh_pci,
true, 4);
1496 case Hexagon::PS_loadri_pci:
1497 return RealCirc(Hexagon::L2_loadri_pci,
true, 4);
1498 case Hexagon::PS_loadrd_pci:
1499 return RealCirc(Hexagon::L2_loadrd_pci,
true, 4);
1500 case Hexagon::PS_loadrub_pcr:
1501 return RealCirc(Hexagon::L2_loadrub_pcr,
false, 3);
1502 case Hexagon::PS_loadrb_pcr:
1503 return RealCirc(Hexagon::L2_loadrb_pcr,
false, 3);
1504 case Hexagon::PS_loadruh_pcr:
1505 return RealCirc(Hexagon::L2_loadruh_pcr,
false, 3);
1506 case Hexagon::PS_loadrh_pcr:
1507 return RealCirc(Hexagon::L2_loadrh_pcr,
false, 3);
1508 case Hexagon::PS_loadri_pcr:
1509 return RealCirc(Hexagon::L2_loadri_pcr,
false, 3);
1510 case Hexagon::PS_loadrd_pcr:
1511 return RealCirc(Hexagon::L2_loadrd_pcr,
false, 3);
1512 case Hexagon::PS_storerb_pci:
1513 return RealCirc(Hexagon::S2_storerb_pci,
true, 3);
1514 case Hexagon::PS_storerh_pci:
1515 return RealCirc(Hexagon::S2_storerh_pci,
true, 3);
1516 case Hexagon::PS_storerf_pci:
1517 return RealCirc(Hexagon::S2_storerf_pci,
true, 3);
1518 case Hexagon::PS_storeri_pci:
1519 return RealCirc(Hexagon::S2_storeri_pci,
true, 3);
1520 case Hexagon::PS_storerd_pci:
1521 return RealCirc(Hexagon::S2_storerd_pci,
true, 3);
1522 case Hexagon::PS_storerb_pcr:
1523 return RealCirc(Hexagon::S2_storerb_pcr,
false, 2);
1524 case Hexagon::PS_storerh_pcr:
1525 return RealCirc(Hexagon::S2_storerh_pcr,
false, 2);
1526 case Hexagon::PS_storerf_pcr:
1527 return RealCirc(Hexagon::S2_storerf_pcr,
false, 2);
1528 case Hexagon::PS_storeri_pcr:
1529 return RealCirc(Hexagon::S2_storeri_pcr,
false, 2);
1530 case Hexagon::PS_storerd_pcr:
1531 return RealCirc(Hexagon::S2_storerd_pcr,
false, 2);
1541 unsigned Opc =
MI.getOpcode();
1545 case Hexagon::V6_vgathermh_pseudo:
1547 .
add(
MI.getOperand(2))
1548 .
add(
MI.getOperand(3))
1549 .
add(
MI.getOperand(4));
1551 .
add(
MI.getOperand(0))
1555 return First.getInstrIterator();
1557 case Hexagon::V6_vgathermw_pseudo:
1559 .
add(
MI.getOperand(2))
1560 .
add(
MI.getOperand(3))
1561 .
add(
MI.getOperand(4));
1563 .
add(
MI.getOperand(0))
1567 return First.getInstrIterator();
1569 case Hexagon::V6_vgathermhw_pseudo:
1571 .
add(
MI.getOperand(2))
1572 .
add(
MI.getOperand(3))
1573 .
add(
MI.getOperand(4));
1575 .
add(
MI.getOperand(0))
1579 return First.getInstrIterator();
1581 case Hexagon::V6_vgathermhq_pseudo:
1583 .
add(
MI.getOperand(2))
1584 .
add(
MI.getOperand(3))
1585 .
add(
MI.getOperand(4))
1586 .
add(
MI.getOperand(5));
1588 .
add(
MI.getOperand(0))
1592 return First.getInstrIterator();
1594 case Hexagon::V6_vgathermwq_pseudo:
1596 .
add(
MI.getOperand(2))
1597 .
add(
MI.getOperand(3))
1598 .
add(
MI.getOperand(4))
1599 .
add(
MI.getOperand(5));
1601 .
add(
MI.getOperand(0))
1605 return First.getInstrIterator();
1607 case Hexagon::V6_vgathermhwq_pseudo:
1609 .
add(
MI.getOperand(2))
1610 .
add(
MI.getOperand(3))
1611 .
add(
MI.getOperand(4))
1612 .
add(
MI.getOperand(5));
1614 .
add(
MI.getOperand(0))
1618 return First.getInstrIterator();
1621 return MI.getIterator();
1630 assert(
Cond[0].
isImm() &&
"First entry in the cond vector not imm-val");
1631 unsigned opcode =
Cond[0].getImm();
1637 Cond[0].setImm(NewOpcode);
1671 int Opc =
MI.getOpcode();
1684 unsigned NOp = 0, NumOps =
MI.getNumOperands();
1685 while (NOp < NumOps) {
1687 if (!
Op.isReg() || !
Op.isDef() ||
Op.isImplicit())
1693 unsigned PredReg, PredRegPos, PredRegFlags;
1694 bool GotPredReg =
getPredReg(
Cond, PredReg, PredRegPos, PredRegFlags);
1697 T.addReg(PredReg, PredRegFlags);
1698 while (NOp < NumOps)
1699 T.add(
MI.getOperand(NOp++));
1701 MI.setDesc(
get(PredOpc));
1702 while (
unsigned n =
MI.getNumOperands())
1703 MI.removeOperand(
n-1);
1704 for (
unsigned i = 0,
n =
T->getNumOperands();
i <
n; ++
i)
1705 MI.addOperand(
T->getOperand(
i));
1722 std::vector<MachineOperand> &Pred,
1723 bool SkipDead)
const {
1731 if (RC == &Hexagon::PredRegsRegClass) {
1736 }
else if (MO.isRegMask()) {
1737 for (
unsigned PR : Hexagon::PredRegsRegClass) {
1738 if (!
MI.modifiesRegister(PR, &HRI))
1749 if (!
MI.getDesc().isPredicable())
1759 switch (
MI.getOpcode()) {
1760 case Hexagon::V6_vL32b_ai:
1761 case Hexagon::V6_vL32b_pi:
1762 case Hexagon::V6_vL32b_ppu:
1763 case Hexagon::V6_vL32b_cur_ai:
1764 case Hexagon::V6_vL32b_cur_pi:
1765 case Hexagon::V6_vL32b_cur_ppu:
1766 case Hexagon::V6_vL32b_nt_ai:
1767 case Hexagon::V6_vL32b_nt_pi:
1768 case Hexagon::V6_vL32b_nt_ppu:
1769 case Hexagon::V6_vL32b_tmp_ai:
1770 case Hexagon::V6_vL32b_tmp_pi:
1771 case Hexagon::V6_vL32b_tmp_ppu:
1772 case Hexagon::V6_vL32b_nt_cur_ai:
1773 case Hexagon::V6_vL32b_nt_cur_pi:
1774 case Hexagon::V6_vL32b_nt_cur_ppu:
1775 case Hexagon::V6_vL32b_nt_tmp_ai:
1776 case Hexagon::V6_vL32b_nt_tmp_pi:
1777 case Hexagon::V6_vL32b_nt_tmp_ppu:
1793 if (
MI.isDebugInstr())
1809 if (
MI.getDesc().isTerminator() ||
MI.isPosition())
1837 bool atInsnStart =
true;
1838 unsigned Length = 0;
1840 for (; *Str; ++Str) {
1844 if (atInsnStart && !isSpace(
static_cast<unsigned char>(*Str))) {
1845 Length += MaxInstLength;
1846 atInsnStart =
false;
1850 atInsnStart =
false;
1855 Length += AStr.
count(Occ)*4;
1873 int64_t &
Value)
const {
1874 unsigned Opc =
MI.getOpcode();
1878 case Hexagon::C2_cmpeq:
1879 case Hexagon::C2_cmpeqp:
1880 case Hexagon::C2_cmpgt:
1881 case Hexagon::C2_cmpgtp:
1882 case Hexagon::C2_cmpgtu:
1883 case Hexagon::C2_cmpgtup:
1884 case Hexagon::C4_cmpneq:
1885 case Hexagon::C4_cmplte:
1886 case Hexagon::C4_cmplteu:
1887 case Hexagon::C2_cmpeqi:
1888 case Hexagon::C2_cmpgti:
1889 case Hexagon::C2_cmpgtui:
1890 case Hexagon::C4_cmpneqi:
1891 case Hexagon::C4_cmplteui:
1892 case Hexagon::C4_cmpltei:
1893 SrcReg =
MI.getOperand(1).getReg();
1896 case Hexagon::A4_cmpbeq:
1897 case Hexagon::A4_cmpbgt:
1898 case Hexagon::A4_cmpbgtu:
1899 case Hexagon::A4_cmpbeqi:
1900 case Hexagon::A4_cmpbgti:
1901 case Hexagon::A4_cmpbgtui:
1902 SrcReg =
MI.getOperand(1).getReg();
1905 case Hexagon::A4_cmpheq:
1906 case Hexagon::A4_cmphgt:
1907 case Hexagon::A4_cmphgtu:
1908 case Hexagon::A4_cmpheqi:
1909 case Hexagon::A4_cmphgti:
1910 case Hexagon::A4_cmphgtui:
1911 SrcReg =
MI.getOperand(1).getReg();
1918 case Hexagon::C2_cmpeq:
1919 case Hexagon::C2_cmpeqp:
1920 case Hexagon::C2_cmpgt:
1921 case Hexagon::C2_cmpgtp:
1922 case Hexagon::C2_cmpgtu:
1923 case Hexagon::C2_cmpgtup:
1924 case Hexagon::A4_cmpbeq:
1925 case Hexagon::A4_cmpbgt:
1926 case Hexagon::A4_cmpbgtu:
1927 case Hexagon::A4_cmpheq:
1928 case Hexagon::A4_cmphgt:
1929 case Hexagon::A4_cmphgtu:
1930 case Hexagon::C4_cmpneq:
1931 case Hexagon::C4_cmplte:
1932 case Hexagon::C4_cmplteu:
1933 SrcReg2 =
MI.getOperand(2).getReg();
1937 case Hexagon::C2_cmpeqi:
1938 case Hexagon::C2_cmpgtui:
1939 case Hexagon::C2_cmpgti:
1940 case Hexagon::C4_cmpneqi:
1941 case Hexagon::C4_cmplteui:
1942 case Hexagon::C4_cmpltei:
1943 case Hexagon::A4_cmpbeqi:
1944 case Hexagon::A4_cmpbgti:
1945 case Hexagon::A4_cmpbgtui:
1946 case Hexagon::A4_cmpheqi:
1947 case Hexagon::A4_cmphgti:
1948 case Hexagon::A4_cmphgtui: {
1953 Value =
MI.getOperand(2).getImm();
1963 unsigned *PredCost)
const {
1989 unsigned BasePosA, OffsetPosA;
1997 unsigned BasePosB, OffsetPosB;
2004 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
2022 if (OffsetA > OffsetB) {
2024 return SizeB <= OffDiff;
2026 if (OffsetA < OffsetB) {
2028 return SizeA <= OffDiff;
2038 unsigned BasePos = 0, OffsetPos = 0;
2042 if (OffsetOp.
isImm()) {
2046 }
else if (
MI.getOpcode() == Hexagon::A2_addi) {
2048 if (AddOp.
isImm()) {
2057 std::pair<unsigned, unsigned>
2065 using namespace HexagonII;
2067 static const std::pair<unsigned, const char*> Flags[] = {
2075 {
MO_IE,
"hexagon-ie"},
2084 using namespace HexagonII;
2086 static const std::pair<unsigned, const char*> Flags[] = {
2096 TRC = &Hexagon::PredRegsRegClass;
2098 TRC = &Hexagon::IntRegsRegClass;
2100 TRC = &Hexagon::DoubleRegsRegClass;
2124 !
MI.getDesc().mayStore() &&
2125 MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2126 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2171 assert(MO.
isImm() &&
"Extendable operand must be Immediate type");
2175 int ImmValue = MO.
getImm();
2177 return (ImmValue < MinValue || ImmValue > MaxValue);
2181 switch (
MI.getOpcode()) {
2182 case Hexagon::L4_return:
2183 case Hexagon::L4_return_t:
2184 case Hexagon::L4_return_f:
2185 case Hexagon::L4_return_tnew_pnt:
2186 case Hexagon::L4_return_fnew_pnt:
2187 case Hexagon::L4_return_tnew_pt:
2188 case Hexagon::L4_return_fnew_pt:
2209 for (
auto &RegA : DefsA)
2210 for (
auto &RegB : UsesB) {
2217 if (RegB == *SubRegs)
2222 if (RegA == *SubRegs)
2231 switch (
MI.getOpcode()) {
2232 case Hexagon::V6_vL32b_cur_pi:
2233 case Hexagon::V6_vL32b_cur_ai:
2257 if (
MI.mayLoadOrStore() ||
MI.isCompare())
2261 unsigned SchedClass =
MI.getDesc().getSchedClass();
2266 return (Opcode == Hexagon::ENDLOOP0 ||
2267 Opcode == Hexagon::ENDLOOP1);
2292 switch (
MI.getOpcode()) {
2294 case Hexagon::PS_fi:
2295 case Hexagon::PS_fia:
2320 unsigned Opcode =
MI.getOpcode();
2330 if (!
I.mayLoad() && !
I.mayStore())
2336 switch (
MI.getOpcode()) {
2337 case Hexagon::J2_callr:
2338 case Hexagon::J2_callrf:
2339 case Hexagon::J2_callrt:
2340 case Hexagon::PS_call_nr:
2347 switch (
MI.getOpcode()) {
2348 case Hexagon::L4_return:
2349 case Hexagon::L4_return_t:
2350 case Hexagon::L4_return_f:
2351 case Hexagon::L4_return_fnew_pnt:
2352 case Hexagon::L4_return_fnew_pt:
2353 case Hexagon::L4_return_tnew_pnt:
2354 case Hexagon::L4_return_tnew_pt:
2361 switch (
MI.getOpcode()) {
2362 case Hexagon::J2_jumpr:
2363 case Hexagon::J2_jumprt:
2364 case Hexagon::J2_jumprf:
2365 case Hexagon::J2_jumprtnewpt:
2366 case Hexagon::J2_jumprfnewpt:
2367 case Hexagon::J2_jumprtnew:
2368 case Hexagon::J2_jumprfnew:
2379 unsigned offset)
const {
2383 return isInt<11>(offset);
2385 switch (
MI.getOpcode()) {
2389 case Hexagon::J2_jump:
2390 case Hexagon::J2_call:
2391 case Hexagon::PS_call_nr:
2392 return isInt<24>(offset);
2393 case Hexagon::J2_jumpt:
2394 case Hexagon::J2_jumpf:
2395 case Hexagon::J2_jumptnew:
2396 case Hexagon::J2_jumptnewpt:
2397 case Hexagon::J2_jumpfnew:
2398 case Hexagon::J2_jumpfnewpt:
2399 case Hexagon::J2_callt:
2400 case Hexagon::J2_callf:
2401 return isInt<17>(offset);
2402 case Hexagon::J2_loop0i:
2403 case Hexagon::J2_loop0iext:
2404 case Hexagon::J2_loop0r:
2405 case Hexagon::J2_loop0rext:
2406 case Hexagon::J2_loop1i:
2407 case Hexagon::J2_loop1iext:
2408 case Hexagon::J2_loop1r:
2409 case Hexagon::J2_loop1rext:
2410 return isInt<9>(offset);
2412 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2413 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2414 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2415 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2416 return isInt<11>(offset);
2430 if (isLate && isEarly) {
2439 switch (
MI.getOpcode()) {
2440 case TargetOpcode::EXTRACT_SUBREG:
2441 case TargetOpcode::INSERT_SUBREG:
2442 case TargetOpcode::SUBREG_TO_REG:
2443 case TargetOpcode::REG_SEQUENCE:
2444 case TargetOpcode::IMPLICIT_DEF:
2445 case TargetOpcode::COPY:
2447 case TargetOpcode::PHI:
2453 unsigned SchedClass =
MI.getDesc().getSchedClass();
2454 return !
is_TC1(SchedClass);
2464 unsigned Opcode =
MI.getOpcode();
2465 return Opcode == Hexagon::J2_loop0i ||
2466 Opcode == Hexagon::J2_loop0r ||
2467 Opcode == Hexagon::J2_loop0iext ||
2468 Opcode == Hexagon::J2_loop0rext ||
2469 Opcode == Hexagon::J2_loop1i ||
2470 Opcode == Hexagon::J2_loop1r ||
2471 Opcode == Hexagon::J2_loop1iext ||
2472 Opcode == Hexagon::J2_loop1rext;
2476 switch (
MI.getOpcode()) {
2477 default:
return false;
2478 case Hexagon::L4_iadd_memopw_io:
2479 case Hexagon::L4_isub_memopw_io:
2480 case Hexagon::L4_add_memopw_io:
2481 case Hexagon::L4_sub_memopw_io:
2482 case Hexagon::L4_and_memopw_io:
2483 case Hexagon::L4_or_memopw_io:
2484 case Hexagon::L4_iadd_memoph_io:
2485 case Hexagon::L4_isub_memoph_io:
2486 case Hexagon::L4_add_memoph_io:
2487 case Hexagon::L4_sub_memoph_io:
2488 case Hexagon::L4_and_memoph_io:
2489 case Hexagon::L4_or_memoph_io:
2490 case Hexagon::L4_iadd_memopb_io:
2491 case Hexagon::L4_isub_memopb_io:
2492 case Hexagon::L4_add_memopb_io:
2493 case Hexagon::L4_sub_memopb_io:
2494 case Hexagon::L4_and_memopb_io:
2495 case Hexagon::L4_or_memopb_io:
2496 case Hexagon::L4_ior_memopb_io:
2497 case Hexagon::L4_ior_memoph_io:
2498 case Hexagon::L4_ior_memopw_io:
2499 case Hexagon::L4_iand_memopb_io:
2500 case Hexagon::L4_iand_memoph_io:
2501 case Hexagon::L4_iand_memopw_io:
2541 unsigned OperandNum)
const {
2591 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2592 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2593 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2594 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2598 switch (
MI.getOpcode()) {
2600 case Hexagon::L2_loadrb_io:
2601 case Hexagon::L4_loadrb_ur:
2602 case Hexagon::L4_loadrb_ap:
2603 case Hexagon::L2_loadrb_pr:
2604 case Hexagon::L2_loadrb_pbr:
2605 case Hexagon::L2_loadrb_pi:
2606 case Hexagon::L2_loadrb_pci:
2607 case Hexagon::L2_loadrb_pcr:
2608 case Hexagon::L2_loadbsw2_io:
2609 case Hexagon::L4_loadbsw2_ur:
2610 case Hexagon::L4_loadbsw2_ap:
2611 case Hexagon::L2_loadbsw2_pr:
2612 case Hexagon::L2_loadbsw2_pbr:
2613 case Hexagon::L2_loadbsw2_pi:
2614 case Hexagon::L2_loadbsw2_pci:
2615 case Hexagon::L2_loadbsw2_pcr:
2616 case Hexagon::L2_loadbsw4_io:
2617 case Hexagon::L4_loadbsw4_ur:
2618 case Hexagon::L4_loadbsw4_ap:
2619 case Hexagon::L2_loadbsw4_pr:
2620 case Hexagon::L2_loadbsw4_pbr:
2621 case Hexagon::L2_loadbsw4_pi:
2622 case Hexagon::L2_loadbsw4_pci:
2623 case Hexagon::L2_loadbsw4_pcr:
2624 case Hexagon::L4_loadrb_rr:
2625 case Hexagon::L2_ploadrbt_io:
2626 case Hexagon::L2_ploadrbt_pi:
2627 case Hexagon::L2_ploadrbf_io:
2628 case Hexagon::L2_ploadrbf_pi:
2629 case Hexagon::L2_ploadrbtnew_io:
2630 case Hexagon::L2_ploadrbfnew_io:
2631 case Hexagon::L4_ploadrbt_rr:
2632 case Hexagon::L4_ploadrbf_rr:
2633 case Hexagon::L4_ploadrbtnew_rr:
2634 case Hexagon::L4_ploadrbfnew_rr:
2635 case Hexagon::L2_ploadrbtnew_pi:
2636 case Hexagon::L2_ploadrbfnew_pi:
2637 case Hexagon::L4_ploadrbt_abs:
2638 case Hexagon::L4_ploadrbf_abs:
2639 case Hexagon::L4_ploadrbtnew_abs:
2640 case Hexagon::L4_ploadrbfnew_abs:
2641 case Hexagon::L2_loadrbgp:
2643 case Hexagon::L2_loadrh_io:
2644 case Hexagon::L4_loadrh_ur:
2645 case Hexagon::L4_loadrh_ap:
2646 case Hexagon::L2_loadrh_pr:
2647 case Hexagon::L2_loadrh_pbr:
2648 case Hexagon::L2_loadrh_pi:
2649 case Hexagon::L2_loadrh_pci:
2650 case Hexagon::L2_loadrh_pcr:
2651 case Hexagon::L4_loadrh_rr:
2652 case Hexagon::L2_ploadrht_io:
2653 case Hexagon::L2_ploadrht_pi:
2654 case Hexagon::L2_ploadrhf_io:
2655 case Hexagon::L2_ploadrhf_pi:
2656 case Hexagon::L2_ploadrhtnew_io:
2657 case Hexagon::L2_ploadrhfnew_io:
2658 case Hexagon::L4_ploadrht_rr:
2659 case Hexagon::L4_ploadrhf_rr:
2660 case Hexagon::L4_ploadrhtnew_rr:
2661 case Hexagon::L4_ploadrhfnew_rr:
2662 case Hexagon::L2_ploadrhtnew_pi:
2663 case Hexagon::L2_ploadrhfnew_pi:
2664 case Hexagon::L4_ploadrht_abs:
2665 case Hexagon::L4_ploadrhf_abs:
2666 case Hexagon::L4_ploadrhtnew_abs:
2667 case Hexagon::L4_ploadrhfnew_abs:
2668 case Hexagon::L2_loadrhgp:
2681 switch (
MI.getOpcode()) {
2682 case Hexagon::STriw_pred:
2683 case Hexagon::LDriw_pred:
2694 for (
auto &
Op :
MI.operands())
2695 if (
Op.isGlobal() ||
Op.isSymbol())
2702 unsigned SchedClass =
MI.getDesc().getSchedClass();
2703 return is_TC1(SchedClass);
2707 unsigned SchedClass =
MI.getDesc().getSchedClass();
2708 return is_TC2(SchedClass);
2712 unsigned SchedClass =
MI.getDesc().getSchedClass();
2717 unsigned SchedClass =
MI.getDesc().getSchedClass();
2728 for (
int I = 0;
I <
N;
I++)
2733 if (MI2.
getOpcode() == Hexagon::V6_vS32b_pi)
2748 if (Offset % Size != 0)
2750 int Count = Offset / Size;
2765 return isInt<4>(Count);
2775 return isInt<3>(Count);
2794 case Hexagon::PS_vstorerq_ai:
2795 case Hexagon::PS_vstorerv_ai:
2796 case Hexagon::PS_vstorerw_ai:
2797 case Hexagon::PS_vstorerw_nt_ai:
2798 case Hexagon::PS_vloadrq_ai:
2799 case Hexagon::PS_vloadrv_ai:
2800 case Hexagon::PS_vloadrw_ai:
2801 case Hexagon::PS_vloadrw_nt_ai:
2802 case Hexagon::V6_vL32b_ai:
2803 case Hexagon::V6_vS32b_ai:
2804 case Hexagon::V6_vS32b_qpred_ai:
2805 case Hexagon::V6_vS32b_nqpred_ai:
2806 case Hexagon::V6_vL32b_nt_ai:
2807 case Hexagon::V6_vS32b_nt_ai:
2808 case Hexagon::V6_vL32Ub_ai:
2809 case Hexagon::V6_vS32Ub_ai:
2810 case Hexagon::V6_vgathermh_pseudo:
2811 case Hexagon::V6_vgathermw_pseudo:
2812 case Hexagon::V6_vgathermhw_pseudo:
2813 case Hexagon::V6_vgathermhq_pseudo:
2814 case Hexagon::V6_vgathermwq_pseudo:
2815 case Hexagon::V6_vgathermhwq_pseudo: {
2818 if (Offset & (VectorSize-1))
2820 return isInt<4>(Offset >>
Log2_32(VectorSize));
2823 case Hexagon::J2_loop0i:
2824 case Hexagon::J2_loop1i:
2825 return isUInt<10>(Offset);
2827 case Hexagon::S4_storeirb_io:
2828 case Hexagon::S4_storeirbt_io:
2829 case Hexagon::S4_storeirbf_io:
2830 return isUInt<6>(Offset);
2832 case Hexagon::S4_storeirh_io:
2833 case Hexagon::S4_storeirht_io:
2834 case Hexagon::S4_storeirhf_io:
2835 return isShiftedUInt<6,1>(Offset);
2837 case Hexagon::S4_storeiri_io:
2838 case Hexagon::S4_storeirit_io:
2839 case Hexagon::S4_storeirif_io:
2840 return isShiftedUInt<6,2>(Offset);
2842 case Hexagon::A4_cmpbeqi:
2844 case Hexagon::A4_cmpbgti:
2852 case Hexagon::L2_loadri_io:
2853 case Hexagon::S2_storeri_io:
2857 case Hexagon::L2_loadrd_io:
2858 case Hexagon::S2_storerd_io:
2862 case Hexagon::L2_loadrh_io:
2863 case Hexagon::L2_loadruh_io:
2864 case Hexagon::S2_storerh_io:
2865 case Hexagon::S2_storerf_io:
2869 case Hexagon::L2_loadrb_io:
2870 case Hexagon::L2_loadrub_io:
2871 case Hexagon::S2_storerb_io:
2875 case Hexagon::A2_addi:
2879 case Hexagon::L4_iadd_memopw_io:
2880 case Hexagon::L4_isub_memopw_io:
2881 case Hexagon::L4_add_memopw_io:
2882 case Hexagon::L4_sub_memopw_io:
2883 case Hexagon::L4_iand_memopw_io:
2884 case Hexagon::L4_ior_memopw_io:
2885 case Hexagon::L4_and_memopw_io:
2886 case Hexagon::L4_or_memopw_io:
2887 return (0 <= Offset && Offset <= 255);
2889 case Hexagon::L4_iadd_memoph_io:
2890 case Hexagon::L4_isub_memoph_io:
2891 case Hexagon::L4_add_memoph_io:
2892 case Hexagon::L4_sub_memoph_io:
2893 case Hexagon::L4_iand_memoph_io:
2894 case Hexagon::L4_ior_memoph_io:
2895 case Hexagon::L4_and_memoph_io:
2896 case Hexagon::L4_or_memoph_io:
2897 return (0 <= Offset && Offset <= 127);
2899 case Hexagon::L4_iadd_memopb_io:
2900 case Hexagon::L4_isub_memopb_io:
2901 case Hexagon::L4_add_memopb_io:
2902 case Hexagon::L4_sub_memopb_io:
2903 case Hexagon::L4_iand_memopb_io:
2904 case Hexagon::L4_ior_memopb_io:
2905 case Hexagon::L4_and_memopb_io:
2906 case Hexagon::L4_or_memopb_io:
2907 return (0 <= Offset && Offset <= 63);
2911 case Hexagon::STriw_pred:
2912 case Hexagon::LDriw_pred:
2913 case Hexagon::STriw_ctr:
2914 case Hexagon::LDriw_ctr:
2917 case Hexagon::PS_fi:
2918 case Hexagon::PS_fia:
2922 case Hexagon::L2_ploadrbt_io:
2923 case Hexagon::L2_ploadrbf_io:
2924 case Hexagon::L2_ploadrubt_io:
2925 case Hexagon::L2_ploadrubf_io:
2926 case Hexagon::S2_pstorerbt_io:
2927 case Hexagon::S2_pstorerbf_io:
2928 return isUInt<6>(Offset);
2930 case Hexagon::L2_ploadrht_io:
2931 case Hexagon::L2_ploadrhf_io:
2932 case Hexagon::L2_ploadruht_io:
2933 case Hexagon::L2_ploadruhf_io:
2934 case Hexagon::S2_pstorerht_io:
2935 case Hexagon::S2_pstorerhf_io:
2936 return isShiftedUInt<6,1>(Offset);
2938 case Hexagon::L2_ploadrit_io:
2939 case Hexagon::L2_ploadrif_io:
2940 case Hexagon::S2_pstorerit_io:
2941 case Hexagon::S2_pstorerif_io:
2942 return isShiftedUInt<6,2>(Offset);
2944 case Hexagon::L2_ploadrdt_io:
2945 case Hexagon::L2_ploadrdf_io:
2946 case Hexagon::S2_pstorerdt_io:
2947 case Hexagon::S2_pstorerdf_io:
2948 return isShiftedUInt<6,3>(Offset);
2950 case Hexagon::L2_loadbsw2_io:
2951 case Hexagon::L2_loadbzw2_io:
2952 return isShiftedInt<11,1>(Offset);
2954 case Hexagon::L2_loadbsw4_io:
2955 case Hexagon::L2_loadbzw4_io:
2956 return isShiftedInt<11,2>(Offset);
2959 dbgs() <<
"Failed Opcode is : " << Opcode <<
" (" <<
getName(Opcode)
2962 "Please define it in the above switch statement!");
2992 switch (
MI.getOpcode()) {
2994 case Hexagon::L2_loadrub_io:
2995 case Hexagon::L4_loadrub_ur:
2996 case Hexagon::L4_loadrub_ap:
2997 case Hexagon::L2_loadrub_pr:
2998 case Hexagon::L2_loadrub_pbr:
2999 case Hexagon::L2_loadrub_pi:
3000 case Hexagon::L2_loadrub_pci:
3001 case Hexagon::L2_loadrub_pcr:
3002 case Hexagon::L2_loadbzw2_io:
3003 case Hexagon::L4_loadbzw2_ur:
3004 case Hexagon::L4_loadbzw2_ap:
3005 case Hexagon::L2_loadbzw2_pr:
3006 case Hexagon::L2_loadbzw2_pbr:
3007 case Hexagon::L2_loadbzw2_pi:
3008 case Hexagon::L2_loadbzw2_pci:
3009 case Hexagon::L2_loadbzw2_pcr:
3010 case Hexagon::L2_loadbzw4_io:
3011 case Hexagon::L4_loadbzw4_ur:
3012 case Hexagon::L4_loadbzw4_ap:
3013 case Hexagon::L2_loadbzw4_pr:
3014 case Hexagon::L2_loadbzw4_pbr:
3015 case Hexagon::L2_loadbzw4_pi:
3016 case Hexagon::L2_loadbzw4_pci:
3017 case Hexagon::L2_loadbzw4_pcr:
3018 case Hexagon::L4_loadrub_rr:
3019 case Hexagon::L2_ploadrubt_io:
3020 case Hexagon::L2_ploadrubt_pi:
3021 case Hexagon::L2_ploadrubf_io:
3022 case Hexagon::L2_ploadrubf_pi:
3023 case Hexagon::L2_ploadrubtnew_io:
3024 case Hexagon::L2_ploadrubfnew_io:
3025 case Hexagon::L4_ploadrubt_rr:
3026 case Hexagon::L4_ploadrubf_rr:
3027 case Hexagon::L4_ploadrubtnew_rr:
3028 case Hexagon::L4_ploadrubfnew_rr:
3029 case Hexagon::L2_ploadrubtnew_pi:
3030 case Hexagon::L2_ploadrubfnew_pi:
3031 case Hexagon::L4_ploadrubt_abs:
3032 case Hexagon::L4_ploadrubf_abs:
3033 case Hexagon::L4_ploadrubtnew_abs:
3034 case Hexagon::L4_ploadrubfnew_abs:
3035 case Hexagon::L2_loadrubgp:
3037 case Hexagon::L2_loadruh_io:
3038 case Hexagon::L4_loadruh_ur:
3039 case Hexagon::L4_loadruh_ap:
3040 case Hexagon::L2_loadruh_pr:
3041 case Hexagon::L2_loadruh_pbr:
3042 case Hexagon::L2_loadruh_pi:
3043 case Hexagon::L2_loadruh_pci:
3044 case Hexagon::L2_loadruh_pcr:
3045 case Hexagon::L4_loadruh_rr:
3046 case Hexagon::L2_ploadruht_io:
3047 case Hexagon::L2_ploadruht_pi:
3048 case Hexagon::L2_ploadruhf_io:
3049 case Hexagon::L2_ploadruhf_pi:
3050 case Hexagon::L2_ploadruhtnew_io:
3051 case Hexagon::L2_ploadruhfnew_io:
3052 case Hexagon::L4_ploadruht_rr:
3053 case Hexagon::L4_ploadruhf_rr:
3054 case Hexagon::L4_ploadruhtnew_rr:
3055 case Hexagon::L4_ploadruhfnew_rr:
3056 case Hexagon::L2_ploadruhtnew_pi:
3057 case Hexagon::L2_ploadruhfnew_pi:
3058 case Hexagon::L4_ploadruht_abs:
3059 case Hexagon::L4_ploadruhf_abs:
3060 case Hexagon::L4_ploadruhtnew_abs:
3061 case Hexagon::L4_ploadruhfnew_abs:
3062 case Hexagon::L2_loadruhgp:
3081 int64_t &Offset,
bool &OffsetIsScalable,
unsigned &
Width,
3083 OffsetIsScalable =
false;
3085 if (!BaseOp || !BaseOp->
isReg())
3087 BaseOps.push_back(BaseOp);
3094 if (Second.
mayStore() &&
First.getOpcode() == Hexagon::S2_allocframe) {
3096 if (
Op.isReg() &&
Op.isUse() &&
Op.getReg() == Hexagon::R29)
3106 if (!Stored.
isReg())
3108 for (
unsigned i = 0,
e =
First.getNumOperands();
i <
e; ++
i) {
3110 if (
Op.isReg() &&
Op.isDef() &&
Op.getReg() == Stored.
getReg())
3119 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
3135 if (Hexagon::getRegForm(
MI.getOpcode()) >= 0)
3138 if (
MI.getDesc().mayLoad() ||
MI.getDesc().mayStore()) {
3145 NonExtOpcode = Hexagon::changeAddrMode_abs_io(
MI.getOpcode());
3151 NonExtOpcode = Hexagon::changeAddrMode_io_rr(
MI.getOpcode());
3154 NonExtOpcode = Hexagon::changeAddrMode_ur_rr(
MI.getOpcode());
3159 if (NonExtOpcode < 0)
3167 return Hexagon::getRealHWInstr(
MI.getOpcode(),
3168 Hexagon::InstrType_Pseudo) >= 0;
3225 if (!MII->isBundle())
3228 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3237 unsigned PredReg)
const {
3240 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3242 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3248 switch (
MI.getOpcode()) {
3249 case Hexagon::A4_addp_c:
3250 case Hexagon::A4_subp_c:
3251 case Hexagon::A4_tlbmatch:
3252 case Hexagon::A5_ACS:
3253 case Hexagon::F2_sfinvsqrta:
3254 case Hexagon::F2_sfrecipa:
3255 case Hexagon::J2_endloop0:
3256 case Hexagon::J2_endloop01:
3257 case Hexagon::J2_ploop1si:
3258 case Hexagon::J2_ploop1sr:
3259 case Hexagon::J2_ploop2si:
3260 case Hexagon::J2_ploop2sr:
3261 case Hexagon::J2_ploop3si:
3262 case Hexagon::J2_ploop3sr:
3263 case Hexagon::S2_cabacdecbin:
3264 case Hexagon::S2_storew_locked:
3265 case Hexagon::S4_stored_locked:
3272 return Opcode == Hexagon::J2_jumpt ||
3273 Opcode == Hexagon::J2_jumptpt ||
3274 Opcode == Hexagon::J2_jumpf ||
3275 Opcode == Hexagon::J2_jumpfpt ||
3276 Opcode == Hexagon::J2_jumptnew ||
3277 Opcode == Hexagon::J2_jumpfnew ||
3278 Opcode == Hexagon::J2_jumptnewpt ||
3279 Opcode == Hexagon::J2_jumpfnewpt;
3299 unsigned &AccessSize)
const {
3308 unsigned BasePos = 0, OffsetPos = 0;
3318 if (!OffsetOp.
isImm())
3320 Offset = OffsetOp.
getImm();
3331 unsigned &BasePos,
unsigned &OffsetPos)
const {
3339 }
else if (
MI.mayStore()) {
3342 }
else if (
MI.mayLoad()) {
3357 if (!
MI.getOperand(BasePos).isReg() || !
MI.getOperand(OffsetPos).isImm())
3396 while (
I->isDebugInstr()) {
3401 if (!isUnpredicatedTerminator(*
I))
3406 Jumpers.push_back(LastInst);
3410 if (&*
I != LastInst && !
I->isBundle() && isUnpredicatedTerminator(*
I)) {
3411 if (!SecondLastInst) {
3412 SecondLastInst = &*
I;
3413 Jumpers.push_back(SecondLastInst);
3434 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3436 switch (
MI.getOpcode()) {
3445 case Hexagon::C2_cmpeq:
3446 case Hexagon::C2_cmpgt:
3447 case Hexagon::C2_cmpgtu:
3448 DstReg =
MI.getOperand(0).getReg();
3449 Src1Reg =
MI.getOperand(1).getReg();
3450 Src2Reg =
MI.getOperand(2).getReg();
3451 if (Hexagon::PredRegsRegClass.
contains(DstReg) &&
3452 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3456 case Hexagon::C2_cmpeqi:
3457 case Hexagon::C2_cmpgti:
3458 case Hexagon::C2_cmpgtui:
3460 DstReg =
MI.getOperand(0).getReg();
3461 SrcReg =
MI.getOperand(1).getReg();
3462 if (Hexagon::PredRegsRegClass.
contains(DstReg) &&
3463 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3465 ((isUInt<5>(
MI.getOperand(2).getImm())) ||
3466 (
MI.getOperand(2).getImm() == -1)))
3469 case Hexagon::A2_tfr:
3471 DstReg =
MI.getOperand(0).getReg();
3472 SrcReg =
MI.getOperand(1).getReg();
3476 case Hexagon::A2_tfrsi:
3480 DstReg =
MI.getOperand(0).getReg();
3484 case Hexagon::S2_tstbit_i:
3485 DstReg =
MI.getOperand(0).getReg();
3486 Src1Reg =
MI.getOperand(1).getReg();
3487 if (Hexagon::PredRegsRegClass.
contains(DstReg) &&
3488 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3489 MI.getOperand(2).isImm() &&
3497 case Hexagon::J2_jumptnew:
3498 case Hexagon::J2_jumpfnew:
3499 case Hexagon::J2_jumptnewpt:
3500 case Hexagon::J2_jumpfnewpt:
3501 Src1Reg =
MI.getOperand(0).getReg();
3502 if (Hexagon::PredRegsRegClass.
contains(Src1Reg) &&
3503 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3510 case Hexagon::J2_jump:
3511 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3512 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3524 if ((GA.
getOpcode() != Hexagon::C2_cmpeqi) ||
3525 (GB.
getOpcode() != Hexagon::J2_jumptnew))
3530 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3538 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3539 : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3542 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3543 : Hexagon::J4_cmpeqi_tp1_jump_nt;
3548 bool ForBigCore)
const {
3556 static const std::map<unsigned, unsigned> DupMap = {
3557 {Hexagon::A2_add, Hexagon::dup_A2_add},
3558 {Hexagon::A2_addi, Hexagon::dup_A2_addi},
3559 {Hexagon::A2_andir, Hexagon::dup_A2_andir},
3560 {Hexagon::A2_combineii, Hexagon::dup_A2_combineii},
3561 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb},
3562 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth},
3563 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr},
3564 {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi},
3565 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb},
3566 {Hexagon::A2_zxth, Hexagon::dup_A2_zxth},
3567 {Hexagon::A4_combineii, Hexagon::dup_A4_combineii},
3568 {Hexagon::A4_combineir, Hexagon::dup_A4_combineir},
3569 {Hexagon::A4_combineri, Hexagon::dup_A4_combineri},
3570 {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif},
3571 {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit},
3572 {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif},
3573 {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit},
3574 {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi},
3575 {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe},
3576 {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io},
3577 {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io},
3578 {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io},
3579 {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io},
3580 {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io},
3581 {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io},
3582 {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe},
3583 {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io},
3584 {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io},
3585 {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io},
3586 {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io},
3587 {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io},
3588 {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io},
3590 unsigned OpNum =
MI.getOpcode();
3593 auto Iter = DupMap.find(OpNum);
3594 if (Iter != DupMap.end())
3595 return Iter->second;
3597 for (
const auto &Iter : DupMap)
3598 if (Iter.second == OpNum)
3605 enum Hexagon::PredSense inPredSense;
3606 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3607 Hexagon::PredSense_true;
3608 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3609 if (CondOpcode >= 0)
3617 switch (
MI.getOpcode()) {
3619 case Hexagon::V6_vL32b_pi:
3620 return Hexagon::V6_vL32b_cur_pi;
3621 case Hexagon::V6_vL32b_ai:
3622 return Hexagon::V6_vL32b_cur_ai;
3623 case Hexagon::V6_vL32b_nt_pi:
3624 return Hexagon::V6_vL32b_nt_cur_pi;
3625 case Hexagon::V6_vL32b_nt_ai:
3626 return Hexagon::V6_vL32b_nt_cur_ai;
3627 case Hexagon::V6_vL32b_ppu:
3628 return Hexagon::V6_vL32b_cur_ppu;
3629 case Hexagon::V6_vL32b_nt_ppu:
3630 return Hexagon::V6_vL32b_nt_cur_ppu;
3637 switch (
MI.getOpcode()) {
3639 case Hexagon::V6_vL32b_cur_pi:
3640 return Hexagon::V6_vL32b_pi;
3641 case Hexagon::V6_vL32b_cur_ai:
3642 return Hexagon::V6_vL32b_ai;
3643 case Hexagon::V6_vL32b_nt_cur_pi:
3644 return Hexagon::V6_vL32b_nt_pi;
3645 case Hexagon::V6_vL32b_nt_cur_ai:
3646 return Hexagon::V6_vL32b_nt_ai;
3647 case Hexagon::V6_vL32b_cur_ppu:
3648 return Hexagon::V6_vL32b_ppu;
3649 case Hexagon::V6_vL32b_nt_cur_ppu:
3650 return Hexagon::V6_vL32b_nt_ppu;
3738 int NVOpcode = Hexagon::getNewValueOpcode(
MI.getOpcode());
3742 switch (
MI.getOpcode()) {
3746 case Hexagon::S4_storerb_ur:
3747 return Hexagon::S4_storerbnew_ur;
3749 case Hexagon::S2_storerb_pci:
3750 return Hexagon::S2_storerb_pci;
3752 case Hexagon::S2_storeri_pci:
3753 return Hexagon::S2_storeri_pci;
3755 case Hexagon::S2_storerh_pci:
3756 return Hexagon::S2_storerh_pci;
3758 case Hexagon::S2_storerd_pci:
3759 return Hexagon::S2_storerd_pci;
3761 case Hexagon::S2_storerf_pci:
3762 return Hexagon::S2_storerf_pci;
3764 case Hexagon::V6_vS32b_ai:
3765 return Hexagon::V6_vS32b_new_ai;
3767 case Hexagon::V6_vS32b_pi:
3768 return Hexagon::V6_vS32b_new_pi;
3793 if (BrTarget.
isMBB()) {
3795 Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3808 bool SawCond =
false, Bad =
false;
3812 if (
I.isConditionalBranch()) {
3819 if (
I.isUnconditionalBranch() && !SawCond) {
3827 if (NextIt ==
B.instr_end()) {
3830 if (!
B.isLayoutSuccessor(SB))
3832 Taken = getEdgeProbability(Src, SB) < OneHalf;
3836 assert(NextIt->isUnconditionalBranch());
3845 Taken =
BT && getEdgeProbability(Src,
BT) < OneHalf;
3852 switch (
MI.getOpcode()) {
3853 case Hexagon::J2_jumpt:
3854 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3855 case Hexagon::J2_jumpf:
3856 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3866 switch (
MI.getOpcode()) {
3868 case Hexagon::J2_jumpt:
3869 case Hexagon::J2_jumpf:
3873 int NewOpcode = Hexagon::getPredNewOpcode(
MI.getOpcode());
3880 int NewOp =
MI.getOpcode();
3882 NewOp = Hexagon::getPredOldOpcode(NewOp);
3886 if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3888 case Hexagon::J2_jumptpt:
3889 NewOp = Hexagon::J2_jumpt;
3891 case Hexagon::J2_jumpfpt:
3892 NewOp = Hexagon::J2_jumpf;
3894 case Hexagon::J2_jumprtpt:
3895 NewOp = Hexagon::J2_jumprt;
3897 case Hexagon::J2_jumprfpt:
3898 NewOp = Hexagon::J2_jumprf;
3903 "Couldn't change predicate new instruction to its old form.");
3907 NewOp = Hexagon::getNonNVStore(NewOp);
3908 assert(NewOp >= 0 &&
"Couldn't change new-value store to its old form.");
3916 case Hexagon::J2_jumpfpt:
3917 return Hexagon::J2_jumpf;
3918 case Hexagon::J2_jumptpt:
3919 return Hexagon::J2_jumpt;
3920 case Hexagon::J2_jumprfpt:
3921 return Hexagon::J2_jumprf;
3922 case Hexagon::J2_jumprtpt:
3923 return Hexagon::J2_jumprt;
3932 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3935 switch (
MI.getOpcode()) {
3943 case Hexagon::L2_loadri_io:
3944 case Hexagon::dup_L2_loadri_io:
3945 DstReg =
MI.getOperand(0).getReg();
3946 SrcReg =
MI.getOperand(1).getReg();
3950 if (Hexagon::IntRegsRegClass.
contains(SrcReg) &&
3952 MI.getOperand(2).isImm() &&
3953 isShiftedUInt<5,2>(
MI.getOperand(2).getImm()))
3957 (
MI.getOperand(2).isImm() &&
3958 isShiftedUInt<4,2>(
MI.getOperand(2).getImm())))
3962 case Hexagon::L2_loadrub_io:
3963 case Hexagon::dup_L2_loadrub_io:
3965 DstReg =
MI.getOperand(0).getReg();
3966 SrcReg =
MI.getOperand(1).getReg();
3968 MI.getOperand(2).isImm() && isUInt<4>(
MI.getOperand(2).getImm()))
3981 case Hexagon::L2_loadrh_io:
3982 case Hexagon::L2_loadruh_io:
3983 case Hexagon::dup_L2_loadrh_io:
3984 case Hexagon::dup_L2_loadruh_io:
3986 DstReg =
MI.getOperand(0).getReg();
3987 SrcReg =
MI.getOperand(1).getReg();
3989 MI.getOperand(2).isImm() &&
3990 isShiftedUInt<3,1>(
MI.getOperand(2).getImm()))
3993 case Hexagon::L2_loadrb_io:
3994 case Hexagon::dup_L2_loadrb_io:
3996 DstReg =
MI.getOperand(0).getReg();
3997 SrcReg =
MI.getOperand(1).getReg();
3999 MI.getOperand(2).isImm() &&
4000 isUInt<3>(
MI.getOperand(2).getImm()))
4003 case Hexagon::L2_loadrd_io:
4004 case Hexagon::dup_L2_loadrd_io:
4006 DstReg =
MI.getOperand(0).getReg();
4007 SrcReg =
MI.getOperand(1).getReg();
4009 Hexagon::IntRegsRegClass.
contains(SrcReg) &&
4011 MI.getOperand(2).isImm() &&
4012 isShiftedUInt<5,3>(
MI.getOperand(2).getImm()))
4017 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
4018 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
4019 case Hexagon::L4_return:
4020 case Hexagon::L2_deallocframe:
4021 case Hexagon::dup_L2_deallocframe:
4023 case Hexagon::EH_RETURN_JMPR:
4024 case Hexagon::PS_jmpret:
4025 case Hexagon::SL2_jumpr31:
4028 DstReg =
MI.getOperand(0).getReg();
4029 if (Hexagon::IntRegsRegClass.
contains(DstReg) && (Hexagon::R31 == DstReg))
4032 case Hexagon::PS_jmprett:
4033 case Hexagon::PS_jmpretf:
4034 case Hexagon::PS_jmprettnewpt:
4035 case Hexagon::PS_jmpretfnewpt:
4036 case Hexagon::PS_jmprettnew:
4037 case Hexagon::PS_jmpretfnew:
4038 case Hexagon::SL2_jumpr31_t:
4039 case Hexagon::SL2_jumpr31_f:
4040 case Hexagon::SL2_jumpr31_tnew:
4041 case Hexagon::SL2_jumpr31_fnew:
4042 DstReg =
MI.getOperand(1).getReg();
4043 SrcReg =
MI.getOperand(0).getReg();
4045 if ((Hexagon::PredRegsRegClass.
contains(SrcReg) &&
4046 (Hexagon::P0 == SrcReg)) &&
4047 (Hexagon::IntRegsRegClass.
contains(DstReg) && (Hexagon::R31 == DstReg)))
4050 case Hexagon::L4_return_t:
4051 case Hexagon::L4_return_f:
4052 case Hexagon::L4_return_tnew_pnt:
4053 case Hexagon::L4_return_fnew_pnt:
4054 case Hexagon::L4_return_tnew_pt:
4055 case Hexagon::L4_return_fnew_pt:
4057 SrcReg =
MI.getOperand(0).getReg();
4058 if (Hexagon::PredRegsRegClass.
contains(SrcReg) && (Hexagon::P0 == SrcReg))
4066 case Hexagon::S2_storeri_io:
4067 case Hexagon::dup_S2_storeri_io:
4070 Src1Reg =
MI.getOperand(0).getReg();
4071 Src2Reg =
MI.getOperand(2).getReg();
4072 if (Hexagon::IntRegsRegClass.
contains(Src1Reg) &&
4075 isShiftedUInt<5,2>(
MI.getOperand(1).getImm()))
4079 MI.getOperand(1).isImm() &&
4080 isShiftedUInt<4,2>(
MI.getOperand(1).getImm()))
4083 case Hexagon::S2_storerb_io:
4084 case Hexagon::dup_S2_storerb_io:
4086 Src1Reg =
MI.getOperand(0).getReg();
4087 Src2Reg =
MI.getOperand(2).getReg();
4089 MI.getOperand(1).isImm() && isUInt<4>(
MI.getOperand(1).getImm()))
4101 case Hexagon::S2_storerh_io:
4102 case Hexagon::dup_S2_storerh_io:
4104 Src1Reg =
MI.getOperand(0).getReg();
4105 Src2Reg =
MI.getOperand(2).getReg();
4107 MI.getOperand(1).isImm() &&
4108 isShiftedUInt<3,1>(
MI.getOperand(1).getImm()))
4111 case Hexagon::S2_storerd_io:
4112 case Hexagon::dup_S2_storerd_io:
4114 Src1Reg =
MI.getOperand(0).getReg();
4115 Src2Reg =
MI.getOperand(2).getReg();
4117 Hexagon::IntRegsRegClass.
contains(Src1Reg) &&
4119 isShiftedInt<6,3>(
MI.getOperand(1).getImm()))
4122 case Hexagon::S4_storeiri_io:
4123 case Hexagon::dup_S4_storeiri_io:
4125 Src1Reg =
MI.getOperand(0).getReg();
4127 isShiftedUInt<4,2>(
MI.getOperand(1).getImm()) &&
4128 MI.getOperand(2).isImm() && isUInt<1>(
MI.getOperand(2).getImm()))
4131 case Hexagon::S4_storeirb_io:
4132 case Hexagon::dup_S4_storeirb_io:
4134 Src1Reg =
MI.getOperand(0).getReg();
4136 MI.getOperand(1).isImm() && isUInt<4>(
MI.getOperand(1).getImm()) &&
4137 MI.getOperand(2).isImm() && isUInt<1>(
MI.getOperand(2).getImm()))
4140 case Hexagon::S2_allocframe:
4141 case Hexagon::dup_S2_allocframe:
4142 if (
MI.getOperand(2).isImm() &&
4143 isShiftedUInt<5,3>(
MI.getOperand(2).getImm()))
4164 case Hexagon::A2_addi:
4165 case Hexagon::dup_A2_addi:
4166 DstReg =
MI.getOperand(0).getReg();
4167 SrcReg =
MI.getOperand(1).getReg();
4170 if (Hexagon::IntRegsRegClass.
contains(SrcReg) &&
4172 isShiftedUInt<6,2>(
MI.getOperand(2).getImm()))
4175 if ((DstReg == SrcReg) &&
MI.getOperand(2).isImm() &&
4176 isInt<7>(
MI.getOperand(2).getImm()))
4181 ((
MI.getOperand(2).getImm() == 1) ||
4182 (
MI.getOperand(2).getImm() == -1)))
4186 case Hexagon::A2_add:
4187 case Hexagon::dup_A2_add:
4189 DstReg =
MI.getOperand(0).getReg();
4190 Src1Reg =
MI.getOperand(1).getReg();
4191 Src2Reg =
MI.getOperand(2).getReg();
4196 case Hexagon::A2_andir:
4197 case Hexagon::dup_A2_andir:
4201 DstReg =
MI.getOperand(0).getReg();
4202 SrcReg =
MI.getOperand(1).getReg();
4204 MI.getOperand(2).isImm() &&
4205 ((
MI.getOperand(2).getImm() == 1) ||
4206 (
MI.getOperand(2).getImm() == 255)))
4209 case Hexagon::A2_tfr:
4210 case Hexagon::dup_A2_tfr:
4212 DstReg =
MI.getOperand(0).getReg();
4213 SrcReg =
MI.getOperand(1).getReg();
4217 case Hexagon::A2_tfrsi:
4218 case Hexagon::dup_A2_tfrsi:
4223 DstReg =
MI.getOperand(0).getReg();
4227 case Hexagon::C2_cmoveit:
4228 case Hexagon::C2_cmovenewit:
4229 case Hexagon::C2_cmoveif:
4230 case Hexagon::C2_cmovenewif:
4231 case Hexagon::dup_C2_cmoveit:
4232 case Hexagon::dup_C2_cmovenewit:
4233 case Hexagon::dup_C2_cmoveif:
4234 case Hexagon::dup_C2_cmovenewif:
4238 DstReg =
MI.getOperand(0).getReg();
4239 SrcReg =
MI.getOperand(1).getReg();
4241 Hexagon::PredRegsRegClass.
contains(SrcReg) && Hexagon::P0 == SrcReg &&
4242 MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0)
4245 case Hexagon::C2_cmpeqi:
4246 case Hexagon::dup_C2_cmpeqi:
4248 DstReg =
MI.getOperand(0).getReg();
4249 SrcReg =
MI.getOperand(1).getReg();
4250 if (Hexagon::PredRegsRegClass.
contains(DstReg) &&
4252 MI.getOperand(2).isImm() && isUInt<2>(
MI.getOperand(2).getImm()))
4255 case Hexagon::A2_combineii:
4256 case Hexagon::A4_combineii:
4257 case Hexagon::dup_A2_combineii:
4258 case Hexagon::dup_A4_combineii:
4260 DstReg =
MI.getOperand(0).getReg();
4262 ((
MI.getOperand(1).isImm() && isUInt<2>(
MI.getOperand(1).getImm())) ||
4263 (
MI.getOperand(1).isGlobal() &&
4264 isUInt<2>(
MI.getOperand(1).getOffset()))) &&
4265 ((
MI.getOperand(2).isImm() && isUInt<2>(
MI.getOperand(2).getImm())) ||
4266 (
MI.getOperand(2).isGlobal() &&
4267 isUInt<2>(
MI.getOperand(2).getOffset()))))
4270 case Hexagon::A4_combineri:
4271 case Hexagon::dup_A4_combineri:
4274 DstReg =
MI.getOperand(0).getReg();
4275 SrcReg =
MI.getOperand(1).getReg();
4277 ((
MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0) ||
4278 (
MI.getOperand(2).isGlobal() &&
MI.getOperand(2).getOffset() == 0)))
4281 case Hexagon::A4_combineir:
4282 case Hexagon::dup_A4_combineir:
4284 DstReg =
MI.getOperand(0).getReg();
4285 SrcReg =
MI.getOperand(2).getReg();
4287 ((
MI.getOperand(1).isImm() &&
MI.getOperand(1).getImm() == 0) ||
4288 (
MI.getOperand(1).isGlobal() &&
MI.getOperand(1).getOffset() == 0)))
4291 case Hexagon::A2_sxtb:
4292 case Hexagon::A2_sxth:
4293 case Hexagon::A2_zxtb:
4294 case Hexagon::A2_zxth:
4295 case Hexagon::dup_A2_sxtb:
4296 case Hexagon::dup_A2_sxth:
4297 case Hexagon::dup_A2_zxtb:
4298 case Hexagon::dup_A2_zxth:
4300 DstReg =
MI.getOperand(0).getReg();
4301 SrcReg =
MI.getOperand(1).getReg();
4311 return Hexagon::getRealHWInstr(
MI.getOpcode(), Hexagon::InstrType_Real);
4321 if (
MI.isTransient())
4338 unsigned UseIdx)
const {
4347 int Idx =
DefMI.findRegisterDefOperandIdx(*SR,
false,
false, &HRI);
4358 int Idx =
UseMI.findRegisterUseOperandIdx(*SR,
false, &HRI);
4385 Cond[0].setImm(Opc);
4392 : Hexagon::getTruePredOpcode(Opc);
4393 if (InvPredOpcode >= 0)
4394 return InvPredOpcode;
4408 return ~(-1U << (
bits - 1));
4410 return ~(-1U <<
bits);
4415 switch (
MI.getOpcode()) {
4416 case Hexagon::L2_loadrbgp:
4417 case Hexagon::L2_loadrdgp:
4418 case Hexagon::L2_loadrhgp:
4419 case Hexagon::L2_loadrigp:
4420 case Hexagon::L2_loadrubgp:
4421 case Hexagon::L2_loadruhgp:
4422 case Hexagon::S2_storerbgp:
4423 case Hexagon::S2_storerbnewgp:
4424 case Hexagon::S2_storerhgp:
4425 case Hexagon::S2_storerhnewgp:
4426 case Hexagon::S2_storerigp:
4427 case Hexagon::S2_storerinewgp:
4428 case Hexagon::S2_storerdgp:
4429 case Hexagon::S2_storerfgp:
4447 if (
MI.getOpcode() == Hexagon::A4_ext)
4461 bool ToBigInstrs)
const {
4473 MII->setDesc(
get(Opcode));
4479 bool ToBigInstrs)
const {
4482 End = MB.instr_end();
4483 Instr != End; ++Instr)
4491 while ((MII !=
MBB->
instr_end()) && MII->isInsideBundle()) {
4498 using namespace HexagonII;
4506 if (
MI.getOpcode() == Hexagon::Y2_dcfetchbo)
4513 return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4528 return -1U << (
bits - 1);
4537 short NonExtOpcode = Hexagon::getRegForm(
MI.getOpcode());
4538 if (NonExtOpcode >= 0)
4539 return NonExtOpcode;
4541 if (
MI.getDesc().mayLoad() ||
MI.getDesc().mayStore()) {
4545 return Hexagon::changeAddrMode_abs_io(
MI.getOpcode());
4547 return Hexagon::changeAddrMode_io_rr(
MI.getOpcode());
4549 return Hexagon::changeAddrMode_ur_rr(
MI.getOpcode());
4559 unsigned &PredReg,
unsigned &PredRegPos,
unsigned &PredRegFlags)
const {
4567 PredReg =
Cond[1].getReg();
4571 if (
Cond[1].isImplicit())
4579 return Hexagon::getRealHWInstr(
MI.getOpcode(), Hexagon::InstrType_Pseudo);
4583 return Hexagon::getRegForm(
MI.getOpcode());
4591 if (
MI.isDebugInstr() ||
MI.isPosition())
4594 unsigned Size =
MI.getDesc().getSize();
4610 unsigned NumDefs = 0;
4611 for (;
MI.getOperand(NumDefs).
isReg() &&
MI.getOperand(NumDefs).isDef();
4613 assert(NumDefs !=
MI.getNumOperands()-2 &&
"No asm string?");
4615 assert(
MI.getOperand(NumDefs).isSymbol() &&
"No asm string?");
4617 const char *AsmStr =
MI.getOperand(NumDefs).getSymbolName();
4643 assert(BundleHead->isBundle() &&
"Not a bundle header");
4653 "Instruction must be extendable");
4659 "Branch with unknown extendable field type");
4671 int TargetPos =
MI.getNumOperands() - 1;
4674 while ((TargetPos > -1) && !
MI.getOperand(TargetPos).isMBB())
4676 assert((TargetPos >= 0) &&
MI.getOperand(TargetPos).isMBB());
4677 MI.getOperand(TargetPos).setMBB(NewTarget);
4681 MI.setDesc(
get(NewOpcode));
4693 for (
unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4694 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4715 int PredRevOpcode = -1;
4717 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4719 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4720 assert(PredRevOpcode > 0);
4721 return PredRevOpcode;
4727 return Cond.empty() || (
Cond[0].isImm() && (
Cond.size() != 1));
4734 if (Operand.
isImm())
4735 Operand.
setImm(Operand.
getImm() | memShufDisabledMask);
4743 return (Operand.
isImm() && (Operand.
getImm() & memShufDisabledMask) != 0);
4748 return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4752 return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4756 return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4760 return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4764 return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4768 return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4772 return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4776 return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;