67#define DEBUG_TYPE "hexagon-instrinfo"
69#define GET_INSTRINFO_CTOR_DTOR
70#define GET_INSTRMAP_INFO
72#include "HexagonGenDFAPacketizer.inc"
73#include "HexagonGenInstrInfo.inc"
77 "packetization boundary."));
84 cl::desc(
"Disable schedule adjustment for new value stores."));
88 cl::desc(
"Enable timing class latency"));
92 cl::desc(
"Enable vec alu forwarding"));
96 cl::desc(
"Enable vec acc forwarding"));
104 cl::desc(
"Use the DFA based hazard recognizer."));
119void HexagonInstrInfo::anchor() {}
126namespace HexagonFUnits {
132 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
133 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
145 for (; MIB != MIE; ++MIB) {
146 if (!MIB->isDebugInstr())
157 if (!(
MI.getMF()->getFunction().hasOptSize()))
158 return MI.isAsCheapAsAMove();
160 if (
MI.getOpcode() == Hexagon::A2_tfrsi) {
161 auto Op =
MI.getOperand(1);
169 int64_t Imm =
Op.getImm();
174 return MI.isAsCheapAsAMove();
189 if (
isFloat(
MI) &&
MI.hasRegisterImplicitUseOperand(Hexagon::USR))
203 if (EndLoopOp == Hexagon::ENDLOOP0) {
204 LOOPi = Hexagon::J2_loop0i;
205 LOOPr = Hexagon::J2_loop0r;
207 LOOPi = Hexagon::J2_loop1i;
208 LOOPr = Hexagon::J2_loop1r;
219 unsigned Opc =
I.getOpcode();
220 if (Opc == LOOPi || Opc == LOOPr)
224 if (Opc == EndLoopOp &&
I.getOperand(0).getMBB() != TargetBB)
251 Uses.push_back(MO.getReg());
290 int &FrameIndex)
const {
291 switch (
MI.getOpcode()) {
294 case Hexagon::L2_loadri_io:
295 case Hexagon::L2_loadrd_io:
296 case Hexagon::V6_vL32b_ai:
297 case Hexagon::V6_vL32b_nt_ai:
298 case Hexagon::V6_vL32Ub_ai:
299 case Hexagon::LDriw_pred:
300 case Hexagon::LDriw_ctr:
301 case Hexagon::PS_vloadrq_ai:
302 case Hexagon::PS_vloadrw_ai:
303 case Hexagon::PS_vloadrw_nt_ai: {
311 return MI.getOperand(0).getReg();
314 case Hexagon::L2_ploadrit_io:
315 case Hexagon::L2_ploadrif_io:
316 case Hexagon::L2_ploadrdt_io:
317 case Hexagon::L2_ploadrdf_io: {
325 return MI.getOperand(0).getReg();
338 int &FrameIndex)
const {
339 switch (
MI.getOpcode()) {
342 case Hexagon::S2_storerb_io:
343 case Hexagon::S2_storerh_io:
344 case Hexagon::S2_storeri_io:
345 case Hexagon::S2_storerd_io:
346 case Hexagon::V6_vS32b_ai:
347 case Hexagon::V6_vS32Ub_ai:
348 case Hexagon::STriw_pred:
349 case Hexagon::STriw_ctr:
350 case Hexagon::PS_vstorerq_ai:
351 case Hexagon::PS_vstorerw_ai: {
359 return MI.getOperand(2).getReg();
362 case Hexagon::S2_pstorerbt_io:
363 case Hexagon::S2_pstorerbf_io:
364 case Hexagon::S2_pstorerht_io:
365 case Hexagon::S2_pstorerhf_io:
366 case Hexagon::S2_pstorerit_io:
367 case Hexagon::S2_pstorerif_io:
368 case Hexagon::S2_pstorerdt_io:
369 case Hexagon::S2_pstorerdf_io: {
377 return MI.getOperand(3).getReg();
393 for (++MII; MII !=
MBB->
instr_end() && MII->isInsideBundle(); ++MII)
411 for (++MII; MII !=
MBB->
instr_end() && MII->isInsideBundle(); ++MII)
439 bool AllowModify)
const {
471 while (
I->isDebugInstr()) {
477 bool JumpToBlock =
I->getOpcode() == Hexagon::J2_jump &&
478 I->getOperand(0).isMBB();
480 if (AllowModify && JumpToBlock &&
483 I->eraseFromParent();
489 if (!isUnpredicatedTerminator(*
I))
497 if (&*
I != LastInst && !
I->isBundle() && isUnpredicatedTerminator(*
I)) {
499 SecondLastInst = &*
I;
510 int SecLastOpcode = SecondLastInst ? SecondLastInst->
getOpcode() : 0;
513 if (LastOpcode == Hexagon::J2_jump && !LastInst->
getOperand(0).
isMBB())
515 if (SecLastOpcode == Hexagon::J2_jump &&
526 if (LastInst && !SecondLastInst) {
527 if (LastOpcode == Hexagon::J2_jump) {
537 if (LastOpcodeHasJMP_c) {
552 <<
" with one jump\n";);
559 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
570 if (SecLastOpcodeHasNVJump &&
572 (LastOpcode == Hexagon::J2_jump)) {
583 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
587 I->eraseFromParent();
592 if (
isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
600 <<
" with two jumps";);
606 int *BytesRemoved)
const {
607 assert(!BytesRemoved &&
"code size not handled");
614 if (
I->isDebugInstr())
619 if (Count && (
I->getOpcode() == Hexagon::J2_jump))
633 int *BytesAdded)
const {
634 unsigned BOpc = Hexagon::J2_jump;
635 unsigned BccOpc = Hexagon::J2_jumpt;
637 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
638 assert(!BytesAdded &&
"code size not handled");
643 if (!
Cond.empty() &&
Cond[0].isImm())
644 BccOpc =
Cond[0].getImm();
664 int EndLoopOp =
Cond[0].getImm();
671 assert(
Loop !=
nullptr &&
"Inserting an ENDLOOP without a LOOP");
672 Loop->getOperand(0).setMBB(
TBB);
676 assert((
Cond.size() == 3) &&
"Only supporting rr/ri version of nvjump");
693 assert((
Cond.size() == 2) &&
"Malformed cond vector");
701 "Cond. cannot be empty when multiple branchings are required");
703 "NV-jump cannot be inserted with another branch");
706 int EndLoopOp =
Cond[0].getImm();
713 assert(
Loop !=
nullptr &&
"Inserting an ENDLOOP without a LOOP");
714 Loop->getOperand(0).setMBB(
TBB);
743 TripCount =
Loop->getOpcode() == Hexagon::J2_loop0r
745 :
Loop->getOperand(1).getImm();
747 LoopCount =
Loop->getOperand(1).getReg();
750 bool shouldIgnoreForPipelining(
const MachineInstr *
MI)
const override {
752 return MI == EndLoop;
755 std::optional<bool> createTripCountGreaterCondition(
758 if (TripCount == -1) {
762 TII->get(Hexagon::C2_cmpgtui),
Done)
770 return TripCount > TC;
778 void adjustTripCount(
int TripCountAdjust)
override {
781 if (
Loop->getOpcode() == Hexagon::J2_loop0i ||
782 Loop->getOpcode() == Hexagon::J2_loop1i) {
783 int64_t TripCount =
Loop->getOperand(1).getImm() + TripCountAdjust;
784 assert(TripCount > 0 &&
"Can't create an empty or negative loop!");
785 Loop->getOperand(1).setImm(TripCount);
794 TII->get(Hexagon::A2_addi), NewLoopCount)
797 Loop->getOperand(1).setReg(NewLoopCount);
800 void disposed()
override {
Loop->eraseFromParent(); }
804std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
812 LoopBB,
I->getOpcode(),
I->getOperand(0).getMBB(), VisitedBBs);
814 return std::make_unique<HexagonPipelinerLoopInfo>(LoopInst, &*
I);
820 unsigned NumCycles,
unsigned ExtraPredCycles,
834 return NumInstrs <= 4;
842 for (
auto I =
B.begin();
I !=
E; ++
I) {
852 for (
auto I =
B.rbegin();
I !=
E; ++
I)
863 if (Hexagon::IntRegsRegClass.
contains(SrcReg, DestReg)) {
865 .
addReg(SrcReg, KillFlag);
868 if (Hexagon::DoubleRegsRegClass.
contains(SrcReg, DestReg)) {
870 .
addReg(SrcReg, KillFlag);
873 if (Hexagon::PredRegsRegClass.
contains(SrcReg, DestReg)) {
879 if (Hexagon::CtrRegsRegClass.
contains(DestReg) &&
880 Hexagon::IntRegsRegClass.
contains(SrcReg)) {
882 .
addReg(SrcReg, KillFlag);
885 if (Hexagon::IntRegsRegClass.
contains(DestReg) &&
886 Hexagon::CtrRegsRegClass.
contains(SrcReg)) {
888 .
addReg(SrcReg, KillFlag);
891 if (Hexagon::ModRegsRegClass.
contains(DestReg) &&
892 Hexagon::IntRegsRegClass.
contains(SrcReg)) {
894 .
addReg(SrcReg, KillFlag);
897 if (Hexagon::PredRegsRegClass.
contains(SrcReg) &&
898 Hexagon::IntRegsRegClass.
contains(DestReg)) {
900 .
addReg(SrcReg, KillFlag);
903 if (Hexagon::IntRegsRegClass.
contains(SrcReg) &&
904 Hexagon::PredRegsRegClass.
contains(DestReg)) {
906 .
addReg(SrcReg, KillFlag);
909 if (Hexagon::PredRegsRegClass.
contains(SrcReg) &&
910 Hexagon::IntRegsRegClass.
contains(DestReg)) {
912 .
addReg(SrcReg, KillFlag);
915 if (Hexagon::HvxVRRegClass.
contains(SrcReg, DestReg)) {
917 addReg(SrcReg, KillFlag);
920 if (Hexagon::HvxWRRegClass.
contains(SrcReg, DestReg)) {
923 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
924 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
928 .
addReg(SrcHi, KillFlag | UndefHi)
929 .
addReg(SrcLo, KillFlag | UndefLo);
932 if (Hexagon::HvxQRRegClass.
contains(SrcReg, DestReg)) {
935 .
addReg(SrcReg, KillFlag);
938 if (Hexagon::HvxQRRegClass.
contains(SrcReg) &&
939 Hexagon::HvxVRRegClass.
contains(DestReg)) {
943 if (Hexagon::HvxQRRegClass.
contains(DestReg) &&
944 Hexagon::HvxVRRegClass.
contains(SrcReg)) {
959 Register SrcReg,
bool isKill,
int FI,
972 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
976 }
else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
980 }
else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
984 }
else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
988 }
else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
992 }
else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
996 }
else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1019 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
1022 }
else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
1025 }
else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
1028 }
else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
1031 }
else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
1034 }
else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
1037 }
else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1058 unsigned Opc =
MI.getOpcode();
1060 auto RealCirc = [&](
unsigned Opc,
bool HasImm,
unsigned MxOp) {
1062 Register CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1064 .
add(
MI.getOperand((HasImm ? 5 : 4)));
1068 MIB.
add(
MI.getOperand(4));
1075 if (
MI.memoperands().empty())
1078 return MMO->getAlign() >= NeedAlign;
1083 case Hexagon::PS_call_instrprof_custom: {
1084 auto Op0 =
MI.getOperand(0);
1086 "First operand must be a global containing handler name.");
1090 StringRef NameStr = Arr->isCString() ? Arr->getAsCString() : Arr->getAsString();
1116 MIB.addExternalSymbol(cstr);
1120 case TargetOpcode::COPY: {
1131 case Hexagon::PS_aligna:
1134 .
addImm(-
MI.getOperand(1).getImm());
1137 case Hexagon::V6_vassignp: {
1140 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1141 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1148 .
addReg(SrcLo, Kill | UndefLo);
1152 case Hexagon::V6_lo: {
1155 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1158 MRI.clearKillFlags(SrcSubLo);
1161 case Hexagon::V6_hi: {
1164 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1167 MRI.clearKillFlags(SrcSubHi);
1170 case Hexagon::PS_vloadrv_ai: {
1174 int Offset =
MI.getOperand(2).getImm();
1175 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1176 unsigned NewOpc = UseAligned(
MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1177 : Hexagon::V6_vL32Ub_ai;
1185 case Hexagon::PS_vloadrw_ai: {
1189 int Offset =
MI.getOperand(2).getImm();
1190 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1191 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1192 unsigned NewOpc = UseAligned(
MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1193 : Hexagon::V6_vL32Ub_ai;
1195 HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1200 HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1207 case Hexagon::PS_vstorerv_ai: {
1212 int Offset =
MI.getOperand(1).getImm();
1213 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1214 unsigned NewOpc = UseAligned(
MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1215 : Hexagon::V6_vS32Ub_ai;
1224 case Hexagon::PS_vstorerw_ai: {
1228 int Offset =
MI.getOperand(1).getImm();
1229 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1230 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1231 unsigned NewOpc = UseAligned(
MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1232 : Hexagon::V6_vS32Ub_ai;
1236 .
addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo))
1241 .
addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi))
1246 case Hexagon::PS_true: {
1254 case Hexagon::PS_false: {
1262 case Hexagon::PS_qtrue: {
1269 case Hexagon::PS_qfalse: {
1276 case Hexagon::PS_vdd0: {
1284 case Hexagon::PS_vmulw: {
1287 Register Src1Reg =
MI.getOperand(1).getReg();
1288 Register Src2Reg =
MI.getOperand(2).getReg();
1289 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1290 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1291 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1292 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1294 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1298 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1302 MRI.clearKillFlags(Src1SubHi);
1303 MRI.clearKillFlags(Src1SubLo);
1304 MRI.clearKillFlags(Src2SubHi);
1305 MRI.clearKillFlags(Src2SubLo);
1308 case Hexagon::PS_vmulw_acc: {
1311 Register Src1Reg =
MI.getOperand(1).getReg();
1312 Register Src2Reg =
MI.getOperand(2).getReg();
1313 Register Src3Reg =
MI.getOperand(3).getReg();
1314 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1315 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1316 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1317 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1318 Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1319 Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1321 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1326 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1331 MRI.clearKillFlags(Src1SubHi);
1332 MRI.clearKillFlags(Src1SubLo);
1333 MRI.clearKillFlags(Src2SubHi);
1334 MRI.clearKillFlags(Src2SubLo);
1335 MRI.clearKillFlags(Src3SubHi);
1336 MRI.clearKillFlags(Src3SubLo);
1339 case Hexagon::PS_pselect: {
1354 .
addReg(Pu, (Rd == Rt) ? K1 : 0)
1363 case Hexagon::PS_vselect: {
1375 unsigned S = Op0.
getReg() != Op3.
getReg() ? PState & ~RegState::Kill
1396 case Hexagon::PS_wselect: {
1408 unsigned S = Op0.
getReg() != Op3.
getReg() ? PState & ~RegState::Kill
1436 case Hexagon::PS_crash: {
1453 OS <<
"MisalignedCrash";
1457 static const CrashPseudoSourceValue CrashPSV(MF.
getTarget());
1469 case Hexagon::PS_tailcall_i:
1470 MI.setDesc(
get(Hexagon::J2_jump));
1472 case Hexagon::PS_tailcall_r:
1473 case Hexagon::PS_jmpret:
1474 MI.setDesc(
get(Hexagon::J2_jumpr));
1476 case Hexagon::PS_jmprett:
1477 MI.setDesc(
get(Hexagon::J2_jumprt));
1479 case Hexagon::PS_jmpretf:
1480 MI.setDesc(
get(Hexagon::J2_jumprf));
1482 case Hexagon::PS_jmprettnewpt:
1483 MI.setDesc(
get(Hexagon::J2_jumprtnewpt));
1485 case Hexagon::PS_jmpretfnewpt:
1486 MI.setDesc(
get(Hexagon::J2_jumprfnewpt));
1488 case Hexagon::PS_jmprettnew:
1489 MI.setDesc(
get(Hexagon::J2_jumprtnew));
1491 case Hexagon::PS_jmpretfnew:
1492 MI.setDesc(
get(Hexagon::J2_jumprfnew));
1495 case Hexagon::PS_loadrub_pci:
1496 return RealCirc(Hexagon::L2_loadrub_pci,
true, 4);
1497 case Hexagon::PS_loadrb_pci:
1498 return RealCirc(Hexagon::L2_loadrb_pci,
true, 4);
1499 case Hexagon::PS_loadruh_pci:
1500 return RealCirc(Hexagon::L2_loadruh_pci,
true, 4);
1501 case Hexagon::PS_loadrh_pci:
1502 return RealCirc(Hexagon::L2_loadrh_pci,
true, 4);
1503 case Hexagon::PS_loadri_pci:
1504 return RealCirc(Hexagon::L2_loadri_pci,
true, 4);
1505 case Hexagon::PS_loadrd_pci:
1506 return RealCirc(Hexagon::L2_loadrd_pci,
true, 4);
1507 case Hexagon::PS_loadrub_pcr:
1508 return RealCirc(Hexagon::L2_loadrub_pcr,
false, 3);
1509 case Hexagon::PS_loadrb_pcr:
1510 return RealCirc(Hexagon::L2_loadrb_pcr,
false, 3);
1511 case Hexagon::PS_loadruh_pcr:
1512 return RealCirc(Hexagon::L2_loadruh_pcr,
false, 3);
1513 case Hexagon::PS_loadrh_pcr:
1514 return RealCirc(Hexagon::L2_loadrh_pcr,
false, 3);
1515 case Hexagon::PS_loadri_pcr:
1516 return RealCirc(Hexagon::L2_loadri_pcr,
false, 3);
1517 case Hexagon::PS_loadrd_pcr:
1518 return RealCirc(Hexagon::L2_loadrd_pcr,
false, 3);
1519 case Hexagon::PS_storerb_pci:
1520 return RealCirc(Hexagon::S2_storerb_pci,
true, 3);
1521 case Hexagon::PS_storerh_pci:
1522 return RealCirc(Hexagon::S2_storerh_pci,
true, 3);
1523 case Hexagon::PS_storerf_pci:
1524 return RealCirc(Hexagon::S2_storerf_pci,
true, 3);
1525 case Hexagon::PS_storeri_pci:
1526 return RealCirc(Hexagon::S2_storeri_pci,
true, 3);
1527 case Hexagon::PS_storerd_pci:
1528 return RealCirc(Hexagon::S2_storerd_pci,
true, 3);
1529 case Hexagon::PS_storerb_pcr:
1530 return RealCirc(Hexagon::S2_storerb_pcr,
false, 2);
1531 case Hexagon::PS_storerh_pcr:
1532 return RealCirc(Hexagon::S2_storerh_pcr,
false, 2);
1533 case Hexagon::PS_storerf_pcr:
1534 return RealCirc(Hexagon::S2_storerf_pcr,
false, 2);
1535 case Hexagon::PS_storeri_pcr:
1536 return RealCirc(Hexagon::S2_storeri_pcr,
false, 2);
1537 case Hexagon::PS_storerd_pcr:
1538 return RealCirc(Hexagon::S2_storerd_pcr,
false, 2);
1548 unsigned Opc =
MI.getOpcode();
1552 case Hexagon::V6_vgathermh_pseudo:
1554 .
add(
MI.getOperand(2))
1555 .
add(
MI.getOperand(3))
1556 .
add(
MI.getOperand(4));
1558 .
add(
MI.getOperand(0))
1562 return First.getInstrIterator();
1564 case Hexagon::V6_vgathermw_pseudo:
1566 .
add(
MI.getOperand(2))
1567 .
add(
MI.getOperand(3))
1568 .
add(
MI.getOperand(4));
1570 .
add(
MI.getOperand(0))
1574 return First.getInstrIterator();
1576 case Hexagon::V6_vgathermhw_pseudo:
1578 .
add(
MI.getOperand(2))
1579 .
add(
MI.getOperand(3))
1580 .
add(
MI.getOperand(4));
1582 .
add(
MI.getOperand(0))
1586 return First.getInstrIterator();
1588 case Hexagon::V6_vgathermhq_pseudo:
1590 .
add(
MI.getOperand(2))
1591 .
add(
MI.getOperand(3))
1592 .
add(
MI.getOperand(4))
1593 .
add(
MI.getOperand(5));
1595 .
add(
MI.getOperand(0))
1599 return First.getInstrIterator();
1601 case Hexagon::V6_vgathermwq_pseudo:
1603 .
add(
MI.getOperand(2))
1604 .
add(
MI.getOperand(3))
1605 .
add(
MI.getOperand(4))
1606 .
add(
MI.getOperand(5));
1608 .
add(
MI.getOperand(0))
1612 return First.getInstrIterator();
1614 case Hexagon::V6_vgathermhwq_pseudo:
1616 .
add(
MI.getOperand(2))
1617 .
add(
MI.getOperand(3))
1618 .
add(
MI.getOperand(4))
1619 .
add(
MI.getOperand(5));
1621 .
add(
MI.getOperand(0))
1625 return First.getInstrIterator();
1628 return MI.getIterator();
1637 assert(
Cond[0].
isImm() &&
"First entry in the cond vector not imm-val");
1638 unsigned opcode =
Cond[0].getImm();
1644 Cond[0].setImm(NewOpcode);
1678 int Opc =
MI.getOpcode();
1691 unsigned NOp = 0, NumOps =
MI.getNumOperands();
1692 while (NOp < NumOps) {
1694 if (!
Op.isReg() || !
Op.isDef() ||
Op.isImplicit())
1701 unsigned PredRegPos, PredRegFlags;
1702 bool GotPredReg =
getPredReg(
Cond, PredReg, PredRegPos, PredRegFlags);
1705 T.addReg(PredReg, PredRegFlags);
1706 while (NOp < NumOps)
1707 T.add(
MI.getOperand(NOp++));
1709 MI.setDesc(
get(PredOpc));
1710 while (
unsigned n =
MI.getNumOperands())
1711 MI.removeOperand(n-1);
1712 for (
unsigned i = 0, n =
T->getNumOperands(); i < n; ++i)
1713 MI.addOperand(
T->getOperand(i));
1719 MRI.clearKillFlags(PredReg);
1730 std::vector<MachineOperand> &Pred,
1731 bool SkipDead)
const {
1739 if (RC == &Hexagon::PredRegsRegClass) {
1744 }
else if (MO.isRegMask()) {
1745 for (
Register PR : Hexagon::PredRegsRegClass) {
1746 if (!
MI.modifiesRegister(PR, &HRI))
1757 if (!
MI.getDesc().isPredicable())
1767 switch (
MI.getOpcode()) {
1768 case Hexagon::V6_vL32b_ai:
1769 case Hexagon::V6_vL32b_pi:
1770 case Hexagon::V6_vL32b_ppu:
1771 case Hexagon::V6_vL32b_cur_ai:
1772 case Hexagon::V6_vL32b_cur_pi:
1773 case Hexagon::V6_vL32b_cur_ppu:
1774 case Hexagon::V6_vL32b_nt_ai:
1775 case Hexagon::V6_vL32b_nt_pi:
1776 case Hexagon::V6_vL32b_nt_ppu:
1777 case Hexagon::V6_vL32b_tmp_ai:
1778 case Hexagon::V6_vL32b_tmp_pi:
1779 case Hexagon::V6_vL32b_tmp_ppu:
1780 case Hexagon::V6_vL32b_nt_cur_ai:
1781 case Hexagon::V6_vL32b_nt_cur_pi:
1782 case Hexagon::V6_vL32b_nt_cur_ppu:
1783 case Hexagon::V6_vL32b_nt_tmp_ai:
1784 case Hexagon::V6_vL32b_nt_tmp_pi:
1785 case Hexagon::V6_vL32b_nt_tmp_ppu:
1801 if (
MI.isDebugInstr())
1817 if (
MI.getDesc().isTerminator() ||
MI.isPosition())
1821 if (
MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1845 bool atInsnStart =
true;
1848 for (; *Str; ++Str) {
1852 if (atInsnStart && !isSpace(
static_cast<unsigned char>(*Str))) {
1854 atInsnStart =
false;
1858 atInsnStart =
false;
1881 int64_t &
Value)
const {
1882 unsigned Opc =
MI.getOpcode();
1886 case Hexagon::C2_cmpeq:
1887 case Hexagon::C2_cmpeqp:
1888 case Hexagon::C2_cmpgt:
1889 case Hexagon::C2_cmpgtp:
1890 case Hexagon::C2_cmpgtu:
1891 case Hexagon::C2_cmpgtup:
1892 case Hexagon::C4_cmpneq:
1893 case Hexagon::C4_cmplte:
1894 case Hexagon::C4_cmplteu:
1895 case Hexagon::C2_cmpeqi:
1896 case Hexagon::C2_cmpgti:
1897 case Hexagon::C2_cmpgtui:
1898 case Hexagon::C4_cmpneqi:
1899 case Hexagon::C4_cmplteui:
1900 case Hexagon::C4_cmpltei:
1901 SrcReg =
MI.getOperand(1).getReg();
1904 case Hexagon::A4_cmpbeq:
1905 case Hexagon::A4_cmpbgt:
1906 case Hexagon::A4_cmpbgtu:
1907 case Hexagon::A4_cmpbeqi:
1908 case Hexagon::A4_cmpbgti:
1909 case Hexagon::A4_cmpbgtui:
1910 SrcReg =
MI.getOperand(1).getReg();
1913 case Hexagon::A4_cmpheq:
1914 case Hexagon::A4_cmphgt:
1915 case Hexagon::A4_cmphgtu:
1916 case Hexagon::A4_cmpheqi:
1917 case Hexagon::A4_cmphgti:
1918 case Hexagon::A4_cmphgtui:
1919 SrcReg =
MI.getOperand(1).getReg();
1926 case Hexagon::C2_cmpeq:
1927 case Hexagon::C2_cmpeqp:
1928 case Hexagon::C2_cmpgt:
1929 case Hexagon::C2_cmpgtp:
1930 case Hexagon::C2_cmpgtu:
1931 case Hexagon::C2_cmpgtup:
1932 case Hexagon::A4_cmpbeq:
1933 case Hexagon::A4_cmpbgt:
1934 case Hexagon::A4_cmpbgtu:
1935 case Hexagon::A4_cmpheq:
1936 case Hexagon::A4_cmphgt:
1937 case Hexagon::A4_cmphgtu:
1938 case Hexagon::C4_cmpneq:
1939 case Hexagon::C4_cmplte:
1940 case Hexagon::C4_cmplteu:
1941 SrcReg2 =
MI.getOperand(2).getReg();
1945 case Hexagon::C2_cmpeqi:
1946 case Hexagon::C2_cmpgtui:
1947 case Hexagon::C2_cmpgti:
1948 case Hexagon::C4_cmpneqi:
1949 case Hexagon::C4_cmplteui:
1950 case Hexagon::C4_cmpltei:
1951 case Hexagon::A4_cmpbeqi:
1952 case Hexagon::A4_cmpbgti:
1953 case Hexagon::A4_cmpbgtui:
1954 case Hexagon::A4_cmpheqi:
1955 case Hexagon::A4_cmphgti:
1956 case Hexagon::A4_cmphgtui: {
1961 Value =
MI.getOperand(2).getImm();
1971 unsigned *PredCost)
const {
1997 unsigned BasePosA, OffsetPosA;
2005 unsigned BasePosB, OffsetPosB;
2012 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
2030 if (OffsetA > OffsetB) {
2032 return SizeB <= OffDiff;
2034 if (OffsetA < OffsetB) {
2036 return SizeA <= OffDiff;
2046 unsigned BasePos = 0, OffsetPos = 0;
2050 if (OffsetOp.
isImm()) {
2054 }
else if (
MI.getOpcode() == Hexagon::A2_addi) {
2056 if (AddOp.
isImm()) {
2065std::pair<unsigned, unsigned>
2073 using namespace HexagonII;
2075 static const std::pair<unsigned, const char*> Flags[] = {
2076 {MO_PCREL,
"hexagon-pcrel"},
2077 {MO_GOT,
"hexagon-got"},
2078 {MO_LO16,
"hexagon-lo16"},
2079 {MO_HI16,
"hexagon-hi16"},
2080 {MO_GPREL,
"hexagon-gprel"},
2081 {MO_GDGOT,
"hexagon-gdgot"},
2082 {MO_GDPLT,
"hexagon-gdplt"},
2083 {MO_IE,
"hexagon-ie"},
2084 {MO_IEGOT,
"hexagon-iegot"},
2085 {MO_TPREL,
"hexagon-tprel"}
2092 using namespace HexagonII;
2094 static const std::pair<unsigned, const char*> Flags[] = {
2095 {HMOTF_ConstExtended,
"hexagon-ext"}
2103 if (VT == MVT::i1) {
2104 TRC = &Hexagon::PredRegsRegClass;
2105 }
else if (VT == MVT::i32 || VT == MVT::f32) {
2106 TRC = &Hexagon::IntRegsRegClass;
2107 }
else if (VT == MVT::i64 || VT == MVT::f64) {
2108 TRC = &Hexagon::DoubleRegsRegClass;
2132 !
MI.getDesc().mayStore() &&
2133 MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2134 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2179 assert(MO.
isImm() &&
"Extendable operand must be Immediate type");
2183 int32_t SValue =
Value;
2186 return SValue < MinValue || SValue > MaxValue;
2191 return UValue < MinValue || UValue > MaxValue;
2195 switch (
MI.getOpcode()) {
2196 case Hexagon::L4_return:
2197 case Hexagon::L4_return_t:
2198 case Hexagon::L4_return_f:
2199 case Hexagon::L4_return_tnew_pnt:
2200 case Hexagon::L4_return_fnew_pnt:
2201 case Hexagon::L4_return_tnew_pt:
2202 case Hexagon::L4_return_fnew_pt:
2223 for (
auto &RegA : DefsA)
2224 for (
auto &RegB : UsesB) {
2241 switch (
MI.getOpcode()) {
2242 case Hexagon::V6_vL32b_cur_pi:
2243 case Hexagon::V6_vL32b_cur_ai:
2267 return (
Opcode == Hexagon::ENDLOOP0 ||
2268 Opcode == Hexagon::ENDLOOP1);
2293 switch (
MI.getOpcode()) {
2295 case Hexagon::PS_fi:
2296 case Hexagon::PS_fia:
2331 if (!
I.mayLoad() && !
I.mayStore())
2337 switch (
MI.getOpcode()) {
2338 case Hexagon::J2_callr:
2339 case Hexagon::J2_callrf:
2340 case Hexagon::J2_callrt:
2341 case Hexagon::PS_call_nr:
2348 switch (
MI.getOpcode()) {
2349 case Hexagon::L4_return:
2350 case Hexagon::L4_return_t:
2351 case Hexagon::L4_return_f:
2352 case Hexagon::L4_return_fnew_pnt:
2353 case Hexagon::L4_return_fnew_pt:
2354 case Hexagon::L4_return_tnew_pnt:
2355 case Hexagon::L4_return_tnew_pt:
2362 switch (
MI.getOpcode()) {
2363 case Hexagon::J2_jumpr:
2364 case Hexagon::J2_jumprt:
2365 case Hexagon::J2_jumprf:
2366 case Hexagon::J2_jumprtnewpt:
2367 case Hexagon::J2_jumprfnewpt:
2368 case Hexagon::J2_jumprtnew:
2369 case Hexagon::J2_jumprfnew:
2380 unsigned offset)
const {
2384 return isInt<11>(offset);
2386 switch (
MI.getOpcode()) {
2390 case Hexagon::J2_jump:
2391 case Hexagon::J2_call:
2392 case Hexagon::PS_call_nr:
2393 return isInt<24>(offset);
2394 case Hexagon::J2_jumpt:
2395 case Hexagon::J2_jumpf:
2396 case Hexagon::J2_jumptnew:
2397 case Hexagon::J2_jumptnewpt:
2398 case Hexagon::J2_jumpfnew:
2399 case Hexagon::J2_jumpfnewpt:
2400 case Hexagon::J2_callt:
2401 case Hexagon::J2_callf:
2402 return isInt<17>(offset);
2403 case Hexagon::J2_loop0i:
2404 case Hexagon::J2_loop0iext:
2405 case Hexagon::J2_loop0r:
2406 case Hexagon::J2_loop0rext:
2407 case Hexagon::J2_loop1i:
2408 case Hexagon::J2_loop1iext:
2409 case Hexagon::J2_loop1r:
2410 case Hexagon::J2_loop1rext:
2411 return isInt<9>(offset);
2413 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2414 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2415 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2416 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2417 return isInt<11>(offset);
2429 return Opcode == Hexagon::J2_loop0i ||
2430 Opcode == Hexagon::J2_loop0r ||
2431 Opcode == Hexagon::J2_loop0iext ||
2432 Opcode == Hexagon::J2_loop0rext ||
2433 Opcode == Hexagon::J2_loop1i ||
2434 Opcode == Hexagon::J2_loop1r ||
2435 Opcode == Hexagon::J2_loop1iext ||
2436 Opcode == Hexagon::J2_loop1rext;
2440 switch (
MI.getOpcode()) {
2441 default:
return false;
2442 case Hexagon::L4_iadd_memopw_io:
2443 case Hexagon::L4_isub_memopw_io:
2444 case Hexagon::L4_add_memopw_io:
2445 case Hexagon::L4_sub_memopw_io:
2446 case Hexagon::L4_and_memopw_io:
2447 case Hexagon::L4_or_memopw_io:
2448 case Hexagon::L4_iadd_memoph_io:
2449 case Hexagon::L4_isub_memoph_io:
2450 case Hexagon::L4_add_memoph_io:
2451 case Hexagon::L4_sub_memoph_io:
2452 case Hexagon::L4_and_memoph_io:
2453 case Hexagon::L4_or_memoph_io:
2454 case Hexagon::L4_iadd_memopb_io:
2455 case Hexagon::L4_isub_memopb_io:
2456 case Hexagon::L4_add_memopb_io:
2457 case Hexagon::L4_sub_memopb_io:
2458 case Hexagon::L4_and_memopb_io:
2459 case Hexagon::L4_or_memopb_io:
2460 case Hexagon::L4_ior_memopb_io:
2461 case Hexagon::L4_ior_memoph_io:
2462 case Hexagon::L4_ior_memopw_io:
2463 case Hexagon::L4_iand_memopb_io:
2464 case Hexagon::L4_iand_memoph_io:
2465 case Hexagon::L4_iand_memopw_io:
2505 unsigned OperandNum)
const {
2555 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2556 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2557 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2558 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2562 switch (
MI.getOpcode()) {
2564 case Hexagon::L2_loadrb_io:
2565 case Hexagon::L4_loadrb_ur:
2566 case Hexagon::L4_loadrb_ap:
2567 case Hexagon::L2_loadrb_pr:
2568 case Hexagon::L2_loadrb_pbr:
2569 case Hexagon::L2_loadrb_pi:
2570 case Hexagon::L2_loadrb_pci:
2571 case Hexagon::L2_loadrb_pcr:
2572 case Hexagon::L2_loadbsw2_io:
2573 case Hexagon::L4_loadbsw2_ur:
2574 case Hexagon::L4_loadbsw2_ap:
2575 case Hexagon::L2_loadbsw2_pr:
2576 case Hexagon::L2_loadbsw2_pbr:
2577 case Hexagon::L2_loadbsw2_pi:
2578 case Hexagon::L2_loadbsw2_pci:
2579 case Hexagon::L2_loadbsw2_pcr:
2580 case Hexagon::L2_loadbsw4_io:
2581 case Hexagon::L4_loadbsw4_ur:
2582 case Hexagon::L4_loadbsw4_ap:
2583 case Hexagon::L2_loadbsw4_pr:
2584 case Hexagon::L2_loadbsw4_pbr:
2585 case Hexagon::L2_loadbsw4_pi:
2586 case Hexagon::L2_loadbsw4_pci:
2587 case Hexagon::L2_loadbsw4_pcr:
2588 case Hexagon::L4_loadrb_rr:
2589 case Hexagon::L2_ploadrbt_io:
2590 case Hexagon::L2_ploadrbt_pi:
2591 case Hexagon::L2_ploadrbf_io:
2592 case Hexagon::L2_ploadrbf_pi:
2593 case Hexagon::L2_ploadrbtnew_io:
2594 case Hexagon::L2_ploadrbfnew_io:
2595 case Hexagon::L4_ploadrbt_rr:
2596 case Hexagon::L4_ploadrbf_rr:
2597 case Hexagon::L4_ploadrbtnew_rr:
2598 case Hexagon::L4_ploadrbfnew_rr:
2599 case Hexagon::L2_ploadrbtnew_pi:
2600 case Hexagon::L2_ploadrbfnew_pi:
2601 case Hexagon::L4_ploadrbt_abs:
2602 case Hexagon::L4_ploadrbf_abs:
2603 case Hexagon::L4_ploadrbtnew_abs:
2604 case Hexagon::L4_ploadrbfnew_abs:
2605 case Hexagon::L2_loadrbgp:
2607 case Hexagon::L2_loadrh_io:
2608 case Hexagon::L4_loadrh_ur:
2609 case Hexagon::L4_loadrh_ap:
2610 case Hexagon::L2_loadrh_pr:
2611 case Hexagon::L2_loadrh_pbr:
2612 case Hexagon::L2_loadrh_pi:
2613 case Hexagon::L2_loadrh_pci:
2614 case Hexagon::L2_loadrh_pcr:
2615 case Hexagon::L4_loadrh_rr:
2616 case Hexagon::L2_ploadrht_io:
2617 case Hexagon::L2_ploadrht_pi:
2618 case Hexagon::L2_ploadrhf_io:
2619 case Hexagon::L2_ploadrhf_pi:
2620 case Hexagon::L2_ploadrhtnew_io:
2621 case Hexagon::L2_ploadrhfnew_io:
2622 case Hexagon::L4_ploadrht_rr:
2623 case Hexagon::L4_ploadrhf_rr:
2624 case Hexagon::L4_ploadrhtnew_rr:
2625 case Hexagon::L4_ploadrhfnew_rr:
2626 case Hexagon::L2_ploadrhtnew_pi:
2627 case Hexagon::L2_ploadrhfnew_pi:
2628 case Hexagon::L4_ploadrht_abs:
2629 case Hexagon::L4_ploadrhf_abs:
2630 case Hexagon::L4_ploadrhtnew_abs:
2631 case Hexagon::L4_ploadrhfnew_abs:
2632 case Hexagon::L2_loadrhgp:
2645 switch (
MI.getOpcode()) {
2646 case Hexagon::STriw_pred:
2647 case Hexagon::LDriw_pred:
2658 for (
auto &
Op :
MI.operands())
2659 if (
Op.isGlobal() ||
Op.isSymbol())
2666 unsigned SchedClass =
MI.getDesc().getSchedClass();
2667 return is_TC1(SchedClass);
2671 unsigned SchedClass =
MI.getDesc().getSchedClass();
2672 return is_TC2(SchedClass);
2676 unsigned SchedClass =
MI.getDesc().getSchedClass();
2681 unsigned SchedClass =
MI.getDesc().getSchedClass();
2692 for (
int I = 0;
I <
N;
I++)
2697 if (MI2.
getOpcode() == Hexagon::V6_vS32b_pi)
2729 return isInt<4>(Count);
2739 return isInt<3>(Count);
2758 case Hexagon::PS_vstorerq_ai:
2759 case Hexagon::PS_vstorerv_ai:
2760 case Hexagon::PS_vstorerw_ai:
2761 case Hexagon::PS_vstorerw_nt_ai:
2762 case Hexagon::PS_vloadrq_ai:
2763 case Hexagon::PS_vloadrv_ai:
2764 case Hexagon::PS_vloadrw_ai:
2765 case Hexagon::PS_vloadrw_nt_ai:
2766 case Hexagon::V6_vL32b_ai:
2767 case Hexagon::V6_vS32b_ai:
2768 case Hexagon::V6_vS32b_qpred_ai:
2769 case Hexagon::V6_vS32b_nqpred_ai:
2770 case Hexagon::V6_vL32b_nt_ai:
2771 case Hexagon::V6_vS32b_nt_ai:
2772 case Hexagon::V6_vL32Ub_ai:
2773 case Hexagon::V6_vS32Ub_ai:
2774 case Hexagon::V6_vgathermh_pseudo:
2775 case Hexagon::V6_vgathermw_pseudo:
2776 case Hexagon::V6_vgathermhw_pseudo:
2777 case Hexagon::V6_vgathermhq_pseudo:
2778 case Hexagon::V6_vgathermwq_pseudo:
2779 case Hexagon::V6_vgathermhwq_pseudo: {
2780 unsigned VectorSize =
TRI->getSpillSize(Hexagon::HvxVRRegClass);
2782 if (
Offset & (VectorSize-1))
2787 case Hexagon::J2_loop0i:
2788 case Hexagon::J2_loop1i:
2789 return isUInt<10>(
Offset);
2791 case Hexagon::S4_storeirb_io:
2792 case Hexagon::S4_storeirbt_io:
2793 case Hexagon::S4_storeirbf_io:
2794 return isUInt<6>(
Offset);
2796 case Hexagon::S4_storeirh_io:
2797 case Hexagon::S4_storeirht_io:
2798 case Hexagon::S4_storeirhf_io:
2799 return isShiftedUInt<6,1>(
Offset);
2801 case Hexagon::S4_storeiri_io:
2802 case Hexagon::S4_storeirit_io:
2803 case Hexagon::S4_storeirif_io:
2804 return isShiftedUInt<6,2>(
Offset);
2806 case Hexagon::A4_cmpbeqi:
2807 return isUInt<8>(
Offset);
2808 case Hexagon::A4_cmpbgti:
2816 case Hexagon::L2_loadri_io:
2817 case Hexagon::S2_storeri_io:
2821 case Hexagon::L2_loadrd_io:
2822 case Hexagon::S2_storerd_io:
2826 case Hexagon::L2_loadrh_io:
2827 case Hexagon::L2_loadruh_io:
2828 case Hexagon::S2_storerh_io:
2829 case Hexagon::S2_storerf_io:
2833 case Hexagon::L2_loadrb_io:
2834 case Hexagon::L2_loadrub_io:
2835 case Hexagon::S2_storerb_io:
2839 case Hexagon::A2_addi:
2843 case Hexagon::L4_iadd_memopw_io:
2844 case Hexagon::L4_isub_memopw_io:
2845 case Hexagon::L4_add_memopw_io:
2846 case Hexagon::L4_sub_memopw_io:
2847 case Hexagon::L4_iand_memopw_io:
2848 case Hexagon::L4_ior_memopw_io:
2849 case Hexagon::L4_and_memopw_io:
2850 case Hexagon::L4_or_memopw_io:
2853 case Hexagon::L4_iadd_memoph_io:
2854 case Hexagon::L4_isub_memoph_io:
2855 case Hexagon::L4_add_memoph_io:
2856 case Hexagon::L4_sub_memoph_io:
2857 case Hexagon::L4_iand_memoph_io:
2858 case Hexagon::L4_ior_memoph_io:
2859 case Hexagon::L4_and_memoph_io:
2860 case Hexagon::L4_or_memoph_io:
2863 case Hexagon::L4_iadd_memopb_io:
2864 case Hexagon::L4_isub_memopb_io:
2865 case Hexagon::L4_add_memopb_io:
2866 case Hexagon::L4_sub_memopb_io:
2867 case Hexagon::L4_iand_memopb_io:
2868 case Hexagon::L4_ior_memopb_io:
2869 case Hexagon::L4_and_memopb_io:
2870 case Hexagon::L4_or_memopb_io:
2875 case Hexagon::STriw_pred:
2876 case Hexagon::LDriw_pred:
2877 case Hexagon::STriw_ctr:
2878 case Hexagon::LDriw_ctr:
2881 case Hexagon::PS_fi:
2882 case Hexagon::PS_fia:
2883 case Hexagon::INLINEASM:
2886 case Hexagon::L2_ploadrbt_io:
2887 case Hexagon::L2_ploadrbf_io:
2888 case Hexagon::L2_ploadrubt_io:
2889 case Hexagon::L2_ploadrubf_io:
2890 case Hexagon::S2_pstorerbt_io:
2891 case Hexagon::S2_pstorerbf_io:
2892 return isUInt<6>(
Offset);
2894 case Hexagon::L2_ploadrht_io:
2895 case Hexagon::L2_ploadrhf_io:
2896 case Hexagon::L2_ploadruht_io:
2897 case Hexagon::L2_ploadruhf_io:
2898 case Hexagon::S2_pstorerht_io:
2899 case Hexagon::S2_pstorerhf_io:
2900 return isShiftedUInt<6,1>(
Offset);
2902 case Hexagon::L2_ploadrit_io:
2903 case Hexagon::L2_ploadrif_io:
2904 case Hexagon::S2_pstorerit_io:
2905 case Hexagon::S2_pstorerif_io:
2906 return isShiftedUInt<6,2>(
Offset);
2908 case Hexagon::L2_ploadrdt_io:
2909 case Hexagon::L2_ploadrdf_io:
2910 case Hexagon::S2_pstorerdt_io:
2911 case Hexagon::S2_pstorerdf_io:
2912 return isShiftedUInt<6,3>(
Offset);
2914 case Hexagon::L2_loadbsw2_io:
2915 case Hexagon::L2_loadbzw2_io:
2916 return isShiftedInt<11,1>(
Offset);
2918 case Hexagon::L2_loadbsw4_io:
2919 case Hexagon::L2_loadbzw4_io:
2920 return isShiftedInt<11,2>(
Offset);
2926 "Please define it in the above switch statement!");
2956 switch (
MI.getOpcode()) {
2958 case Hexagon::L2_loadrub_io:
2959 case Hexagon::L4_loadrub_ur:
2960 case Hexagon::L4_loadrub_ap:
2961 case Hexagon::L2_loadrub_pr:
2962 case Hexagon::L2_loadrub_pbr:
2963 case Hexagon::L2_loadrub_pi:
2964 case Hexagon::L2_loadrub_pci:
2965 case Hexagon::L2_loadrub_pcr:
2966 case Hexagon::L2_loadbzw2_io:
2967 case Hexagon::L4_loadbzw2_ur:
2968 case Hexagon::L4_loadbzw2_ap:
2969 case Hexagon::L2_loadbzw2_pr:
2970 case Hexagon::L2_loadbzw2_pbr:
2971 case Hexagon::L2_loadbzw2_pi:
2972 case Hexagon::L2_loadbzw2_pci:
2973 case Hexagon::L2_loadbzw2_pcr:
2974 case Hexagon::L2_loadbzw4_io:
2975 case Hexagon::L4_loadbzw4_ur:
2976 case Hexagon::L4_loadbzw4_ap:
2977 case Hexagon::L2_loadbzw4_pr:
2978 case Hexagon::L2_loadbzw4_pbr:
2979 case Hexagon::L2_loadbzw4_pi:
2980 case Hexagon::L2_loadbzw4_pci:
2981 case Hexagon::L2_loadbzw4_pcr:
2982 case Hexagon::L4_loadrub_rr:
2983 case Hexagon::L2_ploadrubt_io:
2984 case Hexagon::L2_ploadrubt_pi:
2985 case Hexagon::L2_ploadrubf_io:
2986 case Hexagon::L2_ploadrubf_pi:
2987 case Hexagon::L2_ploadrubtnew_io:
2988 case Hexagon::L2_ploadrubfnew_io:
2989 case Hexagon::L4_ploadrubt_rr:
2990 case Hexagon::L4_ploadrubf_rr:
2991 case Hexagon::L4_ploadrubtnew_rr:
2992 case Hexagon::L4_ploadrubfnew_rr:
2993 case Hexagon::L2_ploadrubtnew_pi:
2994 case Hexagon::L2_ploadrubfnew_pi:
2995 case Hexagon::L4_ploadrubt_abs:
2996 case Hexagon::L4_ploadrubf_abs:
2997 case Hexagon::L4_ploadrubtnew_abs:
2998 case Hexagon::L4_ploadrubfnew_abs:
2999 case Hexagon::L2_loadrubgp:
3001 case Hexagon::L2_loadruh_io:
3002 case Hexagon::L4_loadruh_ur:
3003 case Hexagon::L4_loadruh_ap:
3004 case Hexagon::L2_loadruh_pr:
3005 case Hexagon::L2_loadruh_pbr:
3006 case Hexagon::L2_loadruh_pi:
3007 case Hexagon::L2_loadruh_pci:
3008 case Hexagon::L2_loadruh_pcr:
3009 case Hexagon::L4_loadruh_rr:
3010 case Hexagon::L2_ploadruht_io:
3011 case Hexagon::L2_ploadruht_pi:
3012 case Hexagon::L2_ploadruhf_io:
3013 case Hexagon::L2_ploadruhf_pi:
3014 case Hexagon::L2_ploadruhtnew_io:
3015 case Hexagon::L2_ploadruhfnew_io:
3016 case Hexagon::L4_ploadruht_rr:
3017 case Hexagon::L4_ploadruhf_rr:
3018 case Hexagon::L4_ploadruhtnew_rr:
3019 case Hexagon::L4_ploadruhfnew_rr:
3020 case Hexagon::L2_ploadruhtnew_pi:
3021 case Hexagon::L2_ploadruhfnew_pi:
3022 case Hexagon::L4_ploadruht_abs:
3023 case Hexagon::L4_ploadruhf_abs:
3024 case Hexagon::L4_ploadruhtnew_abs:
3025 case Hexagon::L4_ploadruhfnew_abs:
3026 case Hexagon::L2_loadruhgp:
3045 int64_t &
Offset,
bool &OffsetIsScalable,
unsigned &Width,
3047 OffsetIsScalable =
false;
3049 if (!BaseOp || !BaseOp->
isReg())
3058 if (Second.
mayStore() &&
First.getOpcode() == Hexagon::S2_allocframe) {
3060 if (
Op.isReg() &&
Op.isUse() &&
Op.getReg() == Hexagon::R29)
3070 if (!Stored.
isReg())
3072 for (
unsigned i = 0, e =
First.getNumOperands(); i < e; ++i) {
3074 if (
Op.isReg() &&
Op.isDef() &&
Op.getReg() == Stored.
getReg())
3083 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
3099 if (Hexagon::getRegForm(
MI.getOpcode()) >= 0)
3102 if (
MI.getDesc().mayLoad() ||
MI.getDesc().mayStore()) {
3109 NonExtOpcode = Hexagon::changeAddrMode_abs_io(
MI.getOpcode());
3115 NonExtOpcode = Hexagon::changeAddrMode_io_rr(
MI.getOpcode());
3118 NonExtOpcode = Hexagon::changeAddrMode_ur_rr(
MI.getOpcode());
3123 if (NonExtOpcode < 0)
3131 return Hexagon::getRealHWInstr(
MI.getOpcode(),
3132 Hexagon::InstrType_Pseudo) >= 0;
3189 if (!MII->isBundle())
3192 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3204 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3206 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3212 switch (
MI.getOpcode()) {
3213 case Hexagon::A4_addp_c:
3214 case Hexagon::A4_subp_c:
3215 case Hexagon::A4_tlbmatch:
3216 case Hexagon::A5_ACS:
3217 case Hexagon::F2_sfinvsqrta:
3218 case Hexagon::F2_sfrecipa:
3219 case Hexagon::J2_endloop0:
3220 case Hexagon::J2_endloop01:
3221 case Hexagon::J2_ploop1si:
3222 case Hexagon::J2_ploop1sr:
3223 case Hexagon::J2_ploop2si:
3224 case Hexagon::J2_ploop2sr:
3225 case Hexagon::J2_ploop3si:
3226 case Hexagon::J2_ploop3sr:
3227 case Hexagon::S2_cabacdecbin:
3228 case Hexagon::S2_storew_locked:
3229 case Hexagon::S4_stored_locked:
3236 return Opcode == Hexagon::J2_jumpt ||
3237 Opcode == Hexagon::J2_jumptpt ||
3238 Opcode == Hexagon::J2_jumpf ||
3239 Opcode == Hexagon::J2_jumpfpt ||
3240 Opcode == Hexagon::J2_jumptnew ||
3241 Opcode == Hexagon::J2_jumpfnew ||
3242 Opcode == Hexagon::J2_jumptnewpt ||
3243 Opcode == Hexagon::J2_jumpfnewpt;
3263 unsigned &AccessSize)
const {
3272 unsigned BasePos = 0, OffsetPos = 0;
3282 if (!OffsetOp.
isImm())
3295 unsigned &BasePos,
unsigned &OffsetPos)
const {
3303 }
else if (
MI.mayStore()) {
3306 }
else if (
MI.mayLoad()) {
3321 if (!
MI.getOperand(BasePos).isReg() || !
MI.getOperand(OffsetPos).isImm())
3360 while (
I->isDebugInstr()) {
3365 if (!isUnpredicatedTerminator(*
I))
3374 if (&*
I != LastInst && !
I->isBundle() && isUnpredicatedTerminator(*
I)) {
3375 if (!SecondLastInst) {
3376 SecondLastInst = &*
I;
3398 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3400 switch (
MI.getOpcode()) {
3409 case Hexagon::C2_cmpeq:
3410 case Hexagon::C2_cmpgt:
3411 case Hexagon::C2_cmpgtu:
3412 DstReg =
MI.getOperand(0).getReg();
3413 Src1Reg =
MI.getOperand(1).getReg();
3414 Src2Reg =
MI.getOperand(2).getReg();
3415 if (Hexagon::PredRegsRegClass.
contains(DstReg) &&
3416 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3420 case Hexagon::C2_cmpeqi:
3421 case Hexagon::C2_cmpgti:
3422 case Hexagon::C2_cmpgtui:
3424 DstReg =
MI.getOperand(0).getReg();
3425 SrcReg =
MI.getOperand(1).getReg();
3426 if (Hexagon::PredRegsRegClass.
contains(DstReg) &&
3427 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3429 ((isUInt<5>(
MI.getOperand(2).getImm())) ||
3430 (
MI.getOperand(2).getImm() == -1)))
3433 case Hexagon::A2_tfr:
3435 DstReg =
MI.getOperand(0).getReg();
3436 SrcReg =
MI.getOperand(1).getReg();
3440 case Hexagon::A2_tfrsi:
3444 DstReg =
MI.getOperand(0).getReg();
3448 case Hexagon::S2_tstbit_i:
3449 DstReg =
MI.getOperand(0).getReg();
3450 Src1Reg =
MI.getOperand(1).getReg();
3451 if (Hexagon::PredRegsRegClass.
contains(DstReg) &&
3452 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3453 MI.getOperand(2).isImm() &&
3461 case Hexagon::J2_jumptnew:
3462 case Hexagon::J2_jumpfnew:
3463 case Hexagon::J2_jumptnewpt:
3464 case Hexagon::J2_jumpfnewpt:
3465 Src1Reg =
MI.getOperand(0).getReg();
3466 if (Hexagon::PredRegsRegClass.
contains(Src1Reg) &&
3467 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3474 case Hexagon::J2_jump:
3475 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3476 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3488 if ((GA.
getOpcode() != Hexagon::C2_cmpeqi) ||
3489 (GB.
getOpcode() != Hexagon::J2_jumptnew))
3494 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3502 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3503 : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3506 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3507 : Hexagon::J4_cmpeqi_tp1_jump_nt;
3512 bool ForBigCore)
const {
3520 static const std::map<unsigned, unsigned> DupMap = {
3521 {Hexagon::A2_add, Hexagon::dup_A2_add},
3522 {Hexagon::A2_addi, Hexagon::dup_A2_addi},
3523 {Hexagon::A2_andir, Hexagon::dup_A2_andir},
3524 {Hexagon::A2_combineii, Hexagon::dup_A2_combineii},
3525 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb},
3526 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth},
3527 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr},
3528 {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi},
3529 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb},
3530 {Hexagon::A2_zxth, Hexagon::dup_A2_zxth},
3531 {Hexagon::A4_combineii, Hexagon::dup_A4_combineii},
3532 {Hexagon::A4_combineir, Hexagon::dup_A4_combineir},
3533 {Hexagon::A4_combineri, Hexagon::dup_A4_combineri},
3534 {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif},
3535 {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit},
3536 {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif},
3537 {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit},
3538 {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi},
3539 {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe},
3540 {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io},
3541 {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io},
3542 {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io},
3543 {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io},
3544 {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io},
3545 {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io},
3546 {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe},
3547 {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io},
3548 {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io},
3549 {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io},
3550 {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io},
3551 {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io},
3552 {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io},
3554 unsigned OpNum =
MI.getOpcode();
3557 auto Iter = DupMap.find(OpNum);
3558 if (Iter != DupMap.end())
3559 return Iter->second;
3561 for (
const auto &Iter : DupMap)
3562 if (Iter.second == OpNum)
3569 enum Hexagon::PredSense inPredSense;
3570 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3571 Hexagon::PredSense_true;
3572 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3573 if (CondOpcode >= 0)
3581 switch (
MI.getOpcode()) {
3583 case Hexagon::V6_vL32b_pi:
3584 return Hexagon::V6_vL32b_cur_pi;
3585 case Hexagon::V6_vL32b_ai:
3586 return Hexagon::V6_vL32b_cur_ai;
3587 case Hexagon::V6_vL32b_nt_pi:
3588 return Hexagon::V6_vL32b_nt_cur_pi;
3589 case Hexagon::V6_vL32b_nt_ai:
3590 return Hexagon::V6_vL32b_nt_cur_ai;
3591 case Hexagon::V6_vL32b_ppu:
3592 return Hexagon::V6_vL32b_cur_ppu;
3593 case Hexagon::V6_vL32b_nt_ppu:
3594 return Hexagon::V6_vL32b_nt_cur_ppu;
3601 switch (
MI.getOpcode()) {
3603 case Hexagon::V6_vL32b_cur_pi:
3604 return Hexagon::V6_vL32b_pi;
3605 case Hexagon::V6_vL32b_cur_ai:
3606 return Hexagon::V6_vL32b_ai;
3607 case Hexagon::V6_vL32b_nt_cur_pi:
3608 return Hexagon::V6_vL32b_nt_pi;
3609 case Hexagon::V6_vL32b_nt_cur_ai:
3610 return Hexagon::V6_vL32b_nt_ai;
3611 case Hexagon::V6_vL32b_cur_ppu:
3612 return Hexagon::V6_vL32b_ppu;
3613 case Hexagon::V6_vL32b_nt_cur_ppu:
3614 return Hexagon::V6_vL32b_nt_ppu;
3702 int NVOpcode = Hexagon::getNewValueOpcode(
MI.getOpcode());
3706 switch (
MI.getOpcode()) {
3709 std::to_string(
MI.getOpcode()));
3710 case Hexagon::S4_storerb_ur:
3711 return Hexagon::S4_storerbnew_ur;
3713 case Hexagon::S2_storerb_pci:
3714 return Hexagon::S2_storerb_pci;
3716 case Hexagon::S2_storeri_pci:
3717 return Hexagon::S2_storeri_pci;
3719 case Hexagon::S2_storerh_pci:
3720 return Hexagon::S2_storerh_pci;
3722 case Hexagon::S2_storerd_pci:
3723 return Hexagon::S2_storerd_pci;
3725 case Hexagon::S2_storerf_pci:
3726 return Hexagon::S2_storerf_pci;
3728 case Hexagon::V6_vS32b_ai:
3729 return Hexagon::V6_vS32b_new_ai;
3731 case Hexagon::V6_vS32b_pi:
3732 return Hexagon::V6_vS32b_new_pi;
3757 if (BrTarget.
isMBB()) {
3759 Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3772 bool SawCond =
false, Bad =
false;
3776 if (
I.isConditionalBranch()) {
3783 if (
I.isUnconditionalBranch() && !SawCond) {
3791 if (NextIt ==
B.instr_end()) {
3794 if (!
B.isLayoutSuccessor(SB))
3796 Taken = getEdgeProbability(Src, SB) < OneHalf;
3800 assert(NextIt->isUnconditionalBranch());
3809 Taken =
BT && getEdgeProbability(Src,
BT) < OneHalf;
3816 switch (
MI.getOpcode()) {
3817 case Hexagon::J2_jumpt:
3818 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3819 case Hexagon::J2_jumpf:
3820 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3830 switch (
MI.getOpcode()) {
3832 case Hexagon::J2_jumpt:
3833 case Hexagon::J2_jumpf:
3837 int NewOpcode = Hexagon::getPredNewOpcode(
MI.getOpcode());
3844 int NewOp =
MI.getOpcode();
3846 NewOp = Hexagon::getPredOldOpcode(NewOp);
3850 if (!Subtarget.hasFeature(Hexagon::ArchV60)) {
3852 case Hexagon::J2_jumptpt:
3853 NewOp = Hexagon::J2_jumpt;
3855 case Hexagon::J2_jumpfpt:
3856 NewOp = Hexagon::J2_jumpf;
3858 case Hexagon::J2_jumprtpt:
3859 NewOp = Hexagon::J2_jumprt;
3861 case Hexagon::J2_jumprfpt:
3862 NewOp = Hexagon::J2_jumprf;
3867 "Couldn't change predicate new instruction to its old form.");
3871 NewOp = Hexagon::getNonNVStore(NewOp);
3872 assert(NewOp >= 0 &&
"Couldn't change new-value store to its old form.");
3880 case Hexagon::J2_jumpfpt:
3881 return Hexagon::J2_jumpf;
3882 case Hexagon::J2_jumptpt:
3883 return Hexagon::J2_jumpt;
3884 case Hexagon::J2_jumprfpt:
3885 return Hexagon::J2_jumprf;
3886 case Hexagon::J2_jumprtpt:
3887 return Hexagon::J2_jumprt;
3896 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3899 switch (
MI.getOpcode()) {
3907 case Hexagon::L2_loadri_io:
3908 case Hexagon::dup_L2_loadri_io:
3909 DstReg =
MI.getOperand(0).getReg();
3910 SrcReg =
MI.getOperand(1).getReg();
3914 if (Hexagon::IntRegsRegClass.
contains(SrcReg) &&
3916 MI.getOperand(2).isImm() &&
3917 isShiftedUInt<5,2>(
MI.getOperand(2).getImm()))
3921 (
MI.getOperand(2).isImm() &&
3922 isShiftedUInt<4,2>(
MI.getOperand(2).getImm())))
3926 case Hexagon::L2_loadrub_io:
3927 case Hexagon::dup_L2_loadrub_io:
3929 DstReg =
MI.getOperand(0).getReg();
3930 SrcReg =
MI.getOperand(1).getReg();
3932 MI.getOperand(2).isImm() && isUInt<4>(
MI.getOperand(2).getImm()))
3945 case Hexagon::L2_loadrh_io:
3946 case Hexagon::L2_loadruh_io:
3947 case Hexagon::dup_L2_loadrh_io:
3948 case Hexagon::dup_L2_loadruh_io:
3950 DstReg =
MI.getOperand(0).getReg();
3951 SrcReg =
MI.getOperand(1).getReg();
3953 MI.getOperand(2).isImm() &&
3954 isShiftedUInt<3,1>(
MI.getOperand(2).getImm()))
3957 case Hexagon::L2_loadrb_io:
3958 case Hexagon::dup_L2_loadrb_io:
3960 DstReg =
MI.getOperand(0).getReg();
3961 SrcReg =
MI.getOperand(1).getReg();
3963 MI.getOperand(2).isImm() &&
3964 isUInt<3>(
MI.getOperand(2).getImm()))
3967 case Hexagon::L2_loadrd_io:
3968 case Hexagon::dup_L2_loadrd_io:
3970 DstReg =
MI.getOperand(0).getReg();
3971 SrcReg =
MI.getOperand(1).getReg();
3973 Hexagon::IntRegsRegClass.
contains(SrcReg) &&
3975 MI.getOperand(2).isImm() &&
3976 isShiftedUInt<5,3>(
MI.getOperand(2).getImm()))
3981 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3982 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3983 case Hexagon::L4_return:
3984 case Hexagon::L2_deallocframe:
3985 case Hexagon::dup_L2_deallocframe:
3987 case Hexagon::EH_RETURN_JMPR:
3988 case Hexagon::PS_jmpret:
3989 case Hexagon::SL2_jumpr31:
3992 DstReg =
MI.getOperand(0).getReg();
3993 if (Hexagon::IntRegsRegClass.
contains(DstReg) && (Hexagon::R31 == DstReg))
3996 case Hexagon::PS_jmprett:
3997 case Hexagon::PS_jmpretf:
3998 case Hexagon::PS_jmprettnewpt:
3999 case Hexagon::PS_jmpretfnewpt:
4000 case Hexagon::PS_jmprettnew:
4001 case Hexagon::PS_jmpretfnew:
4002 case Hexagon::SL2_jumpr31_t:
4003 case Hexagon::SL2_jumpr31_f:
4004 case Hexagon::SL2_jumpr31_tnew:
4005 case Hexagon::SL2_jumpr31_fnew:
4006 DstReg =
MI.getOperand(1).getReg();
4007 SrcReg =
MI.getOperand(0).getReg();
4009 if ((Hexagon::PredRegsRegClass.
contains(SrcReg) &&
4010 (Hexagon::P0 == SrcReg)) &&
4011 (Hexagon::IntRegsRegClass.
contains(DstReg) && (Hexagon::R31 == DstReg)))
4014 case Hexagon::L4_return_t:
4015 case Hexagon::L4_return_f:
4016 case Hexagon::L4_return_tnew_pnt:
4017 case Hexagon::L4_return_fnew_pnt:
4018 case Hexagon::L4_return_tnew_pt:
4019 case Hexagon::L4_return_fnew_pt:
4021 SrcReg =
MI.getOperand(0).getReg();
4022 if (Hexagon::PredRegsRegClass.
contains(SrcReg) && (Hexagon::P0 == SrcReg))
4030 case Hexagon::S2_storeri_io:
4031 case Hexagon::dup_S2_storeri_io:
4034 Src1Reg =
MI.getOperand(0).getReg();
4035 Src2Reg =
MI.getOperand(2).getReg();
4036 if (Hexagon::IntRegsRegClass.
contains(Src1Reg) &&
4039 isShiftedUInt<5,2>(
MI.getOperand(1).getImm()))
4043 MI.getOperand(1).isImm() &&
4044 isShiftedUInt<4,2>(
MI.getOperand(1).getImm()))
4047 case Hexagon::S2_storerb_io:
4048 case Hexagon::dup_S2_storerb_io:
4050 Src1Reg =
MI.getOperand(0).getReg();
4051 Src2Reg =
MI.getOperand(2).getReg();
4053 MI.getOperand(1).isImm() && isUInt<4>(
MI.getOperand(1).getImm()))
4065 case Hexagon::S2_storerh_io:
4066 case Hexagon::dup_S2_storerh_io:
4068 Src1Reg =
MI.getOperand(0).getReg();
4069 Src2Reg =
MI.getOperand(2).getReg();
4071 MI.getOperand(1).isImm() &&
4072 isShiftedUInt<3,1>(
MI.getOperand(1).getImm()))
4075 case Hexagon::S2_storerd_io:
4076 case Hexagon::dup_S2_storerd_io:
4078 Src1Reg =
MI.getOperand(0).getReg();
4079 Src2Reg =
MI.getOperand(2).getReg();
4081 Hexagon::IntRegsRegClass.
contains(Src1Reg) &&
4083 isShiftedInt<6,3>(
MI.getOperand(1).getImm()))
4086 case Hexagon::S4_storeiri_io:
4087 case Hexagon::dup_S4_storeiri_io:
4089 Src1Reg =
MI.getOperand(0).getReg();
4091 isShiftedUInt<4,2>(
MI.getOperand(1).getImm()) &&
4092 MI.getOperand(2).isImm() && isUInt<1>(
MI.getOperand(2).getImm()))
4095 case Hexagon::S4_storeirb_io:
4096 case Hexagon::dup_S4_storeirb_io:
4098 Src1Reg =
MI.getOperand(0).getReg();
4100 MI.getOperand(1).isImm() && isUInt<4>(
MI.getOperand(1).getImm()) &&
4101 MI.getOperand(2).isImm() && isUInt<1>(
MI.getOperand(2).getImm()))
4104 case Hexagon::S2_allocframe:
4105 case Hexagon::dup_S2_allocframe:
4106 if (
MI.getOperand(2).isImm() &&
4107 isShiftedUInt<5,3>(
MI.getOperand(2).getImm()))
4128 case Hexagon::A2_addi:
4129 case Hexagon::dup_A2_addi:
4130 DstReg =
MI.getOperand(0).getReg();
4131 SrcReg =
MI.getOperand(1).getReg();
4134 if (Hexagon::IntRegsRegClass.
contains(SrcReg) &&
4136 isShiftedUInt<6,2>(
MI.getOperand(2).getImm()))
4139 if ((DstReg == SrcReg) &&
MI.getOperand(2).isImm() &&
4140 isInt<7>(
MI.getOperand(2).getImm()))
4145 ((
MI.getOperand(2).getImm() == 1) ||
4146 (
MI.getOperand(2).getImm() == -1)))
4150 case Hexagon::A2_add:
4151 case Hexagon::dup_A2_add:
4153 DstReg =
MI.getOperand(0).getReg();
4154 Src1Reg =
MI.getOperand(1).getReg();
4155 Src2Reg =
MI.getOperand(2).getReg();
4160 case Hexagon::A2_andir:
4161 case Hexagon::dup_A2_andir:
4165 DstReg =
MI.getOperand(0).getReg();
4166 SrcReg =
MI.getOperand(1).getReg();
4168 MI.getOperand(2).isImm() &&
4169 ((
MI.getOperand(2).getImm() == 1) ||
4170 (
MI.getOperand(2).getImm() == 255)))
4173 case Hexagon::A2_tfr:
4174 case Hexagon::dup_A2_tfr:
4176 DstReg =
MI.getOperand(0).getReg();
4177 SrcReg =
MI.getOperand(1).getReg();
4181 case Hexagon::A2_tfrsi:
4182 case Hexagon::dup_A2_tfrsi:
4187 DstReg =
MI.getOperand(0).getReg();
4191 case Hexagon::C2_cmoveit:
4192 case Hexagon::C2_cmovenewit:
4193 case Hexagon::C2_cmoveif:
4194 case Hexagon::C2_cmovenewif:
4195 case Hexagon::dup_C2_cmoveit:
4196 case Hexagon::dup_C2_cmovenewit:
4197 case Hexagon::dup_C2_cmoveif:
4198 case Hexagon::dup_C2_cmovenewif:
4202 DstReg =
MI.getOperand(0).getReg();
4203 SrcReg =
MI.getOperand(1).getReg();
4205 Hexagon::PredRegsRegClass.
contains(SrcReg) && Hexagon::P0 == SrcReg &&
4206 MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0)
4209 case Hexagon::C2_cmpeqi:
4210 case Hexagon::dup_C2_cmpeqi:
4212 DstReg =
MI.getOperand(0).getReg();
4213 SrcReg =
MI.getOperand(1).getReg();
4214 if (Hexagon::PredRegsRegClass.
contains(DstReg) &&
4216 MI.getOperand(2).isImm() && isUInt<2>(
MI.getOperand(2).getImm()))
4219 case Hexagon::A2_combineii:
4220 case Hexagon::A4_combineii:
4221 case Hexagon::dup_A2_combineii:
4222 case Hexagon::dup_A4_combineii:
4224 DstReg =
MI.getOperand(0).getReg();
4226 ((
MI.getOperand(1).isImm() && isUInt<2>(
MI.getOperand(1).getImm())) ||
4227 (
MI.getOperand(1).isGlobal() &&
4228 isUInt<2>(
MI.getOperand(1).getOffset()))) &&
4229 ((
MI.getOperand(2).isImm() && isUInt<2>(
MI.getOperand(2).getImm())) ||
4230 (
MI.getOperand(2).isGlobal() &&
4231 isUInt<2>(
MI.getOperand(2).getOffset()))))
4234 case Hexagon::A4_combineri:
4235 case Hexagon::dup_A4_combineri:
4238 DstReg =
MI.getOperand(0).getReg();
4239 SrcReg =
MI.getOperand(1).getReg();
4241 ((
MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0) ||
4242 (
MI.getOperand(2).isGlobal() &&
MI.getOperand(2).getOffset() == 0)))
4245 case Hexagon::A4_combineir:
4246 case Hexagon::dup_A4_combineir:
4248 DstReg =
MI.getOperand(0).getReg();
4249 SrcReg =
MI.getOperand(2).getReg();
4251 ((
MI.getOperand(1).isImm() &&
MI.getOperand(1).getImm() == 0) ||
4252 (
MI.getOperand(1).isGlobal() &&
MI.getOperand(1).getOffset() == 0)))
4255 case Hexagon::A2_sxtb:
4256 case Hexagon::A2_sxth:
4257 case Hexagon::A2_zxtb:
4258 case Hexagon::A2_zxth:
4259 case Hexagon::dup_A2_sxtb:
4260 case Hexagon::dup_A2_sxth:
4261 case Hexagon::dup_A2_zxtb:
4262 case Hexagon::dup_A2_zxth:
4264 DstReg =
MI.getOperand(0).getReg();
4265 SrcReg =
MI.getOperand(1).getReg();
4275 return Hexagon::getRealHWInstr(
MI.getOpcode(), Hexagon::InstrType_Real);
4285 if (
MI.isTransient())
4309 int Idx =
DefMI.findRegisterDefOperandIdx(SR,
false,
false, &HRI);
4320 int Idx =
UseMI.findRegisterUseOperandIdx(SR,
false, &HRI);
4347 Cond[0].setImm(Opc);
4354 : Hexagon::getTruePredOpcode(Opc);
4355 if (InvPredOpcode >= 0)
4356 return InvPredOpcode;
4370 return ~(-1U << (bits - 1));
4372 return ~(-1U << bits);
4377 switch (
MI.getOpcode()) {
4378 case Hexagon::L2_loadrbgp:
4379 case Hexagon::L2_loadrdgp:
4380 case Hexagon::L2_loadrhgp:
4381 case Hexagon::L2_loadrigp:
4382 case Hexagon::L2_loadrubgp:
4383 case Hexagon::L2_loadruhgp:
4384 case Hexagon::S2_storerbgp:
4385 case Hexagon::S2_storerbnewgp:
4386 case Hexagon::S2_storerhgp:
4387 case Hexagon::S2_storerhnewgp:
4388 case Hexagon::S2_storerigp:
4389 case Hexagon::S2_storerinewgp:
4390 case Hexagon::S2_storerdgp:
4391 case Hexagon::S2_storerfgp:
4409 if (
MI.getOpcode() == Hexagon::A4_ext)
4423 bool ToBigInstrs)
const {
4441 bool ToBigInstrs)
const {
4444 End = MB.instr_end();
4445 Instr !=
End; ++Instr)
4453 while ((MII !=
MBB->
instr_end()) && MII->isInsideBundle()) {
4460 using namespace HexagonII;
4463 unsigned S = (
F >> MemAccessSizePos) & MemAccesSizeMask;
4464 unsigned Size = getMemAccessSizeInBytes(MemAccessSize(S));
4468 if (
MI.getOpcode() == Hexagon::Y2_dcfetchbo)
4475 return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4490 return -1U << (bits - 1);
4499 short NonExtOpcode = Hexagon::getRegForm(
MI.getOpcode());
4500 if (NonExtOpcode >= 0)
4501 return NonExtOpcode;
4503 if (
MI.getDesc().mayLoad() ||
MI.getDesc().mayStore()) {
4507 return Hexagon::changeAddrMode_abs_io(
MI.getOpcode());
4509 return Hexagon::changeAddrMode_io_rr(
MI.getOpcode());
4511 return Hexagon::changeAddrMode_ur_rr(
MI.getOpcode());
4521 Register &PredReg,
unsigned &PredRegPos,
unsigned &PredRegFlags)
const {