LLVM  14.0.0git
HexagonInstrInfo.cpp
Go to the documentation of this file.
1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonInstrInfo.h"
14 #include "Hexagon.h"
15 #include "HexagonFrameLowering.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCInstBuilder.h"
44 #include "llvm/MC/MCInstrDesc.h"
46 #include "llvm/MC/MCRegisterInfo.h"
49 #include "llvm/Support/Debug.h"
55 #include <cassert>
56 #include <cctype>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <utility>
62 
63 using namespace llvm;
64 
65 #define DEBUG_TYPE "hexagon-instrinfo"
66 
67 #define GET_INSTRINFO_CTOR_DTOR
68 #define GET_INSTRMAP_INFO
70 #include "HexagonGenDFAPacketizer.inc"
71 #include "HexagonGenInstrInfo.inc"
72 
73 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
74  cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
75  "packetization boundary."));
76 
77 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
78  cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
79 
80 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
82  cl::desc("Disable schedule adjustment for new value stores."));
83 
85  "enable-timing-class-latency", cl::Hidden, cl::init(false),
86  cl::desc("Enable timing class latency"));
87 
89  "enable-alu-forwarding", cl::Hidden, cl::init(true),
90  cl::desc("Enable vec alu forwarding"));
91 
93  "enable-acc-forwarding", cl::Hidden, cl::init(true),
94  cl::desc("Enable vec acc forwarding"));
95 
96 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
97  cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
98 
99 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
101  cl::desc("Use the DFA based hazard recognizer."));
102 
103 /// Constants for Hexagon instructions.
104 const int Hexagon_MEMW_OFFSET_MAX = 4095;
105 const int Hexagon_MEMW_OFFSET_MIN = -4096;
106 const int Hexagon_MEMD_OFFSET_MAX = 8191;
107 const int Hexagon_MEMD_OFFSET_MIN = -8192;
108 const int Hexagon_MEMH_OFFSET_MAX = 2047;
109 const int Hexagon_MEMH_OFFSET_MIN = -2048;
110 const int Hexagon_MEMB_OFFSET_MAX = 1023;
111 const int Hexagon_MEMB_OFFSET_MIN = -1024;
112 const int Hexagon_ADDI_OFFSET_MAX = 32767;
113 const int Hexagon_ADDI_OFFSET_MIN = -32768;
114 
115 // Pin the vtable to this file.
116 void HexagonInstrInfo::anchor() {}
117 
119  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
120  Subtarget(ST) {}
121 
122 namespace llvm {
123 namespace HexagonFUnits {
124  bool isSlot0Only(unsigned units);
125 }
126 }
127 
128 static bool isIntRegForSubInst(unsigned Reg) {
129  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
130  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
131 }
132 
133 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
134  return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
135  isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
136 }
137 
138 /// Calculate number of instructions excluding the debug instructions.
141  unsigned Count = 0;
142  for (; MIB != MIE; ++MIB) {
143  if (!MIB->isDebugInstr())
144  ++Count;
145  }
146  return Count;
147 }
148 
149 // Check if the A2_tfrsi instruction is cheap or not. If the operand has
150 // to be constant-extendend it is not cheap since it occupies two slots
151 // in a packet.
153  // Enable the following steps only at Os/Oz
154  if (!(MI.getMF()->getFunction().hasOptSize()))
155  return MI.isAsCheapAsAMove();
156 
157  if (MI.getOpcode() == Hexagon::A2_tfrsi) {
158  auto Op = MI.getOperand(1);
159  // If the instruction has a global address as operand, it is not cheap
160  // since the operand will be constant extended.
161  if (Op.getType() == MachineOperand::MO_GlobalAddress)
162  return false;
163  // If the instruction has an operand of size > 16bits, its will be
164  // const-extended and hence, it is not cheap.
165  if (Op.isImm()) {
166  int64_t Imm = Op.getImm();
167  if (!isInt<16>(Imm))
168  return false;
169  }
170  }
171  return MI.isAsCheapAsAMove();
172 }
173 
174 // Do not sink floating point instructions that updates USR register.
175 // Example:
176 // feclearexcept
177 // F2_conv_w2sf
178 // fetestexcept
179 // MachineSink sinks F2_conv_w2sf and we are not able to catch exceptions.
180 // TODO: On some of these floating point instructions, USR is marked as Use.
181 // In reality, these instructions also Def the USR. If USR is marked as Def,
182 // some of the assumptions in assembler packetization are broken.
184  // Assumption: A floating point instruction that reads the USR will write
185  // the USR as well.
186  if (isFloat(MI) && MI.hasRegisterImplicitUseOperand(Hexagon::USR))
187  return false;
188  return true;
189 }
190 
191 /// Find the hardware loop instruction used to set-up the specified loop.
192 /// On Hexagon, we have two instructions used to set-up the hardware loop
193 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
194 /// to indicate the end of a loop.
196  unsigned EndLoopOp, MachineBasicBlock *TargetBB,
197  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
198  unsigned LOOPi;
199  unsigned LOOPr;
200  if (EndLoopOp == Hexagon::ENDLOOP0) {
201  LOOPi = Hexagon::J2_loop0i;
202  LOOPr = Hexagon::J2_loop0r;
203  } else { // EndLoopOp == Hexagon::EndLOOP1
204  LOOPi = Hexagon::J2_loop1i;
205  LOOPr = Hexagon::J2_loop1r;
206  }
207 
208  // The loop set-up instruction will be in a predecessor block
209  for (MachineBasicBlock *PB : BB->predecessors()) {
210  // If this has been visited, already skip it.
211  if (!Visited.insert(PB).second)
212  continue;
213  if (PB == BB)
214  continue;
215  for (MachineInstr &I : llvm::reverse(PB->instrs())) {
216  unsigned Opc = I.getOpcode();
217  if (Opc == LOOPi || Opc == LOOPr)
218  return &I;
219  // We've reached a different loop, which means the loop01 has been
220  // removed.
221  if (Opc == EndLoopOp && I.getOperand(0).getMBB() != TargetBB)
222  return nullptr;
223  }
224  // Check the predecessors for the LOOP instruction.
225  if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
226  return Loop;
227  }
228  return nullptr;
229 }
230 
231 /// Gather register def/uses from MI.
232 /// This treats possible (predicated) defs as actually happening ones
233 /// (conservatively).
234 static inline void parseOperands(const MachineInstr &MI,
236  Defs.clear();
237  Uses.clear();
238 
239  for (const MachineOperand &MO : MI.operands()) {
240  if (!MO.isReg())
241  continue;
242 
243  Register Reg = MO.getReg();
244  if (!Reg)
245  continue;
246 
247  if (MO.isUse())
248  Uses.push_back(MO.getReg());
249 
250  if (MO.isDef())
251  Defs.push_back(MO.getReg());
252  }
253 }
254 
255 // Position dependent, so check twice for swap.
256 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
257  switch (Ga) {
259  default:
260  return false;
261  case HexagonII::HSIG_L1:
262  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
263  case HexagonII::HSIG_L2:
264  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
265  Gb == HexagonII::HSIG_A);
266  case HexagonII::HSIG_S1:
267  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
268  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
269  case HexagonII::HSIG_S2:
270  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
271  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
272  Gb == HexagonII::HSIG_A);
273  case HexagonII::HSIG_A:
274  return (Gb == HexagonII::HSIG_A);
276  return (Gb == HexagonII::HSIG_Compound);
277  }
278  return false;
279 }
280 
281 /// isLoadFromStackSlot - If the specified machine instruction is a direct
282 /// load from a stack slot, return the virtual or physical register number of
283 /// the destination along with the FrameIndex of the loaded stack slot. If
284 /// not, return 0. This predicate must return 0 if the instruction has
285 /// any side effects other than loading from the stack slot.
287  int &FrameIndex) const {
288  switch (MI.getOpcode()) {
289  default:
290  break;
291  case Hexagon::L2_loadri_io:
292  case Hexagon::L2_loadrd_io:
293  case Hexagon::V6_vL32b_ai:
294  case Hexagon::V6_vL32b_nt_ai:
295  case Hexagon::V6_vL32Ub_ai:
296  case Hexagon::LDriw_pred:
297  case Hexagon::LDriw_ctr:
298  case Hexagon::PS_vloadrq_ai:
299  case Hexagon::PS_vloadrw_ai:
300  case Hexagon::PS_vloadrw_nt_ai: {
301  const MachineOperand OpFI = MI.getOperand(1);
302  if (!OpFI.isFI())
303  return 0;
304  const MachineOperand OpOff = MI.getOperand(2);
305  if (!OpOff.isImm() || OpOff.getImm() != 0)
306  return 0;
307  FrameIndex = OpFI.getIndex();
308  return MI.getOperand(0).getReg();
309  }
310 
311  case Hexagon::L2_ploadrit_io:
312  case Hexagon::L2_ploadrif_io:
313  case Hexagon::L2_ploadrdt_io:
314  case Hexagon::L2_ploadrdf_io: {
315  const MachineOperand OpFI = MI.getOperand(2);
316  if (!OpFI.isFI())
317  return 0;
318  const MachineOperand OpOff = MI.getOperand(3);
319  if (!OpOff.isImm() || OpOff.getImm() != 0)
320  return 0;
321  FrameIndex = OpFI.getIndex();
322  return MI.getOperand(0).getReg();
323  }
324  }
325 
326  return 0;
327 }
328 
329 /// isStoreToStackSlot - If the specified machine instruction is a direct
330 /// store to a stack slot, return the virtual or physical register number of
331 /// the source reg along with the FrameIndex of the loaded stack slot. If
332 /// not, return 0. This predicate must return 0 if the instruction has
333 /// any side effects other than storing to the stack slot.
335  int &FrameIndex) const {
336  switch (MI.getOpcode()) {
337  default:
338  break;
339  case Hexagon::S2_storerb_io:
340  case Hexagon::S2_storerh_io:
341  case Hexagon::S2_storeri_io:
342  case Hexagon::S2_storerd_io:
343  case Hexagon::V6_vS32b_ai:
344  case Hexagon::V6_vS32Ub_ai:
345  case Hexagon::STriw_pred:
346  case Hexagon::STriw_ctr:
347  case Hexagon::PS_vstorerq_ai:
348  case Hexagon::PS_vstorerw_ai: {
349  const MachineOperand &OpFI = MI.getOperand(0);
350  if (!OpFI.isFI())
351  return 0;
352  const MachineOperand &OpOff = MI.getOperand(1);
353  if (!OpOff.isImm() || OpOff.getImm() != 0)
354  return 0;
355  FrameIndex = OpFI.getIndex();
356  return MI.getOperand(2).getReg();
357  }
358 
359  case Hexagon::S2_pstorerbt_io:
360  case Hexagon::S2_pstorerbf_io:
361  case Hexagon::S2_pstorerht_io:
362  case Hexagon::S2_pstorerhf_io:
363  case Hexagon::S2_pstorerit_io:
364  case Hexagon::S2_pstorerif_io:
365  case Hexagon::S2_pstorerdt_io:
366  case Hexagon::S2_pstorerdf_io: {
367  const MachineOperand &OpFI = MI.getOperand(1);
368  if (!OpFI.isFI())
369  return 0;
370  const MachineOperand &OpOff = MI.getOperand(2);
371  if (!OpOff.isImm() || OpOff.getImm() != 0)
372  return 0;
373  FrameIndex = OpFI.getIndex();
374  return MI.getOperand(3).getReg();
375  }
376  }
377 
378  return 0;
379 }
380 
381 /// This function checks if the instruction or bundle of instructions
382 /// has load from stack slot and returns frameindex and machine memory
383 /// operand of that instruction if true.
385  const MachineInstr &MI,
387  if (MI.isBundle()) {
388  const MachineBasicBlock *MBB = MI.getParent();
389  MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
390  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
391  if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
392  return true;
393  return false;
394  }
395 
396  return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
397 }
398 
399 /// This function checks if the instruction or bundle of instructions
400 /// has store to stack slot and returns frameindex and machine memory
401 /// operand of that instruction if true.
403  const MachineInstr &MI,
405  if (MI.isBundle()) {
406  const MachineBasicBlock *MBB = MI.getParent();
407  MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
408  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
409  if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
410  return true;
411  return false;
412  }
413 
414  return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
415 }
416 
417 /// This function can analyze one/two way branching only and should (mostly) be
418 /// called by target independent side.
419 /// First entry is always the opcode of the branching instruction, except when
420 /// the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a
421 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
422 /// e.g. Jump_c p will have
423 /// Cond[0] = Jump_c
424 /// Cond[1] = p
425 /// HW-loop ENDLOOP:
426 /// Cond[0] = ENDLOOP
427 /// Cond[1] = MBB
428 /// New value jump:
429 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
430 /// Cond[1] = R
431 /// Cond[2] = Imm
433  MachineBasicBlock *&TBB,
434  MachineBasicBlock *&FBB,
436  bool AllowModify) const {
437  TBB = nullptr;
438  FBB = nullptr;
439  Cond.clear();
440 
441  // If the block has no terminators, it just falls into the block after it.
443  if (I == MBB.instr_begin())
444  return false;
445 
446  // A basic block may looks like this:
447  //
448  // [ insn
449  // EH_LABEL
450  // insn
451  // insn
452  // insn
453  // EH_LABEL
454  // insn ]
455  //
456  // It has two succs but does not have a terminator
457  // Don't know how to handle it.
458  do {
459  --I;
460  if (I->isEHLabel())
461  // Don't analyze EH branches.
462  return true;
463  } while (I != MBB.instr_begin());
464 
465  I = MBB.instr_end();
466  --I;
467 
468  while (I->isDebugInstr()) {
469  if (I == MBB.instr_begin())
470  return false;
471  --I;
472  }
473 
474  bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
475  I->getOperand(0).isMBB();
476  // Delete the J2_jump if it's equivalent to a fall-through.
477  if (AllowModify && JumpToBlock &&
478  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
479  LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
480  I->eraseFromParent();
481  I = MBB.instr_end();
482  if (I == MBB.instr_begin())
483  return false;
484  --I;
485  }
486  if (!isUnpredicatedTerminator(*I))
487  return false;
488 
489  // Get the last instruction in the block.
490  MachineInstr *LastInst = &*I;
491  MachineInstr *SecondLastInst = nullptr;
492  // Find one more terminator if present.
493  while (true) {
494  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
495  if (!SecondLastInst)
496  SecondLastInst = &*I;
497  else
498  // This is a third branch.
499  return true;
500  }
501  if (I == MBB.instr_begin())
502  break;
503  --I;
504  }
505 
506  int LastOpcode = LastInst->getOpcode();
507  int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
508  // If the branch target is not a basic block, it could be a tail call.
509  // (It is, if the target is a function.)
510  if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
511  return true;
512  if (SecLastOpcode == Hexagon::J2_jump &&
513  !SecondLastInst->getOperand(0).isMBB())
514  return true;
515 
516  bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
517  bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
518 
519  if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
520  return true;
521 
522  // If there is only one terminator instruction, process it.
523  if (LastInst && !SecondLastInst) {
524  if (LastOpcode == Hexagon::J2_jump) {
525  TBB = LastInst->getOperand(0).getMBB();
526  return false;
527  }
528  if (isEndLoopN(LastOpcode)) {
529  TBB = LastInst->getOperand(0).getMBB();
530  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
531  Cond.push_back(LastInst->getOperand(0));
532  return false;
533  }
534  if (LastOpcodeHasJMP_c) {
535  TBB = LastInst->getOperand(1).getMBB();
536  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
537  Cond.push_back(LastInst->getOperand(0));
538  return false;
539  }
540  // Only supporting rr/ri versions of new-value jumps.
541  if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
542  TBB = LastInst->getOperand(2).getMBB();
543  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
544  Cond.push_back(LastInst->getOperand(0));
545  Cond.push_back(LastInst->getOperand(1));
546  return false;
547  }
548  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
549  << " with one jump\n";);
550  // Otherwise, don't know what this is.
551  return true;
552  }
553 
554  bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
555  bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
556  if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
557  if (!SecondLastInst->getOperand(1).isMBB())
558  return true;
559  TBB = SecondLastInst->getOperand(1).getMBB();
560  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
561  Cond.push_back(SecondLastInst->getOperand(0));
562  FBB = LastInst->getOperand(0).getMBB();
563  return false;
564  }
565 
566  // Only supporting rr/ri versions of new-value jumps.
567  if (SecLastOpcodeHasNVJump &&
568  (SecondLastInst->getNumExplicitOperands() == 3) &&
569  (LastOpcode == Hexagon::J2_jump)) {
570  TBB = SecondLastInst->getOperand(2).getMBB();
571  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
572  Cond.push_back(SecondLastInst->getOperand(0));
573  Cond.push_back(SecondLastInst->getOperand(1));
574  FBB = LastInst->getOperand(0).getMBB();
575  return false;
576  }
577 
578  // If the block ends with two Hexagon:JMPs, handle it. The second one is not
579  // executed, so remove it.
580  if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
581  TBB = SecondLastInst->getOperand(0).getMBB();
582  I = LastInst->getIterator();
583  if (AllowModify)
584  I->eraseFromParent();
585  return false;
586  }
587 
588  // If the block ends with an ENDLOOP, and J2_jump, handle it.
589  if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
590  TBB = SecondLastInst->getOperand(0).getMBB();
591  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
592  Cond.push_back(SecondLastInst->getOperand(0));
593  FBB = LastInst->getOperand(0).getMBB();
594  return false;
595  }
596  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
597  << " with two jumps";);
598  // Otherwise, can't handle this.
599  return true;
600 }
601 
603  int *BytesRemoved) const {
604  assert(!BytesRemoved && "code size not handled");
605 
606  LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
608  unsigned Count = 0;
609  while (I != MBB.begin()) {
610  --I;
611  if (I->isDebugInstr())
612  continue;
613  // Only removing branches from end of MBB.
614  if (!I->isBranch())
615  return Count;
616  if (Count && (I->getOpcode() == Hexagon::J2_jump))
617  llvm_unreachable("Malformed basic block: unconditional branch not last");
618  MBB.erase(&MBB.back());
619  I = MBB.end();
620  ++Count;
621  }
622  return Count;
623 }
624 
626  MachineBasicBlock *TBB,
627  MachineBasicBlock *FBB,
629  const DebugLoc &DL,
630  int *BytesAdded) const {
631  unsigned BOpc = Hexagon::J2_jump;
632  unsigned BccOpc = Hexagon::J2_jumpt;
633  assert(validateBranchCond(Cond) && "Invalid branching condition");
634  assert(TBB && "insertBranch must not be told to insert a fallthrough");
635  assert(!BytesAdded && "code size not handled");
636 
637  // Check if reverseBranchCondition has asked to reverse this branch
638  // If we want to reverse the branch an odd number of times, we want
639  // J2_jumpf.
640  if (!Cond.empty() && Cond[0].isImm())
641  BccOpc = Cond[0].getImm();
642 
643  if (!FBB) {
644  if (Cond.empty()) {
645  // Due to a bug in TailMerging/CFG Optimization, we need to add a
646  // special case handling of a predicated jump followed by an
647  // unconditional jump. If not, Tail Merging and CFG Optimization go
648  // into an infinite loop.
649  MachineBasicBlock *NewTBB, *NewFBB;
651  auto Term = MBB.getFirstTerminator();
652  if (Term != MBB.end() && isPredicated(*Term) &&
653  !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
654  MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
656  removeBranch(MBB);
657  return insertBranch(MBB, TBB, nullptr, Cond, DL);
658  }
659  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
660  } else if (isEndLoopN(Cond[0].getImm())) {
661  int EndLoopOp = Cond[0].getImm();
662  assert(Cond[1].isMBB());
663  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
664  // Check for it, and change the BB target if needed.
666  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
667  VisitedBBs);
668  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
669  Loop->getOperand(0).setMBB(TBB);
670  // Add the ENDLOOP after the finding the LOOP0.
671  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
672  } else if (isNewValueJump(Cond[0].getImm())) {
673  assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
674  // New value jump
675  // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
676  // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
677  unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
678  LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
679  << printMBBReference(MBB););
680  if (Cond[2].isReg()) {
681  unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
682  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
683  addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
684  } else if(Cond[2].isImm()) {
685  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
686  addImm(Cond[2].getImm()).addMBB(TBB);
687  } else
688  llvm_unreachable("Invalid condition for branching");
689  } else {
690  assert((Cond.size() == 2) && "Malformed cond vector");
691  const MachineOperand &RO = Cond[1];
692  unsigned Flags = getUndefRegState(RO.isUndef());
693  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
694  }
695  return 1;
696  }
697  assert((!Cond.empty()) &&
698  "Cond. cannot be empty when multiple branchings are required");
699  assert((!isNewValueJump(Cond[0].getImm())) &&
700  "NV-jump cannot be inserted with another branch");
701  // Special case for hardware loops. The condition is a basic block.
702  if (isEndLoopN(Cond[0].getImm())) {
703  int EndLoopOp = Cond[0].getImm();
704  assert(Cond[1].isMBB());
705  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
706  // Check for it, and change the BB target if needed.
708  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
709  VisitedBBs);
710  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
711  Loop->getOperand(0).setMBB(TBB);
712  // Add the ENDLOOP after the finding the LOOP0.
713  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
714  } else {
715  const MachineOperand &RO = Cond[1];
716  unsigned Flags = getUndefRegState(RO.isUndef());
717  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
718  }
719  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
720 
721  return 2;
722 }
723 
724 namespace {
725 class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
726  MachineInstr *Loop, *EndLoop;
727  MachineFunction *MF;
728  const HexagonInstrInfo *TII;
729  int64_t TripCount;
730  Register LoopCount;
731  DebugLoc DL;
732 
733 public:
734  HexagonPipelinerLoopInfo(MachineInstr *Loop, MachineInstr *EndLoop)
735  : Loop(Loop), EndLoop(EndLoop), MF(Loop->getParent()->getParent()),
736  TII(MF->getSubtarget<HexagonSubtarget>().getInstrInfo()),
737  DL(Loop->getDebugLoc()) {
738  // Inspect the Loop instruction up-front, as it may be deleted when we call
739  // createTripCountGreaterCondition.
740  TripCount = Loop->getOpcode() == Hexagon::J2_loop0r
741  ? -1
742  : Loop->getOperand(1).getImm();
743  if (TripCount == -1)
744  LoopCount = Loop->getOperand(1).getReg();
745  }
746 
747  bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
748  // Only ignore the terminator.
749  return MI == EndLoop;
750  }
751 
753  createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
755  if (TripCount == -1) {
756  // Check if we're done with the loop.
757  unsigned Done = TII->createVR(MF, MVT::i1);
758  MachineInstr *NewCmp = BuildMI(&MBB, DL,
759  TII->get(Hexagon::C2_cmpgtui), Done)
760  .addReg(LoopCount)
761  .addImm(TC);
762  Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
763  Cond.push_back(NewCmp->getOperand(0));
764  return {};
765  }
766 
767  return TripCount > TC;
768  }
769 
770  void setPreheader(MachineBasicBlock *NewPreheader) override {
771  NewPreheader->splice(NewPreheader->getFirstTerminator(), Loop->getParent(),
772  Loop);
773  }
774 
775  void adjustTripCount(int TripCountAdjust) override {
776  // If the loop trip count is a compile-time value, then just change the
777  // value.
778  if (Loop->getOpcode() == Hexagon::J2_loop0i ||
779  Loop->getOpcode() == Hexagon::J2_loop1i) {
780  int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust;
781  assert(TripCount > 0 && "Can't create an empty or negative loop!");
782  Loop->getOperand(1).setImm(TripCount);
783  return;
784  }
785 
786  // The loop trip count is a run-time value. We generate code to subtract
787  // one from the trip count, and update the loop instruction.
788  Register LoopCount = Loop->getOperand(1).getReg();
789  Register NewLoopCount = TII->createVR(MF, MVT::i32);
790  BuildMI(*Loop->getParent(), Loop, Loop->getDebugLoc(),
791  TII->get(Hexagon::A2_addi), NewLoopCount)
792  .addReg(LoopCount)
793  .addImm(TripCountAdjust);
794  Loop->getOperand(1).setReg(NewLoopCount);
795  }
796 
797  void disposed() override { Loop->eraseFromParent(); }
798 };
799 } // namespace
800 
801 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
803  // We really "analyze" only hardware loops right now.
805 
806  if (I != LoopBB->end() && isEndLoopN(I->getOpcode())) {
808  MachineInstr *LoopInst = findLoopInstr(
809  LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
810  if (LoopInst)
811  return std::make_unique<HexagonPipelinerLoopInfo>(LoopInst, &*I);
812  }
813  return nullptr;
814 }
815 
817  unsigned NumCycles, unsigned ExtraPredCycles,
818  BranchProbability Probability) const {
819  return nonDbgBBSize(&MBB) <= 3;
820 }
821 
823  unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
824  unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
825  const {
826  return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
827 }
828 
830  unsigned NumInstrs, BranchProbability Probability) const {
831  return NumInstrs <= 4;
832 }
833 
834 static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
836  const MachineBasicBlock &B = *MI.getParent();
837  Regs.addLiveIns(B);
838  auto E = MachineBasicBlock::const_iterator(MI.getIterator());
839  for (auto I = B.begin(); I != E; ++I) {
840  Clobbers.clear();
841  Regs.stepForward(*I, Clobbers);
842  }
843 }
844 
845 static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
846  const MachineBasicBlock &B = *MI.getParent();
847  Regs.addLiveOuts(B);
848  auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
849  for (auto I = B.rbegin(); I != E; ++I)
850  Regs.stepBackward(*I);
851 }
852 
855  const DebugLoc &DL, MCRegister DestReg,
856  MCRegister SrcReg, bool KillSrc) const {
857  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
858  unsigned KillFlag = getKillRegState(KillSrc);
859 
860  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
861  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
862  .addReg(SrcReg, KillFlag);
863  return;
864  }
865  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
866  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
867  .addReg(SrcReg, KillFlag);
868  return;
869  }
870  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
871  // Map Pd = Ps to Pd = or(Ps, Ps).
872  BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
873  .addReg(SrcReg).addReg(SrcReg, KillFlag);
874  return;
875  }
876  if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
877  Hexagon::IntRegsRegClass.contains(SrcReg)) {
878  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
879  .addReg(SrcReg, KillFlag);
880  return;
881  }
882  if (Hexagon::IntRegsRegClass.contains(DestReg) &&
883  Hexagon::CtrRegsRegClass.contains(SrcReg)) {
884  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
885  .addReg(SrcReg, KillFlag);
886  return;
887  }
888  if (Hexagon::ModRegsRegClass.contains(DestReg) &&
889  Hexagon::IntRegsRegClass.contains(SrcReg)) {
890  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
891  .addReg(SrcReg, KillFlag);
892  return;
893  }
894  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
895  Hexagon::IntRegsRegClass.contains(DestReg)) {
896  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
897  .addReg(SrcReg, KillFlag);
898  return;
899  }
900  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
901  Hexagon::PredRegsRegClass.contains(DestReg)) {
902  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
903  .addReg(SrcReg, KillFlag);
904  return;
905  }
906  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
907  Hexagon::IntRegsRegClass.contains(DestReg)) {
908  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
909  .addReg(SrcReg, KillFlag);
910  return;
911  }
912  if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
913  BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
914  addReg(SrcReg, KillFlag);
915  return;
916  }
917  if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
918  LivePhysRegs LiveAtMI(HRI);
919  getLiveInRegsAt(LiveAtMI, *I);
920  Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
921  Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
922  unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo));
923  unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi));
924  BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
925  .addReg(SrcHi, KillFlag | UndefHi)
926  .addReg(SrcLo, KillFlag | UndefLo);
927  return;
928  }
929  if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
930  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
931  .addReg(SrcReg)
932  .addReg(SrcReg, KillFlag);
933  return;
934  }
935  if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
936  Hexagon::HvxVRRegClass.contains(DestReg)) {
937  llvm_unreachable("Unimplemented pred to vec");
938  return;
939  }
940  if (Hexagon::HvxQRRegClass.contains(DestReg) &&
941  Hexagon::HvxVRRegClass.contains(SrcReg)) {
942  llvm_unreachable("Unimplemented vec to pred");
943  return;
944  }
945 
946 #ifndef NDEBUG
947  // Show the invalid registers to ease debugging.
948  dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
949  << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
950 #endif
951  llvm_unreachable("Unimplemented");
952 }
953 
955  MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI,
956  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
958  MachineFunction &MF = *MBB.getParent();
959  MachineFrameInfo &MFI = MF.getFrameInfo();
960  unsigned KillFlag = getKillRegState(isKill);
961 
964  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
965 
966  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
967  BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
968  .addFrameIndex(FI).addImm(0)
969  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
970  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
971  BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
972  .addFrameIndex(FI).addImm(0)
973  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
974  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
975  BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
976  .addFrameIndex(FI).addImm(0)
977  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
978  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
979  BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
980  .addFrameIndex(FI).addImm(0)
981  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
982  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
983  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
984  .addFrameIndex(FI).addImm(0)
985  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
986  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
987  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerv_ai))
988  .addFrameIndex(FI).addImm(0)
989  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
990  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
991  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerw_ai))
992  .addFrameIndex(FI).addImm(0)
993  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
994  } else {
995  llvm_unreachable("Unimplemented");
996  }
997 }
998 
1001  int FI, const TargetRegisterClass *RC,
1002  const TargetRegisterInfo *TRI) const {
1004  MachineFunction &MF = *MBB.getParent();
1005  MachineFrameInfo &MFI = MF.getFrameInfo();
1006 
1009  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
1010 
1011  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
1012  BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
1013  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1014  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
1015  BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
1016  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1017  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
1018  BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
1019  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1020  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
1021  BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
1022  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1023  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
1024  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
1025  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1026  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
1027  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrv_ai), DestReg)
1028  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1029  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1030  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrw_ai), DestReg)
1031  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
1032  } else {
1033  llvm_unreachable("Can't store this register to stack slot");
1034  }
1035 }
1036 
1037 /// expandPostRAPseudo - This function is called for all pseudo instructions
1038 /// that remain after register allocation. Many pseudo instructions are
1039 /// created to help register allocation. This is the place to convert them
1040 /// into real instructions. The target can edit MI in place, or it can insert
1041 /// new instructions and erase MI. The function should return true if
1042 /// anything was changed.
1044  MachineBasicBlock &MBB = *MI.getParent();
1045  MachineFunction &MF = *MBB.getParent();
1047  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1048  LivePhysRegs LiveIn(HRI), LiveOut(HRI);
1049  DebugLoc DL = MI.getDebugLoc();
1050  unsigned Opc = MI.getOpcode();
1051 
1052  auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1053  Register Mx = MI.getOperand(MxOp).getReg();
1054  unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1055  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1056  .add(MI.getOperand((HasImm ? 5 : 4)));
1057  auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1058  .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1059  if (HasImm)
1060  MIB.add(MI.getOperand(4));
1061  MIB.addReg(CSx, RegState::Implicit);
1062  MBB.erase(MI);
1063  return true;
1064  };
1065 
1066  auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) {
1067  if (MI.memoperands().empty())
1068  return false;
1069  return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) {
1070  return MMO->getAlign() >= NeedAlign;
1071  });
1072  };
1073 
1074  switch (Opc) {
1075  case TargetOpcode::COPY: {
1076  MachineOperand &MD = MI.getOperand(0);
1077  MachineOperand &MS = MI.getOperand(1);
1078  MachineBasicBlock::iterator MBBI = MI.getIterator();
1079  if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1080  copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1081  std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1082  }
1083  MBB.erase(MBBI);
1084  return true;
1085  }
1086  case Hexagon::PS_aligna:
1087  BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1088  .addReg(HRI.getFrameRegister())
1089  .addImm(-MI.getOperand(1).getImm());
1090  MBB.erase(MI);
1091  return true;
1092  case Hexagon::V6_vassignp: {
1093  Register SrcReg = MI.getOperand(1).getReg();
1094  Register DstReg = MI.getOperand(0).getReg();
1095  Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1096  Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1097  getLiveInRegsAt(LiveIn, MI);
1098  unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
1099  unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));
1100  unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1101  BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1102  .addReg(SrcHi, UndefHi)
1103  .addReg(SrcLo, Kill | UndefLo);
1104  MBB.erase(MI);
1105  return true;
1106  }
1107  case Hexagon::V6_lo: {
1108  Register SrcReg = MI.getOperand(1).getReg();
1109  Register DstReg = MI.getOperand(0).getReg();
1110  Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1111  copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1112  MBB.erase(MI);
1113  MRI.clearKillFlags(SrcSubLo);
1114  return true;
1115  }
1116  case Hexagon::V6_hi: {
1117  Register SrcReg = MI.getOperand(1).getReg();
1118  Register DstReg = MI.getOperand(0).getReg();
1119  Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1120  copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1121  MBB.erase(MI);
1122  MRI.clearKillFlags(SrcSubHi);
1123  return true;
1124  }
1125  case Hexagon::PS_vloadrv_ai: {
1126  Register DstReg = MI.getOperand(0).getReg();
1127  const MachineOperand &BaseOp = MI.getOperand(1);
1128  assert(BaseOp.getSubReg() == 0);
1129  int Offset = MI.getOperand(2).getImm();
1130  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1131  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1132  : Hexagon::V6_vL32Ub_ai;
1133  BuildMI(MBB, MI, DL, get(NewOpc), DstReg)
1134  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1135  .addImm(Offset)
1136  .cloneMemRefs(MI);
1137  MBB.erase(MI);
1138  return true;
1139  }
1140  case Hexagon::PS_vloadrw_ai: {
1141  Register DstReg = MI.getOperand(0).getReg();
1142  const MachineOperand &BaseOp = MI.getOperand(1);
1143  assert(BaseOp.getSubReg() == 0);
1144  int Offset = MI.getOperand(2).getImm();
1145  unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1146  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1147  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1148  : Hexagon::V6_vL32Ub_ai;
1149  BuildMI(MBB, MI, DL, get(NewOpc),
1150  HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1151  .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1152  .addImm(Offset)
1153  .cloneMemRefs(MI);
1154  BuildMI(MBB, MI, DL, get(NewOpc),
1155  HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1156  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1157  .addImm(Offset + VecOffset)
1158  .cloneMemRefs(MI);
1159  MBB.erase(MI);
1160  return true;
1161  }
1162  case Hexagon::PS_vstorerv_ai: {
1163  const MachineOperand &SrcOp = MI.getOperand(2);
1164  assert(SrcOp.getSubReg() == 0);
1165  const MachineOperand &BaseOp = MI.getOperand(0);
1166  assert(BaseOp.getSubReg() == 0);
1167  int Offset = MI.getOperand(1).getImm();
1168  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1169  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1170  : Hexagon::V6_vS32Ub_ai;
1171  BuildMI(MBB, MI, DL, get(NewOpc))
1172  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1173  .addImm(Offset)
1175  .cloneMemRefs(MI);
1176  MBB.erase(MI);
1177  return true;
1178  }
1179  case Hexagon::PS_vstorerw_ai: {
1180  Register SrcReg = MI.getOperand(2).getReg();
1181  const MachineOperand &BaseOp = MI.getOperand(0);
1182  assert(BaseOp.getSubReg() == 0);
1183  int Offset = MI.getOperand(1).getImm();
1184  unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1185  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1186  unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1187  : Hexagon::V6_vS32Ub_ai;
1188  BuildMI(MBB, MI, DL, get(NewOpc))
1189  .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1190  .addImm(Offset)
1191  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo))
1192  .cloneMemRefs(MI);
1193  BuildMI(MBB, MI, DL, get(NewOpc))
1194  .addReg(BaseOp.getReg(), getRegState(BaseOp))
1195  .addImm(Offset + VecOffset)
1196  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi))
1197  .cloneMemRefs(MI);
1198  MBB.erase(MI);
1199  return true;
1200  }
1201  case Hexagon::PS_true: {
1202  Register Reg = MI.getOperand(0).getReg();
1203  BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1206  MBB.erase(MI);
1207  return true;
1208  }
1209  case Hexagon::PS_false: {
1210  Register Reg = MI.getOperand(0).getReg();
1211  BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1214  MBB.erase(MI);
1215  return true;
1216  }
1217  case Hexagon::PS_qtrue: {
1218  BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1219  .addReg(Hexagon::V0, RegState::Undef)
1220  .addReg(Hexagon::V0, RegState::Undef);
1221  MBB.erase(MI);
1222  return true;
1223  }
1224  case Hexagon::PS_qfalse: {
1225  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1226  .addReg(Hexagon::V0, RegState::Undef)
1227  .addReg(Hexagon::V0, RegState::Undef);
1228  MBB.erase(MI);
1229  return true;
1230  }
1231  case Hexagon::PS_vdd0: {
1232  Register Vd = MI.getOperand(0).getReg();
1233  BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1234  .addReg(Vd, RegState::Undef)
1235  .addReg(Vd, RegState::Undef);
1236  MBB.erase(MI);
1237  return true;
1238  }
1239  case Hexagon::PS_vmulw: {
1240  // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1241  Register DstReg = MI.getOperand(0).getReg();
1242  Register Src1Reg = MI.getOperand(1).getReg();
1243  Register Src2Reg = MI.getOperand(2).getReg();
1244  Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1245  Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1246  Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1247  Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1248  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1249  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1250  .addReg(Src1SubHi)
1251  .addReg(Src2SubHi);
1252  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1253  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1254  .addReg(Src1SubLo)
1255  .addReg(Src2SubLo);
1256  MBB.erase(MI);
1257  MRI.clearKillFlags(Src1SubHi);
1258  MRI.clearKillFlags(Src1SubLo);
1259  MRI.clearKillFlags(Src2SubHi);
1260  MRI.clearKillFlags(Src2SubLo);
1261  return true;
1262  }
1263  case Hexagon::PS_vmulw_acc: {
1264  // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1265  Register DstReg = MI.getOperand(0).getReg();
1266  Register Src1Reg = MI.getOperand(1).getReg();
1267  Register Src2Reg = MI.getOperand(2).getReg();
1268  Register Src3Reg = MI.getOperand(3).getReg();
1269  Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1270  Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1271  Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1272  Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1273  Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1274  Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1275  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1276  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1277  .addReg(Src1SubHi)
1278  .addReg(Src2SubHi)
1279  .addReg(Src3SubHi);
1280  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1281  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1282  .addReg(Src1SubLo)
1283  .addReg(Src2SubLo)
1284  .addReg(Src3SubLo);
1285  MBB.erase(MI);
1286  MRI.clearKillFlags(Src1SubHi);
1287  MRI.clearKillFlags(Src1SubLo);
1288  MRI.clearKillFlags(Src2SubHi);
1289  MRI.clearKillFlags(Src2SubLo);
1290  MRI.clearKillFlags(Src3SubHi);
1291  MRI.clearKillFlags(Src3SubLo);
1292  return true;
1293  }
1294  case Hexagon::PS_pselect: {
1295  const MachineOperand &Op0 = MI.getOperand(0);
1296  const MachineOperand &Op1 = MI.getOperand(1);
1297  const MachineOperand &Op2 = MI.getOperand(2);
1298  const MachineOperand &Op3 = MI.getOperand(3);
1299  Register Rd = Op0.getReg();
1300  Register Pu = Op1.getReg();
1301  Register Rs = Op2.getReg();
1302  Register Rt = Op3.getReg();
1303  DebugLoc DL = MI.getDebugLoc();
1304  unsigned K1 = getKillRegState(Op1.isKill());
1305  unsigned K2 = getKillRegState(Op2.isKill());
1306  unsigned K3 = getKillRegState(Op3.isKill());
1307  if (Rd != Rs)
1308  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1309  .addReg(Pu, (Rd == Rt) ? K1 : 0)
1310  .addReg(Rs, K2);
1311  if (Rd != Rt)
1312  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1313  .addReg(Pu, K1)
1314  .addReg(Rt, K3);
1315  MBB.erase(MI);
1316  return true;
1317  }
1318  case Hexagon::PS_vselect: {
1319  const MachineOperand &Op0 = MI.getOperand(0);
1320  const MachineOperand &Op1 = MI.getOperand(1);
1321  const MachineOperand &Op2 = MI.getOperand(2);
1322  const MachineOperand &Op3 = MI.getOperand(3);
1323  getLiveOutRegsAt(LiveOut, MI);
1324  bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
1325  Register PReg = Op1.getReg();
1326  assert(Op1.getSubReg() == 0);
1327  unsigned PState = getRegState(Op1);
1328 
1329  if (Op0.getReg() != Op2.getReg()) {
1330  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1331  : PState;
1332  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1333  .add(Op0)
1334  .addReg(PReg, S)
1335  .add(Op2);
1336  if (IsDestLive)
1337  T.addReg(Op0.getReg(), RegState::Implicit);
1338  IsDestLive = true;
1339  }
1340  if (Op0.getReg() != Op3.getReg()) {
1341  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1342  .add(Op0)
1343  .addReg(PReg, PState)
1344  .add(Op3);
1345  if (IsDestLive)
1346  T.addReg(Op0.getReg(), RegState::Implicit);
1347  }
1348  MBB.erase(MI);
1349  return true;
1350  }
1351  case Hexagon::PS_wselect: {
1352  MachineOperand &Op0 = MI.getOperand(0);
1353  MachineOperand &Op1 = MI.getOperand(1);
1354  MachineOperand &Op2 = MI.getOperand(2);
1355  MachineOperand &Op3 = MI.getOperand(3);
1356  getLiveOutRegsAt(LiveOut, MI);
1357  bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
1358  Register PReg = Op1.getReg();
1359  assert(Op1.getSubReg() == 0);
1360  unsigned PState = getRegState(Op1);
1361 
1362  if (Op0.getReg() != Op2.getReg()) {
1363  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1364  : PState;
1365  Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1366  Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1367  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1368  .add(Op0)
1369  .addReg(PReg, S)
1370  .addReg(SrcHi)
1371  .addReg(SrcLo);
1372  if (IsDestLive)
1373  T.addReg(Op0.getReg(), RegState::Implicit);
1374  IsDestLive = true;
1375  }
1376  if (Op0.getReg() != Op3.getReg()) {
1377  Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1378  Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1379  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1380  .add(Op0)
1381  .addReg(PReg, PState)
1382  .addReg(SrcHi)
1383  .addReg(SrcLo);
1384  if (IsDestLive)
1385  T.addReg(Op0.getReg(), RegState::Implicit);
1386  }
1387  MBB.erase(MI);
1388  return true;
1389  }
1390 
1391  case Hexagon::PS_crash: {
1392  // Generate a misaligned load that is guaranteed to cause a crash.
1393  class CrashPseudoSourceValue : public PseudoSourceValue {
1394  public:
1395  CrashPseudoSourceValue(const TargetInstrInfo &TII)
1396  : PseudoSourceValue(TargetCustom, TII) {}
1397 
1398  bool isConstant(const MachineFrameInfo *) const override {
1399  return false;
1400  }
1401  bool isAliased(const MachineFrameInfo *) const override {
1402  return false;
1403  }
1404  bool mayAlias(const MachineFrameInfo *) const override {
1405  return false;
1406  }
1407  void printCustom(raw_ostream &OS) const override {
1408  OS << "MisalignedCrash";
1409  }
1410  };
1411 
1412  static const CrashPseudoSourceValue CrashPSV(*this);
1414  MachinePointerInfo(&CrashPSV),
1416  Align(1));
1417  BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
1418  .addImm(0xBADC0FEE) // Misaligned load.
1419  .addMemOperand(MMO);
1420  MBB.erase(MI);
1421  return true;
1422  }
1423 
1424  case Hexagon::PS_tailcall_i:
1425  MI.setDesc(get(Hexagon::J2_jump));
1426  return true;
1427  case Hexagon::PS_tailcall_r:
1428  case Hexagon::PS_jmpret:
1429  MI.setDesc(get(Hexagon::J2_jumpr));
1430  return true;
1431  case Hexagon::PS_jmprett:
1432  MI.setDesc(get(Hexagon::J2_jumprt));
1433  return true;
1434  case Hexagon::PS_jmpretf:
1435  MI.setDesc(get(Hexagon::J2_jumprf));
1436  return true;
1437  case Hexagon::PS_jmprettnewpt:
1438  MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1439  return true;
1440  case Hexagon::PS_jmpretfnewpt:
1441  MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1442  return true;
1443  case Hexagon::PS_jmprettnew:
1444  MI.setDesc(get(Hexagon::J2_jumprtnew));
1445  return true;
1446  case Hexagon::PS_jmpretfnew:
1447  MI.setDesc(get(Hexagon::J2_jumprfnew));
1448  return true;
1449 
1450  case Hexagon::PS_loadrub_pci:
1451  return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1452  case Hexagon::PS_loadrb_pci:
1453  return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1454  case Hexagon::PS_loadruh_pci:
1455  return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1456  case Hexagon::PS_loadrh_pci:
1457  return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1458  case Hexagon::PS_loadri_pci:
1459  return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1460  case Hexagon::PS_loadrd_pci:
1461  return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1462  case Hexagon::PS_loadrub_pcr:
1463  return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1464  case Hexagon::PS_loadrb_pcr:
1465  return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1466  case Hexagon::PS_loadruh_pcr:
1467  return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1468  case Hexagon::PS_loadrh_pcr:
1469  return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1470  case Hexagon::PS_loadri_pcr:
1471  return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1472  case Hexagon::PS_loadrd_pcr:
1473  return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1474  case Hexagon::PS_storerb_pci:
1475  return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1476  case Hexagon::PS_storerh_pci:
1477  return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1478  case Hexagon::PS_storerf_pci:
1479  return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1480  case Hexagon::PS_storeri_pci:
1481  return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1482  case Hexagon::PS_storerd_pci:
1483  return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1484  case Hexagon::PS_storerb_pcr:
1485  return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1486  case Hexagon::PS_storerh_pcr:
1487  return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1488  case Hexagon::PS_storerf_pcr:
1489  return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1490  case Hexagon::PS_storeri_pcr:
1491  return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1492  case Hexagon::PS_storerd_pcr:
1493  return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1494  }
1495 
1496  return false;
1497 }
1498 
1501  MachineBasicBlock &MBB = *MI.getParent();
1502  const DebugLoc &DL = MI.getDebugLoc();
1503  unsigned Opc = MI.getOpcode();
1505 
1506  switch (Opc) {
1507  case Hexagon::V6_vgathermh_pseudo:
1508  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1509  .add(MI.getOperand(2))
1510  .add(MI.getOperand(3))
1511  .add(MI.getOperand(4));
1512  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1513  .add(MI.getOperand(0))
1514  .addImm(MI.getOperand(1).getImm())
1515  .addReg(Hexagon::VTMP);
1516  MBB.erase(MI);
1517  return First.getInstrIterator();
1518 
1519  case Hexagon::V6_vgathermw_pseudo:
1520  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1521  .add(MI.getOperand(2))
1522  .add(MI.getOperand(3))
1523  .add(MI.getOperand(4));
1524  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1525  .add(MI.getOperand(0))
1526  .addImm(MI.getOperand(1).getImm())
1527  .addReg(Hexagon::VTMP);
1528  MBB.erase(MI);
1529  return First.getInstrIterator();
1530 
1531  case Hexagon::V6_vgathermhw_pseudo:
1532  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1533  .add(MI.getOperand(2))
1534  .add(MI.getOperand(3))
1535  .add(MI.getOperand(4));
1536  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1537  .add(MI.getOperand(0))
1538  .addImm(MI.getOperand(1).getImm())
1539  .addReg(Hexagon::VTMP);
1540  MBB.erase(MI);
1541  return First.getInstrIterator();
1542 
1543  case Hexagon::V6_vgathermhq_pseudo:
1544  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1545  .add(MI.getOperand(2))
1546  .add(MI.getOperand(3))
1547  .add(MI.getOperand(4))
1548  .add(MI.getOperand(5));
1549  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1550  .add(MI.getOperand(0))
1551  .addImm(MI.getOperand(1).getImm())
1552  .addReg(Hexagon::VTMP);
1553  MBB.erase(MI);
1554  return First.getInstrIterator();
1555 
1556  case Hexagon::V6_vgathermwq_pseudo:
1557  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1558  .add(MI.getOperand(2))
1559  .add(MI.getOperand(3))
1560  .add(MI.getOperand(4))
1561  .add(MI.getOperand(5));
1562  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1563  .add(MI.getOperand(0))
1564  .addImm(MI.getOperand(1).getImm())
1565  .addReg(Hexagon::VTMP);
1566  MBB.erase(MI);
1567  return First.getInstrIterator();
1568 
1569  case Hexagon::V6_vgathermhwq_pseudo:
1570  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1571  .add(MI.getOperand(2))
1572  .add(MI.getOperand(3))
1573  .add(MI.getOperand(4))
1574  .add(MI.getOperand(5));
1575  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1576  .add(MI.getOperand(0))
1577  .addImm(MI.getOperand(1).getImm())
1578  .addReg(Hexagon::VTMP);
1579  MBB.erase(MI);
1580  return First.getInstrIterator();
1581  }
1582 
1583  return MI.getIterator();
1584 }
1585 
1586 // We indicate that we want to reverse the branch by
1587 // inserting the reversed branching opcode.
1590  if (Cond.empty())
1591  return true;
1592  assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1593  unsigned opcode = Cond[0].getImm();
1594  //unsigned temp;
1595  assert(get(opcode).isBranch() && "Should be a branching condition.");
1596  if (isEndLoopN(opcode))
1597  return true;
1598  unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1599  Cond[0].setImm(NewOpcode);
1600  return false;
1601 }
1602 
1605  DebugLoc DL;
1606  BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1607 }
1608 
1610  return getAddrMode(MI) == HexagonII::PostInc;
1611 }
1612 
1613 // Returns true if an instruction is predicated irrespective of the predicate
1614 // sense. For example, all of the following will return true.
1615 // if (p0) R1 = add(R2, R3)
1616 // if (!p0) R1 = add(R2, R3)
1617 // if (p0.new) R1 = add(R2, R3)
1618 // if (!p0.new) R1 = add(R2, R3)
1619 // Note: New-value stores are not included here as in the current
1620 // implementation, we don't need to check their predicate sense.
1622  const uint64_t F = MI.getDesc().TSFlags;
1624 }
1625 
1628  if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1629  isEndLoopN(Cond[0].getImm())) {
1630  LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1631  return false;
1632  }
1633  int Opc = MI.getOpcode();
1634  assert (isPredicable(MI) && "Expected predicable instruction");
1635  bool invertJump = predOpcodeHasNot(Cond);
1636 
1637  // We have to predicate MI "in place", i.e. after this function returns,
1638  // MI will need to be transformed into a predicated form. To avoid com-
1639  // plicated manipulations with the operands (handling tied operands,
1640  // etc.), build a new temporary instruction, then overwrite MI with it.
1641 
1642  MachineBasicBlock &B = *MI.getParent();
1643  DebugLoc DL = MI.getDebugLoc();
1644  unsigned PredOpc = getCondOpcode(Opc, invertJump);
1645  MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1646  unsigned NOp = 0, NumOps = MI.getNumOperands();
1647  while (NOp < NumOps) {
1648  MachineOperand &Op = MI.getOperand(NOp);
1649  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1650  break;
1651  T.add(Op);
1652  NOp++;
1653  }
1654 
1655  unsigned PredReg, PredRegPos, PredRegFlags;
1656  bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1657  (void)GotPredReg;
1658  assert(GotPredReg);
1659  T.addReg(PredReg, PredRegFlags);
1660  while (NOp < NumOps)
1661  T.add(MI.getOperand(NOp++));
1662 
1663  MI.setDesc(get(PredOpc));
1664  while (unsigned n = MI.getNumOperands())
1665  MI.RemoveOperand(n-1);
1666  for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1667  MI.addOperand(T->getOperand(i));
1668 
1669  MachineBasicBlock::instr_iterator TI = T->getIterator();
1670  B.erase(TI);
1671 
1672  MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1673  MRI.clearKillFlags(PredReg);
1674  return true;
1675 }
1676 
1678  ArrayRef<MachineOperand> Pred2) const {
1679  // TODO: Fix this
1680  return false;
1681 }
1682 
1684  std::vector<MachineOperand> &Pred,
1685  bool SkipDead) const {
1686  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1687 
1688  for (const MachineOperand &MO : MI.operands()) {
1689  if (MO.isReg()) {
1690  if (!MO.isDef())
1691  continue;
1692  const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1693  if (RC == &Hexagon::PredRegsRegClass) {
1694  Pred.push_back(MO);
1695  return true;
1696  }
1697  continue;
1698  } else if (MO.isRegMask()) {
1699  for (unsigned PR : Hexagon::PredRegsRegClass) {
1700  if (!MI.modifiesRegister(PR, &HRI))
1701  continue;
1702  Pred.push_back(MO);
1703  return true;
1704  }
1705  }
1706  }
1707  return false;
1708 }
1709 
1711  if (!MI.getDesc().isPredicable())
1712  return false;
1713 
1714  if (MI.isCall() || isTailCall(MI)) {
1715  if (!Subtarget.usePredicatedCalls())
1716  return false;
1717  }
1718 
1719  // HVX loads are not predicable on v60, but are on v62.
1720  if (!Subtarget.hasV62Ops()) {
1721  switch (MI.getOpcode()) {
1722  case Hexagon::V6_vL32b_ai:
1723  case Hexagon::V6_vL32b_pi:
1724  case Hexagon::V6_vL32b_ppu:
1725  case Hexagon::V6_vL32b_cur_ai:
1726  case Hexagon::V6_vL32b_cur_pi:
1727  case Hexagon::V6_vL32b_cur_ppu:
1728  case Hexagon::V6_vL32b_nt_ai:
1729  case Hexagon::V6_vL32b_nt_pi:
1730  case Hexagon::V6_vL32b_nt_ppu:
1731  case Hexagon::V6_vL32b_tmp_ai:
1732  case Hexagon::V6_vL32b_tmp_pi:
1733  case Hexagon::V6_vL32b_tmp_ppu:
1734  case Hexagon::V6_vL32b_nt_cur_ai:
1735  case Hexagon::V6_vL32b_nt_cur_pi:
1736  case Hexagon::V6_vL32b_nt_cur_ppu:
1737  case Hexagon::V6_vL32b_nt_tmp_ai:
1738  case Hexagon::V6_vL32b_nt_tmp_pi:
1739  case Hexagon::V6_vL32b_nt_tmp_ppu:
1740  return false;
1741  }
1742  }
1743  return true;
1744 }
1745 
1747  const MachineBasicBlock *MBB,
1748  const MachineFunction &MF) const {
1749  // Debug info is never a scheduling boundary. It's necessary to be explicit
1750  // due to the special treatment of IT instructions below, otherwise a
1751  // dbg_value followed by an IT will result in the IT instruction being
1752  // considered a scheduling hazard, which is wrong. It should be the actual
1753  // instruction preceding the dbg_value instruction(s), just like it is
1754  // when debug info is not present.
1755  if (MI.isDebugInstr())
1756  return false;
1757 
1758  // Throwing call is a boundary.
1759  if (MI.isCall()) {
1760  // Don't mess around with no return calls.
1761  if (doesNotReturn(MI))
1762  return true;
1763  // If any of the block's successors is a landing pad, this could be a
1764  // throwing call.
1765  for (auto I : MBB->successors())
1766  if (I->isEHPad())
1767  return true;
1768  }
1769 
1770  // Terminators and labels can't be scheduled around.
1771  if (MI.getDesc().isTerminator() || MI.isPosition())
1772  return true;
1773 
1774  // INLINEASM_BR can jump to another block
1775  if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1776  return true;
1777 
1778  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1779  return true;
1780 
1781  return false;
1782 }
1783 
1784 /// Measure the specified inline asm to determine an approximation of its
1785 /// length.
1786 /// Comments (which run till the next SeparatorString or newline) do not
1787 /// count as an instruction.
1788 /// Any other non-whitespace text is considered an instruction, with
1789 /// multiple instructions separated by SeparatorString or newlines.
1790 /// Variable-length instructions are not handled here; this function
1791 /// may be overloaded in the target code to do that.
1792 /// Hexagon counts the number of ##'s and adjust for that many
1793 /// constant exenders.
1794 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1795  const MCAsmInfo &MAI,
1796  const TargetSubtargetInfo *STI) const {
1797  StringRef AStr(Str);
1798  // Count the number of instructions in the asm.
1799  bool atInsnStart = true;
1800  unsigned Length = 0;
1801  const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
1802  for (; *Str; ++Str) {
1803  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1804  strlen(MAI.getSeparatorString())) == 0)
1805  atInsnStart = true;
1806  if (atInsnStart && !isSpace(static_cast<unsigned char>(*Str))) {
1807  Length += MaxInstLength;
1808  atInsnStart = false;
1809  }
1810  if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1811  MAI.getCommentString().size()) == 0)
1812  atInsnStart = false;
1813  }
1814 
1815  // Add to size number of constant extenders seen * 4.
1816  StringRef Occ("##");
1817  Length += AStr.count(Occ)*4;
1818  return Length;
1819 }
1820 
1823  const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1824  if (UseDFAHazardRec)
1825  return new HexagonHazardRecognizer(II, this, Subtarget);
1827 }
1828 
1829 /// For a comparison instruction, return the source registers in
1830 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1831 /// compares against in CmpValue. Return true if the comparison instruction
1832 /// can be analyzed.
1834  Register &SrcReg2, int64_t &Mask,
1835  int64_t &Value) const {
1836  unsigned Opc = MI.getOpcode();
1837 
1838  // Set mask and the first source register.
1839  switch (Opc) {
1840  case Hexagon::C2_cmpeq:
1841  case Hexagon::C2_cmpeqp:
1842  case Hexagon::C2_cmpgt:
1843  case Hexagon::C2_cmpgtp:
1844  case Hexagon::C2_cmpgtu:
1845  case Hexagon::C2_cmpgtup:
1846  case Hexagon::C4_cmpneq:
1847  case Hexagon::C4_cmplte:
1848  case Hexagon::C4_cmplteu:
1849  case Hexagon::C2_cmpeqi:
1850  case Hexagon::C2_cmpgti:
1851  case Hexagon::C2_cmpgtui:
1852  case Hexagon::C4_cmpneqi:
1853  case Hexagon::C4_cmplteui:
1854  case Hexagon::C4_cmpltei:
1855  SrcReg = MI.getOperand(1).getReg();
1856  Mask = ~0;
1857  break;
1858  case Hexagon::A4_cmpbeq:
1859  case Hexagon::A4_cmpbgt:
1860  case Hexagon::A4_cmpbgtu:
1861  case Hexagon::A4_cmpbeqi:
1862  case Hexagon::A4_cmpbgti:
1863  case Hexagon::A4_cmpbgtui:
1864  SrcReg = MI.getOperand(1).getReg();
1865  Mask = 0xFF;
1866  break;
1867  case Hexagon::A4_cmpheq:
1868  case Hexagon::A4_cmphgt:
1869  case Hexagon::A4_cmphgtu:
1870  case Hexagon::A4_cmpheqi:
1871  case Hexagon::A4_cmphgti:
1872  case Hexagon::A4_cmphgtui:
1873  SrcReg = MI.getOperand(1).getReg();
1874  Mask = 0xFFFF;
1875  break;
1876  }
1877 
1878  // Set the value/second source register.
1879  switch (Opc) {
1880  case Hexagon::C2_cmpeq:
1881  case Hexagon::C2_cmpeqp:
1882  case Hexagon::C2_cmpgt:
1883  case Hexagon::C2_cmpgtp:
1884  case Hexagon::C2_cmpgtu:
1885  case Hexagon::C2_cmpgtup:
1886  case Hexagon::A4_cmpbeq:
1887  case Hexagon::A4_cmpbgt:
1888  case Hexagon::A4_cmpbgtu:
1889  case Hexagon::A4_cmpheq:
1890  case Hexagon::A4_cmphgt:
1891  case Hexagon::A4_cmphgtu:
1892  case Hexagon::C4_cmpneq:
1893  case Hexagon::C4_cmplte:
1894  case Hexagon::C4_cmplteu:
1895  SrcReg2 = MI.getOperand(2).getReg();
1896  Value = 0;
1897  return true;
1898 
1899  case Hexagon::C2_cmpeqi:
1900  case Hexagon::C2_cmpgtui:
1901  case Hexagon::C2_cmpgti:
1902  case Hexagon::C4_cmpneqi:
1903  case Hexagon::C4_cmplteui:
1904  case Hexagon::C4_cmpltei:
1905  case Hexagon::A4_cmpbeqi:
1906  case Hexagon::A4_cmpbgti:
1907  case Hexagon::A4_cmpbgtui:
1908  case Hexagon::A4_cmpheqi:
1909  case Hexagon::A4_cmphgti:
1910  case Hexagon::A4_cmphgtui: {
1911  SrcReg2 = 0;
1912  const MachineOperand &Op2 = MI.getOperand(2);
1913  if (!Op2.isImm())
1914  return false;
1915  Value = MI.getOperand(2).getImm();
1916  return true;
1917  }
1918  }
1919 
1920  return false;
1921 }
1922 
1924  const MachineInstr &MI,
1925  unsigned *PredCost) const {
1926  return getInstrTimingClassLatency(ItinData, MI);
1927 }
1928 
1930  const TargetSubtargetInfo &STI) const {
1931  const InstrItineraryData *II = STI.getInstrItineraryData();
1932  return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1933 }
1934 
1935 // Inspired by this pair:
1936 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1937 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1938 // Currently AA considers the addresses in these instructions to be aliasing.
1940  const MachineInstr &MIa, const MachineInstr &MIb) const {
1941  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1943  return false;
1944 
1945  // Instructions that are pure loads, not loads and stores like memops are not
1946  // dependent.
1947  if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1948  return true;
1949 
1950  // Get the base register in MIa.
1951  unsigned BasePosA, OffsetPosA;
1952  if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1953  return false;
1954  const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1955  Register BaseRegA = BaseA.getReg();
1956  unsigned BaseSubA = BaseA.getSubReg();
1957 
1958  // Get the base register in MIb.
1959  unsigned BasePosB, OffsetPosB;
1960  if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1961  return false;
1962  const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1963  Register BaseRegB = BaseB.getReg();
1964  unsigned BaseSubB = BaseB.getSubReg();
1965 
1966  if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
1967  return false;
1968 
1969  // Get the access sizes.
1970  unsigned SizeA = getMemAccessSize(MIa);
1971  unsigned SizeB = getMemAccessSize(MIb);
1972 
1973  // Get the offsets. Handle immediates only for now.
1974  const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1975  const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1976  if (!MIa.getOperand(OffsetPosA).isImm() ||
1977  !MIb.getOperand(OffsetPosB).isImm())
1978  return false;
1979  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
1980  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
1981 
1982  // This is a mem access with the same base register and known offsets from it.
1983  // Reason about it.
1984  if (OffsetA > OffsetB) {
1985  uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1986  return SizeB <= OffDiff;
1987  }
1988  if (OffsetA < OffsetB) {
1989  uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1990  return SizeA <= OffDiff;
1991  }
1992 
1993  return false;
1994 }
1995 
1996 /// If the instruction is an increment of a constant value, return the amount.
1998  int &Value) const {
1999  if (isPostIncrement(MI)) {
2000  unsigned BasePos = 0, OffsetPos = 0;
2001  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
2002  return false;
2003  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
2004  if (OffsetOp.isImm()) {
2005  Value = OffsetOp.getImm();
2006  return true;
2007  }
2008  } else if (MI.getOpcode() == Hexagon::A2_addi) {
2009  const MachineOperand &AddOp = MI.getOperand(2);
2010  if (AddOp.isImm()) {
2011  Value = AddOp.getImm();
2012  return true;
2013  }
2014  }
2015 
2016  return false;
2017 }
2018 
2019 std::pair<unsigned, unsigned>
2021  return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
2022  TF & HexagonII::MO_Bitmasks);
2023 }
2024 
2027  using namespace HexagonII;
2028 
2029  static const std::pair<unsigned, const char*> Flags[] = {
2030  {MO_PCREL, "hexagon-pcrel"},
2031  {MO_GOT, "hexagon-got"},
2032  {MO_LO16, "hexagon-lo16"},
2033  {MO_HI16, "hexagon-hi16"},
2034  {MO_GPREL, "hexagon-gprel"},
2035  {MO_GDGOT, "hexagon-gdgot"},
2036  {MO_GDPLT, "hexagon-gdplt"},
2037  {MO_IE, "hexagon-ie"},
2038  {MO_IEGOT, "hexagon-iegot"},
2039  {MO_TPREL, "hexagon-tprel"}
2040  };
2041  return makeArrayRef(Flags);
2042 }
2043 
2046  using namespace HexagonII;
2047 
2048  static const std::pair<unsigned, const char*> Flags[] = {
2049  {HMOTF_ConstExtended, "hexagon-ext"}
2050  };
2051  return makeArrayRef(Flags);
2052 }
2053 
2056  const TargetRegisterClass *TRC;
2057  if (VT == MVT::i1) {
2058  TRC = &Hexagon::PredRegsRegClass;
2059  } else if (VT == MVT::i32 || VT == MVT::f32) {
2060  TRC = &Hexagon::IntRegsRegClass;
2061  } else if (VT == MVT::i64 || VT == MVT::f64) {
2062  TRC = &Hexagon::DoubleRegsRegClass;
2063  } else {
2064  llvm_unreachable("Cannot handle this register class");
2065  }
2066 
2067  Register NewReg = MRI.createVirtualRegister(TRC);
2068  return NewReg;
2069 }
2070 
2072  return (getAddrMode(MI) == HexagonII::AbsoluteSet);
2073 }
2074 
2076  const uint64_t F = MI.getDesc().TSFlags;
2078 }
2079 
2082 }
2083 
2085  return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
2086  !MI.getDesc().mayStore() &&
2087  MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2088  MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2089  !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
2090 }
2091 
2092 // Return true if the instruction is a compund branch instruction.
2094  return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
2095 }
2096 
2097 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
2098 // isFPImm and later getFPImm as well.
2100  const uint64_t F = MI.getDesc().TSFlags;
2102  if (isExtended) // Instruction must be extended.
2103  return true;
2104 
2105  unsigned isExtendable =
2107  if (!isExtendable)
2108  return false;
2109 
2110  if (MI.isCall())
2111  return false;
2112 
2113  short ExtOpNum = getCExtOpNum(MI);
2114  const MachineOperand &MO = MI.getOperand(ExtOpNum);
2115  // Use MO operand flags to determine if MO
2116  // has the HMOTF_ConstExtended flag set.
2118  return true;
2119  // If this is a Machine BB address we are talking about, and it is
2120  // not marked as extended, say so.
2121  if (MO.isMBB())
2122  return false;
2123 
2124  // We could be using an instruction with an extendable immediate and shoehorn
2125  // a global address into it. If it is a global address it will be constant
2126  // extended. We do this for COMBINE.
2127  if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2128  MO.isJTI() || MO.isCPI() || MO.isFPImm())
2129  return true;
2130 
2131  // If the extendable operand is not 'Immediate' type, the instruction should
2132  // have 'isExtended' flag set.
2133  assert(MO.isImm() && "Extendable operand must be Immediate type");
2134 
2135  int MinValue = getMinValue(MI);
2136  int MaxValue = getMaxValue(MI);
2137  int ImmValue = MO.getImm();
2138 
2139  return (ImmValue < MinValue || ImmValue > MaxValue);
2140 }
2141 
2143  switch (MI.getOpcode()) {
2144  case Hexagon::L4_return:
2145  case Hexagon::L4_return_t:
2146  case Hexagon::L4_return_f:
2147  case Hexagon::L4_return_tnew_pnt:
2148  case Hexagon::L4_return_fnew_pnt:
2149  case Hexagon::L4_return_tnew_pt:
2150  case Hexagon::L4_return_fnew_pt:
2151  return true;
2152  }
2153  return false;
2154 }
2155 
2156 // Return true when ConsMI uses a register defined by ProdMI.
2158  const MachineInstr &ConsMI) const {
2159  if (!ProdMI.getDesc().getNumDefs())
2160  return false;
2161  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2162 
2167 
2168  parseOperands(ProdMI, DefsA, UsesA);
2169  parseOperands(ConsMI, DefsB, UsesB);
2170 
2171  for (auto &RegA : DefsA)
2172  for (auto &RegB : UsesB) {
2173  // True data dependency.
2174  if (RegA == RegB)
2175  return true;
2176 
2177  if (Register::isPhysicalRegister(RegA))
2178  for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
2179  if (RegB == *SubRegs)
2180  return true;
2181 
2182  if (Register::isPhysicalRegister(RegB))
2183  for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
2184  if (RegA == *SubRegs)
2185  return true;
2186  }
2187 
2188  return false;
2189 }
2190 
2191 // Returns true if the instruction is alread a .cur.
2193  switch (MI.getOpcode()) {
2194  case Hexagon::V6_vL32b_cur_pi:
2195  case Hexagon::V6_vL32b_cur_ai:
2196  return true;
2197  }
2198  return false;
2199 }
2200 
2201 // Returns true, if any one of the operands is a dot new
2202 // insn, whether it is predicated dot new or register dot new.
2205  return true;
2206 
2207  return false;
2208 }
2209 
2210 /// Symmetrical. See if these two instructions are fit for duplex pair.
2212  const MachineInstr &MIb) const {
2215  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2216 }
2217 
2219  if (MI.mayLoadOrStore() || MI.isCompare())
2220  return true;
2221 
2222  // Multiply
2223  unsigned SchedClass = MI.getDesc().getSchedClass();
2224  return is_TC4x(SchedClass) || is_TC3x(SchedClass);
2225 }
2226 
2227 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2228  return (Opcode == Hexagon::ENDLOOP0 ||
2229  Opcode == Hexagon::ENDLOOP1);
2230 }
2231 
2232 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2233  switch(OpType) {
2240  return true;
2241  default:
2242  return false;
2243  }
2244 }
2245 
2247  const MCInstrDesc &MID = MI.getDesc();
2248  const uint64_t F = MID.TSFlags;
2250  return true;
2251 
2252  // TODO: This is largely obsolete now. Will need to be removed
2253  // in consecutive patches.
2254  switch (MI.getOpcode()) {
2255  // PS_fi and PS_fia remain special cases.
2256  case Hexagon::PS_fi:
2257  case Hexagon::PS_fia:
2258  return true;
2259  default:
2260  return false;
2261  }
2262  return false;
2263 }
2264 
2265 // This returns true in two cases:
2266 // - The OP code itself indicates that this is an extended instruction.
2267 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2269  // First check if this is permanently extended op code.
2270  const uint64_t F = MI.getDesc().TSFlags;
2272  return true;
2273  // Use MO operand flags to determine if one of MI's operands
2274  // has HMOTF_ConstExtended flag set.
2275  for (const MachineOperand &MO : MI.operands())
2276  if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2277  return true;
2278  return false;
2279 }
2280 
2282  unsigned Opcode = MI.getOpcode();
2283  const uint64_t F = get(Opcode).TSFlags;
2284  return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2285 }
2286 
2287 // No V60 HVX VMEM with A_INDIRECT.
2289  const MachineInstr &J) const {
2290  if (!isHVXVec(I))
2291  return false;
2292  if (!I.mayLoad() && !I.mayStore())
2293  return false;
2294  return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2295 }
2296 
2298  switch (MI.getOpcode()) {
2299  case Hexagon::J2_callr:
2300  case Hexagon::J2_callrf:
2301  case Hexagon::J2_callrt:
2302  case Hexagon::PS_call_nr:
2303  return true;
2304  }
2305  return false;
2306 }
2307 
2309  switch (MI.getOpcode()) {
2310  case Hexagon::L4_return:
2311  case Hexagon::L4_return_t:
2312  case Hexagon::L4_return_f:
2313  case Hexagon::L4_return_fnew_pnt:
2314  case Hexagon::L4_return_fnew_pt:
2315  case Hexagon::L4_return_tnew_pnt:
2316  case Hexagon::L4_return_tnew_pt:
2317  return true;
2318  }
2319  return false;
2320 }
2321 
2323  switch (MI.getOpcode()) {
2324  case Hexagon::J2_jumpr:
2325  case Hexagon::J2_jumprt:
2326  case Hexagon::J2_jumprf:
2327  case Hexagon::J2_jumprtnewpt:
2328  case Hexagon::J2_jumprfnewpt:
2329  case Hexagon::J2_jumprtnew:
2330  case Hexagon::J2_jumprfnew:
2331  return true;
2332  }
2333  return false;
2334 }
2335 
2336 // Return true if a given MI can accommodate given offset.
2337 // Use abs estimate as oppose to the exact number.
2338 // TODO: This will need to be changed to use MC level
2339 // definition of instruction extendable field size.
2341  unsigned offset) const {
2342  // This selection of jump instructions matches to that what
2343  // analyzeBranch can parse, plus NVJ.
2344  if (isNewValueJump(MI)) // r9:2
2345  return isInt<11>(offset);
2346 
2347  switch (MI.getOpcode()) {
2348  // Still missing Jump to address condition on register value.
2349  default:
2350  return false;
2351  case Hexagon::J2_jump: // bits<24> dst; // r22:2
2352  case Hexagon::J2_call:
2353  case Hexagon::PS_call_nr:
2354  return isInt<24>(offset);
2355  case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2356  case Hexagon::J2_jumpf:
2357  case Hexagon::J2_jumptnew:
2358  case Hexagon::J2_jumptnewpt:
2359  case Hexagon::J2_jumpfnew:
2360  case Hexagon::J2_jumpfnewpt:
2361  case Hexagon::J2_callt:
2362  case Hexagon::J2_callf:
2363  return isInt<17>(offset);
2364  case Hexagon::J2_loop0i:
2365  case Hexagon::J2_loop0iext:
2366  case Hexagon::J2_loop0r:
2367  case Hexagon::J2_loop0rext:
2368  case Hexagon::J2_loop1i:
2369  case Hexagon::J2_loop1iext:
2370  case Hexagon::J2_loop1r:
2371  case Hexagon::J2_loop1rext:
2372  return isInt<9>(offset);
2373  // TODO: Add all the compound branches here. Can we do this in Relation model?
2374  case Hexagon::J4_cmpeqi_tp0_jump_nt:
2375  case Hexagon::J4_cmpeqi_tp1_jump_nt:
2376  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2377  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2378  return isInt<11>(offset);
2379  }
2380 }
2381 
2383  const MachineInstr &ESMI) const {
2384  bool isLate = isLateResultInstr(LRMI);
2385  bool isEarly = isEarlySourceInstr(ESMI);
2386 
2387  LLVM_DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2388  LLVM_DEBUG(LRMI.dump());
2389  LLVM_DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2390  LLVM_DEBUG(ESMI.dump());
2391 
2392  if (isLate && isEarly) {
2393  LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2394  return true;
2395  }
2396 
2397  return false;
2398 }
2399 
2401  switch (MI.getOpcode()) {
2402  case TargetOpcode::EXTRACT_SUBREG:
2403  case TargetOpcode::INSERT_SUBREG:
2404  case TargetOpcode::SUBREG_TO_REG:
2405  case TargetOpcode::REG_SEQUENCE:
2406  case TargetOpcode::IMPLICIT_DEF:
2407  case TargetOpcode::COPY:
2409  case TargetOpcode::PHI:
2410  return false;
2411  default:
2412  break;
2413  }
2414 
2415  unsigned SchedClass = MI.getDesc().getSchedClass();
2416  return !is_TC1(SchedClass);
2417 }
2418 
2420  // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2421  // resource, but all operands can be received late like an ALU instruction.
2423 }
2424 
2426  unsigned Opcode = MI.getOpcode();
2427  return Opcode == Hexagon::J2_loop0i ||
2428  Opcode == Hexagon::J2_loop0r ||
2429  Opcode == Hexagon::J2_loop0iext ||
2430  Opcode == Hexagon::J2_loop0rext ||
2431  Opcode == Hexagon::J2_loop1i ||
2432  Opcode == Hexagon::J2_loop1r ||
2433  Opcode == Hexagon::J2_loop1iext ||
2434  Opcode == Hexagon::J2_loop1rext;
2435 }
2436 
2438  switch (MI.getOpcode()) {
2439  default: return false;
2440  case Hexagon::L4_iadd_memopw_io:
2441  case Hexagon::L4_isub_memopw_io:
2442  case Hexagon::L4_add_memopw_io:
2443  case Hexagon::L4_sub_memopw_io:
2444  case Hexagon::L4_and_memopw_io:
2445  case Hexagon::L4_or_memopw_io:
2446  case Hexagon::L4_iadd_memoph_io:
2447  case Hexagon::L4_isub_memoph_io:
2448  case Hexagon::L4_add_memoph_io:
2449  case Hexagon::L4_sub_memoph_io:
2450  case Hexagon::L4_and_memoph_io:
2451  case Hexagon::L4_or_memoph_io:
2452  case Hexagon::L4_iadd_memopb_io:
2453  case Hexagon::L4_isub_memopb_io:
2454  case Hexagon::L4_add_memopb_io:
2455  case Hexagon::L4_sub_memopb_io:
2456  case Hexagon::L4_and_memopb_io:
2457  case Hexagon::L4_or_memopb_io:
2458  case Hexagon::L4_ior_memopb_io:
2459  case Hexagon::L4_ior_memoph_io:
2460  case Hexagon::L4_ior_memopw_io:
2461  case Hexagon::L4_iand_memopb_io:
2462  case Hexagon::L4_iand_memoph_io:
2463  case Hexagon::L4_iand_memopw_io:
2464  return true;
2465  }
2466  return false;
2467 }
2468 
2470  const uint64_t F = MI.getDesc().TSFlags;
2472 }
2473 
2474 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2475  const uint64_t F = get(Opcode).TSFlags;
2477 }
2478 
2480  return isNewValueJump(MI) || isNewValueStore(MI);
2481 }
2482 
2484  return isNewValue(MI) && MI.isBranch();
2485 }
2486 
2487 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2488  return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2489 }
2490 
2492  const uint64_t F = MI.getDesc().TSFlags;
2494 }
2495 
2496 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2497  const uint64_t F = get(Opcode).TSFlags;
2499 }
2500 
2501 // Returns true if a particular operand is extendable for an instruction.
2503  unsigned OperandNum) const {
2504  const uint64_t F = MI.getDesc().TSFlags;
2506  == OperandNum;
2507 }
2508 
2510  const uint64_t F = MI.getDesc().TSFlags;
2513 }
2514 
2515 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2516  const uint64_t F = get(Opcode).TSFlags;
2517  assert(isPredicated(Opcode));
2519 }
2520 
2522  const uint64_t F = MI.getDesc().TSFlags;
2523  return !((F >> HexagonII::PredicatedFalsePos) &
2525 }
2526 
2527 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2528  const uint64_t F = get(Opcode).TSFlags;
2529  // Make sure that the instruction is predicated.
2531  return !((F >> HexagonII::PredicatedFalsePos) &
2533 }
2534 
2535 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2536  const uint64_t F = get(Opcode).TSFlags;
2538 }
2539 
2540 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2541  const uint64_t F = get(Opcode).TSFlags;
2543 }
2544 
2545 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2546  const uint64_t F = get(Opcode).TSFlags;
2547  assert(get(Opcode).isBranch() &&
2548  (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2550 }
2551 
2553  return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2554  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2555  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2556  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2557 }
2558 
2560  switch (MI.getOpcode()) {
2561  // Byte
2562  case Hexagon::L2_loadrb_io:
2563  case Hexagon::L4_loadrb_ur:
2564  case Hexagon::L4_loadrb_ap:
2565  case Hexagon::L2_loadrb_pr:
2566  case Hexagon::L2_loadrb_pbr:
2567  case Hexagon::L2_loadrb_pi:
2568  case Hexagon::L2_loadrb_pci:
2569  case Hexagon::L2_loadrb_pcr:
2570  case Hexagon::L2_loadbsw2_io:
2571  case Hexagon::L4_loadbsw2_ur:
2572  case Hexagon::L4_loadbsw2_ap:
2573  case Hexagon::L2_loadbsw2_pr:
2574  case Hexagon::L2_loadbsw2_pbr:
2575  case Hexagon::L2_loadbsw2_pi:
2576  case Hexagon::L2_loadbsw2_pci:
2577  case Hexagon::L2_loadbsw2_pcr:
2578  case Hexagon::L2_loadbsw4_io:
2579  case Hexagon::L4_loadbsw4_ur:
2580  case Hexagon::L4_loadbsw4_ap:
2581  case Hexagon::L2_loadbsw4_pr:
2582  case Hexagon::L2_loadbsw4_pbr:
2583  case Hexagon::L2_loadbsw4_pi:
2584  case Hexagon::L2_loadbsw4_pci:
2585  case Hexagon::L2_loadbsw4_pcr:
2586  case Hexagon::L4_loadrb_rr:
2587  case Hexagon::L2_ploadrbt_io:
2588  case Hexagon::L2_ploadrbt_pi:
2589  case Hexagon::L2_ploadrbf_io:
2590  case Hexagon::L2_ploadrbf_pi:
2591  case Hexagon::L2_ploadrbtnew_io:
2592  case Hexagon::L2_ploadrbfnew_io:
2593  case Hexagon::L4_ploadrbt_rr:
2594  case Hexagon::L4_ploadrbf_rr:
2595  case Hexagon::L4_ploadrbtnew_rr:
2596  case Hexagon::L4_ploadrbfnew_rr:
2597  case Hexagon::L2_ploadrbtnew_pi:
2598  case Hexagon::L2_ploadrbfnew_pi:
2599  case Hexagon::L4_ploadrbt_abs:
2600  case Hexagon::L4_ploadrbf_abs:
2601  case Hexagon::L4_ploadrbtnew_abs:
2602  case Hexagon::L4_ploadrbfnew_abs:
2603  case Hexagon::L2_loadrbgp:
2604  // Half
2605  case Hexagon::L2_loadrh_io:
2606  case Hexagon::L4_loadrh_ur:
2607  case Hexagon::L4_loadrh_ap:
2608  case Hexagon::L2_loadrh_pr:
2609  case Hexagon::L2_loadrh_pbr:
2610  case Hexagon::L2_loadrh_pi:
2611  case Hexagon::L2_loadrh_pci:
2612  case Hexagon::L2_loadrh_pcr:
2613  case Hexagon::L4_loadrh_rr:
2614  case Hexagon::L2_ploadrht_io:
2615  case Hexagon::L2_ploadrht_pi:
2616  case Hexagon::L2_ploadrhf_io:
2617  case Hexagon::L2_ploadrhf_pi:
2618  case Hexagon::L2_ploadrhtnew_io:
2619  case Hexagon::L2_ploadrhfnew_io:
2620  case Hexagon::L4_ploadrht_rr:
2621  case Hexagon::L4_ploadrhf_rr:
2622  case Hexagon::L4_ploadrhtnew_rr:
2623  case Hexagon::L4_ploadrhfnew_rr:
2624  case Hexagon::L2_ploadrhtnew_pi:
2625  case Hexagon::L2_ploadrhfnew_pi:
2626  case Hexagon::L4_ploadrht_abs:
2627  case Hexagon::L4_ploadrhf_abs:
2628  case Hexagon::L4_ploadrhtnew_abs:
2629  case Hexagon::L4_ploadrhfnew_abs:
2630  case Hexagon::L2_loadrhgp:
2631  return true;
2632  default:
2633  return false;
2634  }
2635 }
2636 
2638  const uint64_t F = MI.getDesc().TSFlags;
2640 }
2641 
2643  switch (MI.getOpcode()) {
2644  case Hexagon::STriw_pred:
2645  case Hexagon::LDriw_pred:
2646  return true;
2647  default:
2648  return false;
2649  }
2650 }
2651 
2653  if (!MI.isBranch())
2654  return false;
2655 
2656  for (auto &Op : MI.operands())
2657  if (Op.isGlobal() || Op.isSymbol())
2658  return true;
2659  return false;
2660 }
2661 
2662 // Returns true when SU has a timing class TC1.
2664  unsigned SchedClass = MI.getDesc().getSchedClass();
2665  return is_TC1(SchedClass);
2666 }
2667 
2669  unsigned SchedClass = MI.getDesc().getSchedClass();
2670  return is_TC2(SchedClass);
2671 }
2672 
2674  unsigned SchedClass = MI.getDesc().getSchedClass();
2675  return is_TC2early(SchedClass);
2676 }
2677 
2679  unsigned SchedClass = MI.getDesc().getSchedClass();
2680  return is_TC4x(SchedClass);
2681 }
2682 
2683 // Schedule this ASAP.
2685  const MachineInstr &MI2) const {
2686  if (mayBeCurLoad(MI1)) {
2687  // if (result of SU is used in Next) return true;
2688  Register DstReg = MI1.getOperand(0).getReg();
2689  int N = MI2.getNumOperands();
2690  for (int I = 0; I < N; I++)
2691  if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2692  return true;
2693  }
2694  if (mayBeNewStore(MI2))
2695  if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2696  if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2697  MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2698  return true;
2699  return false;
2700 }
2701 
2703  const uint64_t V = getType(MI);
2705 }
2706 
2707 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2709  int Size = VT.getSizeInBits() / 8;
2710  if (Offset % Size != 0)
2711  return false;
2712  int Count = Offset / Size;
2713 
2714  switch (VT.getSimpleVT().SimpleTy) {
2715  // For scalars the auto-inc is s4
2716  case MVT::i8:
2717  case MVT::i16:
2718  case MVT::i32:
2719  case MVT::i64:
2720  case MVT::f32:
2721  case MVT::f64:
2722  case MVT::v2i16:
2723  case MVT::v2i32:
2724  case MVT::v4i8:
2725  case MVT::v4i16:
2726  case MVT::v8i8:
2727  return isInt<4>(Count);
2728  // For HVX vectors the auto-inc is s3
2729  case MVT::v64i8:
2730  case MVT::v32i16:
2731  case MVT::v16i32:
2732  case MVT::v8i64:
2733  case MVT::v128i8:
2734  case MVT::v64i16:
2735  case MVT::v32i32:
2736  case MVT::v16i64:
2737  return isInt<3>(Count);
2738  default:
2739  break;
2740  }
2741 
2742  llvm_unreachable("Not an valid type!");
2743 }
2744 
2745 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2746  const TargetRegisterInfo *TRI, bool Extend) const {
2747  // This function is to check whether the "Offset" is in the correct range of
2748  // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2749  // inserted to calculate the final address. Due to this reason, the function
2750  // assumes that the "Offset" has correct alignment.
2751  // We used to assert if the offset was not properly aligned, however,
2752  // there are cases where a misaligned pointer recast can cause this
2753  // problem, and we need to allow for it. The front end warns of such
2754  // misaligns with respect to load size.
2755  switch (Opcode) {
2756  case Hexagon::PS_vstorerq_ai:
2757  case Hexagon::PS_vstorerv_ai:
2758  case Hexagon::PS_vstorerw_ai:
2759  case Hexagon::PS_vstorerw_nt_ai:
2760  case Hexagon::PS_vloadrq_ai:
2761  case Hexagon::PS_vloadrv_ai:
2762  case Hexagon::PS_vloadrw_ai:
2763  case Hexagon::PS_vloadrw_nt_ai:
2764  case Hexagon::V6_vL32b_ai:
2765  case Hexagon::V6_vS32b_ai:
2766  case Hexagon::V6_vS32b_qpred_ai:
2767  case Hexagon::V6_vS32b_nqpred_ai:
2768  case Hexagon::V6_vL32b_nt_ai:
2769  case Hexagon::V6_vS32b_nt_ai:
2770  case Hexagon::V6_vL32Ub_ai:
2771  case Hexagon::V6_vS32Ub_ai:
2772  case Hexagon::V6_vgathermh_pseudo:
2773  case Hexagon::V6_vgathermw_pseudo:
2774  case Hexagon::V6_vgathermhw_pseudo:
2775  case Hexagon::V6_vgathermhq_pseudo:
2776  case Hexagon::V6_vgathermwq_pseudo:
2777  case Hexagon::V6_vgathermhwq_pseudo: {
2778  unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2779  assert(isPowerOf2_32(VectorSize));
2780  if (Offset & (VectorSize-1))
2781  return false;
2782  return isInt<4>(Offset >> Log2_32(VectorSize));
2783  }
2784 
2785  case Hexagon::J2_loop0i:
2786  case Hexagon::J2_loop1i:
2787  return isUInt<10>(Offset);
2788 
2789  case Hexagon::S4_storeirb_io:
2790  case Hexagon::S4_storeirbt_io:
2791  case Hexagon::S4_storeirbf_io:
2792  return isUInt<6>(Offset);
2793 
2794  case Hexagon::S4_storeirh_io:
2795  case Hexagon::S4_storeirht_io:
2796  case Hexagon::S4_storeirhf_io:
2797  return isShiftedUInt<6,1>(Offset);
2798 
2799  case Hexagon::S4_storeiri_io:
2800  case Hexagon::S4_storeirit_io:
2801  case Hexagon::S4_storeirif_io:
2802  return isShiftedUInt<6,2>(Offset);
2803  // Handle these two compare instructions that are not extendable.
2804  case Hexagon::A4_cmpbeqi:
2805  return isUInt<8>(Offset);
2806  case Hexagon::A4_cmpbgti:
2807  return isInt<8>(Offset);
2808  }
2809 
2810  if (Extend)
2811  return true;
2812 
2813  switch (Opcode) {
2814  case Hexagon::L2_loadri_io:
2815  case Hexagon::S2_storeri_io:
2816  return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2818 
2819  case Hexagon::L2_loadrd_io:
2820  case Hexagon::S2_storerd_io:
2821  return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2823 
2824  case Hexagon::L2_loadrh_io:
2825  case Hexagon::L2_loadruh_io:
2826  case Hexagon::S2_storerh_io:
2827  case Hexagon::S2_storerf_io:
2828  return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2830 
2831  case Hexagon::L2_loadrb_io:
2832  case Hexagon::L2_loadrub_io:
2833  case Hexagon::S2_storerb_io:
2834  return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2836 
2837  case Hexagon::A2_addi:
2838  return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2840 
2841  case Hexagon::L4_iadd_memopw_io:
2842  case Hexagon::L4_isub_memopw_io:
2843  case Hexagon::L4_add_memopw_io:
2844  case Hexagon::L4_sub_memopw_io:
2845  case Hexagon::L4_iand_memopw_io:
2846  case Hexagon::L4_ior_memopw_io:
2847  case Hexagon::L4_and_memopw_io:
2848  case Hexagon::L4_or_memopw_io:
2849  return (0 <= Offset && Offset <= 255);
2850 
2851  case Hexagon::L4_iadd_memoph_io:
2852  case Hexagon::L4_isub_memoph_io:
2853  case Hexagon::L4_add_memoph_io:
2854  case Hexagon::L4_sub_memoph_io:
2855  case Hexagon::L4_iand_memoph_io:
2856  case Hexagon::L4_ior_memoph_io:
2857  case Hexagon::L4_and_memoph_io:
2858  case Hexagon::L4_or_memoph_io:
2859  return (0 <= Offset && Offset <= 127);
2860 
2861  case Hexagon::L4_iadd_memopb_io:
2862  case Hexagon::L4_isub_memopb_io:
2863  case Hexagon::L4_add_memopb_io:
2864  case Hexagon::L4_sub_memopb_io:
2865  case Hexagon::L4_iand_memopb_io:
2866  case Hexagon::L4_ior_memopb_io:
2867  case Hexagon::L4_and_memopb_io:
2868  case Hexagon::L4_or_memopb_io:
2869  return (0 <= Offset && Offset <= 63);
2870 
2871  // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2872  // any size. Later pass knows how to handle it.
2873  case Hexagon::STriw_pred:
2874  case Hexagon::LDriw_pred:
2875  case Hexagon::STriw_ctr:
2876  case Hexagon::LDriw_ctr:
2877  return true;
2878 
2879  case Hexagon::PS_fi:
2880  case Hexagon::PS_fia:
2881  case Hexagon::INLINEASM:
2882  return true;
2883 
2884  case Hexagon::L2_ploadrbt_io:
2885  case Hexagon::L2_ploadrbf_io:
2886  case Hexagon::L2_ploadrubt_io:
2887  case Hexagon::L2_ploadrubf_io:
2888  case Hexagon::S2_pstorerbt_io:
2889  case Hexagon::S2_pstorerbf_io:
2890  return isUInt<6>(Offset);
2891 
2892  case Hexagon::L2_ploadrht_io:
2893  case Hexagon::L2_ploadrhf_io:
2894  case Hexagon::L2_ploadruht_io:
2895  case Hexagon::L2_ploadruhf_io:
2896  case Hexagon::S2_pstorerht_io:
2897  case Hexagon::S2_pstorerhf_io:
2898  return isShiftedUInt<6,1>(Offset);
2899 
2900  case Hexagon::L2_ploadrit_io:
2901  case Hexagon::L2_ploadrif_io:
2902  case Hexagon::S2_pstorerit_io:
2903  case Hexagon::S2_pstorerif_io:
2904  return isShiftedUInt<6,2>(Offset);
2905 
2906  case Hexagon::L2_ploadrdt_io:
2907  case Hexagon::L2_ploadrdf_io:
2908  case Hexagon::S2_pstorerdt_io:
2909  case Hexagon::S2_pstorerdf_io:
2910  return isShiftedUInt<6,3>(Offset);
2911 
2912  case Hexagon::L2_loadbsw2_io:
2913  case Hexagon::L2_loadbzw2_io:
2914  return isShiftedInt<11,1>(Offset);
2915 
2916  case Hexagon::L2_loadbsw4_io:
2917  case Hexagon::L2_loadbzw4_io:
2918  return isShiftedInt<11,2>(Offset);
2919  } // switch
2920 
2921  dbgs() << "Failed Opcode is : " << Opcode << " (" << getName(Opcode)
2922  << ")\n";
2923  llvm_unreachable("No offset range is defined for this opcode. "
2924  "Please define it in the above switch statement!");
2925 }
2926 
2928  return isHVXVec(MI) && isAccumulator(MI);
2929 }
2930 
2932  const uint64_t F = get(MI.getOpcode()).TSFlags;
2933  const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2934  return
2935  V == HexagonII::TypeCVI_VA ||
2937 }
2938 
2940  const MachineInstr &ConsMI) const {
2941  if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2942  return true;
2943 
2944  if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2945  return true;
2946 
2947  if (mayBeNewStore(ConsMI))
2948  return true;
2949 
2950  return false;
2951 }
2952 
2954  switch (MI.getOpcode()) {
2955  // Byte
2956  case Hexagon::L2_loadrub_io:
2957  case Hexagon::L4_loadrub_ur:
2958  case Hexagon::L4_loadrub_ap:
2959  case Hexagon::L2_loadrub_pr:
2960  case Hexagon::L2_loadrub_pbr:
2961  case Hexagon::L2_loadrub_pi:
2962  case Hexagon::L2_loadrub_pci:
2963  case Hexagon::L2_loadrub_pcr:
2964  case Hexagon::L2_loadbzw2_io:
2965  case Hexagon::L4_loadbzw2_ur:
2966  case Hexagon::L4_loadbzw2_ap:
2967  case Hexagon::L2_loadbzw2_pr:
2968  case Hexagon::L2_loadbzw2_pbr:
2969  case Hexagon::L2_loadbzw2_pi:
2970  case Hexagon::L2_loadbzw2_pci:
2971  case Hexagon::L2_loadbzw2_pcr:
2972  case Hexagon::L2_loadbzw4_io:
2973  case Hexagon::L4_loadbzw4_ur:
2974  case Hexagon::L4_loadbzw4_ap:
2975  case Hexagon::L2_loadbzw4_pr:
2976  case Hexagon::L2_loadbzw4_pbr:
2977  case Hexagon::L2_loadbzw4_pi:
2978  case Hexagon::L2_loadbzw4_pci:
2979  case Hexagon::L2_loadbzw4_pcr:
2980  case Hexagon::L4_loadrub_rr:
2981  case Hexagon::L2_ploadrubt_io:
2982  case Hexagon::L2_ploadrubt_pi:
2983  case Hexagon::L2_ploadrubf_io:
2984  case Hexagon::L2_ploadrubf_pi:
2985  case Hexagon::L2_ploadrubtnew_io:
2986  case Hexagon::L2_ploadrubfnew_io:
2987  case Hexagon::L4_ploadrubt_rr:
2988  case Hexagon::L4_ploadrubf_rr:
2989  case Hexagon::L4_ploadrubtnew_rr:
2990  case Hexagon::L4_ploadrubfnew_rr:
2991  case Hexagon::L2_ploadrubtnew_pi:
2992  case Hexagon::L2_ploadrubfnew_pi:
2993  case Hexagon::L4_ploadrubt_abs:
2994  case Hexagon::L4_ploadrubf_abs:
2995  case Hexagon::L4_ploadrubtnew_abs:
2996  case Hexagon::L4_ploadrubfnew_abs:
2997  case Hexagon::L2_loadrubgp:
2998  // Half
2999  case Hexagon::L2_loadruh_io:
3000  case Hexagon::L4_loadruh_ur:
3001  case Hexagon::L4_loadruh_ap:
3002  case Hexagon::L2_loadruh_pr:
3003  case Hexagon::L2_loadruh_pbr:
3004  case Hexagon::L2_loadruh_pi:
3005  case Hexagon::L2_loadruh_pci:
3006  case Hexagon::L2_loadruh_pcr:
3007  case Hexagon::L4_loadruh_rr:
3008  case Hexagon::L2_ploadruht_io:
3009  case Hexagon::L2_ploadruht_pi:
3010  case Hexagon::L2_ploadruhf_io:
3011  case Hexagon::L2_ploadruhf_pi:
3012  case Hexagon::L2_ploadruhtnew_io:
3013  case Hexagon::L2_ploadruhfnew_io:
3014  case Hexagon::L4_ploadruht_rr:
3015  case Hexagon::L4_ploadruhf_rr:
3016  case Hexagon::L4_ploadruhtnew_rr:
3017  case Hexagon::L4_ploadruhfnew_rr:
3018  case Hexagon::L2_ploadruhtnew_pi:
3019  case Hexagon::L2_ploadruhfnew_pi:
3020  case Hexagon::L4_ploadruht_abs:
3021  case Hexagon::L4_ploadruhf_abs:
3022  case Hexagon::L4_ploadruhtnew_abs:
3023  case Hexagon::L4_ploadruhfnew_abs:
3024  case Hexagon::L2_loadruhgp:
3025  return true;
3026  default:
3027  return false;
3028  }
3029 }
3030 
3031 // Add latency to instruction.
3033  const MachineInstr &MI2) const {
3034  if (isHVXVec(MI1) && isHVXVec(MI2))
3035  if (!isVecUsableNextPacket(MI1, MI2))
3036  return true;
3037  return false;
3038 }
3039 
3040 /// Get the base register and byte offset of a load/store instr.
3043  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
3044  const TargetRegisterInfo *TRI) const {
3045  OffsetIsScalable = false;
3046  const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width);
3047  if (!BaseOp || !BaseOp->isReg())
3048  return false;
3049  BaseOps.push_back(BaseOp);
3050  return true;
3051 }
3052 
3053 /// Can these instructions execute at the same time in a bundle.
3055  const MachineInstr &Second) const {
3056  if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
3057  const MachineOperand &Op = Second.getOperand(0);
3058  if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
3059  return true;
3060  }
3061  if (DisableNVSchedule)
3062  return false;
3063  if (mayBeNewStore(Second)) {
3064  // Make sure the definition of the first instruction is the value being
3065  // stored.
3066  const MachineOperand &Stored =
3067  Second.getOperand(Second.getNumOperands() - 1);
3068  if (!Stored.isReg())
3069  return false;
3070  for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
3071  const MachineOperand &Op = First.getOperand(i);
3072  if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3073  return true;
3074  }
3075  }
3076  return false;
3077 }
3078 
3080  unsigned Opc = CallMI.getOpcode();
3081  return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
3082 }
3083 
3085  for (auto &I : *B)
3086  if (I.isEHLabel())
3087  return true;
3088  return false;
3089 }
3090 
3091 // Returns true if an instruction can be converted into a non-extended
3092 // equivalent instruction.
3094  short NonExtOpcode;
3095  // Check if the instruction has a register form that uses register in place
3096  // of the extended operand, if so return that as the non-extended form.
3097  if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
3098  return true;
3099 
3100  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
3101  // Check addressing mode and retrieve non-ext equivalent instruction.
3102 
3103  switch (getAddrMode(MI)) {
3104  case HexagonII::Absolute:
3105  // Load/store with absolute addressing mode can be converted into
3106  // base+offset mode.
3107  NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
3108  break;
3110  // Load/store with base+offset addressing mode can be converted into
3111  // base+register offset addressing mode. However left shift operand should
3112  // be set to 0.
3113  NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
3114  break;
3116  NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
3117  break;
3118  default:
3119  return false;
3120  }
3121  if (NonExtOpcode < 0)
3122  return false;
3123  return true;
3124  }
3125  return false;
3126 }
3127 
3129  return Hexagon::getRealHWInstr(MI.getOpcode(),
3130  Hexagon::InstrType_Pseudo) >= 0;
3131 }
3132 
3134  const {
3135  MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
3136  while (I != E) {
3137  if (I->isBarrier())
3138  return true;
3139  ++I;
3140  }
3141  return false;
3142 }
3143 
3144 // Returns true, if a LD insn can be promoted to a cur load.
3146  const uint64_t F = MI.getDesc().TSFlags;
3148  Subtarget.hasV60Ops();
3149 }
3150 
3151 // Returns true, if a ST insn can be promoted to a new-value store.
3153  if (MI.mayStore() && !Subtarget.useNewValueStores())
3154  return false;
3155 
3156  const uint64_t F = MI.getDesc().TSFlags;
3158 }
3159 
3161  const MachineInstr &ConsMI) const {
3162  // There is no stall when ProdMI is not a V60 vector.
3163  if (!isHVXVec(ProdMI))
3164  return false;
3165 
3166  // There is no stall when ProdMI and ConsMI are not dependent.
3167  if (!isDependent(ProdMI, ConsMI))
3168  return false;
3169 
3170  // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3171  // are scheduled in consecutive packets.
3172  if (isVecUsableNextPacket(ProdMI, ConsMI))
3173  return false;
3174 
3175  return true;
3176 }
3177 
3180  // There is no stall when I is not a V60 vector.
3181  if (!isHVXVec(MI))
3182  return false;
3183 
3185  MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3186 
3187  if (!MII->isBundle())
3188  return producesStall(*MII, MI);
3189 
3190  for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3191  const MachineInstr &J = *MII;
3192  if (producesStall(J, MI))
3193  return true;
3194  }
3195  return false;
3196 }
3197 
3199  unsigned PredReg) const {
3200  for (const MachineOperand &MO : MI.operands()) {
3201  // Predicate register must be explicitly defined.
3202  if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3203  return false;
3204  if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3205  return false;
3206  }
3207 
3208  // Instruction that produce late predicate cannot be used as sources of
3209  // dot-new.
3210  switch (MI.getOpcode()) {
3211  case Hexagon::A4_addp_c:
3212  case Hexagon::A4_subp_c:
3213  case Hexagon::A4_tlbmatch:
3214  case Hexagon::A5_ACS:
3215  case Hexagon::F2_sfinvsqrta:
3216  case Hexagon::F2_sfrecipa:
3217  case Hexagon::J2_endloop0:
3218  case Hexagon::J2_endloop01:
3219  case Hexagon::J2_ploop1si:
3220  case Hexagon::J2_ploop1sr:
3221  case Hexagon::J2_ploop2si:
3222  case Hexagon::J2_ploop2sr:
3223  case Hexagon::J2_ploop3si:
3224  case Hexagon::J2_ploop3sr:
3225  case Hexagon::S2_cabacdecbin:
3226  case Hexagon::S2_storew_locked:
3227  case Hexagon::S4_stored_locked:
3228  return false;
3229  }
3230  return true;
3231 }
3232 
3233 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3234  return Opcode == Hexagon::J2_jumpt ||
3235  Opcode == Hexagon::J2_jumptpt ||
3236  Opcode == Hexagon::J2_jumpf ||
3237  Opcode == Hexagon::J2_jumpfpt ||
3238  Opcode == Hexagon::J2_jumptnew ||
3239  Opcode == Hexagon::J2_jumpfnew ||
3240  Opcode == Hexagon::J2_jumptnewpt ||
3241  Opcode == Hexagon::J2_jumpfnewpt;
3242 }
3243 
3245  if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3246  return false;
3247  return !isPredicatedTrue(Cond[0].getImm());
3248 }
3249 
3251  const uint64_t F = MI.getDesc().TSFlags;
3253 }
3254 
3255 // Returns the base register in a memory access (load/store). The offset is
3256 // returned in Offset and the access size is returned in AccessSize.
3257 // If the base operand has a subregister or the offset field does not contain
3258 // an immediate value, return nullptr.
3260  int64_t &Offset,
3261  unsigned &AccessSize) const {
3262  // Return if it is not a base+offset type instruction or a MemOp.
3265  !isMemOp(MI) && !isPostIncrement(MI))
3266  return nullptr;
3267 
3268  AccessSize = getMemAccessSize(MI);
3269 
3270  unsigned BasePos = 0, OffsetPos = 0;
3271  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3272  return nullptr;
3273 
3274  // Post increment updates its EA after the mem access,
3275  // so we need to treat its offset as zero.
3276  if (isPostIncrement(MI)) {
3277  Offset = 0;
3278  } else {
3279  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3280  if (!OffsetOp.isImm())
3281  return nullptr;
3282  Offset = OffsetOp.getImm();
3283  }
3284 
3285  const MachineOperand &BaseOp = MI.getOperand(BasePos);
3286  if (BaseOp.getSubReg() != 0)
3287  return nullptr;
3288  return &const_cast<MachineOperand&>(BaseOp);
3289 }
3290 
3291 /// Return the position of the base and offset operands for this instruction.
3293  unsigned &BasePos, unsigned &OffsetPos) const {
3295  return false;
3296 
3297  // Deal with memops first.
3298  if (isMemOp(MI)) {
3299  BasePos = 0;
3300  OffsetPos = 1;
3301  } else if (MI.mayStore()) {
3302  BasePos = 0;
3303  OffsetPos = 1;
3304  } else if (MI.mayLoad()) {
3305  BasePos = 1;
3306  OffsetPos = 2;
3307  } else
3308  return false;
3309 
3310  if (isPredicated(MI)) {
3311  BasePos++;
3312  OffsetPos++;
3313  }
3314  if (isPostIncrement(MI)) {
3315  BasePos++;
3316  OffsetPos++;
3317  }
3318 
3319  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3320  return false;
3321 
3322  return true;
3323 }
3324 
3325 // Inserts branching instructions in reverse order of their occurrence.
3326 // e.g. jump_t t1 (i1)
3327 // jump t2 (i2)
3328 // Jumpers = {i2, i1}
3330  MachineBasicBlock& MBB) const {
3332  // If the block has no terminators, it just falls into the block after it.
3334  if (I == MBB.instr_begin())
3335  return Jumpers;
3336 
3337  // A basic block may looks like this:
3338  //
3339  // [ insn
3340  // EH_LABEL
3341  // insn
3342  // insn
3343  // insn
3344  // EH_LABEL
3345  // insn ]
3346  //
3347  // It has two succs but does not have a terminator
3348  // Don't know how to handle it.
3349  do {
3350  --I;
3351  if (I->isEHLabel())
3352  return Jumpers;
3353  } while (I != MBB.instr_begin());
3354 
3355  I = MBB.instr_end();
3356  --I;
3357 
3358  while (I->isDebugInstr()) {
3359  if (I == MBB.instr_begin())
3360  return Jumpers;
3361  --I;
3362  }
3363  if (!isUnpredicatedTerminator(*I))
3364  return Jumpers;
3365 
3366  // Get the last instruction in the block.
3367  MachineInstr *LastInst = &*I;
3368  Jumpers.push_back(LastInst);
3369  MachineInstr *SecondLastInst = nullptr;
3370  // Find one more terminator if present.
3371  do {
3372  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3373  if (!SecondLastInst) {
3374  SecondLastInst = &*I;
3375  Jumpers.push_back(SecondLastInst);
3376  } else // This is a third branch.
3377  return Jumpers;
3378  }
3379  if (I == MBB.instr_begin())
3380  break;
3381  --I;
3382  } while (true);
3383  return Jumpers;
3384 }
3385 
3386 // Returns Operand Index for the constant extended instruction.
3388  const uint64_t F = MI.getDesc().TSFlags;
3390 }
3391 
3392 // See if instruction could potentially be a duplex candidate.
3393 // If so, return its group. Zero otherwise.
3395  const MachineInstr &MI) const {
3396  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3397 
3398  switch (MI.getOpcode()) {
3399  default:
3400  return HexagonII::HCG_None;
3401  //
3402  // Compound pairs.
3403  // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3404  // "Rd16=#U6 ; jump #r9:2"
3405  // "Rd16=Rs16 ; jump #r9:2"
3406  //
3407  case Hexagon::C2_cmpeq:
3408  case Hexagon::C2_cmpgt:
3409  case Hexagon::C2_cmpgtu:
3410  DstReg = MI.getOperand(0).getReg();
3411  Src1Reg = MI.getOperand(1).getReg();
3412  Src2Reg = MI.getOperand(2).getReg();
3413  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3414  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3415  isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3416  return HexagonII::HCG_A;
3417  break;
3418  case Hexagon::C2_cmpeqi:
3419  case Hexagon::C2_cmpgti:
3420  case Hexagon::C2_cmpgtui:
3421  // P0 = cmp.eq(Rs,#u2)
3422  DstReg = MI.getOperand(0).getReg();
3423  SrcReg = MI.getOperand(1).getReg();
3424  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3425  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3426  isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3427  ((isUInt<5>(MI.getOperand(2).getImm())) ||
3428  (MI.getOperand(2).getImm() == -1)))
3429  return HexagonII::HCG_A;
3430  break;
3431  case Hexagon::A2_tfr:
3432  // Rd = Rs
3433  DstReg = MI.getOperand(0).getReg();
3434  SrcReg = MI.getOperand(1).getReg();
3435  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3436  return HexagonII::HCG_A;
3437  break;
3438  case Hexagon::A2_tfrsi:
3439  // Rd = #u6
3440  // Do not test for #u6 size since the const is getting extended
3441  // regardless and compound could be formed.
3442  DstReg = MI.getOperand(0).getReg();
3443  if (isIntRegForSubInst(DstReg))
3444  return HexagonII::HCG_A;
3445  break;
3446  case Hexagon::S2_tstbit_i:
3447  DstReg = MI.getOperand(0).getReg();
3448  Src1Reg = MI.getOperand(1).getReg();
3449  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3450  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3451  MI.getOperand(2).isImm() &&
3452  isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3453  return HexagonII::HCG_A;
3454  break;
3455  // The fact that .new form is used pretty much guarantees
3456  // that predicate register will match. Nevertheless,
3457  // there could be some false positives without additional
3458  // checking.
3459  case Hexagon::J2_jumptnew:
3460  case Hexagon::J2_jumpfnew:
3461  case Hexagon::J2_jumptnewpt:
3462  case Hexagon::J2_jumpfnewpt:
3463  Src1Reg = MI.getOperand(0).getReg();
3464  if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3465  (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3466  return HexagonII::HCG_B;
3467  break;
3468  // Transfer and jump:
3469  // Rd=#U6 ; jump #r9:2
3470  // Rd=Rs ; jump #r9:2
3471  // Do not test for jump range here.
3472  case Hexagon::J2_jump:
3473  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3474  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3475  return HexagonII::HCG_C;
3476  }
3477 
3478  return HexagonII::HCG_None;
3479 }
3480 
3481 // Returns -1 when there is no opcode found.
3483  const MachineInstr &GB) const {
3486  if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3487  (GB.getOpcode() != Hexagon::J2_jumptnew))
3488  return -1u;
3489  Register DestReg = GA.getOperand(0).getReg();
3490  if (!GB.readsRegister(DestReg))
3491  return -1u;
3492  if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3493  return -1u;
3494  // The value compared against must be either u5 or -1.
3495  const MachineOperand &CmpOp = GA.getOperand(2);
3496  if (!CmpOp.isImm())
3497  return -1u;
3498  int V = CmpOp.getImm();
3499  if (V == -1)
3500  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3501  : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3502  if (!isUInt<5>(V))
3503  return -1u;
3504  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3505  : Hexagon::J4_cmpeqi_tp1_jump_nt;
3506 }
3507 
3508 // Returns -1 if there is no opcode found.
3510  bool ForBigCore) const {
3511  // Static table to switch the opcodes across Tiny Core and Big Core.
3512  // dup_ opcodes are Big core opcodes.
3513  // NOTE: There are special instructions that need to handled later.
3514  // L4_return* instructions, they will only occupy SLOT0 (on big core too).
3515  // PS_jmpret - This pseudo translates to J2_jumpr which occupies only SLOT2.
3516  // The compiler need to base the root instruction to L6_return_map_to_raw
3517  // which can go any slot.
3518  static const std::map<unsigned, unsigned> DupMap = {
3519  {Hexagon::A2_add, Hexagon::dup_A2_add},
3520  {Hexagon::A2_addi, Hexagon::dup_A2_addi},
3521  {Hexagon::A2_andir, Hexagon::dup_A2_andir},
3522  {Hexagon::A2_combineii, Hexagon::dup_A2_combineii},
3523  {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb},
3524  {Hexagon::A2_sxth, Hexagon::dup_A2_sxth},
3525  {Hexagon::A2_tfr, Hexagon::dup_A2_tfr},
3526  {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi},
3527  {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb},
3528  {Hexagon::A2_zxth, Hexagon::dup_A2_zxth},
3529  {Hexagon::A4_combineii, Hexagon::dup_A4_combineii},
3530  {Hexagon::A4_combineir, Hexagon::dup_A4_combineir},
3531  {Hexagon::A4_combineri, Hexagon::dup_A4_combineri},
3532  {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif},
3533  {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit},
3534  {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif},
3535  {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit},
3536  {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi},
3537  {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe},
3538  {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io},
3539  {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io},
3540  {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io},
3541  {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io},
3542  {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io},
3543  {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io},
3544  {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe},
3545  {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io},
3546  {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io},
3547  {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io},
3548  {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io},
3549  {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io},
3550  {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io},
3551  };
3552  unsigned OpNum = MI.getOpcode();
3553  // Conversion to Big core.
3554  if (ForBigCore) {
3555  auto Iter = DupMap.find(OpNum);
3556  if (Iter != DupMap.end())
3557  return Iter->second;
3558  } else { // Conversion to Tiny core.
3559  for (const auto &Iter : DupMap)
3560  if (Iter.second == OpNum)
3561  return Iter.first;
3562  }
3563  return -1;
3564 }
3565 
3566 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3567  enum Hexagon::PredSense inPredSense;
3568  inPredSense = invertPredicate ? Hexagon::PredSense_false :
3569  Hexagon::PredSense_true;
3570  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3571  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3572  return CondOpcode;
3573 
3574  llvm_unreachable("Unexpected predicable instruction");
3575 }
3576 
3577 // Return the cur value instruction for a given store.
3579  switch (MI.getOpcode()) {
3580  default: llvm_unreachable("Unknown .cur type");
3581  case Hexagon::V6_vL32b_pi:
3582  return Hexagon::V6_vL32b_cur_pi;
3583  case Hexagon::V6_vL32b_ai:
3584  return Hexagon::V6_vL32b_cur_ai;
3585  case Hexagon::V6_vL32b_nt_pi:
3586  return Hexagon::V6_vL32b_nt_cur_pi;
3587  case Hexagon::V6_vL32b_nt_ai:
3588  return Hexagon::V6_vL32b_nt_cur_ai;
3589  case Hexagon::V6_vL32b_ppu:
3590  return Hexagon::V6_vL32b_cur_ppu;
3591  case Hexagon::V6_vL32b_nt_ppu:
3592  return Hexagon::V6_vL32b_nt_cur_ppu;
3593  }
3594  return 0;
3595 }
3596 
3597 // Return the regular version of the .cur instruction.
3599  switch (MI.getOpcode()) {
3600  default: llvm_unreachable("Unknown .cur type");
3601  case Hexagon::V6_vL32b_cur_pi:
3602  return Hexagon::V6_vL32b_pi;
3603  case Hexagon::V6_vL32b_cur_ai:
3604  return Hexagon::V6_vL32b_ai;
3605  case Hexagon::V6_vL32b_nt_cur_pi:
3606  return Hexagon::V6_vL32b_nt_pi;
3607  case Hexagon::V6_vL32b_nt_cur_ai:
3608  return Hexagon::V6_vL32b_nt_ai;
3609  case Hexagon::V6_vL32b_cur_ppu:
3610  return Hexagon::V6_vL32b_ppu;
3611  case Hexagon::V6_vL32b_nt_cur_ppu:
3612  return Hexagon::V6_vL32b_nt_ppu;
3613  }
3614  return 0;
3615 }
3616 
3617 // The diagram below shows the steps involved in the conversion of a predicated
3618 // store instruction to its .new predicated new-value form.
3619 //
3620 // Note: It doesn't include conditional new-value stores as they can't be
3621 // converted to .new predicate.
3622 //
3623 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3624 // ^ ^
3625 // / \ (not OK. it will cause new-value store to be
3626 // / X conditional on p0.new while R2 producer is
3627 // / \ on p0)
3628 // / \.
3629 // p.new store p.old NV store
3630 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3631 // ^ ^
3632 // \ /
3633 // \ /
3634 // \ /
3635 // p.old store
3636 // [if (p0)memw(R0+#0)=R2]
3637 //
3638 // The following set of instructions further explains the scenario where
3639 // conditional new-value store becomes invalid when promoted to .new predicate
3640 // form.
3641 //
3642 // { 1) if (p0) r0 = add(r1, r2)
3643 // 2) p0 = cmp.eq(r3, #0) }
3644 //
3645 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3646 // the first two instructions because in instr 1, r0 is conditional on old value
3647 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3648 // is not valid for new-value stores.
3649 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3650 // from the "Conditional Store" list. Because a predicated new value store
3651 // would NOT be promoted to a double dot new store. See diagram below:
3652 // This function returns yes for those stores that are predicated but not
3653 // yet promoted to predicate dot new instructions.
3654 //
3655 // +---------------------+
3656 // /-----| if (p0) memw(..)=r0 |---------\~
3657 // || +---------------------+ ||
3658 // promote || /\ /\ || promote
3659 // || /||\ /||\ ||
3660 // \||/ demote || \||/
3661 // \/ || || \/
3662 // +-------------------------+ || +-------------------------+
3663 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3664 // +-------------------------+ || +-------------------------+
3665 // || || ||
3666 // || demote \||/
3667 // promote || \/ NOT possible
3668 // || || /\~
3669 // \||/ || /||\~
3670 // \/ || ||
3671 // +-----------------------------+
3672 // | if (p0.new) memw(..)=r0.new |
3673 // +-----------------------------+
3674 // Double Dot New Store
3675 //
3676 // Returns the most basic instruction for the .new predicated instructions and
3677 // new-value stores.
3678 // For example, all of the following instructions will be converted back to the
3679 // same instruction:
3680 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3681 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3682 // 3) if (p0.new) memw(R0+#0) = R1 --->
3683 //
3684 // To understand the translation of instruction 1 to its original form, consider
3685 // a packet with 3 instructions.
3686 // { p0 = cmp.eq(R0,R1)
3687 // if (p0.new) R2 = add(R3, R4)
3688 // R5 = add (R3, R1)
3689 // }
3690 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3691 //
3692 // This instruction can be part of the previous packet only if both p0 and R2
3693 // are promoted to .new values. This promotion happens in steps, first
3694 // predicate register is promoted to .new and in the next iteration R2 is
3695 // promoted. Therefore, in case of dependence check failure (due to R5) during
3696 // next iteration, it should be converted back to its most basic form.
3697 
3698 // Return the new value instruction for a given store.
3700  int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3701  if (NVOpcode >= 0) // Valid new-value store instruction.
3702  return NVOpcode;
3703 
3704  switch (MI.getOpcode()) {
3705  default:
3706  report_fatal_error(Twine("Unknown .new type: ") +
3707  std::to_string(MI.getOpcode()));
3708  case Hexagon::S4_storerb_ur:
3709  return Hexagon::S4_storerbnew_ur;
3710 
3711  case Hexagon::S2_storerb_pci:
3712  return Hexagon::S2_storerb_pci;
3713 
3714  case Hexagon::S2_storeri_pci:
3715  return Hexagon::S2_storeri_pci;
3716 
3717  case Hexagon::S2_storerh_pci:
3718  return Hexagon::S2_storerh_pci;
3719 
3720  case Hexagon::S2_storerd_pci:
3721  return Hexagon::S2_storerd_pci;
3722 
3723  case Hexagon::S2_storerf_pci:
3724  return Hexagon::S2_storerf_pci;
3725 
3726  case Hexagon::V6_vS32b_ai:
3727  return Hexagon::V6_vS32b_new_ai;
3728 
3729  case Hexagon::V6_vS32b_pi:
3730  return Hexagon::V6_vS32b_new_pi;
3731  }
3732  return 0;
3733 }
3734 
3735 // Returns the opcode to use when converting MI, which is a conditional jump,
3736 // into a conditional instruction which uses the .new value of the predicate.
3737 // We also use branch probabilities to add a hint to the jump.
3738 // If MBPI is null, all edges will be treated as equally likely for the
3739 // purposes of establishing a predication hint.
3741  const MachineBranchProbabilityInfo *MBPI) const {
3742  // We assume that block can have at most two successors.
3743  const MachineBasicBlock *Src = MI.getParent();
3744  const MachineOperand &BrTarget = MI.getOperand(1);
3745  bool Taken = false;
3746  const BranchProbability OneHalf(1, 2);
3747 
3748  auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3749  const MachineBasicBlock *Dst) {
3750  if (MBPI)
3751  return MBPI->getEdgeProbability(Src, Dst);
3752  return BranchProbability(1, Src->succ_size());
3753  };
3754 
3755  if (BrTarget.isMBB()) {
3756  const MachineBasicBlock *Dst = BrTarget.getMBB();
3757  Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3758  } else {
3759  // The branch target is not a basic block (most likely a function).
3760  // Since BPI only gives probabilities for targets that are basic blocks,
3761  // try to identify another target of this branch (potentially a fall-
3762  // -through) and check the probability of that target.
3763  //
3764  // The only handled branch combinations are:
3765  // - one conditional branch,
3766  // - one conditional branch followed by one unconditional branch.
3767  // Otherwise, assume not-taken.
3768  assert(MI.isConditionalBranch());
3769  const MachineBasicBlock &B = *MI.getParent();
3770  bool SawCond = false, Bad = false;
3771  for (const MachineInstr &I : B) {
3772  if (!I.isBranch())
3773  continue;
3774  if (I.isConditionalBranch()) {
3775  SawCond = true;
3776  if (&I != &MI) {
3777  Bad = true;
3778  break;
3779  }
3780  }
3781  if (I.isUnconditionalBranch() && !SawCond) {
3782  Bad = true;
3783  break;
3784  }
3785  }
3786  if (!Bad) {
3788  MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3789  if (NextIt == B.instr_end()) {
3790  // If this branch is the last, look for the fall-through block.
3791  for (const MachineBasicBlock *SB : B.successors()) {
3792  if (!B.isLayoutSuccessor(SB))
3793  continue;
3794  Taken = getEdgeProbability(Src, SB) < OneHalf;
3795  break;
3796  }
3797  } else {
3798  assert(NextIt->isUnconditionalBranch());
3799  // Find the first MBB operand and assume it's the target.
3800  const MachineBasicBlock *BT = nullptr;
3801  for (const MachineOperand &Op : NextIt->operands()) {
3802  if (!Op.isMBB())
3803  continue;
3804  BT = Op.getMBB();
3805  break;
3806  }
3807  Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3808  }
3809  } // if (!Bad)
3810  }
3811 
3812  // The Taken flag should be set to something reasonable by this point.
3813 
3814  switch (MI.getOpcode()) {
3815  case Hexagon::J2_jumpt:
3816  return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3817  case Hexagon::J2_jumpf:
3818  return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3819 
3820  default:
3821  llvm_unreachable("Unexpected jump instruction.");
3822  }
3823 }
3824 
3825 // Return .new predicate version for an instruction.
3827  const MachineBranchProbabilityInfo *MBPI) const {
3828  switch (MI.getOpcode()) {
3829  // Condtional Jumps
3830  case Hexagon::J2_jumpt:
3831  case Hexagon::J2_jumpf:
3832  return getDotNewPredJumpOp(MI, MBPI);
3833  }
3834 
3835  int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3836  if (NewOpcode >= 0)
3837  return NewOpcode;
3838  return 0;
3839 }
3840 
3842  int NewOp = MI.getOpcode();
3843  if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3844  NewOp = Hexagon::getPredOldOpcode(NewOp);
3845  // All Hexagon architectures have prediction bits on dot-new branches,
3846  // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3847  // to pick the right opcode when converting back to dot-old.
3848  if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3849  switch (NewOp) {
3850  case Hexagon::J2_jumptpt:
3851  NewOp = Hexagon::J2_jumpt;
3852  break;
3853  case Hexagon::J2_jumpfpt:
3854  NewOp = Hexagon::J2_jumpf;
3855  break;
3856  case Hexagon::J2_jumprtpt:
3857  NewOp = Hexagon::J2_jumprt;
3858  break;
3859  case Hexagon::J2_jumprfpt:
3860  NewOp = Hexagon::J2_jumprf;
3861  break;
3862  }
3863  }
3864  assert(NewOp >= 0 &&
3865  "Couldn't change predicate new instruction to its old form.");
3866  }
3867 
3868  if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3869  NewOp = Hexagon::getNonNVStore(NewOp);
3870  assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3871  }
3872 
3873  if (Subtarget.hasV60Ops())
3874  return NewOp;
3875 
3876  // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3877  switch (NewOp) {
3878  case Hexagon::J2_jumpfpt:
3879  return Hexagon::J2_jumpf;
3880  case Hexagon::J2_jumptpt:
3881  return Hexagon::J2_jumpt;
3882  case Hexagon::J2_jumprfpt:
3883  return Hexagon::J2_jumprf;
3884  case Hexagon::J2_jumprtpt:
3885  return Hexagon::J2_jumprt;
3886  }
3887  return NewOp;
3888 }
3889 
3890 // See if instruction could potentially be a duplex candidate.
3891 // If so, return its group. Zero otherwise.
3893  const MachineInstr &MI) const {
3894  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3895  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3896 
3897  switch (MI.getOpcode()) {
3898  default:
3899  return HexagonII::HSIG_None;
3900  //
3901  // Group L1:
3902  //
3903  // Rd = memw(Rs+#u4:2)
3904  // Rd = memub(Rs+#u4:0)
3905  case Hexagon::L2_loadri_io:
3906  case Hexagon::dup_L2_loadri_io:
3907  DstReg = MI.getOperand(0).getReg();
3908  SrcReg = MI.getOperand(1).getReg();
3909  // Special case this one from Group L2.
3910  // Rd = memw(r29+#u5:2)
3911  if (isIntRegForSubInst(DstReg)) {
3912  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3913  HRI.getStackRegister() == SrcReg &&
3914  MI.getOperand(2).isImm() &&
3915  isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3916  return HexagonII::HSIG_L2;
3917  // Rd = memw(Rs+#u4:2)
3918  if (isIntRegForSubInst(SrcReg) &&
3919  (MI.getOperand(2).isImm() &&
3920  isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3921  return HexagonII::HSIG_L1;
3922  }
3923  break;
3924  case Hexagon::L2_loadrub_io:
3925  case Hexagon::dup_L2_loadrub_io:
3926  // Rd = memub(Rs+#u4:0)
3927  DstReg = MI.getOperand(0).getReg();
3928  SrcReg = MI.getOperand(1).getReg();
3929  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3930  MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3931  return HexagonII::HSIG_L1;
3932  break;
3933  //
3934  // Group L2:
3935  //
3936  // Rd = memh/memuh(Rs+#u3:1)
3937  // Rd = memb(Rs+#u3:0)
3938  // Rd = memw(r29+#u5:2) - Handled above.
3939  // Rdd = memd(r29+#u5:3)
3940  // deallocframe
3941  // [if ([!]p0[.new])] dealloc_return
3942  // [if ([!]p0[.new])] jumpr r31
3943  case Hexagon::L2_loadrh_io:
3944  case Hexagon::L2_loadruh_io:
3945  case Hexagon::dup_L2_loadrh_io:
3946  case Hexagon::dup_L2_loadruh_io:
3947  // Rd = memh/memuh(Rs+#u3:1)
3948  DstReg = MI.getOperand(0).getReg();
3949  SrcReg = MI.getOperand(1).getReg();
3950  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3951  MI.getOperand(2).isImm() &&
3952  isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3953  return HexagonII::HSIG_L2;
3954  break;
3955  case Hexagon::L2_loadrb_io:
3956  case Hexagon::dup_L2_loadrb_io:
3957  // Rd = memb(Rs+#u3:0)
3958  DstReg = MI.getOperand(0).getReg();
3959  SrcReg = MI.getOperand(1).getReg();
3960  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3961  MI.getOperand(2).isImm() &&
3962  isUInt<3>(MI.getOperand(2).getImm()))
3963  return HexagonII::HSIG_L2;
3964  break;
3965  case Hexagon::L2_loadrd_io:
3966  case Hexagon::dup_L2_loadrd_io:
3967  // Rdd = memd(r29+#u5:3)
3968  DstReg = MI.getOperand(0).getReg();
3969  SrcReg = MI.getOperand(1).getReg();
3970  if (isDblRegForSubInst(DstReg, HRI) &&
3971  Hexagon::IntRegsRegClass.contains(SrcReg) &&
3972  HRI.getStackRegister() == SrcReg &&
3973  MI.getOperand(2).isImm() &&
3974  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3975  return HexagonII::HSIG_L2;
3976  break;
3977  // dealloc_return is not documented in Hexagon Manual, but marked
3978  // with A_SUBINSN attribute in iset_v4classic.py.
3979  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3980  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3981  case Hexagon::L4_return:
3982  case Hexagon::L2_deallocframe:
3983  case Hexagon::dup_L2_deallocframe:
3984  return HexagonII::HSIG_L2;
3985  case Hexagon::EH_RETURN_JMPR:
3986  case Hexagon::PS_jmpret:
3987  case Hexagon::SL2_jumpr31:
3988  // jumpr r31
3989  // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
3990  DstReg = MI.getOperand(0).getReg();
3991  if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3992  return HexagonII::HSIG_L2;
3993  break;
3994  case Hexagon::PS_jmprett:
3995  case Hexagon::PS_jmpretf:
3996  case Hexagon::PS_jmprettnewpt:
3997  case Hexagon::PS_jmpretfnewpt:
3998  case Hexagon::PS_jmprettnew:
3999  case Hexagon::PS_jmpretfnew:
4000  case Hexagon::SL2_jumpr31_t:
4001  case Hexagon::SL2_jumpr31_f:
4002  case Hexagon::SL2_jumpr31_tnew:
4003  case Hexagon::SL2_jumpr31_fnew:
4004  DstReg = MI.getOperand(1).getReg();
4005  SrcReg = MI.getOperand(0).getReg();
4006  // [if ([!]p0[.new])] jumpr r31
4007  if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
4008  (Hexagon::P0 == SrcReg)) &&
4009  (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
4010  return HexagonII::HSIG_L2;
4011  break;
4012  case Hexagon::L4_return_t:
4013  case Hexagon::L4_return_f:
4014  case Hexagon::L4_return_tnew_pnt:
4015  case Hexagon::L4_return_fnew_pnt:
4016  case Hexagon::L4_return_tnew_pt:
4017  case Hexagon::L4_return_fnew_pt:
4018  // [if ([!]p0[.new])] dealloc_return
4019  SrcReg = MI.getOperand(0).getReg();
4020  if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
4021  return HexagonII::HSIG_L2;
4022  break;
4023  //
4024  // Group S1:
4025  //
4026  // memw(Rs+#u4:2) = Rt
4027  // memb(Rs+#u4:0) = Rt
4028  case Hexagon::S2_storeri_io:
4029  case Hexagon::dup_S2_storeri_io:
4030  // Special case this one from Group S2.
4031  // memw(r29+#u5:2) = Rt
4032  Src1Reg = MI.getOperand(0).getReg();
4033  Src2Reg = MI.getOperand(2).getReg();
4034  if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4035  isIntRegForSubInst(Src2Reg) &&
4036  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
4037  isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
4038  return HexagonII::HSIG_S2;
4039  // memw(Rs+#u4:2) = Rt
4040  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4041  MI.getOperand(1).isImm() &&
4042  isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
4043  return HexagonII::HSIG_S1;
4044  break;
4045  case Hexagon::S2_storerb_io:
4046  case Hexagon::dup_S2_storerb_io:
4047  // memb(Rs+#u4:0) = Rt
4048  Src1Reg = MI.getOperand(0).getReg();
4049  Src2Reg = MI.getOperand(2).getReg();
4050  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4051  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
4052  return HexagonII::HSIG_S1;
4053  break;
4054  //
4055  // Group S2:
4056  //
4057  // memh(Rs+#u3:1) = Rt
4058  // memw(r29+#u5:2) = Rt
4059  // memd(r29+#s6:3) = Rtt
4060  // memw(Rs+#u4:2) = #U1
4061  // memb(Rs+#u4) = #U1
4062  // allocframe(#u5:3)
4063  case Hexagon::S2_storerh_io:
4064  case Hexagon::dup_S2_storerh_io:
4065  // memh(Rs+#u3:1) = Rt
4066  Src1Reg = MI.getOperand(0).getReg();
4067  Src2Reg = MI.getOperand(2).getReg();
4068  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
4069  MI.getOperand(1).isImm() &&
4070  isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
4071  return HexagonII::HSIG_S1;
4072  break;
4073  case Hexagon::S2_storerd_io:
4074  case Hexagon::dup_S2_storerd_io:
4075  // memd(r29+#s6:3) = Rtt
4076  Src1Reg = MI.getOperand(0).getReg();
4077  Src2Reg = MI.getOperand(2).getReg();
4078  if (isDblRegForSubInst(Src2Reg, HRI) &&
4079  Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4080  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
4081  isShiftedInt<6,3>(MI.getOperand(1).getImm()))
4082  return HexagonII::HSIG_S2;
4083  break;
4084  case Hexagon::S4_storeiri_io:
4085  case Hexagon::dup_S4_storeiri_io:
4086  // memw(Rs+#u4:2) = #U1
4087  Src1Reg = MI.getOperand(0).getReg();
4088  if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
4089  isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
4090  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4091  return HexagonII::HSIG_S2;
4092  break;
4093  case Hexagon::S4_storeirb_io:
4094  case Hexagon::dup_S4_storeirb_io:
4095  // memb(Rs+#u4) = #U1
4096  Src1Reg = MI.getOperand(0).getReg();
4097  if (isIntRegForSubInst(Src1Reg) &&
4098  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
4099  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4100  return HexagonII::HSIG_S2;
4101  break;
4102  case Hexagon::S2_allocframe:
4103  case Hexagon::dup_S2_allocframe:
4104  if (MI.getOperand(2).isImm() &&
4105  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
4106  return HexagonII::HSIG_S1;
4107  break;
4108  //
4109  // Group A:
4110  //
4111  // Rx = add(Rx,#s7)
4112  // Rd = Rs
4113  // Rd = #u6
4114  // Rd = #-1
4115  // if ([!]P0[.new]) Rd = #0
4116  // Rd = add(r29,#u6:2)
4117  // Rx = add(Rx,Rs)
4118  // P0 = cmp.eq(Rs,#u2)
4119  // Rdd = combine(#0,Rs)
4120  // Rdd = combine(Rs,#0)
4121  // Rdd = combine(#u2,#U2)
4122  // Rd = add(Rs,#1)
4123  // Rd = add(Rs,#-1)
4124  // Rd = sxth/sxtb/zxtb/zxth(Rs)
4125  // Rd = and(Rs,#1)
4126  case Hexagon::A2_addi:
4127  case Hexagon::dup_A2_addi:
4128  DstReg = MI.getOperand(0).getReg();
4129  SrcReg = MI.getOperand(1).getReg();
4130  if (isIntRegForSubInst(DstReg)) {
4131  // Rd = add(r29,#u6:2)
4132  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
4133  HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
4134  isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
4135  return HexagonII::HSIG_A;
4136  // Rx = add(Rx,#s7)
4137  if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
4138  isInt<7>(MI.getOperand(2).getImm()))
4139  return HexagonII::HSIG_A;
4140  // Rd = add(Rs,#1)
4141  // Rd = add(Rs,#-1)
4142  if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
4143  ((MI.getOperand(2).getImm() == 1) ||
4144  (MI.getOperand(2).getImm() == -1)))
4145  return HexagonII::HSIG_A;
4146  }
4147  break;
4148  case Hexagon::A2_add:
4149  case Hexagon::dup_A2_add:
4150  // Rx = add(Rx,Rs)
4151  DstReg = MI.getOperand(0).getReg();
4152  Src1Reg = MI.getOperand(1).getReg();
4153  Src2Reg = MI.getOperand(2).getReg();
4154  if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
4155  isIntRegForSubInst(Src2Reg))
4156  return HexagonII::HSIG_A;
4157  break;
4158  case Hexagon::A2_andir:
4159  case Hexagon::dup_A2_andir:
4160  // Same as zxtb.
4161  // Rd16=and(Rs16,#255)
4162  // Rd16=and(Rs16,#1)
4163  DstReg = MI.getOperand(0).getReg();
4164  SrcReg = MI.getOperand(1).getReg();
4165  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
4166  MI.getOperand(2).isImm() &&
4167  ((MI.getOperand(2).getImm() == 1) ||
4168  (MI.getOperand(2).getImm() == 255)))
4169  return HexagonII::HSIG_A;
4170  break;
4171  case Hexagon::A2_tfr:
4172  case Hexagon::dup_A2_tfr:
4173  // Rd = Rs
4174  DstReg = MI.getOperand(0).getReg();
4175  SrcReg = MI.getOperand(1).getReg();
4176  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4177  return HexagonII::HSIG_A;
4178  break;
4179  case Hexagon::A2_tfrsi:
4180  case Hexagon::dup_A2_tfrsi:
4181  // Rd = #u6
4182  // Do not test for #u6 size since the const is getting extended
4183  // regardless and compound could be formed.
4184  // Rd = #-1
4185  DstReg = MI.getOperand(0).getReg();
4186  if (isIntRegForSubInst(DstReg))
4187  return HexagonII::HSIG_A;
4188  break;
4189  case Hexagon::C2_cmoveit:
4190  case Hexagon::C2_cmovenewit:
4191  case Hexagon::C2_cmoveif:
4192  case Hexagon::C2_cmovenewif:
4193  case Hexagon::dup_C2_cmoveit:
4194  case Hexagon::dup_C2_cmovenewit:
4195  case Hexagon::dup_C2_cmoveif:
4196  case Hexagon::dup_C2_cmovenewif:
4197  // if ([!]P0[.new]) Rd = #0
4198  // Actual form:
4199  // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
4200  DstReg = MI.getOperand(0).getReg();
4201  SrcReg = MI.getOperand(1).getReg();
4202  if (isIntRegForSubInst(DstReg) &&
4203  Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4204  MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4205  return HexagonII::HSIG_A;
4206  break;
4207  case Hexagon::C2_cmpeqi:
4208  case Hexagon::dup_C2_cmpeqi:
4209  // P0 = cmp.eq(Rs,#u2)
4210  DstReg = MI.getOperand(0).getReg();
4211  SrcReg = MI.getOperand(1).getReg();
4212  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
4213  Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
4214  MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4215  return HexagonII::HSIG_A;
4216  break;
4217  case Hexagon::A2_combineii:
4218  case Hexagon::A4_combineii:
4219  case Hexagon::dup_A2_combineii:
4220  case Hexagon::dup_A4_combineii:
4221  // Rdd = combine(#u2,#U2)
4222  DstReg = MI.getOperand(0).getReg();
4223  if (isDblRegForSubInst(DstReg, HRI) &&
4224  ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4225  (MI.getOperand(1).isGlobal() &&
4226  isUInt<2>(MI.getOperand(1).getOffset()))) &&
4227  ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4228  (MI.getOperand(2).isGlobal() &&
4229  isUInt<2>(MI.getOperand(2).getOffset()))))
4230  return HexagonII::HSIG_A;
4231  break;
4232  case Hexagon::A4_combineri:
4233  case Hexagon::dup_A4_combineri:
4234  // Rdd = combine(Rs,#0)
4235  // Rdd = combine(Rs,#0)
4236  DstReg = MI.getOperand(0).getReg();
4237  SrcReg = MI.getOperand(1).getReg();
4238  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4239  ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4240  (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4241  return HexagonII::HSIG_A;
4242  break;
4243  case Hexagon::A4_combineir:
4244  case Hexagon::dup_A4_combineir:
4245  // Rdd = combine(#0,Rs)
4246  DstReg = MI.getOperand(0).getReg();
4247  SrcReg = MI.getOperand(2).getReg();
4248  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4249  ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4250  (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4251  return HexagonII::HSIG_A;
4252  break;
4253  case Hexagon::A2_sxtb:
4254  case Hexagon::A2_sxth:
4255  case Hexagon::A2_zxtb:
4256  case Hexagon::A2_zxth:
4257  case Hexagon::dup_A2_sxtb:
4258  case Hexagon::dup_A2_sxth:
4259  case Hexagon::dup_A2_zxtb:
4260  case Hexagon::dup_A2_zxth:
4261  // Rd = sxth/sxtb/zxtb/zxth(Rs)
4262  DstReg = MI.getOperand(0).getReg();
4263  SrcReg = MI.getOperand(1).getReg();
4264  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4265  return HexagonII::HSIG_A;
4266  break;
4267  }
4268 
4269  return HexagonII::HSIG_None;
4270 }
4271 
4273  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4274 }
4275 
4277  const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4278  // Default to one cycle for no itinerary. However, an "empty" itinerary may
4279  // still have a MinLatency property, which getStageLatency checks.
4280  if (!ItinData)
4281  return getInstrLatency(ItinData, MI);
4282 
4283  if (MI.isTransient())
4284  return 0;
4285  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4286 }
4287 
4288 /// getOperandLatency - Compute and return the use operand latency of a given
4289 /// pair of def and use.
4290 /// In most cases, the static scheduling itinerary was enough to determine the
4291 /// operand latency. But it may not be possible for instructions with variable
4292 /// number of defs / uses.
4293 ///
4294 /// This is a raw interface to the itinerary that may be directly overriden by
4295 /// a target. Use computeOperandLatency to get the best estimate of latency.
4297  const MachineInstr &DefMI,
4298  unsigned DefIdx,
4299  const MachineInstr &UseMI,
4300  unsigned UseIdx) const {
4301  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4302 
4303  // Get DefIdx and UseIdx for super registers.
4304  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4305 
4306  if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) {
4307  if (DefMO.isImplicit()) {
4308  for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
4309  int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
4310  if (Idx != -1) {
4311  DefIdx = Idx;
4312  break;
4313  }
4314  }
4315  }
4316 
4317  const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4318  if (UseMO.isImplicit()) {
4319  for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
4320  int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
4321  if (Idx != -1) {
4322  UseIdx = Idx;
4323  break;
4324  }
4325  }
4326  }
4327  }
4328 
4329  int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
4330  UseMI, UseIdx);
4331  if (!Latency)
4332  // We should never have 0 cycle latency between two instructions unless
4333  // they can be packetized together. However, this decision can't be made
4334  // here.
4335  Latency = 1;
4336  return Latency;
4337 }
4338 
4339 // inverts the predication logic.
4340 // p -> NotP
4341 // NotP -> P
4344  if (Cond.empty())
4345  return false;
4346  unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4347  Cond[0].setImm(Opc);
4348  return true;
4349 }
4350 
4351 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4352  int InvPredOpcode;
4353  InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4354  : Hexagon::getTruePredOpcode(Opc);
4355  if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4356  return InvPredOpcode;
4357 
4358  llvm_unreachable("Unexpected predicated instruction");
4359 }
4360 
4361 // Returns the max value that doesn't need to be extended.
4363  const uint64_t F = MI.getDesc().TSFlags;
4364  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4366  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4368 
4369  if (isSigned) // if value is signed
4370  return ~(-1U << (bits - 1));
4371  else
4372  return ~(-1U << bits);
4373 }
4374 
4375 
4377  switch (MI.getOpcode()) {
4378  case Hexagon::L2_loadrbgp:
4379  case Hexagon::L2_loadrdgp:
4380  case Hexagon::L2_loadrhgp:
4381  case Hexagon::L2_loadrigp:
4382  case Hexagon::L2_loadrubgp:
4383  case Hexagon::L2_loadruhgp:
4384  case Hexagon::S2_storerbgp:
4385  case Hexagon::S2_storerbnewgp:
4386  case Hexagon::S2_storerhgp:
4387  case Hexagon::S2_storerhnewgp:
4388  case Hexagon::S2_storerigp:
4389  case Hexagon::S2_storerinewgp:
4390  case Hexagon::S2_storerdgp:
4391  case Hexagon::S2_storerfgp:
4392  return true;
4393  }
4394  const uint64_t F = MI.getDesc().TSFlags;
4395  unsigned addrMode =
4397  // Disallow any base+offset instruction. The assembler does not yet reorder
4398  // based up any zero offset instruction.
4399  return (addrMode == HexagonII::BaseRegOffset ||
4400  addrMode == HexagonII::BaseImmOffset ||
4401  addrMode == HexagonII::BaseLongOffset);
4402 }
4403 
4405  // Workaround for the Global Scheduler. Sometimes, it creates
4406  // A4_ext as a Pseudo instruction and calls this function to see if
4407  // it can be added to an existing bundle. Since the instruction doesn't
4408  // belong to any BB yet, we can't use getUnits API.
4409  if (MI.getOpcode() == Hexagon::A4_ext)
4410  return false;
4411 
4412  unsigned FuncUnits = getUnits(MI);
4413  return HexagonFUnits::isSlot0Only(FuncUnits);
4414 }
4415 
4417  const uint64_t F = MI.getDesc().TSFlags;
4418  return ((F >> HexagonII::RestrictNoSlot1StorePos) &
4420 }
4421 
4423  bool ToBigInstrs) const {
4424  int Opcode = -1;
4425  if (ToBigInstrs) { // To BigCore Instr.
4426  // Check if the instruction can form a Duplex.
4427  if (getDuplexCandidateGroup(*MII))
4428  // Get the opcode marked "dup_*" tag.
4429  Opcode = getDuplexOpcode(*MII, ToBigInstrs);
4430  } else // To TinyCore Instr.
4431  Opcode = getDuplexOpcode(*MII, ToBigInstrs);
4432 
4433  // Change the opcode of the instruction.
4434  if (Opcode >= 0)
4435  MII->setDesc(get(Opcode));
4436 }
4437 
4438 // This function is used to translate instructions to facilitate generating
4439 // Duplexes on TinyCore.
4441  bool ToBigInstrs) const {
4442  for (auto &MB : MF)
4443  for (MachineBasicBlock::instr_iterator Instr = MB.instr_begin(),
4444  End = MB.instr_end();
4445  Instr != End; ++Instr)
4446  changeDuplexOpcode(Instr, ToBigInstrs);
4447 }
4448 
4449 // This is a specialized form of above function.
4451  MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const {
4452  MachineBasicBlock *MBB = MII->getParent();
4453  while ((MII != MBB->instr_end()) && MII->isInsideBundle()) {
4454  changeDuplexOpcode(MII, ToBigInstrs);
4455  ++MII;
4456  }
4457 }
4458 
4460  using namespace HexagonII;
4461 
4462  const uint64_t F = MI.getDesc().TSFlags;
4463  unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4465  if (Size != 0)
4466  return Size;
4467 
4468  // Handle vector access sizes.
4469  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4470  switch (S) {
4472  return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4473  default:
4474  llvm_unreachable("Unexpected instruction");
4475  }
4476 }
4477 
4478 // Returns the min value that doesn't need to be extended.
4480  const uint64_t F = MI.getDesc().TSFlags;
4481  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4483  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4485 
4486  if (isSigned) // if value is signed
4487  return -1U << (bits - 1);
4488  else
4489  return 0;
4490 }
4491 
4492 // Returns opcode of the non-extended equivalent instruction.
4494  // Check if the instruction has a register form that uses register in place
4495  // of the extended operand, if so return that as the non-extended form.
4496  short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4497  if (NonExtOpcode >= 0)
4498  return NonExtOpcode;
4499 
4500  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4501  // Check addressing mode and retrieve non-ext equivalent instruction.
4502  switch (getAddrMode(MI)) {
4503  case HexagonII::Absolute:
4504  return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4506  return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4508  return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4509 
4510  default:
4511  return -1;
4512  }
4513  }
4514  return -1;
4515 }
4516 
4518  unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4519  if (Cond.empty())
4520  return false;
4521  assert(Cond.size() == 2);
4522  if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4523  LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4524  return false;
4525  }
4526  PredReg = Cond[1].getReg();
4527  PredRegPos = 1;
4528  // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4529  PredRegFlags = 0;
4530  if (Cond[1].isImplicit())
4531  PredRegFlags = RegState::Implicit;
4532  if (Cond[1].isUndef())
4533  PredRegFlags |= RegState::Undef;
4534  return true;
4535 }
4536 
4538  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4539 }
4540 
4542  return Hexagon::getRegForm(MI.getOpcode());
4543 }
4544 
4545 // Return the number of bytes required to encode the instruction.
4546 // Hexagon instructions are fixed length, 4 bytes, unless they
4547 // use a constant extender, which requires another 4 bytes.
4548 // For debug instructions and prolog labels, return 0.
4550  if (MI.isDebugInstr() || MI.isPosition())
4551  return 0;
4552 
4553  unsigned Size = MI.getDesc().getSize();
4554  if (!Size)
4555  // Assume the default insn size in case it cannot be determined
4556  // for whatever reason.
4558 
4559  if (isConstExtended(MI) || isExtended(MI))
4561 
4562  // Try and compute number of instructions in asm.
4563  if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) {
4564  const MachineBasicBlock &MBB = *MI.getParent();
4565  const MachineFunction *MF = MBB.getParent();
4566  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4567 
4568  // Count the number of register definitions to find the asm string.
4569  unsigned NumDefs = 0;
4570  for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4571  ++NumDefs)
4572  assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4573 
4574  assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4575  // Disassemble the AsmStr and approximate number of instructions.
4576  const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4577  Size = getInlineAsmLength(AsmStr, *MAI);
4578  }
4579 
4580  return Size;
4581 }
4582 
4584  const uint64_t F = MI.getDesc().TSFlags;
4586 }
4587 
4589  const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4590  const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4591 
4592  return IS.getUnits();
4593 }
4594 
4595 // Calculate size of the basic block without debug instructions.
4597  return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4598 }
4599 
4601  MachineBasicBlock::const_iterator BundleHead) const {
4602  assert(BundleHead->isBundle() && "Not a bundle header");
4603  auto MII = BundleHead.getInstrIterator();
4604  // Skip the bundle header.
4605  return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4606 }
4607 
4608 /// immediateExtend - Changes the instruction in place to one using an immediate
4609 /// extender.
4612  "Instruction must be extendable");
4613  // Find which operand is extendable.
4614  short ExtOpNum = getCExtOpNum(MI);
4615  MachineOperand &MO = MI.getOperand(ExtOpNum);
4616  // This needs to be something we understand.
4617  assert((MO.isMBB() || MO.isImm()) &&
4618  "Branch with unknown extendable field type");
4619  // Mark given operand as extended.
4621 }
4622 
4624  MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4625  LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4626  << printMBBReference(*NewTarget);
4627  MI.dump(););
4628  assert(MI.isBranch());
4629  unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4630  int TargetPos = MI.getNumOperands() - 1;
4631  // In general branch target is the last operand,
4632  // but some implicit defs added at the end might change it.
4633  while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4634  --TargetPos;
4635  assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4636  MI.getOperand(TargetPos).setMBB(NewTarget);
4638  NewOpcode = reversePrediction(NewOpcode);
4639  }
4640  MI.setDesc(get(NewOpcode));
4641  return true;
4642 }
4643 
4645  /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4647  MachineBasicBlock &B = *A;
4648  MachineBasicBlock::iterator I = B.begin();
4649  DebugLoc DL = I->getDebugLoc();
4650  MachineInstr *NewMI;
4651 
4652  for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4653  insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4654  NewMI = BuildMI(B, I, DL, get(insn));
4655  LLVM_DEBUG(dbgs() << "\n"
4656  << getName(NewMI->getOpcode())
4657  << " Class: " << NewMI->getDesc().getSchedClass());
4658  NewMI->eraseFromParent();
4659  }
4660  /* --- The code above is used to generate complete set of Hexagon Insn --- */
4661 }
4662 
4663 // inverts the predication logic.
4664 // p -> NotP
4665 // NotP -> P
4667  LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4668  MI.setDesc(get(getInvertedPredicatedOpcode(MI.getOpcode())));
4669  return true;
4670 }
4671 
4672 // Reverse the branch prediction.
4673 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4674  int PredRevOpcode = -1;
4675  if (isPredictedTaken(Opcode))
4676  PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4677  else
4678  PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4679  assert(PredRevOpcode > 0);
4680  return PredRevOpcode;
4681 }
4682 
4683 // TODO: Add more rigorous validation.
4685  const {
4686  return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4687 }
4688 
4689 void HexagonInstrInfo::
4691  assert(MIB->isBundle());
4692  MachineOperand &Operand = MIB->getOperand(0);
4693  if (Operand.isImm())
4694  Operand.setImm(Operand.getImm() | memShufDisabledMask);
4695  else
4696  MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4697 }
4698 
4700  assert(MIB.isBundle());
4701  const MachineOperand &Operand = MIB.getOperand(0);
4702  return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4703 }
4704 
4705 // Addressing mode relations.
4707  return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4708 }
4709 
4711  return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4712 }
4713 
4715  return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4716 }
4717 
4719  return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4720 }
4721 
4723  return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4724 }
4725 
4727  return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4728 }
4729 
4731  return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4732 }
4733 
4735  return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4736 }
4737 
4739  static const MCInst Nop = MCInstBuilder(Hexagon::A2_nop);
4740 
4741  return MCInstBuilder(Hexagon::BUNDLE)
4742  .addImm(0)
4743  .addInst(&Nop);
4744 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::HexagonInstrInfo::isTailCall
bool isTailCall(const MachineInstr &MI) const override
Definition: HexagonInstrInfo.cpp:2652
llvm::HexagonII::CompoundGroup
CompoundGroup
Definition: HexagonBaseInfo.h:233
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:243
llvm::HexagonII::FPMask
@ FPMask
Definition: HexagonBaseInfo.h:140
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:63
llvm::HexagonII::HSIG_Compound
@ HSIG_Compound
Definition: HexagonBaseInfo.h:229
llvm::HexagonInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Test if the given instruction should be considered a scheduling boundary.
Definition: HexagonInstrInfo.cpp:1746
llvm::HexagonInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Definition: HexagonInstrInfo.cpp:334
getName
static StringRef getName(Value *V)
Definition: ProvenanceAnalysisEvaluator.cpp:42
llvm::HexagonSubtarget::useNewValueStores
bool useNewValueStores() const
Definition: HexagonSubtarget.h:208
ScheduleDAG.h
llvm::HexagonII::TakenMask
@ TakenMask
Definition: HexagonBaseInfo.h:136
llvm::HexagonII::HSIG_S2
@ HSIG_S2
Definition: HexagonBaseInfo.h:227
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::MCAsmInfo::getCommentString
StringRef getCommentString() const
Definition: MCAsmInfo.h:641
llvm::HexagonII::AddrModePos
@ AddrModePos
Definition: HexagonBaseInfo.h:128
llvm::HexagonInstrInfo::nonDbgBBSize
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
Definition: HexagonInstrInfo.cpp:4596
llvm::ARMII::MO_HI16
@ MO_HI16
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address.
Definition: ARMBaseInfo.h:254
llvm::HexagonInstrInfo::HexagonInstrInfo
HexagonInstrInfo(HexagonSubtarget &ST)
Definition: HexagonInstrInfo.cpp:118
llvm::HexagonII::NewValuePos
@ NewValuePos
Definition: HexagonBaseInfo.h:77
llvm::MachineOperand::isBlockAddress
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Definition: MachineOperand.h:343
llvm::MCAsmInfo::getSeparatorString
const char * getSeparatorString() const
Definition: MCAsmInfo.h:635
UseMI
MachineInstrBuilder & UseMI<