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LanaiDisassembler.cpp
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1 //===- LanaiDisassembler.cpp - Disassembler for Lanai -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the Lanai Disassembler.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "LanaiDisassembler.h"
14 
15 #include "LanaiAluCode.h"
16 #include "LanaiCondCode.h"
17 #include "LanaiInstrInfo.h"
20 #include "llvm/MC/MCInst.h"
24 
25 using namespace llvm;
26 
28 
29 namespace llvm {
31 }
32 
34  const MCSubtargetInfo &STI,
35  MCContext &Ctx) {
36  return new LanaiDisassembler(STI, Ctx);
37 }
38 
40  // Register the disassembler
43 }
44 
46  : MCDisassembler(STI, Ctx) {}
47 
48 // Forward declare because the autogenerated code will reference this.
49 // Definition is further down.
50 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
51  uint64_t Address,
52  const void *Decoder);
53 
54 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
55  uint64_t Address, const void *Decoder);
56 
57 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
58  uint64_t Address, const void *Decoder);
59 
60 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
61  uint64_t Address, const void *Decoder);
62 
63 static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
64  const void *Decoder);
65 
66 static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val,
67  uint64_t Address,
68  const void *Decoder);
69 
70 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
71  uint64_t Address, const void *Decoder);
72 
73 #include "LanaiGenDisassemblerTables.inc"
74 
76  uint32_t &Insn) {
77  // We want to read exactly 4 bytes of data.
78  if (Bytes.size() < 4) {
79  Size = 0;
80  return MCDisassembler::Fail;
81  }
82 
83  // Encoded as big-endian 32-bit word in the stream.
84  Insn =
85  (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 8) | (Bytes[3] << 0);
86 
88 }
89 
90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) {
91  unsigned AluOp = LPAC::ADD;
92  // Fix up for pre and post operations.
93  int PqShift = -1;
94  if (isRMOpcode(Instr.getOpcode()))
95  PqShift = 16;
96  else if (isSPLSOpcode(Instr.getOpcode()))
97  PqShift = 10;
98  else if (isRRMOpcode(Instr.getOpcode())) {
99  PqShift = 16;
100  // Determine RRM ALU op.
101  AluOp = (Insn >> 8) & 0x7;
102  if (AluOp == 7)
103  // Handle JJJJJ
104  // 0b10000 or 0b11000
105  AluOp |= 0x20 | (((Insn >> 3) & 0xf) << 1);
106  }
107 
108  if (PqShift != -1) {
109  unsigned PQ = (Insn >> PqShift) & 0x3;
110  switch (PQ) {
111  case 0x0:
112  if (Instr.getOperand(2).isReg()) {
113  Instr.getOperand(2).setReg(Lanai::R0);
114  }
115  if (Instr.getOperand(2).isImm())
116  Instr.getOperand(2).setImm(0);
117  break;
118  case 0x1:
119  AluOp = LPAC::makePostOp(AluOp);
120  break;
121  case 0x2:
122  break;
123  case 0x3:
124  AluOp = LPAC::makePreOp(AluOp);
125  break;
126  }
127  Instr.addOperand(MCOperand::createImm(AluOp));
128  }
129 }
130 
133  ArrayRef<uint8_t> Bytes, uint64_t Address,
134  raw_ostream & /*CStream*/) const {
135  uint32_t Insn;
136 
137  DecodeStatus Result = readInstruction32(Bytes, Size, Insn);
138 
139  if (Result == MCDisassembler::Fail)
140  return MCDisassembler::Fail;
141 
142  // Call auto-generated decoder function
143  Result =
144  decodeInstruction(DecoderTableLanai32, Instr, Insn, Address, this, STI);
145 
146  if (Result != MCDisassembler::Fail) {
147  PostOperandDecodeAdjust(Instr, Insn);
148  Size = 4;
149  return Result;
150  }
151 
152  return MCDisassembler::Fail;
153 }
154 
155 static const unsigned GPRDecoderTable[] = {
156  Lanai::R0, Lanai::R1, Lanai::PC, Lanai::R3, Lanai::SP, Lanai::FP,
157  Lanai::R6, Lanai::R7, Lanai::RV, Lanai::R9, Lanai::RR1, Lanai::RR2,
158  Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
159  Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
160  Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
161  Lanai::R30, Lanai::R31};
162 
164  uint64_t /*Address*/,
165  const void * /*Decoder*/) {
166  if (RegNo > 31)
167  return MCDisassembler::Fail;
168 
169  unsigned Reg = GPRDecoderTable[RegNo];
172 }
173 
174 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
175  uint64_t Address, const void *Decoder) {
176  // RI memory values encoded using 23 bits:
177  // 5 bit register, 16 bit constant
178  unsigned Register = (Insn >> 18) & 0x1f;
180  unsigned Offset = (Insn & 0xffff);
181  Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));
182 
184 }
185 
186 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
187  uint64_t Address, const void *Decoder) {
188  // RR memory values encoded using 20 bits:
189  // 5 bit register, 5 bit register, 2 bit PQ, 3 bit ALU operator, 5 bit JJJJJ
190  unsigned Register = (Insn >> 15) & 0x1f;
192  Register = (Insn >> 10) & 0x1f;
194 
196 }
197 
198 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
199  uint64_t Address, const void *Decoder) {
200  // RI memory values encoded using 17 bits:
201  // 5 bit register, 10 bit constant
202  unsigned Register = (Insn >> 12) & 0x1f;
204  unsigned Offset = (Insn & 0x3ff);
205  Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset)));
206 
208 }
209 
210 static bool tryAddingSymbolicOperand(int64_t Value, bool IsBranch,
211  uint64_t Address, uint64_t Offset,
213  const void *Decoder) {
214  const MCDisassembler *Dis = static_cast<const MCDisassembler *>(Decoder);
215  return Dis->tryAddingSymbolicOperand(MI, Value, Address, IsBranch, Offset,
216  Width);
217 }
218 
219 static DecodeStatus decodeBranch(MCInst &MI, unsigned Insn, uint64_t Address,
220  const void *Decoder) {
221  if (!tryAddingSymbolicOperand(Insn + Address, false, Address, 2, 23, MI,
222  Decoder))
223  MI.addOperand(MCOperand::createImm(Insn));
225 }
226 
227 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
228  uint64_t Address, const void *Decoder) {
229  unsigned Offset = (Insn & 0xffff);
230  Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));
231 
233 }
234 
235 static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val,
236  uint64_t Address,
237  const void *Decoder) {
238  if (Val >= LPCC::UNKNOWN)
239  return MCDisassembler::Fail;
240  Inst.addOperand(MCOperand::createImm(Val));
242 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
MCFixedLenDisassembler.h
llvm::LPAC::ADD
@ ADD
Definition: LanaiAluCode.h:23
LanaiAluCode.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
MathExtras.h
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
decodeRiMemoryValue
static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: LanaiDisassembler.cpp:174
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:916
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
tryAddingSymbolicOperand
static bool tryAddingSymbolicOperand(int64_t Value, bool IsBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const void *Decoder)
Definition: LanaiDisassembler.cpp:210
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::getTheLanaiTarget
Target & getTheLanaiTarget()
Definition: LanaiTargetInfo.cpp:14
PostOperandDecodeAdjust
static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn)
Definition: LanaiDisassembler.cpp:90
decodeRrMemoryValue
static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: LanaiDisassembler.cpp:186
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:103
LanaiCondCode.h
MCInst.h
llvm::LPAC::makePreOp
static unsigned makePreOp(unsigned AluOp)
Definition: LanaiAluCode.h:62
MCSubtargetInfo.h
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:100
llvm::isRMOpcode
static bool isRMOpcode(unsigned Opcode)
Definition: LanaiInstrInfo.h:160
DecodeGPRRegisterClass
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: LanaiDisassembler.cpp:163
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:170
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::isSPLSOpcode
static bool isSPLSOpcode(unsigned Opcode)
Definition: LanaiInstrInfo.h:146
llvm::LanaiDisassembler::getInstruction
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
Definition: LanaiDisassembler.cpp:132
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
decodeBranch
static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: LanaiDisassembler.cpp:219
uint64_t
LanaiTargetInfo.h
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:76
readInstruction32
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t &Size, uint32_t &Insn)
Definition: LanaiDisassembler.cpp:75
llvm::HighlightColor::Address
@ Address
GPRDecoderTable
static const unsigned GPRDecoderTable[]
Definition: LanaiDisassembler.cpp:155
LanaiDisassembler.h
llvm::MCOperand::setImm
void setImm(int64_t Val)
Definition: MCInst.h:85
llvm::LanaiDisassembler::LanaiDisassembler
LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: LanaiDisassembler.cpp:45
R6
#define R6(n)
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
Definition: MCDisassembler.cpp:26
decodePredicateOperand
static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
Definition: LanaiDisassembler.cpp:235
llvm::LPAC::makePostOp
static unsigned makePostOp(unsigned AluOp)
Definition: LanaiAluCode.h:67
llvm::ArrayRef< uint8_t >
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: LanaiDisassembler.cpp:27
uint32_t
llvm::LPCC::UNKNOWN
@ UNKNOWN
Definition: LanaiCondCode.h:31
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:101
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::LanaiDisassembler
Definition: LanaiDisassembler.h:22
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:410
llvm::isRRMOpcode
static bool isRRMOpcode(unsigned Opcode)
Definition: LanaiInstrInfo.h:170
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::MCOperand::setReg
void setReg(unsigned Reg)
Set the register number.
Definition: MCInst.h:75
LLVMInitializeLanaiDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiDisassembler()
Definition: LanaiDisassembler.cpp:39
decodeShiftImm
static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: LanaiDisassembler.cpp:227
LanaiInstrInfo.h
createLanaiDisassembler
static MCDisassembler * createLanaiDisassembler(const Target &, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: LanaiDisassembler.cpp:33
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
decodeSplsValue
static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: LanaiDisassembler.cpp:198
llvm::Value
LLVM Value Representation.
Definition: Value.h:75