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73 #include "LanaiGenDisassemblerTables.inc"
78 if (Bytes.
size() < 4) {
85 (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 8) | (Bytes[3] << 0);
101 AluOp = (
Insn >> 8) & 0x7;
105 AluOp |= 0x20 | (((
Insn >> 3) & 0xf) << 1);
109 unsigned PQ = (
Insn >> PqShift) & 0
x3;
144 decodeInstruction(DecoderTableLanai32, Instr,
Insn, Address,
this,
STI);
156 Lanai::R0, Lanai::R1, Lanai::PC, Lanai::R3, Lanai::SP, Lanai::FP,
157 Lanai::R6, Lanai::R7, Lanai::RV, Lanai::R9, Lanai::RR1, Lanai::RR2,
158 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
159 Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
160 Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
161 Lanai::R30, Lanai::R31};
This is an optimization pass for GlobalISel generic memory operations.
static MCOperand createImm(int64_t Val)
Context object for machine code objects.
Target - Wrapper for Target specific information.
Reg
All possible values of the reg field in the ModR/M byte.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Instances of this class represent a single low-level machine instruction.
static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Target & getTheLanaiTarget()
static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn)
static unsigned makePreOp(unsigned AluOp)
This class implements an extremely fast bulk output stream that can only output to a stream.
static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)
DecodeStatus
Ternary decode status.
static bool isRMOpcode(unsigned Opcode)
const MCSubtargetInfo & STI
void addOperand(const MCOperand Op)
static bool isSPLSOpcode(unsigned Opcode)
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
#define LLVM_EXTERNAL_VISIBILITY
Superclass for all disassemblers.
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t &Size, uint32_t &Insn)
static const unsigned GPRDecoderTable[]
LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static unsigned makePostOp(unsigned AluOp)
static MCOperand createReg(unsigned Reg)
MCDisassembler::DecodeStatus DecodeStatus
Wrapper class representing virtual and physical registers.
static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
unsigned getOpcode() const
static bool isRRMOpcode(unsigned Opcode)
const MCOperand & getOperand(unsigned i) const
size_t size() const
size - Get the array size.
static bool tryAddingSymbolicOperand(int64_t Value, bool IsBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const MCDisassembler *Decoder)
void setReg(unsigned Reg)
Set the register number.
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiDisassembler()
static MCDisassembler * createLanaiDisassembler(const Target &, const MCSubtargetInfo &STI, MCContext &Ctx)
Generic base class for all target subtargets.
LLVM Value Representation.