34 #define DEBUG_TYPE "arm-disassembler"
53 void advanceITState() {
58 bool instrInITBlock() {
59 return !ITStates.empty();
63 bool instrLastInITBlock() {
64 return ITStates.size() == 1;
71 void setITState(
char Firstcond,
char Mask) {
73 unsigned NumTZ = countTrailingZeros<uint8_t>(
Mask);
74 unsigned char CCBits =
static_cast<unsigned char>(Firstcond & 0xf);
75 assert(NumTZ <= 3 &&
"Invalid IT mask!");
77 for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
79 ITStates.push_back(CCBits ^
Else);
81 ITStates.push_back(CCBits);
85 std::vector<unsigned char> ITStates;
91 unsigned getVPTPred() {
93 if (instrInVPTBlock())
94 Pred = VPTStates.back();
98 void advanceVPTState() {
102 bool instrInVPTBlock() {
103 return !VPTStates.empty();
106 bool instrLastInVPTBlock() {
107 return VPTStates.size() == 1;
110 void setVPTState(
char Mask) {
112 unsigned NumTZ = countTrailingZeros<uint8_t>(
Mask);
113 assert(NumTZ <= 3 &&
"Invalid VPT mask!");
115 for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
116 bool T = ((
Mask >> Pos) & 1) == 0;
136 ~ARMDisassembler()
override =
default;
151 mutable ITStatus ITBlock;
152 mutable VPTStatus VPTBlock;
178 uint64_t Address,
const void *Decoder);
180 uint64_t Address,
const void *Decoder);
182 uint64_t Address,
const void *Decoder);
184 uint64_t Address,
const void *Decoder);
187 uint64_t Address,
const void *Decoder);
190 const void *Decoder);
193 const void *Decoder);
196 const void *Decoder);
199 const void *Decoder);
201 MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
203 uint64_t Address,
const void *Decoder);
205 uint64_t Address,
const void *Decoder);
207 uint64_t Address,
const void *Decoder);
209 uint64_t Address,
const void *Decoder);
211 uint64_t Address,
const void *Decoder);
214 const void *Decoder);
216 uint64_t Address,
const void *Decoder);
218 uint64_t Address,
const void *Decoder);
220 uint64_t Address,
const void *Decoder);
222 uint64_t Address,
const void *Decoder);
224 uint64_t Address,
const void *Decoder);
228 const void *Decoder);
230 uint64_t Address,
const void *Decoder);
232 uint64_t Address,
const void *Decoder);
235 const void *Decoder);
238 const void *Decoder);
240 uint64_t Address,
const void *Decoder);
243 const void *Decoder);
246 uint64_t Address,
const void *Decoder);
248 uint64_t Address,
const void *Decoder);
250 uint64_t Address,
const void *Decoder);
252 uint64_t Address,
const void *Decoder);
254 uint64_t Address,
const void *Decoder);
257 uint64_t Address,
const void *Decoder);
259 uint64_t Address,
const void *Decoder);
263 const void *Decoder);
265 uint64_t Address,
const void *Decoder);
267 uint64_t Address,
const void *Decoder);
269 uint64_t Address,
const void *Decoder);
271 uint64_t Address,
const void *Decoder);
276 const void *Decoder);
278 uint64_t Address,
const void *Decoder);
280 uint64_t Address,
const void *Decoder);
282 uint64_t Address,
const void *Decoder);
284 uint64_t Address,
const void *Decoder);
286 uint64_t Address,
const void *Decoder);
288 uint64_t Address,
const void *Decoder);
290 uint64_t Address,
const void *Decoder);
292 uint64_t Address,
const void *Decoder);
295 const void *Decoder);
297 uint64_t Address,
const void *Decoder);
299 uint64_t Address,
const void *Decoder);
301 uint64_t Address,
const void *Decoder);
303 uint64_t Address,
const void *Decoder);
305 uint64_t Address,
const void *Decoder);
307 uint64_t Address,
const void *Decoder);
309 uint64_t Address,
const void *Decoder);
311 uint64_t Address,
const void *Decoder);
313 uint64_t Address,
const void *Decoder);
315 uint64_t Address,
const void *Decoder);
317 uint64_t Address,
const void *Decoder);
319 uint64_t Address,
const void *Decoder);
321 uint64_t Address,
const void *Decoder);
323 uint64_t Address,
const void *Decoder);
325 uint64_t Address,
const void *Decoder);
327 uint64_t Address,
const void *Decoder);
329 uint64_t Address,
const void *Decoder);
331 uint64_t Address,
const void *Decoder);
333 uint64_t Address,
const void *Decoder);
335 uint64_t Address,
const void *Decoder);
337 uint64_t Address,
const void *Decoder);
339 uint64_t Address,
const void *Decoder);
341 uint64_t Address,
const void *Decoder);
343 uint64_t Address,
const void *Decoder);
345 uint64_t Address,
const void *Decoder);
347 uint64_t Address,
const void *Decoder);
349 uint64_t Address,
const void *Decoder);
351 uint64_t Address,
const void *Decoder);
354 uint64_t Address,
const void *Decoder);
356 uint64_t Address,
const void *Decoder);
358 uint64_t Address,
const void *Decoder);
360 uint64_t Address,
const void *Decoder);
362 uint64_t Address,
const void *Decoder);
364 uint64_t Address,
const void *Decoder);
366 uint64_t Address,
const void *Decoder);
368 uint64_t Address,
const void *Decoder);
370 uint64_t Address,
const void *Decoder);
372 uint64_t Address,
const void *Decoder);
374 uint64_t Address,
const void *Decoder);
376 uint64_t Address,
const void *Decoder);
378 uint64_t Address,
const void *Decoder);
380 uint64_t Address,
const void *Decoder);
382 uint64_t Address,
const void *Decoder);
384 uint64_t Address,
const void *Decoder);
386 uint64_t Address,
const void *Decoder);
388 uint64_t Address,
const void *Decoder);
390 uint64_t Address,
const void *Decoder);
392 uint64_t Address,
const void *Decoder);
394 uint64_t Address,
const void *Decoder);
396 uint64_t Address,
const void *Decoder);
398 uint64_t Address,
const void *Decoder);
400 uint64_t Address,
const void *Decoder);
402 uint64_t Address,
const void *Decoder);
404 uint64_t Address,
const void *Decoder);
408 const void *Decoder);
411 uint64_t Address,
const void *Decoder);
413 uint64_t Address,
const void *Decoder);
415 uint64_t Address,
const void *Decoder);
417 uint64_t Address,
const void *Decoder);
419 uint64_t Address,
const void *Decoder);
421 uint64_t Address,
const void *Decoder);
423 uint64_t Address,
const void *Decoder);
425 uint64_t Address,
const void *Decoder);
427 uint64_t Address,
const void *Decoder);
429 uint64_t Address,
const void *Decoder);
431 uint64_t Address,
const void* Decoder);
433 uint64_t Address,
const void* Decoder);
435 uint64_t Address,
const void* Decoder);
437 uint64_t Address,
const void* Decoder);
439 uint64_t Address,
const void *Decoder);
441 uint64_t Address,
const void *Decoder);
443 uint64_t Address,
const void *Decoder);
446 const void *Decoder);
448 uint64_t Address,
const void *Decoder);
450 uint64_t Address,
const void *Decoder);
453 uint64_t Address,
const void *Decoder);
455 uint64_t Address,
const void *Decoder);
458 uint64_t Address,
const void *Decoder);
459 template<
int shift,
int WriteBack>
461 uint64_t Address,
const void *Decoder);
463 uint64_t Address,
const void *Decoder);
465 uint64_t Address,
const void *Decoder);
467 uint64_t Address,
const void *Decoder);
469 uint64_t Address,
const void *Decoder);
471 uint64_t Address,
const void *Decoder);
473 uint64_t Address,
const void *Decoder);
475 uint64_t Address,
const void *Decoder);
477 uint64_t Address,
const void *Decoder);
479 uint64_t Address,
const void *Decoder);
481 uint64_t Address,
const void *Decoder);
483 uint64_t Address,
const void *Decoder);
485 uint64_t Address,
const void *Decoder);
487 uint64_t Address,
const void *Decoder);
489 uint64_t Address,
const void *Decoder);
491 uint64_t Address,
const void *Decoder);
493 uint64_t Address,
const void *Decoder);
495 uint64_t Address,
const void *Decoder);
498 uint64_t Address,
const void *Decoder);
500 uint64_t Address,
const void *Decoder);
502 uint64_t Address,
const void *Decoder);
504 template <
bool isSigned,
bool isNeg,
bool zeroPermitted,
int size>
506 uint64_t Address,
const void *Decoder);
509 const void *Decoder);
512 const void *Decoder);
514 const void *Decoder);
517 const void *Decoder);
519 const void *Decoder);
521 uint64_t Address,
const void *Decoder);
523 uint64_t Address,
const void *Decoder);
526 const void *Decoder);
529 const void *Decoder);
532 const void *Decoder);
536 const void *Decoder);
537 template<
bool Writeback>
540 const void *Decoder);
543 uint64_t Address,
const void *Decoder);
546 uint64_t Address,
const void *Decoder);
549 uint64_t Address,
const void *Decoder);
550 template<
unsigned MinLog,
unsigned MaxLog>
553 const void *Decoder);
554 template<
unsigned start>
557 const void *Decoder);
560 const void *Decoder);
563 const void *Decoder);
565 uint64_t Address,
const void *Decoder);
567 uint64_t Address,
const void *Decoder);
568 template<
bool scalar, OperandDecoder predicate_decoder>
570 uint64_t Address,
const void *Decoder);
572 uint64_t Address,
const void *Decoder);
574 uint64_t Address,
const void *Decoder);
577 const void *Decoder);
579 uint64_t Address,
const void *Decoder);
581 #include "ARMGenDisassemblerTables.inc"
586 return new ARMDisassembler(STI, Ctx);
594 switch (
MI.getOpcode()) {
613 if (
MI.getOperand(0).getReg() == ARM::SP &&
614 MI.getOperand(1).getReg() != ARM::SP)
617 default:
return Result;
625 if (STI.getFeatureBits()[ARM::ModeThumb])
626 return getThumbInstruction(
MI,
Size, Bytes, Address, CS);
627 return getARMInstruction(
MI,
Size, Bytes, Address, CS);
636 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
637 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
641 if (Bytes.
size() < 4) {
648 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
652 decodeInstruction(DecoderTableARM32,
MI,
Insn, Address,
this, STI);
663 const DecodeTable Tables[] = {
664 {DecoderTableVFP32,
false}, {DecoderTableVFPV832,
false},
665 {DecoderTableNEONData32,
true}, {DecoderTableNEONLoadStore32,
true},
666 {DecoderTableNEONDup32,
true}, {DecoderTablev8NEON32,
false},
667 {DecoderTablev8Crypto32,
false},
670 for (
auto Table : Tables) {
671 Result = decodeInstruction(Table.P,
MI,
Insn, Address,
this, STI);
683 decodeInstruction(DecoderTableCoProc32,
MI,
Insn, Address,
this, STI);
730 const void *Decoder) {
743 for (
unsigned i = 0;
i < NumOps; ++
i, ++
I) {
744 if (
I ==
MI.end())
break;
745 if (OpInfo[
i].isOptionalDef() && OpInfo[
i].RegClass == ARM::CCRRegClassID) {
746 if (
i > 0 && OpInfo[
i-1].isPredicate())
continue;
758 for (
unsigned i = 0;
i < NumOps; ++
i) {
770 ARMDisassembler::AddThumbPredicate(
MCInst &
MI)
const {
773 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
777 switch (
MI.getOpcode()) {
794 if (ITBlock.instrInITBlock())
800 if (
MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
809 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
826 if (ITBlock.instrInITBlock()) {
827 CC = ITBlock.getITCC();
828 ITBlock.advanceITState();
829 }
else if (VPTBlock.instrInVPTBlock()) {
830 VCC = VPTBlock.getVPTPred();
831 VPTBlock.advanceVPTState();
838 for (
unsigned i = 0;
i < NumOps; ++
i, ++CCI) {
839 if (OpInfo[
i].isPredicate() || CCI ==
MI.end())
break;
855 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
873 "Inactive register in vpred_r is not tied to an output!");
889 void ARMDisassembler::UpdateThumbVFPPredicate(
892 CC = ITBlock.getITCC();
895 if (ITBlock.instrInITBlock())
896 ITBlock.advanceITState();
897 else if (VPTBlock.instrInVPTBlock()) {
898 CC = VPTBlock.getVPTPred();
899 VPTBlock.advanceVPTState();
905 for (
unsigned i = 0;
i < NumOps; ++
i, ++
I) {
906 if (OpInfo[
i].isPredicate() ) {
914 I->setReg(ARM::CPSR);
926 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
927 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
930 if (Bytes.
size() < 2) {
935 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
937 decodeInstruction(DecoderTableThumb16,
MI, Insn16, Address,
this, STI);
940 Check(Result, AddThumbPredicate(
MI));
944 Result = decodeInstruction(DecoderTableThumbSBit16,
MI, Insn16, Address,
this,
948 bool InITBlock = ITBlock.instrInITBlock();
949 Check(Result, AddThumbPredicate(
MI));
955 decodeInstruction(DecoderTableThumb216,
MI, Insn16, Address,
this, STI);
961 if (
MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
964 Check(Result, AddThumbPredicate(
MI));
969 if (
MI.getOpcode() == ARM::t2IT) {
970 unsigned Firstcond =
MI.getOperand(0).getImm();
971 unsigned Mask =
MI.getOperand(1).getImm();
972 ITBlock.setITState(Firstcond,
Mask);
976 CS <<
"unpredictable IT predicate sequence";
983 if (Bytes.
size() < 4) {
989 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
992 decodeInstruction(DecoderTableMVE32,
MI, Insn32, Address,
this, STI);
998 if (
isVPTOpcode(
MI.getOpcode()) && VPTBlock.instrInVPTBlock())
1001 Check(Result, AddThumbPredicate(
MI));
1004 unsigned Mask =
MI.getOperand(0).getImm();
1005 VPTBlock.setVPTState(
Mask);
1012 decodeInstruction(DecoderTableThumb32,
MI, Insn32, Address,
this, STI);
1015 bool InITBlock = ITBlock.instrInITBlock();
1016 Check(Result, AddThumbPredicate(
MI));
1022 decodeInstruction(DecoderTableThumb232,
MI, Insn32, Address,
this, STI);
1025 Check(Result, AddThumbPredicate(
MI));
1029 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1031 decodeInstruction(DecoderTableVFP32,
MI, Insn32, Address,
this, STI);
1034 UpdateThumbVFPPredicate(Result,
MI);
1040 decodeInstruction(DecoderTableVFPV832,
MI, Insn32, Address,
this, STI);
1046 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1047 Result = decodeInstruction(DecoderTableNEONDup32,
MI, Insn32, Address,
this,
1051 Check(Result, AddThumbPredicate(
MI));
1056 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
1058 NEONLdStInsn &= 0xF0FFFFFF;
1059 NEONLdStInsn |= 0x04000000;
1060 Result = decodeInstruction(DecoderTableNEONLoadStore32,
MI, NEONLdStInsn,
1061 Address,
this, STI);
1064 Check(Result, AddThumbPredicate(
MI));
1069 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
1071 NEONDataInsn &= 0xF0FFFFFF;
1072 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4;
1073 NEONDataInsn |= 0x12000000;
1074 Result = decodeInstruction(DecoderTableNEONData32,
MI, NEONDataInsn,
1075 Address,
this, STI);
1078 Check(Result, AddThumbPredicate(
MI));
1083 NEONCryptoInsn &= 0xF0FFFFFF;
1084 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4;
1085 NEONCryptoInsn |= 0x12000000;
1086 Result = decodeInstruction(DecoderTablev8Crypto32,
MI, NEONCryptoInsn,
1087 Address,
this, STI);
1094 NEONv8Insn &= 0xF3FFFFFF;
1095 Result = decodeInstruction(DecoderTablev8NEON32,
MI, NEONv8Insn, Address,
1103 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
1105 ? DecoderTableThumb2CDE32
1106 : DecoderTableThumb2CoProc32;
1108 decodeInstruction(DecoderTable,
MI, Insn32, Address,
this, STI);
1111 Check(Result, AddThumbPredicate(
MI));
1131 ARM::R0, ARM::R1,
ARM::R2, ARM::R3,
1133 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1134 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1138 ARM::R0, ARM::R1,
ARM::R2, ARM::R3,
1140 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1141 ARM::R12, 0, ARM::LR, ARM::APSR
1145 uint64_t Address,
const void *Decoder) {
1156 const void *Decoder) {
1170 uint64_t Address,
const void *Decoder) {
1183 const void *Decoder) {
1196 uint64_t Address,
const void *Decoder) {
1211 uint64_t Address,
const void *Decoder) {
1229 uint64_t Address,
const void *Decoder) {
1238 uint64_t Address,
const void *Decoder) {
1245 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1246 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1250 uint64_t Address,
const void *Decoder) {
1267 uint64_t Address,
const void *Decoder) {
1274 if ((RegNo & 1) || RegNo > 10)
1281 const void *Decoder) {
1291 uint64_t Address,
const void *Decoder) {
1321 uint64_t Address,
const void *Decoder) {
1325 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1327 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1335 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1336 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1337 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1338 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1339 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1340 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1341 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1342 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1346 uint64_t Address,
const void *Decoder) {
1356 uint64_t Address,
const void *Decoder) {
1361 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1362 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1363 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1364 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1365 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1366 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1367 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1368 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1372 uint64_t Address,
const void *Decoder) {
1374 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1376 bool hasD32 = featureBits[ARM::FeatureD32];
1378 if (RegNo > 31 || (!hasD32 && RegNo > 15))
1387 uint64_t Address,
const void *Decoder) {
1394 uint64_t Address,
const void *Decoder) {
1402 uint64_t Address,
const void *Decoder) {
1409 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1410 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1411 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1412 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1416 uint64_t Address,
const void *Decoder) {
1417 if (RegNo > 31 || (RegNo & 1) != 0)
1427 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1428 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1429 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1430 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1431 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1436 uint64_t Address,
const void *Decoder) {
1446 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1447 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1448 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1449 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1450 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1451 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1452 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1453 ARM::D28_D30, ARM::D29_D31
1459 const void *Decoder) {
1469 uint64_t Address,
const void *Decoder) {
1473 if (Inst.
getOpcode() == ARM::tBcc && Val == 0xE)
1486 uint64_t Address,
const void *Decoder) {
1495 uint64_t Address,
const void *Decoder) {
1498 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1499 unsigned type = fieldFromInstruction(Val, 5, 2);
1500 unsigned imm = fieldFromInstruction(Val, 7, 5);
1525 unsigned Op =
Shift | (imm << 3);
1532 uint64_t Address,
const void *Decoder) {
1535 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1536 unsigned type = fieldFromInstruction(Val, 5, 2);
1537 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1567 uint64_t Address,
const void *Decoder) {
1570 bool NeedDisjointWriteback =
false;
1571 unsigned WritebackReg = 0;
1576 case ARM::LDMIA_UPD:
1577 case ARM::LDMDB_UPD:
1578 case ARM::LDMIB_UPD:
1579 case ARM::LDMDA_UPD:
1580 case ARM::t2LDMIA_UPD:
1581 case ARM::t2LDMDB_UPD:
1582 case ARM::t2STMIA_UPD:
1583 case ARM::t2STMDB_UPD:
1584 NeedDisjointWriteback =
true;
1594 for (
unsigned i = 0;
i < 16; ++
i) {
1595 if (Val & (1 <<
i)) {
1604 if (NeedDisjointWriteback && WritebackReg == Inst.
end()[-1].getReg())
1614 uint64_t Address,
const void *Decoder) {
1617 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1618 unsigned regs = fieldFromInstruction(Val, 0, 8);
1621 if (regs == 0 || (Vd + regs) > 32) {
1622 regs = Vd + regs > 32 ? 32 - Vd : regs;
1629 for (
unsigned i = 0;
i < (regs - 1); ++
i) {
1638 uint64_t Address,
const void *Decoder) {
1641 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1642 unsigned regs = fieldFromInstruction(Val, 1, 7);
1645 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1646 regs = Vd + regs > 32 ? 32 - Vd : regs;
1654 for (
unsigned i = 0;
i < (regs - 1); ++
i) {
1663 uint64_t Address,
const void *Decoder) {
1669 unsigned msb = fieldFromInstruction(Val, 5, 5);
1670 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1682 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1683 uint32_t lsb_mask = (1U << lsb) - 1;
1690 uint64_t Address,
const void *Decoder) {
1693 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
1694 unsigned CRd = fieldFromInstruction(
Insn, 12, 4);
1695 unsigned coproc = fieldFromInstruction(
Insn, 8, 4);
1696 unsigned imm = fieldFromInstruction(
Insn, 0, 8);
1697 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
1698 unsigned U = fieldFromInstruction(
Insn, 23, 1);
1700 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1703 case ARM::LDC_OFFSET:
1706 case ARM::LDC_OPTION:
1707 case ARM::LDCL_OFFSET:
1709 case ARM::LDCL_POST:
1710 case ARM::LDCL_OPTION:
1711 case ARM::STC_OFFSET:
1714 case ARM::STC_OPTION:
1715 case ARM::STCL_OFFSET:
1717 case ARM::STCL_POST:
1718 case ARM::STCL_OPTION:
1719 case ARM::t2LDC_OFFSET:
1720 case ARM::t2LDC_PRE:
1721 case ARM::t2LDC_POST:
1722 case ARM::t2LDC_OPTION:
1723 case ARM::t2LDCL_OFFSET:
1724 case ARM::t2LDCL_PRE:
1725 case ARM::t2LDCL_POST:
1726 case ARM::t2LDCL_OPTION:
1727 case ARM::t2STC_OFFSET:
1728 case ARM::t2STC_PRE:
1729 case ARM::t2STC_POST:
1730 case ARM::t2STC_OPTION:
1731 case ARM::t2STCL_OFFSET:
1732 case ARM::t2STCL_PRE:
1733 case ARM::t2STCL_POST:
1734 case ARM::t2STCL_OPTION:
1735 case ARM::t2LDC2_OFFSET:
1736 case ARM::t2LDC2L_OFFSET:
1737 case ARM::t2LDC2_PRE:
1738 case ARM::t2LDC2L_PRE:
1739 case ARM::t2STC2_OFFSET:
1740 case ARM::t2STC2L_OFFSET:
1741 case ARM::t2STC2_PRE:
1742 case ARM::t2STC2L_PRE:
1743 case ARM::LDC2_OFFSET:
1744 case ARM::LDC2L_OFFSET:
1746 case ARM::LDC2L_PRE:
1747 case ARM::STC2_OFFSET:
1748 case ARM::STC2L_OFFSET:
1750 case ARM::STC2L_PRE:
1751 case ARM::t2LDC2_OPTION:
1752 case ARM::t2STC2_OPTION:
1753 case ARM::t2LDC2_POST:
1754 case ARM::t2LDC2L_POST:
1755 case ARM::t2STC2_POST:
1756 case ARM::t2STC2L_POST:
1757 case ARM::LDC2_POST:
1758 case ARM::LDC2L_POST:
1759 case ARM::STC2_POST:
1760 case ARM::STC2L_POST:
1761 if (coproc == 0xA || coproc == 0xB ||
1762 (featureBits[ARM::HasV8_1MMainlineOps] &&
1763 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1764 coproc == 0xE || coproc == 0xF)))
1771 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1780 case ARM::t2LDC2_OFFSET:
1781 case ARM::t2LDC2L_OFFSET:
1782 case ARM::t2LDC2_PRE:
1783 case ARM::t2LDC2L_PRE:
1784 case ARM::t2STC2_OFFSET:
1785 case ARM::t2STC2L_OFFSET:
1786 case ARM::t2STC2_PRE:
1787 case ARM::t2STC2L_PRE:
1788 case ARM::LDC2_OFFSET:
1789 case ARM::LDC2L_OFFSET:
1791 case ARM::LDC2L_PRE:
1792 case ARM::STC2_OFFSET:
1793 case ARM::STC2L_OFFSET:
1795 case ARM::STC2L_PRE:
1796 case ARM::t2LDC_OFFSET:
1797 case ARM::t2LDCL_OFFSET:
1798 case ARM::t2LDC_PRE:
1799 case ARM::t2LDCL_PRE:
1800 case ARM::t2STC_OFFSET:
1801 case ARM::t2STCL_OFFSET:
1802 case ARM::t2STC_PRE:
1803 case ARM::t2STCL_PRE:
1804 case ARM::LDC_OFFSET:
1805 case ARM::LDCL_OFFSET:
1808 case ARM::STC_OFFSET:
1809 case ARM::STCL_OFFSET:
1815 case ARM::t2LDC2_POST:
1816 case ARM::t2LDC2L_POST:
1817 case ARM::t2STC2_POST:
1818 case ARM::t2STC2L_POST:
1819 case ARM::LDC2_POST:
1820 case ARM::LDC2L_POST:
1821 case ARM::STC2_POST:
1822 case ARM::STC2L_POST:
1823 case ARM::t2LDC_POST:
1824 case ARM::t2LDCL_POST:
1825 case ARM::t2STC_POST:
1826 case ARM::t2STCL_POST:
1828 case ARM::LDCL_POST:
1830 case ARM::STCL_POST:
1841 case ARM::LDC_OFFSET:
1844 case ARM::LDC_OPTION:
1845 case ARM::LDCL_OFFSET:
1847 case ARM::LDCL_POST:
1848 case ARM::LDCL_OPTION:
1849 case ARM::STC_OFFSET:
1852 case ARM::STC_OPTION:
1853 case ARM::STCL_OFFSET:
1855 case ARM::STCL_POST:
1856 case ARM::STCL_OPTION:
1869 uint64_t Address,
const void *Decoder) {
1872 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
1873 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
1874 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
1875 unsigned imm = fieldFromInstruction(
Insn, 0, 12);
1876 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
1877 unsigned reg = fieldFromInstruction(
Insn, 25, 1);
1878 unsigned P = fieldFromInstruction(
Insn, 24, 1);
1879 unsigned W = fieldFromInstruction(
Insn, 21, 1);
1883 case ARM::STR_POST_IMM:
1884 case ARM::STR_POST_REG:
1885 case ARM::STRB_POST_IMM:
1886 case ARM::STRB_POST_REG:
1887 case ARM::STRT_POST_REG:
1888 case ARM::STRT_POST_IMM:
1889 case ARM::STRBT_POST_REG:
1890 case ARM::STRBT_POST_IMM:
1903 case ARM::LDR_POST_IMM:
1904 case ARM::LDR_POST_REG:
1905 case ARM::LDRB_POST_IMM:
1906 case ARM::LDRB_POST_REG:
1907 case ARM::LDRBT_POST_REG:
1908 case ARM::LDRBT_POST_IMM:
1909 case ARM::LDRT_POST_REG:
1910 case ARM::LDRT_POST_IMM:
1922 if (!fieldFromInstruction(
Insn, 23, 1))
1925 bool writeback = (
P == 0) || (
W == 1);
1926 unsigned idx_mode = 0;
1929 else if (!
P && writeback)
1932 if (writeback && (Rn == 15 || Rn == Rt))
1939 switch( fieldFromInstruction(
Insn, 5, 2)) {
1955 unsigned amt = fieldFromInstruction(
Insn, 7, 5);
1974 uint64_t Address,
const void *Decoder) {
1977 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1978 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1979 unsigned type = fieldFromInstruction(Val, 5, 2);
1980 unsigned imm = fieldFromInstruction(Val, 7, 5);
1981 unsigned U = fieldFromInstruction(Val, 12, 1);
2018 uint64_t Address,
const void *Decoder) {
2021 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
2022 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2023 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
2024 unsigned type = fieldFromInstruction(
Insn, 22, 1);
2025 unsigned imm = fieldFromInstruction(
Insn, 8, 4);
2026 unsigned U = ((~fieldFromInstruction(
Insn, 23, 1)) & 1) << 8;
2027 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2028 unsigned W = fieldFromInstruction(
Insn, 21, 1);
2029 unsigned P = fieldFromInstruction(
Insn, 24, 1);
2030 unsigned Rt2 = Rt + 1;
2032 bool writeback = (
W == 1) | (
P == 0);
2038 case ARM::STRD_POST:
2041 case ARM::LDRD_POST:
2050 case ARM::STRD_POST:
2051 if (
P == 0 &&
W == 1)
2054 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2056 if (
type && Rm == 15)
2060 if (!
type && fieldFromInstruction(
Insn, 8, 4))
2065 case ARM::STRH_POST:
2068 if (writeback && (Rn == 15 || Rn == Rt))
2070 if (!
type && Rm == 15)
2075 case ARM::LDRD_POST:
2076 if (
type && Rn == 15) {
2081 if (
P == 0 &&
W == 1)
2083 if (!
type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2085 if (!
type && writeback && Rn == 15)
2087 if (writeback && (Rn == Rt || Rn == Rt2))
2092 case ARM::LDRH_POST:
2093 if (
type && Rn == 15) {
2100 if (!
type && Rm == 15)
2102 if (!
type && writeback && (Rn == 15 || Rn == Rt))
2106 case ARM::LDRSH_PRE:
2107 case ARM::LDRSH_POST:
2109 case ARM::LDRSB_PRE:
2110 case ARM::LDRSB_POST:
2111 if (
type && Rn == 15) {
2116 if (
type && (Rt == 15 || (writeback && Rn == Rt)))
2118 if (!
type && (Rt == 15 || Rm == 15))
2120 if (!
type && writeback && (Rn == 15 || Rn == Rt))
2137 case ARM::STRD_POST:
2140 case ARM::STRH_POST:
2154 case ARM::STRD_POST:
2157 case ARM::LDRD_POST:
2170 case ARM::LDRD_POST:
2173 case ARM::LDRH_POST:
2175 case ARM::LDRSH_PRE:
2176 case ARM::LDRSH_POST:
2178 case ARM::LDRSB_PRE:
2179 case ARM::LDRSB_POST:
2209 uint64_t Address,
const void *Decoder) {
2212 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2213 unsigned mode = fieldFromInstruction(
Insn, 23, 2);
2238 uint64_t Address,
const void *Decoder) {
2241 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
2242 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
2243 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2244 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2262 uint64_t Address,
const void *Decoder) {
2265 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2266 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2267 unsigned reglist = fieldFromInstruction(
Insn, 0, 16);
2275 case ARM::LDMDA_UPD:
2281 case ARM::LDMDB_UPD:
2287 case ARM::LDMIA_UPD:
2293 case ARM::LDMIB_UPD:
2299 case ARM::STMDA_UPD:
2305 case ARM::STMDB_UPD:
2311 case ARM::STMIA_UPD:
2317 case ARM::STMIB_UPD:
2325 if (fieldFromInstruction(
Insn, 20, 1) == 0) {
2327 if (!(fieldFromInstruction(
Insn, 22, 1) == 1 &&
2328 fieldFromInstruction(
Insn, 20, 1) == 0))
2353 uint64_t Address,
const void *Decoder) {
2354 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2355 unsigned imm8 = fieldFromInstruction(
Insn, 0, 8);
2368 if (imm8 == 0x10 &&
pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2375 uint64_t Address,
const void *Decoder) {
2376 unsigned imod = fieldFromInstruction(
Insn, 18, 2);
2377 unsigned M = fieldFromInstruction(
Insn, 17, 1);
2378 unsigned iflags = fieldFromInstruction(
Insn, 6, 3);
2379 unsigned mode = fieldFromInstruction(
Insn, 0, 5);
2385 if (fieldFromInstruction(
Insn, 5, 1) != 0 ||
2386 fieldFromInstruction(
Insn, 16, 1) != 0 ||
2387 fieldFromInstruction(
Insn, 20, 8) != 0x10)
2402 }
else if (imod && !
M) {
2407 }
else if (!imod &&
M) {
2422 uint64_t Address,
const void *Decoder) {
2423 unsigned imod = fieldFromInstruction(
Insn, 9, 2);
2424 unsigned M = fieldFromInstruction(
Insn, 8, 1);
2425 unsigned iflags = fieldFromInstruction(
Insn, 5, 3);
2426 unsigned mode = fieldFromInstruction(
Insn, 0, 5);
2442 }
else if (imod && !
M) {
2447 }
else if (!imod &&
M) {
2453 int imm = fieldFromInstruction(
Insn, 0, 8);
2465 const void *Decoder) {
2466 unsigned imm = fieldFromInstruction(
Insn, 0, 8);
2468 unsigned Opcode = ARM::t2HINT;
2471 Opcode = ARM::t2PACBTI;
2472 }
else if (imm == 0x1D) {
2473 Opcode = ARM::t2PAC;
2474 }
else if (imm == 0x2D) {
2475 Opcode = ARM::t2AUT;
2476 }
else if (imm == 0x0F) {
2477 Opcode = ARM::t2BTI;
2481 if (Opcode == ARM::t2HINT) {
2489 uint64_t Address,
const void *Decoder) {
2492 unsigned Rd = fieldFromInstruction(
Insn, 8, 4);
2495 imm |= (fieldFromInstruction(
Insn, 0, 8) << 0);
2496 imm |= (fieldFromInstruction(
Insn, 12, 3) << 8);
2497 imm |= (fieldFromInstruction(
Insn, 16, 4) << 12);
2498 imm |= (fieldFromInstruction(
Insn, 26, 1) << 11);
2513 uint64_t Address,
const void *Decoder) {
2516 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
2517 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2520 imm |= (fieldFromInstruction(
Insn, 0, 12) << 0);
2521 imm |= (fieldFromInstruction(
Insn, 16, 4) << 12);
2540 uint64_t Address,
const void *Decoder) {
2543 unsigned Rd = fieldFromInstruction(
Insn, 16, 4);
2544 unsigned Rn = fieldFromInstruction(
Insn, 0, 4);
2545 unsigned Rm = fieldFromInstruction(
Insn, 8, 4);
2546 unsigned Ra = fieldFromInstruction(
Insn, 12, 4);
2547 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2568 uint64_t Address,
const void *Decoder) {
2571 unsigned Pred = fieldFromInstruction(
Insn, 28, 4);
2572 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2573 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
2589 uint64_t Address,
const void *Decoder) {
2592 unsigned Imm = fieldFromInstruction(
Insn, 9, 1);
2597 if (!FeatureBits[ARM::HasV8_1aOps] ||
2598 !FeatureBits[ARM::HasV8Ops])
2603 if (fieldFromInstruction(
Insn, 20,12) != 0xf11 ||
2604 fieldFromInstruction(
Insn, 4,4) != 0)
2606 if (fieldFromInstruction(
Insn, 10,10) != 0 ||
2607 fieldFromInstruction(
Insn, 0,4) != 0)
2617 uint64_t Address,
const void *Decoder) {
2620 unsigned add = fieldFromInstruction(Val, 12, 1);
2621 unsigned imm = fieldFromInstruction(Val, 0, 12);
2622 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2627 if (!
add) imm *= -1;
2628 if (imm == 0 && !
add) imm = INT32_MIN;
2637 uint64_t Address,
const void *Decoder) {
2640 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2642 unsigned U = fieldFromInstruction(Val, 8, 1);
2643 unsigned imm = fieldFromInstruction(Val, 0, 8);
2657 uint64_t Address,
const void *Decoder) {
2660 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2662 unsigned U = fieldFromInstruction(Val, 8, 1);
2663 unsigned imm = fieldFromInstruction(Val, 0, 8);
2677 uint64_t Address,
const void *Decoder) {
2683 uint64_t Address,
const void *Decoder) {
2692 unsigned S = fieldFromInstruction(
Insn, 26, 1);
2693 unsigned J1 = fieldFromInstruction(
Insn, 13, 1);
2694 unsigned J2 = fieldFromInstruction(
Insn, 11, 1);
2695 unsigned I1 = !(J1 ^
S);
2696 unsigned I2 = !(J2 ^
S);
2697 unsigned imm10 = fieldFromInstruction(
Insn, 16, 10);
2698 unsigned imm11 = fieldFromInstruction(
Insn, 0, 11);
2699 unsigned tmp = (
S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2700 int imm32 = SignExtend32<25>(
tmp << 1);
2702 true, 4, Inst, Decoder))
2710 uint64_t Address,
const void *Decoder) {
2713 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2714 unsigned imm = fieldFromInstruction(
Insn, 0, 24) << 2;
2718 imm |= fieldFromInstruction(
Insn, 24, 1) << 1;
2720 true, 4, Inst, Decoder))
2726 true, 4, Inst, Decoder))
2739 uint64_t Address,
const void *Decoder) {
2742 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2743 unsigned align = fieldFromInstruction(Val, 4, 2);
2756 uint64_t Address,
const void *Decoder) {
2759 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
2760 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
2761 unsigned wb = fieldFromInstruction(
Insn, 16, 4);
2762 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2763 Rn |= fieldFromInstruction(
Insn, 4, 2) << 4;
2764 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
2768 case ARM::VLD1q16:
case ARM::VLD1q32:
case ARM::VLD1q64:
case ARM::VLD1q8:
2769 case ARM::VLD1q16wb_fixed:
case ARM::VLD1q16wb_register:
2770 case ARM::VLD1q32wb_fixed:
case ARM::VLD1q32wb_register:
2771 case ARM::VLD1q64wb_fixed:
case ARM::VLD1q64wb_register:
2772 case ARM::VLD1q8wb_fixed:
case ARM::VLD1q8wb_register:
2773 case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d8:
2774 case ARM::VLD2d16wb_fixed:
case ARM::VLD2d16wb_register:
2775 case ARM::VLD2d32wb_fixed:
case ARM::VLD2d32wb_register:
2776 case ARM::VLD2d8wb_fixed:
case ARM::VLD2d8wb_register:
2783 case ARM::VLD2b16wb_fixed:
2784 case ARM::VLD2b16wb_register:
2785 case ARM::VLD2b32wb_fixed:
2786 case ARM::VLD2b32wb_register:
2787 case ARM::VLD2b8wb_fixed:
2788 case ARM::VLD2b8wb_register:
2802 case ARM::VLD3d8_UPD:
2803 case ARM::VLD3d16_UPD:
2804 case ARM::VLD3d32_UPD:
2808 case ARM::VLD4d8_UPD:
2809 case ARM::VLD4d16_UPD:
2810 case ARM::VLD4d32_UPD:
2817 case ARM::VLD3q8_UPD:
2818 case ARM::VLD3q16_UPD:
2819 case ARM::VLD3q32_UPD:
2823 case ARM::VLD4q8_UPD:
2824 case ARM::VLD4q16_UPD:
2825 case ARM::VLD4q32_UPD:
2838 case ARM::VLD3d8_UPD:
2839 case ARM::VLD3d16_UPD:
2840 case ARM::VLD3d32_UPD:
2844 case ARM::VLD4d8_UPD:
2845 case ARM::VLD4d16_UPD:
2846 case ARM::VLD4d32_UPD:
2853 case ARM::VLD3q8_UPD:
2854 case ARM::VLD3q16_UPD:
2855 case ARM::VLD3q32_UPD:
2859 case ARM::VLD4q8_UPD:
2860 case ARM::VLD4q16_UPD:
2861 case ARM::VLD4q32_UPD:
2874 case ARM::VLD4d8_UPD:
2875 case ARM::VLD4d16_UPD:
2876 case ARM::VLD4d32_UPD:
2883 case ARM::VLD4q8_UPD:
2884 case ARM::VLD4q16_UPD:
2885 case ARM::VLD4q32_UPD:
2895 case ARM::VLD1d8wb_fixed:
2896 case ARM::VLD1d16wb_fixed:
2897 case ARM::VLD1d32wb_fixed:
2898 case ARM::VLD1d64wb_fixed:
2899 case ARM::VLD1d8wb_register:
2900 case ARM::VLD1d16wb_register:
2901 case ARM::VLD1d32wb_register:
2902 case ARM::VLD1d64wb_register:
2903 case ARM::VLD1q8wb_fixed:
2904 case ARM::VLD1q16wb_fixed:
2905 case ARM::VLD1q32wb_fixed:
2906 case ARM::VLD1q64wb_fixed:
2907 case ARM::VLD1q8wb_register:
2908 case ARM::VLD1q16wb_register:
2909 case ARM::VLD1q32wb_register:
2910 case ARM::VLD1q64wb_register:
2911 case ARM::VLD1d8Twb_fixed:
2912 case ARM::VLD1d8Twb_register:
2913 case ARM::VLD1d16Twb_fixed:
2914 case ARM::VLD1d16Twb_register:
2915 case ARM::VLD1d32Twb_fixed:
2916 case ARM::VLD1d32Twb_register:
2917 case ARM::VLD1d64Twb_fixed:
2918 case ARM::VLD1d64Twb_register:
2919 case ARM::VLD1d8Qwb_fixed:
2920 case ARM::VLD1d8Qwb_register:
2921 case ARM::VLD1d16Qwb_fixed:
2922 case ARM::VLD1d16Qwb_register:
2923 case ARM::VLD1d32Qwb_fixed:
2924 case ARM::VLD1d32Qwb_register:
2925 case ARM::VLD1d64Qwb_fixed:
2926 case ARM::VLD1d64Qwb_register:
2927 case ARM::VLD2d8wb_fixed:
2928 case ARM::VLD2d16wb_fixed:
2929 case ARM::VLD2d32wb_fixed:
2930 case ARM::VLD2q8wb_fixed:
2931 case ARM::VLD2q16wb_fixed:
2932 case ARM::VLD2q32wb_fixed:
2933 case ARM::VLD2d8wb_register:
2934 case ARM::VLD2d16wb_register:
2935 case ARM::VLD2d32wb_register:
2936 case ARM::VLD2q8wb_register:
2937 case ARM::VLD2q16wb_register:
2938 case ARM::VLD2q32wb_register:
2939 case ARM::VLD2b8wb_fixed:
2940 case ARM::VLD2b16wb_fixed:
2941 case ARM::VLD2b32wb_fixed:
2942 case ARM::VLD2b8wb_register:
2943 case ARM::VLD2b16wb_register:
2944 case ARM::VLD2b32wb_register:
2947 case ARM::VLD3d8_UPD:
2948 case ARM::VLD3d16_UPD:
2949 case ARM::VLD3d32_UPD:
2950 case ARM::VLD3q8_UPD:
2951 case ARM::VLD3q16_UPD:
2952 case ARM::VLD3q32_UPD:
2953 case ARM::VLD4d8_UPD:
2954 case ARM::VLD4d16_UPD:
2955 case ARM::VLD4d32_UPD:
2956 case ARM::VLD4q8_UPD:
2957 case ARM::VLD4q16_UPD:
2958 case ARM::VLD4q32_UPD:
2985 case ARM::VLD1d8wb_fixed:
2986 case ARM::VLD1d16wb_fixed:
2987 case ARM::VLD1d32wb_fixed:
2988 case ARM::VLD1d64wb_fixed:
2989 case ARM::VLD1d8Twb_fixed:
2990 case ARM::VLD1d16Twb_fixed:
2991 case ARM::VLD1d32Twb_fixed:
2992 case ARM::VLD1d64Twb_fixed:
2993 case ARM::VLD1d8Qwb_fixed:
2994 case ARM::VLD1d16Qwb_fixed:
2995 case ARM::VLD1d32Qwb_fixed:
2996 case ARM::VLD1d64Qwb_fixed:
2997 case ARM::VLD1d8wb_register:
2998 case ARM::VLD1d16wb_register:
2999 case ARM::VLD1d32wb_register:
3000 case ARM::VLD1d64wb_register:
3001 case ARM::VLD1q8wb_fixed:
3002 case ARM::VLD1q16wb_fixed:
3003 case ARM::VLD1q32wb_fixed:
3004 case ARM::VLD1q64wb_fixed:
3005 case ARM::VLD1q8wb_register:
3006 case ARM::VLD1q16wb_register:
3007 case ARM::VLD1q32wb_register:
3008 case ARM::VLD1q64wb_register:
3012 if (Rm != 0xD && Rm != 0xF &&
3016 case ARM::VLD2d8wb_fixed:
3017 case ARM::VLD2d16wb_fixed:
3018 case ARM::VLD2d32wb_fixed:
3019 case ARM::VLD2b8wb_fixed:
3020 case ARM::VLD2b16wb_fixed:
3021 case ARM::VLD2b32wb_fixed:
3022 case ARM::VLD2q8wb_fixed:
3023 case ARM::VLD2q16wb_fixed:
3024 case ARM::VLD2q32wb_fixed:
3032 uint64_t Address,
const void *Decoder) {
3033 unsigned type = fieldFromInstruction(
Insn, 8, 4);
3034 unsigned align = fieldFromInstruction(
Insn, 4, 2);
3039 unsigned load = fieldFromInstruction(
Insn, 21, 1);
3045 uint64_t Address,
const void *Decoder) {
3046 unsigned size = fieldFromInstruction(
Insn, 6, 2);
3049 unsigned type = fieldFromInstruction(
Insn, 8, 4);
3050 unsigned align = fieldFromInstruction(
Insn, 4, 2);
3054 unsigned load = fieldFromInstruction(
Insn, 21, 1);
3060 uint64_t Address,
const void *Decoder) {
3061 unsigned size = fieldFromInstruction(
Insn, 6, 2);
3064 unsigned align = fieldFromInstruction(
Insn, 4, 2);
3067 unsigned load = fieldFromInstruction(
Insn, 21, 1);
3073 uint64_t Address,
const void *Decoder) {
3074 unsigned size = fieldFromInstruction(
Insn, 6, 2);
3077 unsigned load = fieldFromInstruction(
Insn, 21, 1);
3083 uint64_t Address,
const void *Decoder) {
3086 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3087 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3088 unsigned wb = fieldFromInstruction(
Insn, 16, 4);
3089 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3090 Rn |= fieldFromInstruction(
Insn, 4, 2) << 4;
3091 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3095 case ARM::VST1d8wb_fixed:
3096 case ARM::VST1d16wb_fixed:
3097 case ARM::VST1d32wb_fixed:
3098 case ARM::VST1d64wb_fixed:
3099 case ARM::VST1d8wb_register:
3100 case ARM::VST1d16wb_register:
3101 case ARM::VST1d32wb_register:
3102 case ARM::VST1d64wb_register:
3103 case ARM::VST1q8wb_fixed:
3104 case ARM::VST1q16wb_fixed:
3105 case ARM::VST1q32wb_fixed:
3106 case ARM::VST1q64wb_fixed:
3107 case ARM::VST1q8wb_register:
3108 case ARM::VST1q16wb_register:
3109 case ARM::VST1q32wb_register:
3110 case ARM::VST1q64wb_register:
3111 case ARM::VST1d8Twb_fixed:
3112 case ARM::VST1d16Twb_fixed:
3113 case ARM::VST1d32Twb_fixed:
3114 case ARM::VST1d64Twb_fixed:
3115 case ARM::VST1d8Twb_register:
3116 case ARM::VST1d16Twb_register:
3117 case ARM::VST1d32Twb_register:
3118 case ARM::VST1d64Twb_register:
3119 case ARM::VST1d8Qwb_fixed:
3120 case ARM::VST1d16Qwb_fixed:
3121 case ARM::VST1d32Qwb_fixed:
3122 case ARM::VST1d64Qwb_fixed:
3123 case ARM::VST1d8Qwb_register:
3124 case ARM::VST1d16Qwb_register:
3125 case ARM::VST1d32Qwb_register:
3126 case ARM::VST1d64Qwb_register:
3127 case ARM::VST2d8wb_fixed:
3128 case ARM::VST2d16wb_fixed:
3129 case ARM::VST2d32wb_fixed:
3130 case ARM::VST2d8wb_register:
3131 case ARM::VST2d16wb_register:
3132 case ARM::VST2d32wb_register:
3133 case ARM::VST2q8wb_fixed:
3134 case ARM::VST2q16wb_fixed:
3135 case ARM::VST2q32wb_fixed:
3136 case ARM::VST2q8wb_register:
3137 case ARM::VST2q16wb_register:
3138 case ARM::VST2q32wb_register:
3139 case ARM::VST2b8wb_fixed:
3140 case ARM::VST2b16wb_fixed:
3141 case ARM::VST2b32wb_fixed:
3142 case ARM::VST2b8wb_register:
3143 case ARM::VST2b16wb_register:
3144 case ARM::VST2b32wb_register:
3149 case ARM::VST3d8_UPD:
3150 case ARM::VST3d16_UPD:
3151 case ARM::VST3d32_UPD:
3152 case ARM::VST3q8_UPD:
3153 case ARM::VST3q16_UPD:
3154 case ARM::VST3q32_UPD:
3155 case ARM::VST4d8_UPD:
3156 case ARM::VST4d16_UPD:
3157 case ARM::VST4d32_UPD:
3158 case ARM::VST4q8_UPD:
3159 case ARM::VST4q16_UPD:
3160 case ARM::VST4q32_UPD:
3177 else if (Rm != 0xF) {
3182 case ARM::VST1d8wb_fixed:
3183 case ARM::VST1d16wb_fixed:
3184 case ARM::VST1d32wb_fixed:
3185 case ARM::VST1d64wb_fixed:
3186 case ARM::VST1q8wb_fixed:
3187 case ARM::VST1q16wb_fixed:
3188 case ARM::VST1q32wb_fixed:
3189 case ARM::VST1q64wb_fixed:
3190 case ARM::VST1d8Twb_fixed:
3191 case ARM::VST1d16Twb_fixed:
3192 case ARM::VST1d32Twb_fixed:
3193 case ARM::VST1d64Twb_fixed:
3194 case ARM::VST1d8Qwb_fixed:
3195 case ARM::VST1d16Qwb_fixed:
3196 case ARM::VST1d32Qwb_fixed:
3197 case ARM::VST1d64Qwb_fixed:
3198 case ARM::VST2d8wb_fixed:
3199 case ARM::VST2d16wb_fixed:
3200 case ARM::VST2d32wb_fixed:
3201 case ARM::VST2q8wb_fixed:
3202 case ARM::VST2q16wb_fixed:
3203 case ARM::VST2q32wb_fixed:
3204 case ARM::VST2b8wb_fixed:
3205 case ARM::VST2b16wb_fixed:
3206 case ARM::VST2b32wb_fixed:
3216 case ARM::VST1q16wb_fixed:
3217 case ARM::VST1q16wb_register:
3218 case ARM::VST1q32wb_fixed:
3219 case ARM::VST1q32wb_register:
3220 case ARM::VST1q64wb_fixed:
3221 case ARM::VST1q64wb_register:
3222 case ARM::VST1q8wb_fixed:
3223 case ARM::VST1q8wb_register:
3227 case ARM::VST2d16wb_fixed:
3228 case ARM::VST2d16wb_register:
3229 case ARM::VST2d32wb_fixed:
3230 case ARM::VST2d32wb_register:
3231 case ARM::VST2d8wb_fixed:
3232 case ARM::VST2d8wb_register:
3239 case ARM::VST2b16wb_fixed:
3240 case ARM::VST2b16wb_register:
3241 case ARM::VST2b32wb_fixed:
3242 case ARM::VST2b32wb_register:
3243 case ARM::VST2b8wb_fixed:
3244 case ARM::VST2b8wb_register:
3258 case ARM::VST3d8_UPD:
3259 case ARM::VST3d16_UPD:
3260 case ARM::VST3d32_UPD:
3264 case ARM::VST4d8_UPD:
3265 case ARM::VST4d16_UPD:
3266 case ARM::VST4d32_UPD:
3273 case ARM::VST3q8_UPD:
3274 case ARM::VST3q16_UPD:
3275 case ARM::VST3q32_UPD:
3279 case ARM::VST4q8_UPD:
3280 case ARM::VST4q16_UPD:
3281 case ARM::VST4q32_UPD:
3294 case ARM::VST3d8_UPD:
3295 case ARM::VST3d16_UPD:
3296 case ARM::VST3d32_UPD:
3300 case ARM::VST4d8_UPD:
3301 case ARM::VST4d16_UPD:
3302 case ARM::VST4d32_UPD:
3309 case ARM::VST3q8_UPD:
3310 case ARM::VST3q16_UPD:
3311 case ARM::VST3q32_UPD:
3315 case ARM::VST4q8_UPD:
3316 case ARM::VST4q16_UPD:
3317 case ARM::VST4q32_UPD:
3330 case ARM::VST4d8_UPD:
3331 case ARM::VST4d16_UPD:
3332 case ARM::VST4d32_UPD:
3339 case ARM::VST4q8_UPD:
3340 case ARM::VST4q16_UPD:
3341 case ARM::VST4q32_UPD:
3353 uint64_t Address,
const void *Decoder) {
3356 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3357 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3358 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3359 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3360 unsigned align = fieldFromInstruction(
Insn, 4, 1);
3361 unsigned size = fieldFromInstruction(
Insn, 6, 2);
3368 case ARM::VLD1DUPq16:
case ARM::VLD1DUPq32:
case ARM::VLD1DUPq8:
3369 case ARM::VLD1DUPq16wb_fixed:
case ARM::VLD1DUPq16wb_register:
3370 case ARM::VLD1DUPq32wb_fixed:
case ARM::VLD1DUPq32wb_register:
3371 case ARM::VLD1DUPq8wb_fixed:
case ARM::VLD1DUPq8wb_register:
3392 if (Rm != 0xD && Rm != 0xF &&
3400 uint64_t Address,
const void *Decoder) {
3403 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3404 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3405 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3406 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3407 unsigned align = fieldFromInstruction(
Insn, 4, 1);
3408 unsigned size = 1 << fieldFromInstruction(
Insn, 6, 2);
3412 case ARM::VLD2DUPd16:
case ARM::VLD2DUPd32:
case ARM::VLD2DUPd8:
3413 case ARM::VLD2DUPd16wb_fixed:
case ARM::VLD2DUPd16wb_register:
3414 case ARM::VLD2DUPd32wb_fixed:
case ARM::VLD2DUPd32wb_register:
3415 case ARM::VLD2DUPd8wb_fixed:
case ARM::VLD2DUPd8wb_register:
3419 case ARM::VLD2DUPd16x2:
case ARM::VLD2DUPd32x2:
case ARM::VLD2DUPd8x2:
3420 case ARM::VLD2DUPd16x2wb_fixed:
case ARM::VLD2DUPd16x2wb_register:
3421 case ARM::VLD2DUPd32x2wb_fixed:
case ARM::VLD2DUPd32x2wb_register:
3422 case ARM::VLD2DUPd8x2wb_fixed:
case ARM::VLD2DUPd8x2wb_register:
3439 if (Rm != 0xD && Rm != 0xF) {
3448 uint64_t Address,
const void *Decoder) {
3451 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3452 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3453 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3454 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3455 unsigned inc = fieldFromInstruction(
Insn, 5, 1) + 1;
3474 else if (Rm != 0xF) {
3483 uint64_t Address,
const void *Decoder) {
3486 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3487 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3488 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3489 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3490 unsigned size = fieldFromInstruction(
Insn, 6, 2);
3491 unsigned inc = fieldFromInstruction(
Insn, 5, 1) + 1;
3492 unsigned align = fieldFromInstruction(
Insn, 4, 1);
3526 else if (Rm != 0xF) {
3536 uint64_t Address,
const void *Decoder) {
3539 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3540 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3541 unsigned imm = fieldFromInstruction(
Insn, 0, 4);
3542 imm |= fieldFromInstruction(
Insn, 16, 3) << 4;
3543 imm |= fieldFromInstruction(
Insn, 24, 1) << 7;
3544 imm |= fieldFromInstruction(
Insn, 8, 4) << 8;
3545 imm |= fieldFromInstruction(
Insn, 5, 1) << 12;
3546 unsigned Q = fieldFromInstruction(
Insn, 6, 1);
3559 case ARM::VORRiv4i16:
3560 case ARM::VORRiv2i32:
3561 case ARM::VBICiv4i16:
3562 case ARM::VBICiv2i32:
3566 case ARM::VORRiv8i16:
3567 case ARM::VORRiv4i32:
3568 case ARM::VBICiv8i16:
3569 case ARM::VBICiv4i32:
3582 uint64_t Address,
const void *Decoder) {
3585 unsigned Qd = ((fieldFromInstruction(
Insn, 22, 1) << 3) |
3586 fieldFromInstruction(
Insn, 13, 3));
3587 unsigned cmode = fieldFromInstruction(
Insn, 8, 4);
3588 unsigned imm = fieldFromInstruction(
Insn, 0, 4);
3589 imm |= fieldFromInstruction(
Insn, 16, 3) << 4;
3590 imm |= fieldFromInstruction(
Insn, 28, 1) << 7;
3592 imm |= fieldFromInstruction(
Insn, 5, 1) << 12;
3594 if (cmode == 0xF && Inst.
getOpcode() == ARM::MVE_VMVNimmi32)
3610 uint64_t Address,
const void *Decoder) {
3613 unsigned Qd = fieldFromInstruction(
Insn, 13, 3);
3614 Qd |= fieldFromInstruction(
Insn, 22, 1) << 3;
3619 unsigned Qn = fieldFromInstruction(
Insn, 17, 3);
3620 Qn |= fieldFromInstruction(
Insn, 7, 1) << 3;
3623 unsigned Qm = fieldFromInstruction(
Insn, 1, 3);
3624 Qm |= fieldFromInstruction(
Insn, 5, 1) << 3;
3627 if (!fieldFromInstruction(
Insn, 12, 1))
3635 uint64_t Address,
const void *Decoder) {
3638 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3639 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3640 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3641 Rm |= fieldFromInstruction(
Insn, 5, 1) << 4;
3642 unsigned size = fieldFromInstruction(
Insn, 18, 2);
3654 uint64_t Address,
const void *Decoder) {
3660 uint64_t Address,
const void *Decoder) {
3666 uint64_t Address,
const void *Decoder) {
3672 uint64_t Address,
const void *Decoder) {
3678 uint64_t Address,
const void *Decoder) {
3681 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3682 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3683 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3684 Rn |= fieldFromInstruction(
Insn, 7, 1) << 4;
3685 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3686 Rm |= fieldFromInstruction(
Insn, 5, 1) << 4;
3687 unsigned op = fieldFromInstruction(
Insn, 6, 1);
3714 uint64_t Address,
const void *Decoder) {
3717 unsigned dst = fieldFromInstruction(
Insn, 8, 3);
3718 unsigned imm = fieldFromInstruction(
Insn, 0, 8);
3738 uint64_t Address,
const void *Decoder) {
3740 true, 2, Inst, Decoder))
3746 uint64_t Address,
const void *Decoder) {
3748 true, 4, Inst, Decoder))
3754 uint64_t Address,
const void *Decoder) {
3756 true, 2, Inst, Decoder))
3762 uint64_t Address,
const void *Decoder) {
3765 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3766 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3777 uint64_t Address,
const void *Decoder) {
3780 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3781 unsigned imm = fieldFromInstruction(Val, 3, 5);
3791 uint64_t Address,
const void *Decoder) {
3792 unsigned imm = Val << 2;
3801 uint64_t Address,
const void *Decoder) {
3809 uint64_t Address,
const void *Decoder) {
3812 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3813 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3814 unsigned imm = fieldFromInstruction(Val, 0, 2);
3838 uint64_t Address,
const void *Decoder) {
3841 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
3842 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3845 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3847 bool hasMP = featureBits[ARM::FeatureMP];
3848 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3903 if (!hasV7Ops || !hasMP)
3911 unsigned addrmode = fieldFromInstruction(
Insn, 4, 2);
3912 addrmode |= fieldFromInstruction(
Insn, 0, 4) << 2;
3913 addrmode |= fieldFromInstruction(
Insn, 16, 4) << 6;
3921 uint64_t Address,
const void* Decoder) {
3924 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3925 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
3926 unsigned U = fieldFromInstruction(
Insn, 9, 1);
3927 unsigned imm = fieldFromInstruction(
Insn, 0, 8);
3930 unsigned add = fieldFromInstruction(
Insn, 9, 1);
3933 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3935 bool hasMP = featureBits[ARM::FeatureMP];
3936 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3946 case ARM::t2LDRSBi8:
3952 case ARM::t2LDRSHi8:
3969 case ARM::t2LDRSHi8:
3975 case ARM::t2LDRSBi8:
3991 if (!hasV7Ops || !hasMP)
4005 uint64_t Address,
const void* Decoder) {
4008 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4009 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4010 unsigned imm = fieldFromInstruction(
Insn, 0, 12);
4014 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4016 bool hasMP = featureBits[ARM::FeatureMP];
4017 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4024 case ARM::t2LDRHi12:
4027 case ARM::t2LDRSHi12:
4030 case ARM::t2LDRBi12:
4033 case ARM::t2LDRSBi12:
4050 case ARM::t2LDRSHi12:
4052 case ARM::t2LDRHi12:
4055 case ARM::t2LDRSBi12:
4070 case ARM::t2PLDWi12:
4071 if (!hasV7Ops || !hasMP)
4085 uint64_t Address,
const void* Decoder) {
4088 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4089 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4090 unsigned imm = fieldFromInstruction(
Insn, 0, 8);
4124 uint64_t Address,
const void* Decoder) {
4127 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4128 unsigned U = fieldFromInstruction(
Insn, 23, 1);
4129 int imm = fieldFromInstruction(
Insn, 0, 12);
4132 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4134 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4138 case ARM::t2LDRBpci:
4139 case ARM::t2LDRHpci:
4142 case ARM::t2LDRSBpci:
4145 case ARM::t2LDRSHpci:
4177 uint64_t Address,
const void *Decoder) {
4181 int imm = Val & 0xFF;
4183 if (!(Val & 0x100)) imm *= -1;
4191 const void *Decoder) {
4195 int imm = Val & 0x7F;
4206 uint64_t Address,
const void *Decoder) {
4209 unsigned Rn = fieldFromInstruction(Val, 9, 4);
4210 unsigned imm = fieldFromInstruction(Val, 0, 9);
4222 const void *Decoder) {
4225 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4226 unsigned imm = fieldFromInstruction(Val, 0, 8);
4237 uint64_t Address,
const void *Decoder) {
4240 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4241 unsigned imm = fieldFromInstruction(Val, 0, 8);
4252 uint64_t Address,
const void *Decoder) {
4253 int imm = Val & 0xFF;
4256 else if (!(Val & 0x100))
4265 uint64_t Address,
const void *Decoder) {
4266 int imm = Val & 0x7F;
4269 else if (!(Val & 0x80))
4271 if (imm != INT32_MIN)
4272 imm *= (1U <<
shift);
4279 uint64_t Address,
const void *Decoder) {
4282 unsigned Rn = fieldFromInstruction(Val, 9, 4);
4283 unsigned imm = fieldFromInstruction(Val, 0, 9);
4327 const void *Decoder) {
4330 unsigned Rn = fieldFromInstruction(Val, 8, 3);
4331 unsigned imm = fieldFromInstruction(Val, 0, 8);
4335 if (!
Check(
S, DecodeT2Imm7<shift>(Inst, imm,
Address, Decoder)))
4341 template<
int shift,
int WriteBack>
4344 const void *Decoder) {
4347 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4348 unsigned imm = fieldFromInstruction(Val, 0, 8);
4354 if (!
Check(
S, DecodeT2Imm7<shift>(Inst, imm,
Address, Decoder)))
4361 uint64_t Address,
const void *Decoder) {
4364 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4365 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4366 unsigned addr = fieldFromInstruction(
Insn, 0, 8);
4367 addr |= fieldFromInstruction(
Insn, 9, 1) << 8;
4369 unsigned load = fieldFromInstruction(
Insn, 20, 1);
4373 case ARM::t2LDR_PRE:
4374 case ARM::t2LDR_POST:
4377 case ARM::t2LDRB_PRE:
4378 case ARM::t2LDRB_POST:
4381 case ARM::t2LDRH_PRE:
4382 case ARM::t2LDRH_POST:
4385 case ARM::t2LDRSB_PRE:
4386 case ARM::t2LDRSB_POST:
4392 case ARM::t2LDRSH_PRE:
4393 case ARM::t2LDRSH_POST:
4422 uint64_t Address,
const void *Decoder) {
4425 unsigned Rn = fieldFromInstruction(Val, 13, 4);
4426 unsigned imm = fieldFromInstruction(Val, 0, 12);
4431 case ARM::t2STRBi12:
4432 case ARM::t2STRHi12:
4448 uint64_t Address,
const void *Decoder) {
4449 unsigned imm = fieldFromInstruction(
Insn, 0, 7);
4459 uint64_t Address,
const void *Decoder) {
4463 unsigned Rdm = fieldFromInstruction(
Insn, 0, 3);
4464 Rdm |= fieldFromInstruction(
Insn, 7, 1) << 3;
4471 }
else if (Inst.
getOpcode() == ARM::tADDspr) {
4472 unsigned Rm = fieldFromInstruction(
Insn, 3, 4);
4484 uint64_t Address,
const void *Decoder) {
4485 unsigned imod = fieldFromInstruction(
Insn, 4, 1) | 0x2;
4486 unsigned flags = fieldFromInstruction(
Insn, 0, 3);
4495 uint64_t Address,
const void *Decoder) {
4497 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
4498 unsigned add = fieldFromInstruction(
Insn, 4, 1);
4508 uint64_t Address,
const void *Decoder) {
4510 unsigned Rn = fieldFromInstruction(
Insn, 3, 4);
4511 unsigned Qm = fieldFromInstruction(
Insn, 0, 3);
4523 uint64_t Address,
const void *Decoder) {
4525 unsigned Qm = fieldFromInstruction(
Insn, 8, 3);
4526 int imm = fieldFromInstruction(
Insn, 0, 7);
4531 if(!fieldFromInstruction(
Insn, 7, 1)) {
4537 if (imm != INT32_MIN)
4538 imm *= (1U <<
shift);
4545 uint64_t Address,
const void *Decoder) {
4553 unsigned S = (Val >> 23) & 1;
4554 unsigned J1 = (Val >> 22) & 1;
4555 unsigned J2 = (Val >> 21) & 1;
4556 unsigned I1 = !(J1 ^
S);
4557 unsigned I2 = !(J2 ^
S);
4558 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4559 int imm32 = SignExtend32<25>(
tmp << 1);
4563 true, 4, Inst, Decoder))
4569 uint64_t Address,
const void *Decoder) {
4570 if (Val == 0xA || Val == 0xB)
4574 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4585 uint64_t Address,
const void *Decoder) {
4587 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4590 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4591 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);