LLVM  14.0.0git
ARMDisassembler.cpp
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1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ARMBaseInstrInfo.h"
14 #include "Utils/ARMBaseInfo.h"
15 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/TargetRegistry.h"
23 #include "llvm/Support/Compiler.h"
27 #include <algorithm>
28 #include <cassert>
29 #include <cstdint>
30 #include <vector>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "arm-disassembler"
35 
37 
38 namespace {
39 
40  // Handles the condition code status of instructions in IT blocks
41  class ITStatus
42  {
43  public:
44  // Returns the condition code for instruction in IT block
45  unsigned getITCC() {
46  unsigned CC = ARMCC::AL;
47  if (instrInITBlock())
48  CC = ITStates.back();
49  return CC;
50  }
51 
52  // Advances the IT block state to the next T or E
53  void advanceITState() {
54  ITStates.pop_back();
55  }
56 
57  // Returns true if the current instruction is in an IT block
58  bool instrInITBlock() {
59  return !ITStates.empty();
60  }
61 
62  // Returns true if current instruction is the last instruction in an IT block
63  bool instrLastInITBlock() {
64  return ITStates.size() == 1;
65  }
66 
67  // Called when decoding an IT instruction. Sets the IT state for
68  // the following instructions that for the IT block. Firstcond
69  // corresponds to the field in the IT instruction encoding; Mask
70  // is in the MCOperand format in which 1 means 'else' and 0 'then'.
71  void setITState(char Firstcond, char Mask) {
72  // (3 - the number of trailing zeros) is the number of then / else.
73  unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
74  unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
75  assert(NumTZ <= 3 && "Invalid IT mask!");
76  // push condition codes onto the stack the correct order for the pops
77  for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
78  unsigned Else = (Mask >> Pos) & 1;
79  ITStates.push_back(CCBits ^ Else);
80  }
81  ITStates.push_back(CCBits);
82  }
83 
84  private:
85  std::vector<unsigned char> ITStates;
86  };
87 
88  class VPTStatus
89  {
90  public:
91  unsigned getVPTPred() {
92  unsigned Pred = ARMVCC::None;
93  if (instrInVPTBlock())
94  Pred = VPTStates.back();
95  return Pred;
96  }
97 
98  void advanceVPTState() {
99  VPTStates.pop_back();
100  }
101 
102  bool instrInVPTBlock() {
103  return !VPTStates.empty();
104  }
105 
106  bool instrLastInVPTBlock() {
107  return VPTStates.size() == 1;
108  }
109 
110  void setVPTState(char Mask) {
111  // (3 - the number of trailing zeros) is the number of then / else.
112  unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
113  assert(NumTZ <= 3 && "Invalid VPT mask!");
114  // push predicates onto the stack the correct order for the pops
115  for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
116  bool T = ((Mask >> Pos) & 1) == 0;
117  if (T)
118  VPTStates.push_back(ARMVCC::Then);
119  else
120  VPTStates.push_back(ARMVCC::Else);
121  }
122  VPTStates.push_back(ARMVCC::Then);
123  }
124 
125  private:
127  };
128 
129 /// ARM disassembler for all ARM platforms.
130 class ARMDisassembler : public MCDisassembler {
131 public:
132  ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
133  MCDisassembler(STI, Ctx) {
134  }
135 
136  ~ARMDisassembler() override = default;
137 
138  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
140  raw_ostream &CStream) const override;
141 
142 private:
143  DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size,
145  raw_ostream &CStream) const;
146 
147  DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,
149  raw_ostream &CStream) const;
150 
151  mutable ITStatus ITBlock;
152  mutable VPTStatus VPTBlock;
153 
154  DecodeStatus AddThumbPredicate(MCInst&) const;
155  void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
156 };
157 
158 } // end anonymous namespace
159 
160 static bool Check(DecodeStatus &Out, DecodeStatus In) {
161  switch (In) {
163  // Out stays the same.
164  return true;
166  Out = In;
167  return true;
169  Out = In;
170  return false;
171  }
172  llvm_unreachable("Invalid DecodeStatus!");
173 }
174 
175 // Forward declare these because the autogenerated code will reference them.
176 // Definitions are further down.
177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
178  uint64_t Address, const void *Decoder);
179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
180  uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
182  uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
184  uint64_t Address, const void *Decoder);
185 static DecodeStatus
186 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
187  uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
189  uint64_t Address,
190  const void *Decoder);
191 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
192  uint64_t Address,
193  const void *Decoder);
195  unsigned RegNo, uint64_t Address,
196  const void *Decoder);
198  unsigned RegNo, uint64_t Address,
199  const void *Decoder);
201  MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder);
202 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
203  uint64_t Address, const void *Decoder);
204 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
205  uint64_t Address, const void *Decoder);
206 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
207  uint64_t Address, const void *Decoder);
208 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
209  uint64_t Address, const void *Decoder);
210 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo,
211  uint64_t Address, const void *Decoder);
212 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
213  uint64_t Address,
214  const void *Decoder);
215 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
216  uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
218  uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
220  uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
222  uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
224  uint64_t Address, const void *Decoder);
226  unsigned RegNo,
227  uint64_t Address,
228  const void *Decoder);
229 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
230  uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
232  uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
234  uint64_t Address,
235  const void *Decoder);
236 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
237  uint64_t Address,
238  const void *Decoder);
239 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
240  uint64_t Address, const void *Decoder);
242  unsigned RegNo, uint64_t Address,
243  const void *Decoder);
244 
245 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
246  uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
248  uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
250  uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
252  uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
254  uint64_t Address, const void *Decoder);
255 
256 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
257  uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
259  uint64_t Address, const void *Decoder);
261  unsigned Insn,
262  uint64_t Address,
263  const void *Decoder);
264 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
265  uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
267  uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
269  uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
271  uint64_t Address, const void *Decoder);
272 
274  unsigned Insn,
275  uint64_t Adddress,
276  const void *Decoder);
277 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
278  uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
280  uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
282  uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
284  uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
286  uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
288  uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
290  uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
292  uint64_t Address, const void *Decoder);
294  uint64_t Address,
295  const void *Decoder);
296 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
297  uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
299  uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
301  uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
303  uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
305  uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
307  uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
309  uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
311  uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
313  uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
315  uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
317  uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
319  uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
321  uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
323  uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
325  uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
327  uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
329  uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val,
331  uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val,
333  uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
335  uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
337  uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
339  uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
341  uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
343  uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
345  uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
347  uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
349  uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
351  uint64_t Address, const void *Decoder);
352 template<int shift>
353 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
354  uint64_t Address, const void *Decoder);
355 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
356  uint64_t Address, const void *Decoder);
357 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
358  uint64_t Address, const void *Decoder);
359 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
360  uint64_t Address, const void *Decoder);
361 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
362  uint64_t Address, const void *Decoder);
363 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
364  uint64_t Address, const void *Decoder);
365 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
366  uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
368  uint64_t Address, const void *Decoder);
369 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
370  uint64_t Address, const void *Decoder);
371 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
372  uint64_t Address, const void *Decoder);
373 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
374  uint64_t Address, const void *Decoder);
375 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
376  uint64_t Address, const void *Decoder);
377 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
378  uint64_t Address, const void *Decoder);
379 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
380  uint64_t Address, const void *Decoder);
381 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
382  uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
384  uint64_t Address, const void *Decoder);
385 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
386  uint64_t Address, const void *Decoder);
387 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
388  uint64_t Address, const void *Decoder);
389 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
390  uint64_t Address, const void *Decoder);
391 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
392  uint64_t Address, const void *Decoder);
393 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
394  uint64_t Address, const void *Decoder);
395 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
396  uint64_t Address, const void *Decoder);
397 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
398  uint64_t Address, const void *Decoder);
399 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
400  uint64_t Address, const void *Decoder);
401 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
402  uint64_t Address, const void *Decoder);
403 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
404  uint64_t Address, const void *Decoder);
406  unsigned Val,
407  uint64_t Address,
408  const void *Decoder);
409 
411  uint64_t Address, const void *Decoder);
412 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
413  uint64_t Address, const void *Decoder);
414 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
415  uint64_t Address, const void *Decoder);
416 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
417  uint64_t Address, const void *Decoder);
418 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
419  uint64_t Address, const void *Decoder);
420 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
421  uint64_t Address, const void *Decoder);
422 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
423  uint64_t Address, const void *Decoder);
424 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
425  uint64_t Address, const void *Decoder);
426 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
427  uint64_t Address, const void *Decoder);
428 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
429  uint64_t Address, const void *Decoder);
430 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
431  uint64_t Address, const void* Decoder);
432 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
433  uint64_t Address, const void* Decoder);
434 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
435  uint64_t Address, const void* Decoder);
436 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
437  uint64_t Address, const void* Decoder);
438 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
439  uint64_t Address, const void *Decoder);
440 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val,
441  uint64_t Address, const void *Decoder);
442 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
443  uint64_t Address, const void *Decoder);
444 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
445  uint64_t Address,
446  const void *Decoder);
447 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
448  uint64_t Address, const void *Decoder);
449 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
450  uint64_t Address, const void *Decoder);
451 template<int shift>
452 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
453  uint64_t Address, const void *Decoder);
454 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
455  uint64_t Address, const void *Decoder);
456 template<int shift>
457 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
458  uint64_t Address, const void *Decoder);
459 template<int shift, int WriteBack>
460 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
461  uint64_t Address, const void *Decoder);
463  uint64_t Address, const void *Decoder);
465  uint64_t Address, const void *Decoder);
467  uint64_t Address, const void *Decoder);
468 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
469  uint64_t Address, const void *Decoder);
470 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
471  uint64_t Address, const void *Decoder);
472 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
473  uint64_t Address, const void *Decoder);
474 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
475  uint64_t Address, const void *Decoder);
476 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
477  uint64_t Address, const void *Decoder);
478 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
479  uint64_t Address, const void *Decoder);
480 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
481  uint64_t Address, const void *Decoder);
482 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
483  uint64_t Address, const void *Decoder);
484 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
485  uint64_t Address, const void *Decoder);
486 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
487  uint64_t Address, const void *Decoder);
488 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
489  uint64_t Address, const void *Decoder);
490 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
491  uint64_t Address, const void *Decoder);
492 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
493  uint64_t Address, const void *Decoder);
494 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
495  uint64_t Address, const void *Decoder);
496 
497 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
498  uint64_t Address, const void *Decoder);
499 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
500  uint64_t Address, const void *Decoder);
501 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
502  uint64_t Address, const void *Decoder);
503 
504 template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
505 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
506  uint64_t Address, const void *Decoder);
507 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
508  uint64_t Address,
509  const void *Decoder);
510 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
511  uint64_t Address,
512  const void *Decoder);
513 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
514  const void *Decoder);
515 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
516  uint64_t Address,
517  const void *Decoder);
518 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
519  const void *Decoder);
520 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
521  uint64_t Address, const void *Decoder);
522 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
523  uint64_t Address, const void *Decoder);
524 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val,
525  uint64_t Address,
526  const void *Decoder);
527 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val,
528  uint64_t Address,
529  const void *Decoder);
530 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val,
531  uint64_t Address,
532  const void *Decoder);
534  unsigned Val,
535  uint64_t Address,
536  const void *Decoder);
537 template<bool Writeback>
538 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
539  uint64_t Address,
540  const void *Decoder);
541 template<int shift>
542 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
543  uint64_t Address, const void *Decoder);
544 template<int shift>
545 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
546  uint64_t Address, const void *Decoder);
547 template<int shift>
548 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
549  uint64_t Address, const void *Decoder);
550 template<unsigned MinLog, unsigned MaxLog>
551 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
552  uint64_t Address,
553  const void *Decoder);
554 template<unsigned start>
555 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val,
556  uint64_t Address,
557  const void *Decoder);
558 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
559  uint64_t Address,
560  const void *Decoder);
561 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
562  uint64_t Address,
563  const void *Decoder);
564 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
565  uint64_t Address, const void *Decoder);
566 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
567  uint64_t Address, const void *Decoder);
568 template<bool scalar, OperandDecoder predicate_decoder>
569 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn,
570  uint64_t Address, const void *Decoder);
571 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn,
572  uint64_t Address, const void *Decoder);
573 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
574  uint64_t Address, const void *Decoder);
576  uint64_t Address,
577  const void *Decoder);
578 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
579  uint64_t Address, const void *Decoder);
580 
581 #include "ARMGenDisassemblerTables.inc"
582 
584  const MCSubtargetInfo &STI,
585  MCContext &Ctx) {
586  return new ARMDisassembler(STI, Ctx);
587 }
588 
589 // Post-decoding checks
591  uint64_t Address, raw_ostream &CS,
592  uint32_t Insn,
593  DecodeStatus Result) {
594  switch (MI.getOpcode()) {
595  case ARM::HVC: {
596  // HVC is undefined if condition = 0xf otherwise upredictable
597  // if condition != 0xe
598  uint32_t Cond = (Insn >> 28) & 0xF;
599  if (Cond == 0xF)
600  return MCDisassembler::Fail;
601  if (Cond != 0xE)
603  return Result;
604  }
605  case ARM::t2ADDri:
606  case ARM::t2ADDri12:
607  case ARM::t2ADDrr:
608  case ARM::t2ADDrs:
609  case ARM::t2SUBri:
610  case ARM::t2SUBri12:
611  case ARM::t2SUBrr:
612  case ARM::t2SUBrs:
613  if (MI.getOperand(0).getReg() == ARM::SP &&
614  MI.getOperand(1).getReg() != ARM::SP)
616  return Result;
617  default: return Result;
618  }
619 }
620 
621 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
622  ArrayRef<uint8_t> Bytes,
623  uint64_t Address,
624  raw_ostream &CS) const {
625  if (STI.getFeatureBits()[ARM::ModeThumb])
626  return getThumbInstruction(MI, Size, Bytes, Address, CS);
627  return getARMInstruction(MI, Size, Bytes, Address, CS);
628 }
629 
630 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
631  ArrayRef<uint8_t> Bytes,
632  uint64_t Address,
633  raw_ostream &CS) const {
634  CommentStream = &CS;
635 
636  assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
637  "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
638  "mode!");
639 
640  // We want to read exactly 4 bytes of data.
641  if (Bytes.size() < 4) {
642  Size = 0;
643  return MCDisassembler::Fail;
644  }
645 
646  // Encoded as a small-endian 32-bit word in the stream.
647  uint32_t Insn =
648  (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
649 
650  // Calling the auto-generated decoder function.
652  decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
653  if (Result != MCDisassembler::Fail) {
654  Size = 4;
655  return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
656  }
657 
658  struct DecodeTable {
659  const uint8_t *P;
660  bool DecodePred;
661  };
662 
663  const DecodeTable Tables[] = {
664  {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
665  {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
666  {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
667  {DecoderTablev8Crypto32, false},
668  };
669 
670  for (auto Table : Tables) {
671  Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
672  if (Result != MCDisassembler::Fail) {
673  Size = 4;
674  // Add a fake predicate operand, because we share these instruction
675  // definitions with Thumb2 where these instructions are predicable.
676  if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
677  return MCDisassembler::Fail;
678  return Result;
679  }
680  }
681 
682  Result =
683  decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
684  if (Result != MCDisassembler::Fail) {
685  Size = 4;
686  return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
687  }
688 
689  Size = 4;
690  return MCDisassembler::Fail;
691 }
692 
693 namespace llvm {
694 
695 extern const MCInstrDesc ARMInsts[];
696 
697 } // end namespace llvm
698 
699 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
700 /// immediate Value in the MCInst. The immediate Value has had any PC
701 /// adjustment made by the caller. If the instruction is a branch instruction
702 /// then isBranch is true, else false. If the getOpInfo() function was set as
703 /// part of the setupForSymbolicDisassembly() call then that function is called
704 /// to get any symbolic information at the Address for this instruction. If
705 /// that returns non-zero then the symbolic information it returns is used to
706 /// create an MCExpr and that is added as an operand to the MCInst. If
707 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
708 /// Value is done and if a symbol is found an MCExpr is created with that, else
709 /// an MCExpr with Value is created. This function returns true if it adds an
710 /// operand to the MCInst and false otherwise.
711 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
712  bool isBranch, uint64_t InstSize,
713  MCInst &MI, const void *Decoder) {
714  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
715  // FIXME: Does it make sense for value to be negative?
717  /* Offset */ 0, InstSize);
718 }
719 
720 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
721 /// referenced by a load instruction with the base register that is the Pc.
722 /// These can often be values in a literal pool near the Address of the
723 /// instruction. The Address of the instruction and its immediate Value are
724 /// used as a possible literal pool entry. The SymbolLookUp call back will
725 /// return the name of a symbol referenced by the literal pool's entry if
726 /// the referenced address is that of a symbol. Or it will return a pointer to
727 /// a literal 'C' string if the referenced address of the literal pool's entry
728 /// is an address into a section with 'C' string literals.
730  const void *Decoder) {
731  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
733 }
734 
735 // Thumb1 instructions don't have explicit S bits. Rather, they
736 // implicitly set CPSR. Since it's not represented in the encoding, the
737 // auto-generated decoder won't inject the CPSR operand. We need to fix
738 // that as a post-pass.
739 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
740  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
741  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
742  MCInst::iterator I = MI.begin();
743  for (unsigned i = 0; i < NumOps; ++i, ++I) {
744  if (I == MI.end()) break;
745  if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
746  if (i > 0 && OpInfo[i-1].isPredicate()) continue;
747  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
748  return;
749  }
750  }
751 
752  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
753 }
754 
755 static bool isVectorPredicable(unsigned Opcode) {
756  const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
757  unsigned short NumOps = ARMInsts[Opcode].NumOperands;
758  for (unsigned i = 0; i < NumOps; ++i) {
759  if (ARM::isVpred(OpInfo[i].OperandType))
760  return true;
761  }
762  return false;
763 }
764 
765 // Most Thumb instructions don't have explicit predicates in the
766 // encoding, but rather get their predicates from IT context. We need
767 // to fix up the predicate operands using this context information as a
768 // post-pass.
770 ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
772 
773  const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
774 
775  // A few instructions actually have predicates encoded in them. Don't
776  // try to overwrite it if we're seeing one of those.
777  switch (MI.getOpcode()) {
778  case ARM::tBcc:
779  case ARM::t2Bcc:
780  case ARM::tCBZ:
781  case ARM::tCBNZ:
782  case ARM::tCPS:
783  case ARM::t2CPS3p:
784  case ARM::t2CPS2p:
785  case ARM::t2CPS1p:
786  case ARM::t2CSEL:
787  case ARM::t2CSINC:
788  case ARM::t2CSINV:
789  case ARM::t2CSNEG:
790  case ARM::tMOVSr:
791  case ARM::tSETEND:
792  // Some instructions (mostly conditional branches) are not
793  // allowed in IT blocks.
794  if (ITBlock.instrInITBlock())
795  S = SoftFail;
796  else
797  return Success;
798  break;
799  case ARM::t2HINT:
800  if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
801  S = SoftFail;
802  break;
803  case ARM::tB:
804  case ARM::t2B:
805  case ARM::t2TBB:
806  case ARM::t2TBH:
807  // Some instructions (mostly unconditional branches) can
808  // only appears at the end of, or outside of, an IT.
809  if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
810  S = SoftFail;
811  break;
812  default:
813  break;
814  }
815 
816  // Warn on non-VPT predicable instruction in a VPT block and a VPT
817  // predicable instruction in an IT block
818  if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) ||
819  (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock()))
820  S = SoftFail;
821 
822  // If we're in an IT/VPT block, base the predicate on that. Otherwise,
823  // assume a predicate of AL.
824  unsigned CC = ARMCC::AL;
825  unsigned VCC = ARMVCC::None;
826  if (ITBlock.instrInITBlock()) {
827  CC = ITBlock.getITCC();
828  ITBlock.advanceITState();
829  } else if (VPTBlock.instrInVPTBlock()) {
830  VCC = VPTBlock.getVPTPred();
831  VPTBlock.advanceVPTState();
832  }
833 
834  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
835  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
836 
837  MCInst::iterator CCI = MI.begin();
838  for (unsigned i = 0; i < NumOps; ++i, ++CCI) {
839  if (OpInfo[i].isPredicate() || CCI == MI.end()) break;
840  }
841 
842  if (ARMInsts[MI.getOpcode()].isPredicable()) {
843  CCI = MI.insert(CCI, MCOperand::createImm(CC));
844  ++CCI;
845  if (CC == ARMCC::AL)
846  MI.insert(CCI, MCOperand::createReg(0));
847  else
848  MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
849  } else if (CC != ARMCC::AL) {
850  Check(S, SoftFail);
851  }
852 
853  MCInst::iterator VCCI = MI.begin();
854  unsigned VCCPos;
855  for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
856  if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break;
857  }
858 
859  if (isVectorPredicable(MI.getOpcode())) {
860  VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
861  ++VCCI;
862  if (VCC == ARMVCC::None)
863  VCCI = MI.insert(VCCI, MCOperand::createReg(0));
864  else
865  VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0));
866  ++VCCI;
867  VCCI = MI.insert(VCCI, MCOperand::createReg(0));
868  ++VCCI;
869  if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
870  int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint(
871  VCCPos + 3, MCOI::TIED_TO);
872  assert(TiedOp >= 0 &&
873  "Inactive register in vpred_r is not tied to an output!");
874  // Copy the operand to ensure it's not invalidated when MI grows.
875  MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp)));
876  }
877  } else if (VCC != ARMVCC::None) {
878  Check(S, SoftFail);
879  }
880 
881  return S;
882 }
883 
884 // Thumb VFP instructions are a special case. Because we share their
885 // encodings between ARM and Thumb modes, and they are predicable in ARM
886 // mode, the auto-generated decoder will give them an (incorrect)
887 // predicate operand. We need to rewrite these operands based on the IT
888 // context as a post-pass.
889 void ARMDisassembler::UpdateThumbVFPPredicate(
890  DecodeStatus &S, MCInst &MI) const {
891  unsigned CC;
892  CC = ITBlock.getITCC();
893  if (CC == 0xF)
894  CC = ARMCC::AL;
895  if (ITBlock.instrInITBlock())
896  ITBlock.advanceITState();
897  else if (VPTBlock.instrInVPTBlock()) {
898  CC = VPTBlock.getVPTPred();
899  VPTBlock.advanceVPTState();
900  }
901 
902  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
903  MCInst::iterator I = MI.begin();
904  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
905  for (unsigned i = 0; i < NumOps; ++i, ++I) {
906  if (OpInfo[i].isPredicate() ) {
907  if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
908  Check(S, SoftFail);
909  I->setImm(CC);
910  ++I;
911  if (CC == ARMCC::AL)
912  I->setReg(0);
913  else
914  I->setReg(ARM::CPSR);
915  return;
916  }
917  }
918 }
919 
920 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
921  ArrayRef<uint8_t> Bytes,
922  uint64_t Address,
923  raw_ostream &CS) const {
924  CommentStream = &CS;
925 
926  assert(STI.getFeatureBits()[ARM::ModeThumb] &&
927  "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
928 
929  // We want to read exactly 2 bytes of data.
930  if (Bytes.size() < 2) {
931  Size = 0;
932  return MCDisassembler::Fail;
933  }
934 
935  uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
937  decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
938  if (Result != MCDisassembler::Fail) {
939  Size = 2;
940  Check(Result, AddThumbPredicate(MI));
941  return Result;
942  }
943 
944  Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
945  STI);
946  if (Result) {
947  Size = 2;
948  bool InITBlock = ITBlock.instrInITBlock();
949  Check(Result, AddThumbPredicate(MI));
950  AddThumb1SBit(MI, InITBlock);
951  return Result;
952  }
953 
954  Result =
955  decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
956  if (Result != MCDisassembler::Fail) {
957  Size = 2;
958 
959  // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
960  // the Thumb predicate.
961  if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
963 
964  Check(Result, AddThumbPredicate(MI));
965 
966  // If we find an IT instruction, we need to parse its condition
967  // code and mask operands so that we can apply them correctly
968  // to the subsequent instructions.
969  if (MI.getOpcode() == ARM::t2IT) {
970  unsigned Firstcond = MI.getOperand(0).getImm();
971  unsigned Mask = MI.getOperand(1).getImm();
972  ITBlock.setITState(Firstcond, Mask);
973 
974  // An IT instruction that would give a 'NV' predicate is unpredictable.
975  if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
976  CS << "unpredictable IT predicate sequence";
977  }
978 
979  return Result;
980  }
981 
982  // We want to read exactly 4 bytes of data.
983  if (Bytes.size() < 4) {
984  Size = 0;
985  return MCDisassembler::Fail;
986  }
987 
988  uint32_t Insn32 =
989  (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
990 
991  Result =
992  decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
993  if (Result != MCDisassembler::Fail) {
994  Size = 4;
995 
996  // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
997  // the VPT predicate.
998  if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
1000 
1001  Check(Result, AddThumbPredicate(MI));
1002 
1003  if (isVPTOpcode(MI.getOpcode())) {
1004  unsigned Mask = MI.getOperand(0).getImm();
1005  VPTBlock.setVPTState(Mask);
1006  }
1007 
1008  return Result;
1009  }
1010 
1011  Result =
1012  decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
1013  if (Result != MCDisassembler::Fail) {
1014  Size = 4;
1015  bool InITBlock = ITBlock.instrInITBlock();
1016  Check(Result, AddThumbPredicate(MI));
1017  AddThumb1SBit(MI, InITBlock);
1018  return Result;
1019  }
1020 
1021  Result =
1022  decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
1023  if (Result != MCDisassembler::Fail) {
1024  Size = 4;
1025  Check(Result, AddThumbPredicate(MI));
1026  return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result);
1027  }
1028 
1029  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1030  Result =
1031  decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
1032  if (Result != MCDisassembler::Fail) {
1033  Size = 4;
1034  UpdateThumbVFPPredicate(Result, MI);
1035  return Result;
1036  }
1037  }
1038 
1039  Result =
1040  decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
1041  if (Result != MCDisassembler::Fail) {
1042  Size = 4;
1043  return Result;
1044  }
1045 
1046  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1047  Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
1048  STI);
1049  if (Result != MCDisassembler::Fail) {
1050  Size = 4;
1051  Check(Result, AddThumbPredicate(MI));
1052  return Result;
1053  }
1054  }
1055 
1056  if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
1057  uint32_t NEONLdStInsn = Insn32;
1058  NEONLdStInsn &= 0xF0FFFFFF;
1059  NEONLdStInsn |= 0x04000000;
1060  Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
1061  Address, this, STI);
1062  if (Result != MCDisassembler::Fail) {
1063  Size = 4;
1064  Check(Result, AddThumbPredicate(MI));
1065  return Result;
1066  }
1067  }
1068 
1069  if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
1070  uint32_t NEONDataInsn = Insn32;
1071  NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
1072  NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1073  NEONDataInsn |= 0x12000000; // Set bits 28 and 25
1074  Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
1075  Address, this, STI);
1076  if (Result != MCDisassembler::Fail) {
1077  Size = 4;
1078  Check(Result, AddThumbPredicate(MI));
1079  return Result;
1080  }
1081 
1082  uint32_t NEONCryptoInsn = Insn32;
1083  NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
1084  NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1085  NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
1086  Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
1087  Address, this, STI);
1088  if (Result != MCDisassembler::Fail) {
1089  Size = 4;
1090  return Result;
1091  }
1092 
1093  uint32_t NEONv8Insn = Insn32;
1094  NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
1095  Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
1096  this, STI);
1097  if (Result != MCDisassembler::Fail) {
1098  Size = 4;
1099  return Result;
1100  }
1101  }
1102 
1103  uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
1104  const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)
1105  ? DecoderTableThumb2CDE32
1106  : DecoderTableThumb2CoProc32;
1107  Result =
1108  decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI);
1109  if (Result != MCDisassembler::Fail) {
1110  Size = 4;
1111  Check(Result, AddThumbPredicate(MI));
1112  return Result;
1113  }
1114 
1115  Size = 0;
1116  return MCDisassembler::Fail;
1117 }
1118 
1128 }
1129 
1130 static const uint16_t GPRDecoderTable[] = {
1131  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1132  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1133  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1134  ARM::R12, ARM::SP, ARM::LR, ARM::PC
1135 };
1136 
1137 static const uint16_t CLRMGPRDecoderTable[] = {
1138  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1139  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1140  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1141  ARM::R12, 0, ARM::LR, ARM::APSR
1142 };
1143 
1144 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1145  uint64_t Address, const void *Decoder) {
1146  if (RegNo > 15)
1147  return MCDisassembler::Fail;
1148 
1149  unsigned Register = GPRDecoderTable[RegNo];
1151  return MCDisassembler::Success;
1152 }
1153 
1154 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1155  uint64_t Address,
1156  const void *Decoder) {
1157  if (RegNo > 15)
1158  return MCDisassembler::Fail;
1159 
1160  unsigned Register = CLRMGPRDecoderTable[RegNo];
1161  if (Register == 0)
1162  return MCDisassembler::Fail;
1163 
1165  return MCDisassembler::Success;
1166 }
1167 
1168 static DecodeStatus
1169 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
1170  uint64_t Address, const void *Decoder) {
1172 
1173  if (RegNo == 15)
1175 
1176  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1177 
1178  return S;
1179 }
1180 
1181 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
1182  uint64_t Address,
1183  const void *Decoder) {
1185 
1186  if (RegNo == 13)
1188 
1189  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1190 
1191  return S;
1192 }
1193 
1194 static DecodeStatus
1196  uint64_t Address, const void *Decoder) {
1198 
1199  if (RegNo == 15)
1200  {
1201  Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
1202  return MCDisassembler::Success;
1203  }
1204 
1205  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1206  return S;
1207 }
1208 
1209 static DecodeStatus
1210 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
1211  uint64_t Address, const void *Decoder) {
1213 
1214  if (RegNo == 15)
1215  {
1216  Inst.addOperand(MCOperand::createReg(ARM::ZR));
1217  return MCDisassembler::Success;
1218  }
1219 
1220  if (RegNo == 13)
1222 
1223  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1224  return S;
1225 }
1226 
1227 static DecodeStatus
1229  uint64_t Address, const void *Decoder) {
1231  if (RegNo == 13)
1232  return MCDisassembler::Fail;
1233  Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
1234  return S;
1235 }
1236 
1237 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1238  uint64_t Address, const void *Decoder) {
1239  if (RegNo > 7)
1240  return MCDisassembler::Fail;
1241  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
1242 }
1243 
1244 static const uint16_t GPRPairDecoderTable[] = {
1245  ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1246  ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1247 };
1248 
1249 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
1250  uint64_t Address, const void *Decoder) {
1252 
1253  // According to the Arm ARM RegNo = 14 is undefined, but we return fail
1254  // rather than SoftFail as there is no GPRPair table entry for index 7.
1255  if (RegNo > 13)
1256  return MCDisassembler::Fail;
1257 
1258  if (RegNo & 1)
1260 
1261  unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1262  Inst.addOperand(MCOperand::createReg(RegisterPair));
1263  return S;
1264 }
1265 
1267  uint64_t Address, const void *Decoder) {
1268  if (RegNo > 13)
1269  return MCDisassembler::Fail;
1270 
1271  unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1272  Inst.addOperand(MCOperand::createReg(RegisterPair));
1273 
1274  if ((RegNo & 1) || RegNo > 10)
1275  return MCDisassembler::SoftFail;
1276  return MCDisassembler::Success;
1277 }
1278 
1279 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
1280  uint64_t Address,
1281  const void *Decoder) {
1282  if (RegNo != 13)
1283  return MCDisassembler::Fail;
1284 
1285  unsigned Register = GPRDecoderTable[RegNo];
1287  return MCDisassembler::Success;
1288 }
1289 
1290 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1291  uint64_t Address, const void *Decoder) {
1292  unsigned Register = 0;
1293  switch (RegNo) {
1294  case 0:
1295  Register = ARM::R0;
1296  break;
1297  case 1:
1298  Register = ARM::R1;
1299  break;
1300  case 2:
1301  Register = ARM::R2;
1302  break;
1303  case 3:
1304  Register = ARM::R3;
1305  break;
1306  case 9:
1307  Register = ARM::R9;
1308  break;
1309  case 12:
1310  Register = ARM::R12;
1311  break;
1312  default:
1313  return MCDisassembler::Fail;
1314  }
1315 
1317  return MCDisassembler::Success;
1318 }
1319 
1320 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1321  uint64_t Address, const void *Decoder) {
1323 
1324  const FeatureBitset &featureBits =
1325  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1326 
1327  if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1329 
1330  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1331  return S;
1332 }
1333 
1334 static const uint16_t SPRDecoderTable[] = {
1335  ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1336  ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1337  ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1338  ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1339  ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1340  ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1341  ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1342  ARM::S28, ARM::S29, ARM::S30, ARM::S31
1343 };
1344 
1345 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1346  uint64_t Address, const void *Decoder) {
1347  if (RegNo > 31)
1348  return MCDisassembler::Fail;
1349 
1350  unsigned Register = SPRDecoderTable[RegNo];
1352  return MCDisassembler::Success;
1353 }
1354 
1355 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1356  uint64_t Address, const void *Decoder) {
1357  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1358 }
1359 
1360 static const uint16_t DPRDecoderTable[] = {
1361  ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1362  ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1363  ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1364  ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1365  ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1366  ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1367  ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1368  ARM::D28, ARM::D29, ARM::D30, ARM::D31
1369 };
1370 
1371 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1372  uint64_t Address, const void *Decoder) {
1373  const FeatureBitset &featureBits =
1374  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1375 
1376  bool hasD32 = featureBits[ARM::FeatureD32];
1377 
1378  if (RegNo > 31 || (!hasD32 && RegNo > 15))
1379  return MCDisassembler::Fail;
1380 
1381  unsigned Register = DPRDecoderTable[RegNo];
1383  return MCDisassembler::Success;
1384 }
1385 
1386 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1387  uint64_t Address, const void *Decoder) {
1388  if (RegNo > 7)
1389  return MCDisassembler::Fail;
1390  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1391 }
1392 
1393 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1394  uint64_t Address, const void *Decoder) {
1395  if (RegNo > 15)
1396  return MCDisassembler::Fail;
1397  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1398 }
1399 
1400 static DecodeStatus
1401 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1402  uint64_t Address, const void *Decoder) {
1403  if (RegNo > 15)
1404  return MCDisassembler::Fail;
1405  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1406 }
1407 
1408 static const uint16_t QPRDecoderTable[] = {
1409  ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1410  ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1411  ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1412  ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1413 };
1414 
1415 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1416  uint64_t Address, const void *Decoder) {
1417  if (RegNo > 31 || (RegNo & 1) != 0)
1418  return MCDisassembler::Fail;
1419  RegNo >>= 1;
1420 
1421  unsigned Register = QPRDecoderTable[RegNo];
1423  return MCDisassembler::Success;
1424 }
1425 
1426 static const uint16_t DPairDecoderTable[] = {
1427  ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1428  ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1429  ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1430  ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1431  ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1432  ARM::Q15
1433 };
1434 
1435 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1436  uint64_t Address, const void *Decoder) {
1437  if (RegNo > 30)
1438  return MCDisassembler::Fail;
1439 
1440  unsigned Register = DPairDecoderTable[RegNo];
1442  return MCDisassembler::Success;
1443 }
1444 
1446  ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1447  ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1448  ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1449  ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1450  ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1451  ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1452  ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1453  ARM::D28_D30, ARM::D29_D31
1454 };
1455 
1457  unsigned RegNo,
1458  uint64_t Address,
1459  const void *Decoder) {
1460  if (RegNo > 29)
1461  return MCDisassembler::Fail;
1462 
1463  unsigned Register = DPairSpacedDecoderTable[RegNo];
1465  return MCDisassembler::Success;
1466 }
1467 
1468 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1469  uint64_t Address, const void *Decoder) {
1471  if (Val == 0xF) return MCDisassembler::Fail;
1472  // AL predicate is not allowed on Thumb1 branches.
1473  if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1474  return MCDisassembler::Fail;
1475  if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable())
1477  Inst.addOperand(MCOperand::createImm(Val));
1478  if (Val == ARMCC::AL) {
1480  } else
1481  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1482  return S;
1483 }
1484 
1485 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1486  uint64_t Address, const void *Decoder) {
1487  if (Val)
1488  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1489  else
1491  return MCDisassembler::Success;
1492 }
1493 
1494 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1495  uint64_t Address, const void *Decoder) {
1497 
1498  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1499  unsigned type = fieldFromInstruction(Val, 5, 2);
1500  unsigned imm = fieldFromInstruction(Val, 7, 5);
1501 
1502  // Register-immediate
1503  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1504  return MCDisassembler::Fail;
1505 
1507  switch (type) {
1508  case 0:
1509  Shift = ARM_AM::lsl;
1510  break;
1511  case 1:
1512  Shift = ARM_AM::lsr;
1513  break;
1514  case 2:
1515  Shift = ARM_AM::asr;
1516  break;
1517  case 3:
1518  Shift = ARM_AM::ror;
1519  break;
1520  }
1521 
1522  if (Shift == ARM_AM::ror && imm == 0)
1523  Shift = ARM_AM::rrx;
1524 
1525  unsigned Op = Shift | (imm << 3);
1527 
1528  return S;
1529 }
1530 
1531 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1532  uint64_t Address, const void *Decoder) {
1534 
1535  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1536  unsigned type = fieldFromInstruction(Val, 5, 2);
1537  unsigned Rs = fieldFromInstruction(Val, 8, 4);
1538 
1539  // Register-register
1540  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1541  return MCDisassembler::Fail;
1542  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1543  return MCDisassembler::Fail;
1544 
1546  switch (type) {
1547  case 0:
1548  Shift = ARM_AM::lsl;
1549  break;
1550  case 1:
1551  Shift = ARM_AM::lsr;
1552  break;
1553  case 2:
1554  Shift = ARM_AM::asr;
1555  break;
1556  case 3:
1557  Shift = ARM_AM::ror;
1558  break;
1559  }
1560 
1562 
1563  return S;
1564 }
1565 
1566 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1567  uint64_t Address, const void *Decoder) {
1569 
1570  bool NeedDisjointWriteback = false;
1571  unsigned WritebackReg = 0;
1572  bool CLRM = false;
1573  switch (Inst.getOpcode()) {
1574  default:
1575  break;
1576  case ARM::LDMIA_UPD:
1577  case ARM::LDMDB_UPD:
1578  case ARM::LDMIB_UPD:
1579  case ARM::LDMDA_UPD:
1580  case ARM::t2LDMIA_UPD:
1581  case ARM::t2LDMDB_UPD:
1582  case ARM::t2STMIA_UPD:
1583  case ARM::t2STMDB_UPD:
1584  NeedDisjointWriteback = true;
1585  WritebackReg = Inst.getOperand(0).getReg();
1586  break;
1587  case ARM::t2CLRM:
1588  CLRM = true;
1589  break;
1590  }
1591 
1592  // Empty register lists are not allowed.
1593  if (Val == 0) return MCDisassembler::Fail;
1594  for (unsigned i = 0; i < 16; ++i) {
1595  if (Val & (1 << i)) {
1596  if (CLRM) {
1597  if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
1598  return MCDisassembler::Fail;
1599  }
1600  } else {
1601  if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1602  return MCDisassembler::Fail;
1603  // Writeback not allowed if Rn is in the target list.
1604  if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1606  }
1607  }
1608  }
1609 
1610  return S;
1611 }
1612 
1613 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1614  uint64_t Address, const void *Decoder) {
1616 
1617  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1618  unsigned regs = fieldFromInstruction(Val, 0, 8);
1619 
1620  // In case of unpredictable encoding, tweak the operands.
1621  if (regs == 0 || (Vd + regs) > 32) {
1622  regs = Vd + regs > 32 ? 32 - Vd : regs;
1623  regs = std::max( 1u, regs);
1625  }
1626 
1627  if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1628  return MCDisassembler::Fail;
1629  for (unsigned i = 0; i < (regs - 1); ++i) {
1630  if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1631  return MCDisassembler::Fail;
1632  }
1633 
1634  return S;
1635 }
1636 
1637 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1638  uint64_t Address, const void *Decoder) {
1640 
1641  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1642  unsigned regs = fieldFromInstruction(Val, 1, 7);
1643 
1644  // In case of unpredictable encoding, tweak the operands.
1645  if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1646  regs = Vd + regs > 32 ? 32 - Vd : regs;
1647  regs = std::max( 1u, regs);
1648  regs = std::min(16u, regs);
1650  }
1651 
1652  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1653  return MCDisassembler::Fail;
1654  for (unsigned i = 0; i < (regs - 1); ++i) {
1655  if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1656  return MCDisassembler::Fail;
1657  }
1658 
1659  return S;
1660 }
1661 
1662 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1663  uint64_t Address, const void *Decoder) {
1664  // This operand encodes a mask of contiguous zeros between a specified MSB
1665  // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1666  // the mask of all bits LSB-and-lower, and then xor them to create
1667  // the mask of that's all ones on [msb, lsb]. Finally we not it to
1668  // create the final mask.
1669  unsigned msb = fieldFromInstruction(Val, 5, 5);
1670  unsigned lsb = fieldFromInstruction(Val, 0, 5);
1671 
1673  if (lsb > msb) {
1675  // The check above will cause the warning for the "potentially undefined
1676  // instruction encoding" but we can't build a bad MCOperand value here
1677  // with a lsb > msb or else printing the MCInst will cause a crash.
1678  lsb = msb;
1679  }
1680 
1681  uint32_t msb_mask = 0xFFFFFFFF;
1682  if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1683  uint32_t lsb_mask = (1U << lsb) - 1;
1684 
1685  Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1686  return S;
1687 }
1688 
1690  uint64_t Address, const void *Decoder) {
1692 
1693  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1694  unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1695  unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1696  unsigned imm = fieldFromInstruction(Insn, 0, 8);
1697  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1698  unsigned U = fieldFromInstruction(Insn, 23, 1);
1699  const FeatureBitset &featureBits =
1700  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1701 
1702  switch (Inst.getOpcode()) {
1703  case ARM::LDC_OFFSET:
1704  case ARM::LDC_PRE:
1705  case ARM::LDC_POST:
1706  case ARM::LDC_OPTION:
1707  case ARM::LDCL_OFFSET:
1708  case ARM::LDCL_PRE:
1709  case ARM::LDCL_POST:
1710  case ARM::LDCL_OPTION:
1711  case ARM::STC_OFFSET:
1712  case ARM::STC_PRE:
1713  case ARM::STC_POST:
1714  case ARM::STC_OPTION:
1715  case ARM::STCL_OFFSET:
1716  case ARM::STCL_PRE:
1717  case ARM::STCL_POST:
1718  case ARM::STCL_OPTION:
1719  case ARM::t2LDC_OFFSET:
1720  case ARM::t2LDC_PRE:
1721  case ARM::t2LDC_POST:
1722  case ARM::t2LDC_OPTION:
1723  case ARM::t2LDCL_OFFSET:
1724  case ARM::t2LDCL_PRE:
1725  case ARM::t2LDCL_POST:
1726  case ARM::t2LDCL_OPTION:
1727  case ARM::t2STC_OFFSET:
1728  case ARM::t2STC_PRE:
1729  case ARM::t2STC_POST:
1730  case ARM::t2STC_OPTION:
1731  case ARM::t2STCL_OFFSET:
1732  case ARM::t2STCL_PRE:
1733  case ARM::t2STCL_POST:
1734  case ARM::t2STCL_OPTION:
1735  case ARM::t2LDC2_OFFSET:
1736  case ARM::t2LDC2L_OFFSET:
1737  case ARM::t2LDC2_PRE:
1738  case ARM::t2LDC2L_PRE:
1739  case ARM::t2STC2_OFFSET:
1740  case ARM::t2STC2L_OFFSET:
1741  case ARM::t2STC2_PRE:
1742  case ARM::t2STC2L_PRE:
1743  case ARM::LDC2_OFFSET:
1744  case ARM::LDC2L_OFFSET:
1745  case ARM::LDC2_PRE:
1746  case ARM::LDC2L_PRE:
1747  case ARM::STC2_OFFSET:
1748  case ARM::STC2L_OFFSET:
1749  case ARM::STC2_PRE:
1750  case ARM::STC2L_PRE:
1751  case ARM::t2LDC2_OPTION:
1752  case ARM::t2STC2_OPTION:
1753  case ARM::t2LDC2_POST:
1754  case ARM::t2LDC2L_POST:
1755  case ARM::t2STC2_POST:
1756  case ARM::t2STC2L_POST:
1757  case ARM::LDC2_POST:
1758  case ARM::LDC2L_POST:
1759  case ARM::STC2_POST:
1760  case ARM::STC2L_POST:
1761  if (coproc == 0xA || coproc == 0xB ||
1762  (featureBits[ARM::HasV8_1MMainlineOps] &&
1763  (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1764  coproc == 0xE || coproc == 0xF)))
1765  return MCDisassembler::Fail;
1766  break;
1767  default:
1768  break;
1769  }
1770 
1771  if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1772  return MCDisassembler::Fail;
1773 
1774  Inst.addOperand(MCOperand::createImm(coproc));
1775  Inst.addOperand(MCOperand::createImm(CRd));
1776  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1777  return MCDisassembler::Fail;
1778 
1779  switch (Inst.getOpcode()) {
1780  case ARM::t2LDC2_OFFSET:
1781  case ARM::t2LDC2L_OFFSET:
1782  case ARM::t2LDC2_PRE:
1783  case ARM::t2LDC2L_PRE:
1784  case ARM::t2STC2_OFFSET:
1785  case ARM::t2STC2L_OFFSET:
1786  case ARM::t2STC2_PRE:
1787  case ARM::t2STC2L_PRE:
1788  case ARM::LDC2_OFFSET:
1789  case ARM::LDC2L_OFFSET:
1790  case ARM::LDC2_PRE:
1791  case ARM::LDC2L_PRE:
1792  case ARM::STC2_OFFSET:
1793  case ARM::STC2L_OFFSET:
1794  case ARM::STC2_PRE:
1795  case ARM::STC2L_PRE:
1796  case ARM::t2LDC_OFFSET:
1797  case ARM::t2LDCL_OFFSET:
1798  case ARM::t2LDC_PRE:
1799  case ARM::t2LDCL_PRE:
1800  case ARM::t2STC_OFFSET:
1801  case ARM::t2STCL_OFFSET:
1802  case ARM::t2STC_PRE:
1803  case ARM::t2STCL_PRE:
1804  case ARM::LDC_OFFSET:
1805  case ARM::LDCL_OFFSET:
1806  case ARM::LDC_PRE:
1807  case ARM::LDCL_PRE:
1808  case ARM::STC_OFFSET:
1809  case ARM::STCL_OFFSET:
1810  case ARM::STC_PRE:
1811  case ARM::STCL_PRE:
1812  imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1813  Inst.addOperand(MCOperand::createImm(imm));
1814  break;
1815  case ARM::t2LDC2_POST:
1816  case ARM::t2LDC2L_POST:
1817  case ARM::t2STC2_POST:
1818  case ARM::t2STC2L_POST:
1819  case ARM::LDC2_POST:
1820  case ARM::LDC2L_POST:
1821  case ARM::STC2_POST:
1822  case ARM::STC2L_POST:
1823  case ARM::t2LDC_POST:
1824  case ARM::t2LDCL_POST:
1825  case ARM::t2STC_POST:
1826  case ARM::t2STCL_POST:
1827  case ARM::LDC_POST:
1828  case ARM::LDCL_POST:
1829  case ARM::STC_POST:
1830  case ARM::STCL_POST:
1831  imm |= U << 8;
1833  default:
1834  // The 'option' variant doesn't encode 'U' in the immediate since
1835  // the immediate is unsigned [0,255].
1836  Inst.addOperand(MCOperand::createImm(imm));
1837  break;
1838  }
1839 
1840  switch (Inst.getOpcode()) {
1841  case ARM::LDC_OFFSET:
1842  case ARM::LDC_PRE:
1843  case ARM::LDC_POST:
1844  case ARM::LDC_OPTION:
1845  case ARM::LDCL_OFFSET:
1846  case ARM::LDCL_PRE:
1847  case ARM::LDCL_POST:
1848  case ARM::LDCL_OPTION:
1849  case ARM::STC_OFFSET:
1850  case ARM::STC_PRE:
1851  case ARM::STC_POST:
1852  case ARM::STC_OPTION:
1853  case ARM::STCL_OFFSET:
1854  case ARM::STCL_PRE:
1855  case ARM::STCL_POST:
1856  case ARM::STCL_OPTION:
1857  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1858  return MCDisassembler::Fail;
1859  break;
1860  default:
1861  break;
1862  }
1863 
1864  return S;
1865 }
1866 
1867 static DecodeStatus
1869  uint64_t Address, const void *Decoder) {
1871 
1872  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1873  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1874  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1875  unsigned imm = fieldFromInstruction(Insn, 0, 12);
1876  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1877  unsigned reg = fieldFromInstruction(Insn, 25, 1);
1878  unsigned P = fieldFromInstruction(Insn, 24, 1);
1879  unsigned W = fieldFromInstruction(Insn, 21, 1);
1880 
1881  // On stores, the writeback operand precedes Rt.
1882  switch (Inst.getOpcode()) {
1883  case ARM::STR_POST_IMM:
1884  case ARM::STR_POST_REG:
1885  case ARM::STRB_POST_IMM:
1886  case ARM::STRB_POST_REG:
1887  case ARM::STRT_POST_REG:
1888  case ARM::STRT_POST_IMM:
1889  case ARM::STRBT_POST_REG:
1890  case ARM::STRBT_POST_IMM:
1891  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1892  return MCDisassembler::Fail;
1893  break;
1894  default:
1895  break;
1896  }
1897 
1898  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1899  return MCDisassembler::Fail;
1900 
1901  // On loads, the writeback operand comes after Rt.
1902  switch (Inst.getOpcode()) {
1903  case ARM::LDR_POST_IMM:
1904  case ARM::LDR_POST_REG:
1905  case ARM::LDRB_POST_IMM:
1906  case ARM::LDRB_POST_REG:
1907  case ARM::LDRBT_POST_REG:
1908  case ARM::LDRBT_POST_IMM:
1909  case ARM::LDRT_POST_REG:
1910  case ARM::LDRT_POST_IMM:
1911  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1912  return MCDisassembler::Fail;
1913  break;
1914  default:
1915  break;
1916  }
1917 
1918  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1919  return MCDisassembler::Fail;
1920 
1922  if (!fieldFromInstruction(Insn, 23, 1))
1923  Op = ARM_AM::sub;
1924 
1925  bool writeback = (P == 0) || (W == 1);
1926  unsigned idx_mode = 0;
1927  if (P && writeback)
1928  idx_mode = ARMII::IndexModePre;
1929  else if (!P && writeback)
1930  idx_mode = ARMII::IndexModePost;
1931 
1932  if (writeback && (Rn == 15 || Rn == Rt))
1933  S = MCDisassembler::SoftFail; // UNPREDICTABLE
1934 
1935  if (reg) {
1936  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1937  return MCDisassembler::Fail;
1939  switch( fieldFromInstruction(Insn, 5, 2)) {
1940  case 0:
1941  Opc = ARM_AM::lsl;
1942  break;
1943  case 1:
1944  Opc = ARM_AM::lsr;
1945  break;
1946  case 2:
1947  Opc = ARM_AM::asr;
1948  break;
1949  case 3:
1950  Opc = ARM_AM::ror;
1951  break;
1952  default:
1953  return MCDisassembler::Fail;
1954  }
1955  unsigned amt = fieldFromInstruction(Insn, 7, 5);
1956  if (Opc == ARM_AM::ror && amt == 0)
1957  Opc = ARM_AM::rrx;
1958  unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1959 
1960  Inst.addOperand(MCOperand::createImm(imm));
1961  } else {
1963  unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1965  }
1966 
1967  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1968  return MCDisassembler::Fail;
1969 
1970  return S;
1971 }
1972 
1973 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1974  uint64_t Address, const void *Decoder) {
1976 
1977  unsigned Rn = fieldFromInstruction(Val, 13, 4);
1978  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1979  unsigned type = fieldFromInstruction(Val, 5, 2);
1980  unsigned imm = fieldFromInstruction(Val, 7, 5);
1981  unsigned U = fieldFromInstruction(Val, 12, 1);
1982 
1984  switch (type) {
1985  case 0:
1986  ShOp = ARM_AM::lsl;
1987  break;
1988  case 1:
1989  ShOp = ARM_AM::lsr;
1990  break;
1991  case 2:
1992  ShOp = ARM_AM::asr;
1993  break;
1994  case 3:
1995  ShOp = ARM_AM::ror;
1996  break;
1997  }
1998 
1999  if (ShOp == ARM_AM::ror && imm == 0)
2000  ShOp = ARM_AM::rrx;
2001 
2002  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2003  return MCDisassembler::Fail;
2004  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2005  return MCDisassembler::Fail;
2006  unsigned shift;
2007  if (U)
2008  shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
2009  else
2010  shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
2012 
2013  return S;
2014 }
2015 
2016 static DecodeStatus
2018  uint64_t Address, const void *Decoder) {
2020 
2021  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
2022  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2023  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2024  unsigned type = fieldFromInstruction(Insn, 22, 1);
2025  unsigned imm = fieldFromInstruction(Insn, 8, 4);
2026  unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
2027  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2028  unsigned W = fieldFromInstruction(Insn, 21, 1);
2029  unsigned P = fieldFromInstruction(Insn, 24, 1);
2030  unsigned Rt2 = Rt + 1;
2031 
2032  bool writeback = (W == 1) | (P == 0);
2033 
2034  // For {LD,ST}RD, Rt must be even, else undefined.
2035  switch (Inst.getOpcode()) {
2036  case ARM::STRD:
2037  case ARM::STRD_PRE:
2038  case ARM::STRD_POST:
2039  case ARM::LDRD:
2040  case ARM::LDRD_PRE:
2041  case ARM::LDRD_POST:
2042  if (Rt & 0x1) S = MCDisassembler::SoftFail;
2043  break;
2044  default:
2045  break;
2046  }
2047  switch (Inst.getOpcode()) {
2048  case ARM::STRD:
2049  case ARM::STRD_PRE:
2050  case ARM::STRD_POST:
2051  if (P == 0 && W == 1)
2053 
2054  if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2056  if (type && Rm == 15)
2058  if (Rt2 == 15)
2060  if (!type && fieldFromInstruction(Insn, 8, 4))
2062  break;
2063  case ARM::STRH:
2064  case ARM::STRH_PRE:
2065  case ARM::STRH_POST:
2066  if (Rt == 15)
2068  if (writeback && (Rn == 15 || Rn == Rt))
2070  if (!type && Rm == 15)
2072  break;
2073  case ARM::LDRD:
2074  case ARM::LDRD_PRE:
2075  case ARM::LDRD_POST:
2076  if (type && Rn == 15) {
2077  if (Rt2 == 15)
2079  break;
2080  }
2081  if (P == 0 && W == 1)
2083  if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2085  if (!type && writeback && Rn == 15)
2087  if (writeback && (Rn == Rt || Rn == Rt2))
2089  break;
2090  case ARM::LDRH:
2091  case ARM::LDRH_PRE:
2092  case ARM::LDRH_POST:
2093  if (type && Rn == 15) {
2094  if (Rt == 15)
2096  break;
2097  }
2098  if (Rt == 15)
2100  if (!type && Rm == 15)
2102  if (!type && writeback && (Rn == 15 || Rn == Rt))
2104  break;
2105  case ARM::LDRSH:
2106  case ARM::LDRSH_PRE:
2107  case ARM::LDRSH_POST:
2108  case ARM::LDRSB:
2109  case ARM::LDRSB_PRE:
2110  case ARM::LDRSB_POST:
2111  if (type && Rn == 15) {
2112  if (Rt == 15)
2114  break;
2115  }
2116  if (type && (Rt == 15 || (writeback && Rn == Rt)))
2118  if (!type && (Rt == 15 || Rm == 15))
2120  if (!type && writeback && (Rn == 15 || Rn == Rt))
2122  break;
2123  default:
2124  break;
2125  }
2126 
2127  if (writeback) { // Writeback
2128  if (P)
2129  U |= ARMII::IndexModePre << 9;
2130  else
2131  U |= ARMII::IndexModePost << 9;
2132 
2133  // On stores, the writeback operand precedes Rt.
2134  switch (Inst.getOpcode()) {
2135  case ARM::STRD:
2136  case ARM::STRD_PRE:
2137  case ARM::STRD_POST:
2138  case ARM::STRH:
2139  case ARM::STRH_PRE:
2140  case ARM::STRH_POST:
2141  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2142  return MCDisassembler::Fail;
2143  break;
2144  default:
2145  break;
2146  }
2147  }
2148 
2149  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2150  return MCDisassembler::Fail;
2151  switch (Inst.getOpcode()) {
2152  case ARM::STRD:
2153  case ARM::STRD_PRE:
2154  case ARM::STRD_POST:
2155  case ARM::LDRD:
2156  case ARM::LDRD_PRE:
2157  case ARM::LDRD_POST:
2158  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2159  return MCDisassembler::Fail;
2160  break;
2161  default:
2162  break;
2163  }
2164 
2165  if (writeback) {
2166  // On loads, the writeback operand comes after Rt.
2167  switch (Inst.getOpcode()) {
2168  case ARM::LDRD:
2169  case ARM::LDRD_PRE:
2170  case ARM::LDRD_POST:
2171  case ARM::LDRH:
2172  case ARM::LDRH_PRE:
2173  case ARM::LDRH_POST:
2174  case ARM::LDRSH:
2175  case ARM::LDRSH_PRE:
2176  case ARM::LDRSH_POST:
2177  case ARM::LDRSB:
2178  case ARM::LDRSB_PRE:
2179  case ARM::LDRSB_POST:
2180  case ARM::LDRHTr:
2181  case ARM::LDRSBTr:
2182  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2183  return MCDisassembler::Fail;
2184  break;
2185  default:
2186  break;
2187  }
2188  }
2189 
2190  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2191  return MCDisassembler::Fail;
2192 
2193  if (type) {
2195  Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2196  } else {
2197  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2198  return MCDisassembler::Fail;
2200  }
2201 
2202  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2203  return MCDisassembler::Fail;
2204 
2205  return S;
2206 }
2207 
2209  uint64_t Address, const void *Decoder) {
2211 
2212  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2213  unsigned mode = fieldFromInstruction(Insn, 23, 2);
2214 
2215  switch (mode) {
2216  case 0:
2217  mode = ARM_AM::da;
2218  break;
2219  case 1:
2220  mode = ARM_AM::ia;
2221  break;
2222  case 2:
2223  mode = ARM_AM::db;
2224  break;
2225  case 3:
2226  mode = ARM_AM::ib;
2227  break;
2228  }
2229 
2231  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2232  return MCDisassembler::Fail;
2233 
2234  return S;
2235 }
2236 
2238  uint64_t Address, const void *Decoder) {
2240 
2241  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2242  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2243  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2244  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2245 
2246  if (pred == 0xF)
2247  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2248 
2249  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2250  return MCDisassembler::Fail;
2251  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2252  return MCDisassembler::Fail;
2253  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2254  return MCDisassembler::Fail;
2255  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2256  return MCDisassembler::Fail;
2257  return S;
2258 }
2259 
2261  unsigned Insn,
2262  uint64_t Address, const void *Decoder) {
2264 
2265  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2266  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2267  unsigned reglist = fieldFromInstruction(Insn, 0, 16);
2268 
2269  if (pred == 0xF) {
2270  // Ambiguous with RFE and SRS
2271  switch (Inst.getOpcode()) {
2272  case ARM::LDMDA:
2273  Inst.setOpcode(ARM::RFEDA);
2274  break;
2275  case ARM::LDMDA_UPD:
2276  Inst.setOpcode(ARM::RFEDA_UPD);
2277  break;
2278  case ARM::LDMDB:
2279  Inst.setOpcode(ARM::RFEDB);
2280  break;
2281  case ARM::LDMDB_UPD:
2282  Inst.setOpcode(ARM::RFEDB_UPD);
2283  break;
2284  case ARM::LDMIA:
2285  Inst.setOpcode(ARM::RFEIA);
2286  break;
2287  case ARM::LDMIA_UPD:
2288  Inst.setOpcode(ARM::RFEIA_UPD);
2289  break;
2290  case ARM::LDMIB:
2291  Inst.setOpcode(ARM::RFEIB);
2292  break;
2293  case ARM::LDMIB_UPD:
2294  Inst.setOpcode(ARM::RFEIB_UPD);
2295  break;
2296  case ARM::STMDA:
2297  Inst.setOpcode(ARM::SRSDA);
2298  break;
2299  case ARM::STMDA_UPD:
2300  Inst.setOpcode(ARM::SRSDA_UPD);
2301  break;
2302  case ARM::STMDB:
2303  Inst.setOpcode(ARM::SRSDB);
2304  break;
2305  case ARM::STMDB_UPD:
2306  Inst.setOpcode(ARM::SRSDB_UPD);
2307  break;
2308  case ARM::STMIA:
2309  Inst.setOpcode(ARM::SRSIA);
2310  break;
2311  case ARM::STMIA_UPD:
2312  Inst.setOpcode(ARM::SRSIA_UPD);
2313  break;
2314  case ARM::STMIB:
2315  Inst.setOpcode(ARM::SRSIB);
2316  break;
2317  case ARM::STMIB_UPD:
2318  Inst.setOpcode(ARM::SRSIB_UPD);
2319  break;
2320  default:
2321  return MCDisassembler::Fail;
2322  }
2323 
2324  // For stores (which become SRS's, the only operand is the mode.
2325  if (fieldFromInstruction(Insn, 20, 1) == 0) {
2326  // Check SRS encoding constraints
2327  if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
2328  fieldFromInstruction(Insn, 20, 1) == 0))
2329  return MCDisassembler::Fail;
2330 
2331  Inst.addOperand(
2332  MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
2333  return S;
2334  }
2335 
2336  return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
2337  }
2338 
2339  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2340  return MCDisassembler::Fail;
2341  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2342  return MCDisassembler::Fail; // Tied
2343  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2344  return MCDisassembler::Fail;
2345  if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
2346  return MCDisassembler::Fail;
2347 
2348  return S;
2349 }
2350 
2351 // Check for UNPREDICTABLE predicated ESB instruction
2353  uint64_t Address, const void *Decoder) {
2354  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2355  unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
2356  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2357  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2358 
2360 
2361  Inst.addOperand(MCOperand::createImm(imm8));
2362 
2363  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2364  return MCDisassembler::Fail;
2365 
2366  // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
2367  // so all predicates should be allowed.
2368  if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2370 
2371  return S;
2372 }
2373 
2375  uint64_t Address, const void *Decoder) {
2376  unsigned imod = fieldFromInstruction(Insn, 18, 2);
2377  unsigned M = fieldFromInstruction(Insn, 17, 1);
2378  unsigned iflags = fieldFromInstruction(Insn, 6, 3);
2379  unsigned mode = fieldFromInstruction(Insn, 0, 5);
2380 
2382 
2383  // This decoder is called from multiple location that do not check
2384  // the full encoding is valid before they do.
2385  if (fieldFromInstruction(Insn, 5, 1) != 0 ||
2386  fieldFromInstruction(Insn, 16, 1) != 0 ||
2387  fieldFromInstruction(Insn, 20, 8) != 0x10)
2388  return MCDisassembler::Fail;
2389 
2390  // imod == '01' --> UNPREDICTABLE
2391  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2392  // return failure here. The '01' imod value is unprintable, so there's
2393  // nothing useful we could do even if we returned UNPREDICTABLE.
2394 
2395  if (imod == 1) return MCDisassembler::Fail;
2396 
2397  if (imod && M) {
2398  Inst.setOpcode(ARM::CPS3p);
2399  Inst.addOperand(MCOperand::createImm(imod));
2400  Inst.addOperand(MCOperand::createImm(iflags));
2402  } else if (imod && !M) {
2403  Inst.setOpcode(ARM::CPS2p);
2404  Inst.addOperand(MCOperand::createImm(imod));
2405  Inst.addOperand(MCOperand::createImm(iflags));
2407  } else if (!imod && M) {
2408  Inst.setOpcode(ARM::CPS1p);
2410  if (iflags) S = MCDisassembler::SoftFail;
2411  } else {
2412  // imod == '00' && M == '0' --> UNPREDICTABLE
2413  Inst.setOpcode(ARM::CPS1p);
2416  }
2417 
2418  return S;
2419 }
2420 
2422  uint64_t Address, const void *Decoder) {
2423  unsigned imod = fieldFromInstruction(Insn, 9, 2);
2424  unsigned M = fieldFromInstruction(Insn, 8, 1);
2425  unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2426  unsigned mode = fieldFromInstruction(Insn, 0, 5);
2427 
2429 
2430  // imod == '01' --> UNPREDICTABLE
2431  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2432  // return failure here. The '01' imod value is unprintable, so there's
2433  // nothing useful we could do even if we returned UNPREDICTABLE.
2434 
2435  if (imod == 1) return MCDisassembler::Fail;
2436 
2437  if (imod && M) {
2438  Inst.setOpcode(ARM::t2CPS3p);
2439  Inst.addOperand(MCOperand::createImm(imod));
2440  Inst.addOperand(MCOperand::createImm(iflags));
2442  } else if (imod && !M) {
2443  Inst.setOpcode(ARM::t2CPS2p);
2444  Inst.addOperand(MCOperand::createImm(imod));
2445  Inst.addOperand(MCOperand::createImm(iflags));
2447  } else if (!imod && M) {
2448  Inst.setOpcode(ARM::t2CPS1p);
2450  if (iflags) S = MCDisassembler::SoftFail;
2451  } else {
2452  // imod == '00' && M == '0' --> this is a HINT instruction
2453  int imm = fieldFromInstruction(Insn, 0, 8);
2454  // HINT are defined only for immediate in [0..4]
2455  if(imm > 4) return MCDisassembler::Fail;
2456  Inst.setOpcode(ARM::t2HINT);
2457  Inst.addOperand(MCOperand::createImm(imm));
2458  }
2459 
2460  return S;
2461 }
2462 
2464  uint64_t Address,
2465  const void *Decoder) {
2466  unsigned imm = fieldFromInstruction(Insn, 0, 8);
2467 
2468  unsigned Opcode = ARM::t2HINT;
2469 
2470  if (imm == 0x0D) {
2471  Opcode = ARM::t2PACBTI;
2472  } else if (imm == 0x1D) {
2473  Opcode = ARM::t2PAC;
2474  } else if (imm == 0x2D) {
2475  Opcode = ARM::t2AUT;
2476  } else if (imm == 0x0F) {
2477  Opcode = ARM::t2BTI;
2478  }
2479 
2480  Inst.setOpcode(Opcode);
2481  if (Opcode == ARM::t2HINT) {
2482  Inst.addOperand(MCOperand::createImm(imm));
2483  }
2484 
2485  return MCDisassembler::Success;
2486 }
2487 
2489  uint64_t Address, const void *Decoder) {
2491 
2492  unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2493  unsigned imm = 0;
2494 
2495  imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2496  imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2497  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2498  imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2499 
2500  if (Inst.getOpcode() == ARM::t2MOVTi16)
2501  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2502  return MCDisassembler::Fail;
2503  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2504  return MCDisassembler::Fail;
2505 
2506  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2507  Inst.addOperand(MCOperand::createImm(imm));
2508 
2509  return S;
2510 }
2511 
2513  uint64_t Address, const void *Decoder) {
2515 
2516  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2517  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2518  unsigned imm = 0;
2519 
2520  imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2521  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2522 
2523  if (Inst.getOpcode() == ARM::MOVTi16)
2524  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2525  return MCDisassembler::Fail;
2526 
2527  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2528  return MCDisassembler::Fail;
2529 
2530  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2531  Inst.addOperand(MCOperand::createImm(imm));
2532 
2533  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2534  return MCDisassembler::Fail;
2535 
2536  return S;
2537 }
2538 
2540  uint64_t Address, const void *Decoder) {
2542 
2543  unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2544  unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2545  unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2546  unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2547  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2548 
2549  if (pred == 0xF)
2550  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2551 
2552  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2553  return MCDisassembler::Fail;
2554  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2555  return MCDisassembler::Fail;
2556  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2557  return MCDisassembler::Fail;
2558  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2559  return MCDisassembler::Fail;
2560 
2561  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2562  return MCDisassembler::Fail;
2563 
2564  return S;
2565 }
2566 
2568  uint64_t Address, const void *Decoder) {
2570 
2571  unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2572  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2573  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2574 
2575  if (Pred == 0xF)
2576  return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2577 
2578  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2579  return MCDisassembler::Fail;
2580  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2581  return MCDisassembler::Fail;
2582  if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2583  return MCDisassembler::Fail;
2584 
2585  return S;
2586 }
2587 
2589  uint64_t Address, const void *Decoder) {
2591 
2592  unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2593 
2594  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2595  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2596 
2597  if (!FeatureBits[ARM::HasV8_1aOps] ||
2598  !FeatureBits[ARM::HasV8Ops])
2599  return MCDisassembler::Fail;
2600 
2601  // Decoder can be called from DecodeTST, which does not check the full
2602  // encoding is valid.
2603  if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2604  fieldFromInstruction(Insn, 4,4) != 0)
2605  return MCDisassembler::Fail;
2606  if (fieldFromInstruction(Insn, 10,10) != 0 ||
2607  fieldFromInstruction(Insn, 0,4) != 0)
2609 
2610  Inst.setOpcode(ARM::SETPAN);
2611  Inst.addOperand(MCOperand::createImm(Imm));
2612 
2613  return S;
2614 }
2615 
2617  uint64_t Address, const void *Decoder) {
2619 
2620  unsigned add = fieldFromInstruction(Val, 12, 1);
2621  unsigned imm = fieldFromInstruction(Val, 0, 12);
2622  unsigned Rn = fieldFromInstruction(Val, 13, 4);
2623 
2624  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2625  return MCDisassembler::Fail;
2626 
2627  if (!add) imm *= -1;
2628  if (imm == 0 && !add) imm = INT32_MIN;
2629  Inst.addOperand(MCOperand::createImm(imm));
2630  if (Rn == 15)
2631  tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2632 
2633  return S;
2634 }
2635 
2636 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2637  uint64_t Address, const void *Decoder) {
2639 
2640  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2641  // U == 1 to add imm, 0 to subtract it.
2642  unsigned U = fieldFromInstruction(Val, 8, 1);
2643  unsigned imm = fieldFromInstruction(Val, 0, 8);
2644 
2645  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2646  return MCDisassembler::Fail;
2647 
2648  if (U)
2650  else
2652 
2653  return S;
2654 }
2655 
2657  uint64_t Address, const void *Decoder) {
2659 
2660  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2661  // U == 1 to add imm, 0 to subtract it.
2662  unsigned U = fieldFromInstruction(Val, 8, 1);
2663  unsigned imm = fieldFromInstruction(Val, 0, 8);
2664 
2665  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2666  return MCDisassembler::Fail;
2667 
2668  if (U)
2670  else
2672 
2673  return S;
2674 }
2675 
2676 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2677  uint64_t Address, const void *Decoder) {
2678  return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2679 }
2680 
2681 static DecodeStatus
2683  uint64_t Address, const void *Decoder) {
2685 
2686  // Note the J1 and J2 values are from the encoded instruction. So here
2687  // change them to I1 and I2 values via as documented:
2688  // I1 = NOT(J1 EOR S);
2689  // I2 = NOT(J2 EOR S);
2690  // and build the imm32 with one trailing zero as documented:
2691  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2692  unsigned S = fieldFromInstruction(Insn, 26, 1);
2693  unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2694  unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2695  unsigned I1 = !(J1 ^ S);
2696  unsigned I2 = !(J2 ^ S);
2697  unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2698  unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2699  unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2700  int imm32 = SignExtend32<25>(tmp << 1);
2701  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2702  true, 4, Inst, Decoder))
2703  Inst.addOperand(MCOperand::createImm(imm32));
2704 
2705  return Status;
2706 }
2707 
2708 static DecodeStatus
2710  uint64_t Address, const void *Decoder) {
2712 
2713  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2714  unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2715 
2716  if (pred == 0xF) {
2717  Inst.setOpcode(ARM::BLXi);
2718  imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2719  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2720  true, 4, Inst, Decoder))
2721  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2722  return S;
2723  }
2724 
2725  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2726  true, 4, Inst, Decoder))
2727  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2728 
2729  // We already have BL_pred for BL w/ predicate, no need to add addition
2730  // predicate opreands for BL
2731  if (Inst.getOpcode() != ARM::BL)
2732  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2733  return MCDisassembler::Fail;
2734 
2735  return S;
2736 }
2737 
2738 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2739  uint64_t Address, const void *Decoder) {
2741 
2742  unsigned Rm = fieldFromInstruction(Val, 0, 4);
2743  unsigned align = fieldFromInstruction(Val, 4, 2);
2744 
2745  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2746  return MCDisassembler::Fail;
2747  if (!align)
2749  else
2751 
2752  return S;
2753 }
2754 
2756  uint64_t Address, const void *Decoder) {
2758 
2759  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2760  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2761  unsigned wb = fieldFromInstruction(Insn, 16, 4);
2762  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2763  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2764  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2765 
2766  // First output register
2767  switch (Inst.getOpcode()) {
2768  case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2769  case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2770  case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2771  case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2772  case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2773  case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2774  case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2775  case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2776  case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2777  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2778  return MCDisassembler::Fail;
2779  break;
2780  case ARM::VLD2b16:
2781  case ARM::VLD2b32:
2782  case ARM::VLD2b8:
2783  case ARM::VLD2b16wb_fixed:
2784  case ARM::VLD2b16wb_register:
2785  case ARM::VLD2b32wb_fixed:
2786  case ARM::VLD2b32wb_register:
2787  case ARM::VLD2b8wb_fixed:
2788  case ARM::VLD2b8wb_register:
2789  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2790  return MCDisassembler::Fail;
2791  break;
2792  default:
2793  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2794  return MCDisassembler::Fail;
2795  }
2796 
2797  // Second output register
2798  switch (Inst.getOpcode()) {
2799  case ARM::VLD3d8:
2800  case ARM::VLD3d16:
2801  case ARM::VLD3d32:
2802  case ARM::VLD3d8_UPD:
2803  case ARM::VLD3d16_UPD:
2804  case ARM::VLD3d32_UPD:
2805  case ARM::VLD4d8:
2806  case ARM::VLD4d16:
2807  case ARM::VLD4d32:
2808  case ARM::VLD4d8_UPD:
2809  case ARM::VLD4d16_UPD:
2810  case ARM::VLD4d32_UPD:
2811  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2812  return MCDisassembler::Fail;
2813  break;
2814  case ARM::VLD3q8:
2815  case ARM::VLD3q16:
2816  case ARM::VLD3q32:
2817  case ARM::VLD3q8_UPD:
2818  case ARM::VLD3q16_UPD:
2819  case ARM::VLD3q32_UPD:
2820  case ARM::VLD4q8:
2821  case ARM::VLD4q16:
2822  case ARM::VLD4q32:
2823  case ARM::VLD4q8_UPD:
2824  case ARM::VLD4q16_UPD:
2825  case ARM::VLD4q32_UPD:
2826  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2827  return MCDisassembler::Fail;
2828  break;
2829  default:
2830  break;
2831  }
2832 
2833  // Third output register
2834  switch(Inst.getOpcode()) {
2835  case ARM::VLD3d8:
2836  case ARM::VLD3d16:
2837  case ARM::VLD3d32:
2838  case ARM::VLD3d8_UPD:
2839  case ARM::VLD3d16_UPD:
2840  case ARM::VLD3d32_UPD:
2841  case ARM::VLD4d8:
2842  case ARM::VLD4d16:
2843  case ARM::VLD4d32:
2844  case ARM::VLD4d8_UPD:
2845  case ARM::VLD4d16_UPD:
2846  case ARM::VLD4d32_UPD:
2847  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2848  return MCDisassembler::Fail;
2849  break;
2850  case ARM::VLD3q8:
2851  case ARM::VLD3q16:
2852  case ARM::VLD3q32:
2853  case ARM::VLD3q8_UPD:
2854  case ARM::VLD3q16_UPD:
2855  case ARM::VLD3q32_UPD:
2856  case ARM::VLD4q8:
2857  case ARM::VLD4q16:
2858  case ARM::VLD4q32:
2859  case ARM::VLD4q8_UPD:
2860  case ARM::VLD4q16_UPD:
2861  case ARM::VLD4q32_UPD:
2862  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2863  return MCDisassembler::Fail;
2864  break;
2865  default:
2866  break;
2867  }
2868 
2869  // Fourth output register
2870  switch (Inst.getOpcode()) {
2871  case ARM::VLD4d8:
2872  case ARM::VLD4d16:
2873  case ARM::VLD4d32:
2874  case ARM::VLD4d8_UPD:
2875  case ARM::VLD4d16_UPD:
2876  case ARM::VLD4d32_UPD:
2877  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2878  return MCDisassembler::Fail;
2879  break;
2880  case ARM::VLD4q8:
2881  case ARM::VLD4q16:
2882  case ARM::VLD4q32:
2883  case ARM::VLD4q8_UPD:
2884  case ARM::VLD4q16_UPD:
2885  case ARM::VLD4q32_UPD:
2886  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2887  return MCDisassembler::Fail;
2888  break;
2889  default:
2890  break;
2891  }
2892 
2893  // Writeback operand
2894  switch (Inst.getOpcode()) {
2895  case ARM::VLD1d8wb_fixed:
2896  case ARM::VLD1d16wb_fixed:
2897  case ARM::VLD1d32wb_fixed:
2898  case ARM::VLD1d64wb_fixed:
2899  case ARM::VLD1d8wb_register:
2900  case ARM::VLD1d16wb_register:
2901  case ARM::VLD1d32wb_register:
2902  case ARM::VLD1d64wb_register:
2903  case ARM::VLD1q8wb_fixed:
2904  case ARM::VLD1q16wb_fixed:
2905  case ARM::VLD1q32wb_fixed:
2906  case ARM::VLD1q64wb_fixed:
2907  case ARM::VLD1q8wb_register:
2908  case ARM::VLD1q16wb_register:
2909  case ARM::VLD1q32wb_register:
2910  case ARM::VLD1q64wb_register:
2911  case ARM::VLD1d8Twb_fixed:
2912  case ARM::VLD1d8Twb_register:
2913  case ARM::VLD1d16Twb_fixed:
2914  case ARM::VLD1d16Twb_register:
2915  case ARM::VLD1d32Twb_fixed:
2916  case ARM::VLD1d32Twb_register:
2917  case ARM::VLD1d64Twb_fixed:
2918  case ARM::VLD1d64Twb_register:
2919  case ARM::VLD1d8Qwb_fixed:
2920  case ARM::VLD1d8Qwb_register:
2921  case ARM::VLD1d16Qwb_fixed:
2922  case ARM::VLD1d16Qwb_register:
2923  case ARM::VLD1d32Qwb_fixed:
2924  case ARM::VLD1d32Qwb_register:
2925  case ARM::VLD1d64Qwb_fixed:
2926  case ARM::VLD1d64Qwb_register:
2927  case ARM::VLD2d8wb_fixed:
2928  case ARM::VLD2d16wb_fixed:
2929  case ARM::VLD2d32wb_fixed:
2930  case ARM::VLD2q8wb_fixed:
2931  case ARM::VLD2q16wb_fixed:
2932  case ARM::VLD2q32wb_fixed:
2933  case ARM::VLD2d8wb_register:
2934  case ARM::VLD2d16wb_register:
2935  case ARM::VLD2d32wb_register:
2936  case ARM::VLD2q8wb_register:
2937  case ARM::VLD2q16wb_register:
2938  case ARM::VLD2q32wb_register:
2939  case ARM::VLD2b8wb_fixed:
2940  case ARM::VLD2b16wb_fixed:
2941  case ARM::VLD2b32wb_fixed:
2942  case ARM::VLD2b8wb_register:
2943  case ARM::VLD2b16wb_register:
2944  case ARM::VLD2b32wb_register:
2946  break;
2947  case ARM::VLD3d8_UPD:
2948  case ARM::VLD3d16_UPD:
2949  case ARM::VLD3d32_UPD:
2950  case ARM::VLD3q8_UPD:
2951  case ARM::VLD3q16_UPD:
2952  case ARM::VLD3q32_UPD:
2953  case ARM::VLD4d8_UPD:
2954  case ARM::VLD4d16_UPD:
2955  case ARM::VLD4d32_UPD:
2956  case ARM::VLD4q8_UPD:
2957  case ARM::VLD4q16_UPD:
2958  case ARM::VLD4q32_UPD:
2959  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2960  return MCDisassembler::Fail;
2961  break;
2962  default:
2963  break;
2964  }
2965 
2966  // AddrMode6 Base (register+alignment)
2967  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2968  return MCDisassembler::Fail;
2969 
2970  // AddrMode6 Offset (register)
2971  switch (Inst.getOpcode()) {
2972  default:
2973  // The below have been updated to have explicit am6offset split
2974  // between fixed and register offset. For those instructions not
2975  // yet updated, we need to add an additional reg0 operand for the
2976  // fixed variant.
2977  //
2978  // The fixed offset encodes as Rm == 0xd, so we check for that.
2979  if (Rm == 0xd) {
2981  break;
2982  }
2983  // Fall through to handle the register offset variant.
2985  case ARM::VLD1d8wb_fixed:
2986  case ARM::VLD1d16wb_fixed:
2987  case ARM::VLD1d32wb_fixed:
2988  case ARM::VLD1d64wb_fixed:
2989  case ARM::VLD1d8Twb_fixed:
2990  case ARM::VLD1d16Twb_fixed:
2991  case ARM::VLD1d32Twb_fixed:
2992  case ARM::VLD1d64Twb_fixed:
2993  case ARM::VLD1d8Qwb_fixed:
2994  case ARM::VLD1d16Qwb_fixed:
2995  case ARM::VLD1d32Qwb_fixed:
2996  case ARM::VLD1d64Qwb_fixed:
2997  case ARM::VLD1d8wb_register:
2998  case ARM::VLD1d16wb_register:
2999  case ARM::VLD1d32wb_register:
3000  case ARM::VLD1d64wb_register:
3001  case ARM::VLD1q8wb_fixed:
3002  case ARM::VLD1q16wb_fixed:
3003  case ARM::VLD1q32wb_fixed:
3004  case ARM::VLD1q64wb_fixed:
3005  case ARM::VLD1q8wb_register:
3006  case ARM::VLD1q16wb_register:
3007  case ARM::VLD1q32wb_register:
3008  case ARM::VLD1q64wb_register:
3009  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3010  // variant encodes Rm == 0xf. Anything else is a register offset post-
3011  // increment and we need to add the register operand to the instruction.
3012  if (Rm != 0xD && Rm != 0xF &&
3013  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3014  return MCDisassembler::Fail;
3015  break;
3016  case ARM::VLD2d8wb_fixed:
3017  case ARM::VLD2d16wb_fixed:
3018  case ARM::VLD2d32wb_fixed:
3019  case ARM::VLD2b8wb_fixed:
3020  case ARM::VLD2b16wb_fixed:
3021  case ARM::VLD2b32wb_fixed:
3022  case ARM::VLD2q8wb_fixed:
3023  case ARM::VLD2q16wb_fixed:
3024  case ARM::VLD2q32wb_fixed:
3025  break;
3026  }
3027 
3028  return S;
3029 }
3030 
3032  uint64_t Address, const void *Decoder) {
3033  unsigned type = fieldFromInstruction(Insn, 8, 4);
3034  unsigned align = fieldFromInstruction(Insn, 4, 2);
3035  if (type == 6 && (align & 2)) return MCDisassembler::Fail;
3036  if (type == 7 && (align & 2)) return MCDisassembler::Fail;
3037  if (type == 10 && align == 3) return MCDisassembler::Fail;
3038 
3039  unsigned load = fieldFromInstruction(Insn, 21, 1);
3040  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3041  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3042 }
3043 
3045  uint64_t Address, const void *Decoder) {
3046  unsigned size = fieldFromInstruction(Insn, 6, 2);
3047  if (size == 3) return MCDisassembler::Fail;
3048 
3049  unsigned type = fieldFromInstruction(Insn, 8, 4);
3050  unsigned align = fieldFromInstruction(Insn, 4, 2);
3051  if (type == 8 && align == 3) return MCDisassembler::Fail;
3052  if (type == 9 && align == 3) return MCDisassembler::Fail;
3053 
3054  unsigned load = fieldFromInstruction(Insn, 21, 1);
3055  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3056  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3057 }
3058 
3060  uint64_t Address, const void *Decoder) {
3061  unsigned size = fieldFromInstruction(Insn, 6, 2);
3062  if (size == 3) return MCDisassembler::Fail;
3063 
3064  unsigned align = fieldFromInstruction(Insn, 4, 2);
3065  if (align & 2) return MCDisassembler::Fail;
3066 
3067  unsigned load = fieldFromInstruction(Insn, 21, 1);
3068  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3069  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3070 }
3071 
3073  uint64_t Address, const void *Decoder) {
3074  unsigned size = fieldFromInstruction(Insn, 6, 2);
3075  if (size == 3) return MCDisassembler::Fail;
3076 
3077  unsigned load = fieldFromInstruction(Insn, 21, 1);
3078  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3079  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3080 }
3081 
3083  uint64_t Address, const void *Decoder) {
3085 
3086  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3087  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3088  unsigned wb = fieldFromInstruction(Insn, 16, 4);
3089  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3090  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
3091  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3092 
3093  // Writeback Operand
3094  switch (Inst.getOpcode()) {
3095  case ARM::VST1d8wb_fixed:
3096  case ARM::VST1d16wb_fixed:
3097  case ARM::VST1d32wb_fixed:
3098  case ARM::VST1d64wb_fixed:
3099  case ARM::VST1d8wb_register:
3100  case ARM::VST1d16wb_register:
3101  case ARM::VST1d32wb_register:
3102  case ARM::VST1d64wb_register:
3103  case ARM::VST1q8wb_fixed:
3104  case ARM::VST1q16wb_fixed:
3105  case ARM::VST1q32wb_fixed:
3106  case ARM::VST1q64wb_fixed:
3107  case ARM::VST1q8wb_register:
3108  case ARM::VST1q16wb_register:
3109  case ARM::VST1q32wb_register:
3110  case ARM::VST1q64wb_register:
3111  case ARM::VST1d8Twb_fixed:
3112  case ARM::VST1d16Twb_fixed:
3113  case ARM::VST1d32Twb_fixed:
3114  case ARM::VST1d64Twb_fixed:
3115  case ARM::VST1d8Twb_register:
3116  case ARM::VST1d16Twb_register:
3117  case ARM::VST1d32Twb_register:
3118  case ARM::VST1d64Twb_register:
3119  case ARM::VST1d8Qwb_fixed:
3120  case ARM::VST1d16Qwb_fixed:
3121  case ARM::VST1d32Qwb_fixed:
3122  case ARM::VST1d64Qwb_fixed:
3123  case ARM::VST1d8Qwb_register:
3124  case ARM::VST1d16Qwb_register:
3125  case ARM::VST1d32Qwb_register:
3126  case ARM::VST1d64Qwb_register:
3127  case ARM::VST2d8wb_fixed:
3128  case ARM::VST2d16wb_fixed:
3129  case ARM::VST2d32wb_fixed:
3130  case ARM::VST2d8wb_register:
3131  case ARM::VST2d16wb_register:
3132  case ARM::VST2d32wb_register:
3133  case ARM::VST2q8wb_fixed:
3134  case ARM::VST2q16wb_fixed:
3135  case ARM::VST2q32wb_fixed:
3136  case ARM::VST2q8wb_register:
3137  case ARM::VST2q16wb_register:
3138  case ARM::VST2q32wb_register:
3139  case ARM::VST2b8wb_fixed:
3140  case ARM::VST2b16wb_fixed:
3141  case ARM::VST2b32wb_fixed:
3142  case ARM::VST2b8wb_register:
3143  case ARM::VST2b16wb_register:
3144  case ARM::VST2b32wb_register:
3145  if (Rm == 0xF)
3146  return MCDisassembler::Fail;
3148  break;
3149  case ARM::VST3d8_UPD:
3150  case ARM::VST3d16_UPD:
3151  case ARM::VST3d32_UPD:
3152  case ARM::VST3q8_UPD:
3153  case ARM::VST3q16_UPD:
3154  case ARM::VST3q32_UPD:
3155  case ARM::VST4d8_UPD:
3156  case ARM::VST4d16_UPD:
3157  case ARM::VST4d32_UPD:
3158  case ARM::VST4q8_UPD:
3159  case ARM::VST4q16_UPD:
3160  case ARM::VST4q32_UPD:
3161  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3162  return MCDisassembler::Fail;
3163  break;
3164  default:
3165  break;
3166  }
3167 
3168  // AddrMode6 Base (register+alignment)
3169  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3170  return MCDisassembler::Fail;
3171 
3172  // AddrMode6 Offset (register)
3173  switch (Inst.getOpcode()) {
3174  default:
3175  if (Rm == 0xD)
3177  else if (Rm != 0xF) {
3178  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3179  return MCDisassembler::Fail;
3180  }
3181  break;
3182  case ARM::VST1d8wb_fixed:
3183  case ARM::VST1d16wb_fixed:
3184  case ARM::VST1d32wb_fixed:
3185  case ARM::VST1d64wb_fixed:
3186  case ARM::VST1q8wb_fixed:
3187  case ARM::VST1q16wb_fixed:
3188  case ARM::VST1q32wb_fixed:
3189  case ARM::VST1q64wb_fixed:
3190  case ARM::VST1d8Twb_fixed:
3191  case ARM::VST1d16Twb_fixed:
3192  case ARM::VST1d32Twb_fixed:
3193  case ARM::VST1d64Twb_fixed:
3194  case ARM::VST1d8Qwb_fixed:
3195  case ARM::VST1d16Qwb_fixed:
3196  case ARM::VST1d32Qwb_fixed:
3197  case ARM::VST1d64Qwb_fixed:
3198  case ARM::VST2d8wb_fixed:
3199  case ARM::VST2d16wb_fixed:
3200  case ARM::VST2d32wb_fixed:
3201  case ARM::VST2q8wb_fixed:
3202  case ARM::VST2q16wb_fixed:
3203  case ARM::VST2q32wb_fixed:
3204  case ARM::VST2b8wb_fixed:
3205  case ARM::VST2b16wb_fixed:
3206  case ARM::VST2b32wb_fixed:
3207  break;
3208  }
3209 
3210  // First input register
3211  switch (Inst.getOpcode()) {
3212  case ARM::VST1q16:
3213  case ARM::VST1q32:
3214  case ARM::VST1q64:
3215  case ARM::VST1q8:
3216  case ARM::VST1q16wb_fixed:
3217  case ARM::VST1q16wb_register:
3218  case ARM::VST1q32wb_fixed:
3219  case ARM::VST1q32wb_register:
3220  case ARM::VST1q64wb_fixed:
3221  case ARM::VST1q64wb_register:
3222  case ARM::VST1q8wb_fixed:
3223  case ARM::VST1q8wb_register:
3224  case ARM::VST2d16:
3225  case ARM::VST2d32:
3226  case ARM::VST2d8:
3227  case ARM::VST2d16wb_fixed:
3228  case ARM::VST2d16wb_register:
3229  case ARM::VST2d32wb_fixed:
3230  case ARM::VST2d32wb_register:
3231  case ARM::VST2d8wb_fixed:
3232  case ARM::VST2d8wb_register:
3233  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3234  return MCDisassembler::Fail;
3235  break;
3236  case ARM::VST2b16:
3237  case ARM::VST2b32:
3238  case ARM::VST2b8:
3239  case ARM::VST2b16wb_fixed:
3240  case ARM::VST2b16wb_register:
3241  case ARM::VST2b32wb_fixed:
3242  case ARM::VST2b32wb_register:
3243  case ARM::VST2b8wb_fixed:
3244  case ARM::VST2b8wb_register:
3245  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3246  return MCDisassembler::Fail;
3247  break;
3248  default:
3249  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3250  return MCDisassembler::Fail;
3251  }
3252 
3253  // Second input register
3254  switch (Inst.getOpcode()) {
3255  case ARM::VST3d8:
3256  case ARM::VST3d16:
3257  case ARM::VST3d32:
3258  case ARM::VST3d8_UPD:
3259  case ARM::VST3d16_UPD:
3260  case ARM::VST3d32_UPD:
3261  case ARM::VST4d8:
3262  case ARM::VST4d16:
3263  case ARM::VST4d32:
3264  case ARM::VST4d8_UPD:
3265  case ARM::VST4d16_UPD:
3266  case ARM::VST4d32_UPD:
3267  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
3268  return MCDisassembler::Fail;
3269  break;
3270  case ARM::VST3q8:
3271  case ARM::VST3q16:
3272  case ARM::VST3q32:
3273  case ARM::VST3q8_UPD:
3274  case ARM::VST3q16_UPD:
3275  case ARM::VST3q32_UPD:
3276  case ARM::VST4q8:
3277  case ARM::VST4q16:
3278  case ARM::VST4q32:
3279  case ARM::VST4q8_UPD:
3280  case ARM::VST4q16_UPD:
3281  case ARM::VST4q32_UPD:
3282  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3283  return MCDisassembler::Fail;
3284  break;
3285  default:
3286  break;
3287  }
3288 
3289  // Third input register
3290  switch (Inst.getOpcode()) {
3291  case ARM::VST3d8:
3292  case ARM::VST3d16:
3293  case ARM::VST3d32:
3294  case ARM::VST3d8_UPD:
3295  case ARM::VST3d16_UPD:
3296  case ARM::VST3d32_UPD:
3297  case ARM::VST4d8:
3298  case ARM::VST4d16:
3299  case ARM::VST4d32:
3300  case ARM::VST4d8_UPD:
3301  case ARM::VST4d16_UPD:
3302  case ARM::VST4d32_UPD:
3303  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3304  return MCDisassembler::Fail;
3305  break;
3306  case ARM::VST3q8:
3307  case ARM::VST3q16:
3308  case ARM::VST3q32:
3309  case ARM::VST3q8_UPD:
3310  case ARM::VST3q16_UPD:
3311  case ARM::VST3q32_UPD:
3312  case ARM::VST4q8:
3313  case ARM::VST4q16:
3314  case ARM::VST4q32:
3315  case ARM::VST4q8_UPD:
3316  case ARM::VST4q16_UPD:
3317  case ARM::VST4q32_UPD:
3318  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
3319  return MCDisassembler::Fail;
3320  break;
3321  default:
3322  break;
3323  }
3324 
3325  // Fourth input register
3326  switch (Inst.getOpcode()) {
3327  case ARM::VST4d8:
3328  case ARM::VST4d16:
3329  case ARM::VST4d32:
3330  case ARM::VST4d8_UPD:
3331  case ARM::VST4d16_UPD:
3332  case ARM::VST4d32_UPD:
3333  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
3334  return MCDisassembler::Fail;
3335  break;
3336  case ARM::VST4q8:
3337  case ARM::VST4q16:
3338  case ARM::VST4q32:
3339  case ARM::VST4q8_UPD:
3340  case ARM::VST4q16_UPD:
3341  case ARM::VST4q32_UPD:
3342  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
3343  return MCDisassembler::Fail;
3344  break;
3345  default:
3346  break;
3347  }
3348 
3349  return S;
3350 }
3351 
3353  uint64_t Address, const void *Decoder) {
3355 
3356  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3357  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3358  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3359  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3360  unsigned align = fieldFromInstruction(Insn, 4, 1);
3361  unsigned size = fieldFromInstruction(Insn, 6, 2);
3362 
3363  if (size == 0 && align == 1)
3364  return MCDisassembler::Fail;
3365  align *= (1 << size);
3366 
3367  switch (Inst.getOpcode()) {
3368  case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
3369  case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
3370  case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
3371  case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
3372  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3373  return MCDisassembler::Fail;
3374  break;
3375  default:
3376  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3377  return MCDisassembler::Fail;
3378  break;
3379  }
3380  if (Rm != 0xF) {
3381  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3382  return MCDisassembler::Fail;
3383  }
3384 
3385  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3386  return MCDisassembler::Fail;
3388 
3389  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3390  // variant encodes Rm == 0xf. Anything else is a register offset post-
3391  // increment and we need to add the register operand to the instruction.
3392  if (Rm != 0xD && Rm != 0xF &&
3393  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3394  return MCDisassembler::Fail;
3395 
3396  return S;
3397 }
3398 
3400  uint64_t Address, const void *Decoder) {
3402 
3403  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3404  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3405  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3406  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3407  unsigned align = fieldFromInstruction(Insn, 4, 1);
3408  unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
3409  align *= 2*size;
3410 
3411  switch (Inst.getOpcode()) {
3412  case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
3413  case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
3414  case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
3415  case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
3416  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3417  return MCDisassembler::Fail;
3418  break;
3419  case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
3420  case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
3421  case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
3422  case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3423  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3424  return MCDisassembler::Fail;
3425  break;
3426  default:
3427  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3428  return MCDisassembler::Fail;
3429  break;
3430  }
3431 
3432  if (Rm != 0xF)
3434 
3435  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3436  return MCDisassembler::Fail;
3438 
3439  if (Rm != 0xD && Rm != 0xF) {
3440  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3441  return MCDisassembler::Fail;
3442  }
3443 
3444  return S;
3445 }
3446 
3448  uint64_t Address, const void *Decoder) {
3450 
3451  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3452  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3453  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3454  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3455  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3456 
3457  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3458  return MCDisassembler::Fail;
3459  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3460  return MCDisassembler::Fail;
3461  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3462  return MCDisassembler::Fail;
3463  if (Rm != 0xF) {
3464  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3465  return MCDisassembler::Fail;
3466  }
3467 
3468  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3469  return MCDisassembler::Fail;
3471 
3472  if (Rm == 0xD)
3474  else if (Rm != 0xF) {
3475  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3476  return MCDisassembler::Fail;
3477  }
3478 
3479  return S;
3480 }
3481 
3483  uint64_t Address, const void *Decoder) {
3485 
3486  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3487  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3488  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3489  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3490  unsigned size = fieldFromInstruction(Insn, 6, 2);
3491  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3492  unsigned align = fieldFromInstruction(Insn, 4, 1);
3493 
3494  if (size == 0x3) {
3495  if (align == 0)
3496  return MCDisassembler::Fail;
3497  align = 16;
3498  } else {
3499  if (size == 2) {
3500  align *= 8;
3501  } else {
3502  size = 1 << size;
3503  align *= 4*size;
3504  }
3505  }
3506 
3507  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3508  return MCDisassembler::Fail;
3509  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3510  return MCDisassembler::Fail;
3511  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3512  return MCDisassembler::Fail;
3513  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3514  return MCDisassembler::Fail;
3515  if (Rm != 0xF) {
3516  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3517  return MCDisassembler::Fail;
3518  }
3519 
3520  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3521  return MCDisassembler::Fail;
3523 
3524  if (Rm == 0xD)
3526  else if (Rm != 0xF) {
3527  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3528  return MCDisassembler::Fail;
3529  }
3530 
3531  return S;
3532 }
3533 
3534 static DecodeStatus
3536  uint64_t Address, const void *Decoder) {
3538 
3539  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3540  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3541  unsigned imm = fieldFromInstruction(Insn, 0, 4);
3542  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3543  imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3544  imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3545  imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3546  unsigned Q = fieldFromInstruction(Insn, 6, 1);
3547 
3548  if (Q) {
3549  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3550  return MCDisassembler::Fail;
3551  } else {
3552  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3553  return MCDisassembler::Fail;
3554  }
3555 
3556  Inst.addOperand(MCOperand::createImm(imm));
3557 
3558  switch (Inst.getOpcode()) {
3559  case ARM::VORRiv4i16:
3560  case ARM::VORRiv2i32:
3561  case ARM::VBICiv4i16:
3562  case ARM::VBICiv2i32:
3563  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3564  return MCDisassembler::Fail;
3565  break;
3566  case ARM::VORRiv8i16:
3567  case ARM::VORRiv4i32:
3568  case ARM::VBICiv8i16:
3569  case ARM::VBICiv4i32:
3570  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3571  return MCDisassembler::Fail;
3572  break;
3573  default:
3574  break;
3575  }
3576 
3577  return S;
3578 }
3579 
3580 static DecodeStatus
3582  uint64_t Address, const void *Decoder) {
3584 
3585  unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
3586  fieldFromInstruction(Insn, 13, 3));
3587  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
3588  unsigned imm = fieldFromInstruction(Insn, 0, 4);
3589  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3590  imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3591  imm |= cmode << 8;
3592  imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3593 
3594  if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3595  return MCDisassembler::Fail;
3596 
3597  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3598  return MCDisassembler::Fail;
3599 
3600  Inst.addOperand(MCOperand::createImm(imm));
3601 
3605 
3606  return S;
3607 }
3608 
3610  uint64_t Address, const void *Decoder) {
3612 
3613  unsigned Qd = fieldFromInstruction(Insn, 13, 3);
3614  Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
3615  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3616  return MCDisassembler::Fail;
3617  Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3618 
3619  unsigned Qn = fieldFromInstruction(Insn, 17, 3);
3620  Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
3621  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
3622  return MCDisassembler::Fail;
3623  unsigned Qm = fieldFromInstruction(Insn, 1, 3);
3624  Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
3625  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3626  return MCDisassembler::Fail;
3627  if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
3628  Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3629  Inst.addOperand(MCOperand::createImm(Qd));
3630 
3631  return S;
3632 }
3633 
3635  uint64_t Address, const void *Decoder) {
3637 
3638  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3639  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3640  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3641  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3642  unsigned size = fieldFromInstruction(Insn, 18, 2);
3643 
3644  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3645  return MCDisassembler::Fail;
3646  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3647  return MCDisassembler::Fail;
3648  Inst.addOperand(MCOperand::createImm(8 << size));
3649 
3650  return S;
3651 }
3652 
3653 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3654  uint64_t Address, const void *Decoder) {
3655  Inst.addOperand(MCOperand::createImm(8 - Val));
3656  return MCDisassembler::Success;
3657 }
3658 
3659 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3660  uint64_t Address, const void *Decoder) {
3661  Inst.addOperand(MCOperand::createImm(16 - Val));
3662  return MCDisassembler::Success;
3663 }
3664 
3665 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3666  uint64_t Address, const void *Decoder) {
3667  Inst.addOperand(MCOperand::createImm(32 - Val));
3668  return MCDisassembler::Success;
3669 }
3670 
3671 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3672  uint64_t Address, const void *Decoder) {
3673  Inst.addOperand(MCOperand::createImm(64 - Val));
3674  return MCDisassembler::Success;
3675 }
3676 
3678  uint64_t Address, const void *Decoder) {
3680 
3681  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3682  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3683  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3684  Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3685  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3686  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3687  unsigned op = fieldFromInstruction(Insn, 6, 1);
3688 
3689  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3690  return MCDisassembler::Fail;
3691  if (op) {
3692  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3693  return MCDisassembler::Fail; // Writeback
3694  }
3695 
3696  switch (Inst.getOpcode()) {
3697  case ARM::VTBL2:
3698  case ARM::VTBX2:
3699  if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3700  return MCDisassembler::Fail;
3701  break;
3702  default:
3703  if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3704  return MCDisassembler::Fail;
3705  }
3706 
3707  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3708  return MCDisassembler::Fail;
3709 
3710  return S;
3711 }
3712 
3714  uint64_t Address, const void *Decoder) {
3716 
3717  unsigned dst = fieldFromInstruction(Insn, 8, 3);
3718  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3719 
3720  if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3721  return MCDisassembler::Fail;
3722 
3723  switch(Inst.getOpcode()) {
3724  default:
3725  return MCDisassembler::Fail;
3726  case ARM::tADR:
3727  break; // tADR does not explicitly represent the PC as an operand.
3728  case ARM::tADDrSPi:
3729  Inst.addOperand(MCOperand::createReg(ARM::SP));
3730  break;
3731  }
3732 
3733  Inst.addOperand(MCOperand::createImm(imm));
3734  return S;
3735 }
3736 
3737 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3738  uint64_t Address, const void *Decoder) {
3739  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3740  true, 2, Inst, Decoder))
3741  Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3742  return MCDisassembler::Success;
3743 }
3744 
3745 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3746  uint64_t Address, const void *Decoder) {
3747  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3748  true, 4, Inst, Decoder))
3749  Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3750  return MCDisassembler::Success;
3751 }
3752 
3753 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3754  uint64_t Address, const void *Decoder) {
3755  if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3756  true, 2, Inst, Decoder))
3757  Inst.addOperand(MCOperand::createImm(Val << 1));
3758  return MCDisassembler::Success;
3759 }
3760 
3761 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3762  uint64_t Address, const void *Decoder) {
3764 
3765  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3766  unsigned Rm = fieldFromInstruction(Val, 3, 3);
3767 
3768  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3769  return MCDisassembler::Fail;
3770  if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3771  return MCDisassembler::Fail;
3772 
3773  return S;
3774 }
3775 
3776 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3777  uint64_t Address, const void *Decoder) {
3779 
3780  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3781  unsigned imm = fieldFromInstruction(Val, 3, 5);
3782 
3783  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3784  return MCDisassembler::Fail;
3785  Inst.addOperand(MCOperand::createImm(imm));
3786 
3787  return S;
3788 }
3789 
3790 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3791  uint64_t Address, const void *Decoder) {
3792  unsigned imm = Val << 2;
3793 
3794  Inst.addOperand(MCOperand::createImm(imm));
3795  tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3796 
3797  return MCDisassembler::Success;
3798 }
3799 
3800 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3801  uint64_t Address, const void *Decoder) {
3802  Inst.addOperand(MCOperand::createReg(ARM::SP));
3803  Inst.addOperand(MCOperand::createImm(Val));
3804 
3805  return MCDisassembler::Success;
3806 }
3807 
3808 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3809  uint64_t Address, const void *Decoder) {
3811 
3812  unsigned Rn = fieldFromInstruction(Val, 6, 4);
3813  unsigned Rm = fieldFromInstruction(Val, 2, 4);
3814  unsigned imm = fieldFromInstruction(Val, 0, 2);
3815 
3816  // Thumb stores cannot use PC as dest register.
3817  switch (Inst.getOpcode()) {
3818  case ARM::t2STRHs:
3819  case ARM::t2STRBs:
3820  case ARM::t2STRs:
3821  if (Rn == 15)
3822  return MCDisassembler::Fail;
3823  break;
3824  default:
3825  break;
3826  }
3827 
3828  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3829  return MCDisassembler::Fail;
3830  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3831  return MCDisassembler::Fail;
3832  Inst.addOperand(MCOperand::createImm(imm));
3833 
3834  return S;
3835 }
3836 
3838  uint64_t Address, const void *Decoder) {
3840 
3841  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3842  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3843 
3844  const FeatureBitset &featureBits =
3845  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3846 
3847  bool hasMP = featureBits[ARM::FeatureMP];
3848  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3849 
3850  if (Rn == 15) {
3851  switch (Inst.getOpcode()) {
3852  case ARM::t2LDRBs:
3853  Inst.setOpcode(ARM::t2LDRBpci);
3854  break;
3855  case ARM::t2LDRHs:
3856  Inst.setOpcode(ARM::t2LDRHpci);
3857  break;
3858  case ARM::t2LDRSHs:
3859  Inst.setOpcode(ARM::t2LDRSHpci);
3860  break;
3861  case ARM::t2LDRSBs:
3862  Inst.setOpcode(ARM::t2LDRSBpci);
3863  break;
3864  case ARM::t2LDRs:
3865  Inst.setOpcode(ARM::t2LDRpci);
3866  break;
3867  case ARM::t2PLDs:
3868  Inst.setOpcode(ARM::t2PLDpci);
3869  break;
3870  case ARM::t2PLIs:
3871  Inst.setOpcode(ARM::t2PLIpci);
3872  break;
3873  default:
3874  return MCDisassembler::Fail;
3875  }
3876 
3877  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3878  }
3879 
3880  if (Rt == 15) {
3881  switch (Inst.getOpcode()) {
3882  case ARM::t2LDRSHs:
3883  return MCDisassembler::Fail;
3884  case ARM::t2LDRHs:
3885  Inst.setOpcode(ARM::t2PLDWs);
3886  break;
3887  case ARM::t2LDRSBs:
3888  Inst.setOpcode(ARM::t2PLIs);
3889  break;
3890  default:
3891  break;
3892  }
3893  }
3894 
3895  switch (Inst.getOpcode()) {
3896  case ARM::t2PLDs:
3897  break;
3898  case ARM::t2PLIs:
3899  if (!hasV7Ops)
3900  return MCDisassembler::Fail;
3901  break;
3902  case ARM::t2PLDWs:
3903  if (!hasV7Ops || !hasMP)
3904  return MCDisassembler::Fail;
3905  break;
3906  default:
3907  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3908  return MCDisassembler::Fail;
3909  }
3910 
3911  unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3912  addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3913  addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3914  if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3915  return MCDisassembler::Fail;
3916 
3917  return S;
3918 }
3919 
3920 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3921  uint64_t Address, const void* Decoder) {
3923 
3924  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3925  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3926  unsigned U = fieldFromInstruction(Insn, 9, 1);
3927  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3928  imm |= (U << 8);
3929  imm |= (Rn << 9);
3930  unsigned add = fieldFromInstruction(Insn, 9, 1);
3931 
3932  const FeatureBitset &featureBits =
3933  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3934 
3935  bool hasMP = featureBits[ARM::FeatureMP];
3936  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3937 
3938  if (Rn == 15) {
3939  switch (Inst.getOpcode()) {
3940  case ARM::t2LDRi8:
3941  Inst.setOpcode(ARM::t2LDRpci);
3942  break;
3943  case ARM::t2LDRBi8:
3944  Inst.setOpcode(ARM::t2LDRBpci);
3945  break;
3946  case ARM::t2LDRSBi8:
3947  Inst.setOpcode(ARM::t2LDRSBpci);
3948  break;
3949  case ARM::t2LDRHi8:
3950  Inst.setOpcode(ARM::t2LDRHpci);
3951  break;
3952  case ARM::t2LDRSHi8:
3953  Inst.setOpcode(ARM::t2LDRSHpci);
3954  break;
3955  case ARM::t2PLDi8:
3956  Inst.setOpcode(ARM::t2PLDpci);
3957  break;
3958  case ARM::t2PLIi8:
3959  Inst.setOpcode(ARM::t2PLIpci);
3960  break;
3961  default:
3962  return MCDisassembler::Fail;
3963  }
3964  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3965  }
3966 
3967  if (Rt == 15) {
3968  switch (Inst.getOpcode()) {
3969  case ARM::t2LDRSHi8:
3970  return MCDisassembler::Fail;
3971  case ARM::t2LDRHi8:
3972  if (!add)
3973  Inst.setOpcode(ARM::t2PLDWi8);
3974  break;
3975  case ARM::t2LDRSBi8:
3976  Inst.setOpcode(ARM::t2PLIi8);
3977  break;
3978  default:
3979  break;
3980  }
3981  }
3982 
3983  switch (Inst.getOpcode()) {
3984  case ARM::t2PLDi8:
3985  break;
3986  case ARM::t2PLIi8:
3987  if (!hasV7Ops)
3988  return MCDisassembler::Fail;
3989  break;
3990  case ARM::t2PLDWi8:
3991  if (!hasV7Ops || !hasMP)
3992  return MCDisassembler::Fail;
3993  break;
3994  default:
3995  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3996  return MCDisassembler::Fail;
3997  }
3998 
3999  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4000  return MCDisassembler::Fail;
4001  return S;
4002 }
4003 
4005  uint64_t Address, const void* Decoder) {
4007 
4008  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4009  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4010  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4011  imm |= (Rn << 13);
4012 
4013  const FeatureBitset &featureBits =
4014  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4015 
4016  bool hasMP = featureBits[ARM::FeatureMP];
4017  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4018 
4019  if (Rn == 15) {
4020  switch (Inst.getOpcode()) {
4021  case ARM::t2LDRi12:
4022  Inst.setOpcode(ARM::t2LDRpci);
4023  break;
4024  case ARM::t2LDRHi12:
4025  Inst.setOpcode(ARM::t2LDRHpci);
4026  break;
4027  case ARM::t2LDRSHi12:
4028  Inst.setOpcode(ARM::t2LDRSHpci);
4029  break;
4030  case ARM::t2LDRBi12:
4031  Inst.setOpcode(ARM::t2LDRBpci);
4032  break;
4033  case ARM::t2LDRSBi12:
4034  Inst.setOpcode(ARM::t2LDRSBpci);
4035  break;
4036  case ARM::t2PLDi12:
4037  Inst.setOpcode(ARM::t2PLDpci);
4038  break;
4039  case ARM::t2PLIi12:
4040  Inst.setOpcode(ARM::t2PLIpci);
4041  break;
4042  default:
4043  return MCDisassembler::Fail;
4044  }
4045  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4046  }
4047 
4048  if (Rt == 15) {
4049  switch (Inst.getOpcode()) {
4050  case ARM::t2LDRSHi12:
4051  return MCDisassembler::Fail;
4052  case ARM::t2LDRHi12:
4053  Inst.setOpcode(ARM::t2PLDWi12);
4054  break;
4055  case ARM::t2LDRSBi12:
4056  Inst.setOpcode(ARM::t2PLIi12);
4057  break;
4058  default:
4059  break;
4060  }
4061  }
4062 
4063  switch (Inst.getOpcode()) {
4064  case ARM::t2PLDi12:
4065  break;
4066  case ARM::t2PLIi12:
4067  if (!hasV7Ops)
4068  return MCDisassembler::Fail;
4069  break;
4070  case ARM::t2PLDWi12:
4071  if (!hasV7Ops || !hasMP)
4072  return MCDisassembler::Fail;
4073  break;
4074  default:
4075  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4076  return MCDisassembler::Fail;
4077  }
4078 
4079  if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
4080  return MCDisassembler::Fail;
4081  return S;
4082 }
4083 
4084 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
4085  uint64_t Address, const void* Decoder) {
4087 
4088  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4089  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4090  unsigned imm = fieldFromInstruction(Insn, 0, 8);
4091  imm |= (Rn << 9);
4092 
4093  if (Rn == 15) {
4094  switch (Inst.getOpcode()) {
4095  case ARM::t2LDRT:
4096  Inst.setOpcode(ARM::t2LDRpci);
4097  break;
4098  case ARM::t2LDRBT:
4099  Inst.setOpcode(ARM::t2LDRBpci);
4100  break;
4101  case ARM::t2LDRHT:
4102  Inst.setOpcode(ARM::t2LDRHpci);
4103  break;
4104  case ARM::t2LDRSBT:
4105  Inst.setOpcode(ARM::t2LDRSBpci);
4106  break;
4107  case ARM::t2LDRSHT:
4108  Inst.setOpcode(ARM::t2LDRSHpci);
4109  break;
4110  default:
4111  return MCDisassembler::Fail;
4112  }
4113  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4114  }
4115 
4116  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4117  return MCDisassembler::Fail;
4118  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4119  return MCDisassembler::Fail;
4120  return S;
4121 }
4122 
4124  uint64_t Address, const void* Decoder) {
4126 
4127  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4128  unsigned U = fieldFromInstruction(Insn, 23, 1);
4129  int imm = fieldFromInstruction(Insn, 0, 12);
4130 
4131  const FeatureBitset &featureBits =
4132  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4133 
4134  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4135 
4136  if (Rt == 15) {
4137  switch (Inst.getOpcode()) {
4138  case ARM::t2LDRBpci:
4139  case ARM::t2LDRHpci:
4140  Inst.setOpcode(ARM::t2PLDpci);
4141  break;
4142  case ARM::t2LDRSBpci:
4143  Inst.setOpcode(ARM::t2PLIpci);
4144  break;
4145  case ARM::t2LDRSHpci:
4146  return MCDisassembler::Fail;
4147  default:
4148  break;
4149  }
4150  }
4151 
4152  switch(Inst.getOpcode()) {
4153  case ARM::t2PLDpci:
4154  break;
4155  case ARM::t2PLIpci:
4156  if (!hasV7Ops)
4157  return MCDisassembler::Fail;
4158  break;
4159  default:
4160  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4161  return MCDisassembler::Fail;
4162  }
4163 
4164  if (!U) {
4165  // Special case for #-0.
4166  if (imm == 0)
4167  imm = INT32_MIN;
4168  else
4169  imm = -imm;
4170  }
4171  Inst.addOperand(MCOperand::createImm(imm));
4172 
4173  return S;
4174 }
4175 
4176 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
4177  uint64_t Address, const void *Decoder) {
4178  if (Val == 0)
4179  Inst.addOperand(MCOperand::createImm(INT32_MIN));
4180  else {
4181  int imm = Val & 0xFF;
4182 
4183  if (!(Val & 0x100)) imm *= -1;
4184  Inst.addOperand(MCOperand::createImm(imm * 4));
4185  }
4186 
4187  return MCDisassembler::Success;
4188 }
4189 
4190 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
4191  const void *Decoder) {
4192  if (Val == 0)
4193  Inst.addOperand(MCOperand::createImm(INT32_MIN));
4194  else {
4195  int imm = Val & 0x7F;
4196 
4197  if (!(Val & 0x80))
4198  imm *= -1;
4199  Inst.addOperand(MCOperand::createImm(imm * 4));
4200  }
4201 
4202  return MCDisassembler::Success;
4203 }
4204 
4205 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
4206  uint64_t Address, const void *Decoder) {
4208 
4209  unsigned Rn = fieldFromInstruction(Val, 9, 4);
4210  unsigned imm = fieldFromInstruction(Val, 0, 9);
4211 
4212  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4213  return MCDisassembler::Fail;
4214  if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
4215  return MCDisassembler::Fail;
4216 
4217  return S;
4218 }
4219 
4220 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
4221  uint64_t Address,
4222  const void *Decoder) {
4224 
4225  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4226  unsigned imm = fieldFromInstruction(Val, 0, 8);
4227 
4228  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4229  return MCDisassembler::Fail;
4230  if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
4231  return MCDisassembler::Fail;
4232 
4233  return S;
4234 }
4235 
4237  uint64_t Address, const void *Decoder) {
4239 
4240  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4241  unsigned imm = fieldFromInstruction(Val, 0, 8);
4242 
4243  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4244  return MCDisassembler::Fail;
4245 
4246  Inst.addOperand(MCOperand::createImm(imm));
4247 
4248  return S;
4249 }
4250 
4251 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
4252  uint64_t Address, const void *Decoder) {
4253  int imm = Val & 0xFF;
4254  if (Val == 0)
4255  imm = INT32_MIN;
4256  else if (!(Val & 0x100))
4257  imm *= -1;
4258  Inst.addOperand(MCOperand::createImm(imm));
4259 
4260  return MCDisassembler::Success;
4261 }
4262 
4263 template<int shift>
4264 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
4265  uint64_t Address, const void *Decoder) {
4266  int imm = Val & 0x7F;
4267  if (Val == 0)
4268  imm = INT32_MIN;
4269  else if (!(Val & 0x80))
4270  imm *= -1;
4271  if (imm != INT32_MIN)
4272  imm *= (1U << shift);
4273  Inst.addOperand(MCOperand::createImm(imm));
4274 
4275  return MCDisassembler::Success;
4276 }
4277 
4278 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
4279  uint64_t Address, const void *Decoder) {
4281 
4282  unsigned Rn = fieldFromInstruction(Val, 9, 4);
4283  unsigned imm = fieldFromInstruction(Val, 0, 9);
4284 
4285  // Thumb stores cannot use PC as dest register.
4286  switch (Inst.getOpcode()) {
4287  case ARM::t2STRT:
4288  case ARM::t2STRBT:
4289  case ARM::t2STRHT:
4290  case ARM::t2STRi8:
4291  case ARM::t2STRHi8:
4292  case ARM::t2STRBi8:
4293  if (Rn == 15)
4294  return MCDisassembler::Fail;
4295  break;
4296  default:
4297  break;
4298  }
4299 
4300  // Some instructions always use an additive offset.
4301  switch (Inst.getOpcode()) {
4302  case ARM::t2LDRT:
4303  case ARM::t2LDRBT:
4304  case ARM::t2LDRHT:
4305  case ARM::t2LDRSBT:
4306  case ARM::t2LDRSHT:
4307  case ARM::t2STRT:
4308  case ARM::t2STRBT:
4309  case ARM::t2STRHT:
4310  imm |= 0x100;
4311  break;
4312  default:
4313  break;
4314  }
4315 
4316  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4317  return MCDisassembler::Fail;
4318  if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
4319  return MCDisassembler::Fail;
4320 
4321  return S;
4322 }
4323 
4324 template<int shift>
4325 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
4326  uint64_t Address,
4327  const void *Decoder) {
4329 
4330  unsigned Rn = fieldFromInstruction(Val, 8, 3);
4331  unsigned imm = fieldFromInstruction(Val, 0, 8);
4332 
4333  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4334  return MCDisassembler::Fail;
4335  if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4336  return MCDisassembler::Fail;
4337 
4338  return S;
4339 }
4340 
4341 template<int shift, int WriteBack>
4342 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
4343  uint64_t Address,
4344  const void *Decoder) {
4346 
4347  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4348  unsigned imm = fieldFromInstruction(Val, 0, 8);
4349  if (WriteBack) {
4350  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4351  return MCDisassembler::Fail;
4352  } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4353  return MCDisassembler::Fail;
4354  if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4355  return MCDisassembler::Fail;
4356 
4357  return S;
4358 }
4359 
4360 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
4361  uint64_t Address, const void *Decoder) {
4363 
4364  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4365  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4366  unsigned addr = fieldFromInstruction(Insn, 0, 8);
4367  addr |= fieldFromInstruction(Insn, 9, 1) << 8;
4368  addr |= Rn << 9;
4369  unsigned load = fieldFromInstruction(Insn, 20, 1);
4370 
4371  if (Rn == 15) {
4372  switch (Inst.getOpcode()) {
4373  case ARM::t2LDR_PRE:
4374  case ARM::t2LDR_POST:
4375  Inst.setOpcode(ARM::t2LDRpci);
4376  break;
4377  case ARM::t2LDRB_PRE:
4378  case ARM::t2LDRB_POST:
4379  Inst.setOpcode(ARM::t2LDRBpci);
4380  break;
4381  case ARM::t2LDRH_PRE:
4382  case ARM::t2LDRH_POST:
4383  Inst.setOpcode(ARM::t2LDRHpci);
4384  break;
4385  case ARM::t2LDRSB_PRE:
4386  case ARM::t2LDRSB_POST:
4387  if (Rt == 15)
4388  Inst.setOpcode(ARM::t2PLIpci);
4389  else
4390  Inst.setOpcode(ARM::t2LDRSBpci);
4391  break;
4392  case ARM::t2LDRSH_PRE:
4393  case ARM::t2LDRSH_POST:
4394  Inst.setOpcode(ARM::t2LDRSHpci);
4395  break;
4396  default:
4397  return MCDisassembler::Fail;
4398  }
4399  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4400  }
4401 
4402  if (!load) {
4403  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4404  return MCDisassembler::Fail;
4405  }
4406 
4407  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4408  return MCDisassembler::Fail;
4409 
4410  if (load) {
4411  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4412  return MCDisassembler::Fail;
4413  }
4414 
4415  if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
4416  return MCDisassembler::Fail;
4417 
4418  return S;
4419 }
4420 
4421 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
4422  uint64_t Address, const void *Decoder) {
4424 
4425  unsigned Rn = fieldFromInstruction(Val, 13, 4);
4426  unsigned imm = fieldFromInstruction(Val, 0, 12);
4427 
4428  // Thumb stores cannot use PC as dest register.
4429  switch (Inst.getOpcode()) {
4430  case ARM::t2STRi12:
4431  case ARM::t2STRBi12:
4432  case ARM::t2STRHi12:
4433  if (Rn == 15)
4434  return MCDisassembler::Fail;
4435  break;
4436  default:
4437  break;
4438  }
4439 
4440  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4441  return MCDisassembler::Fail;
4442  Inst.addOperand(MCOperand::createImm(imm));
4443 
4444  return S;
4445 }
4446 
4448  uint64_t Address, const void *Decoder) {
4449  unsigned imm = fieldFromInstruction(Insn, 0, 7);
4450 
4451  Inst.addOperand(MCOperand::createReg(ARM::SP));
4452  Inst.addOperand(MCOperand::createReg(ARM::SP));
4453  Inst.addOperand(MCOperand::createImm(imm));
4454 
4455  return MCDisassembler::Success;
4456 }
4457 
4459  uint64_t Address, const void *Decoder) {
4461 
4462  if (Inst.getOpcode() == ARM::tADDrSP) {
4463  unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
4464  Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
4465 
4466  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4467  return MCDisassembler::Fail;
4468  Inst.addOperand(MCOperand::createReg(ARM::SP));
4469  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4470  return MCDisassembler::Fail;
4471  } else if (Inst.getOpcode() == ARM::tADDspr) {
4472  unsigned Rm = fieldFromInstruction(Insn, 3, 4);
4473 
4474  Inst.addOperand(MCOperand::createReg(ARM::SP));
4475  Inst.addOperand(MCOperand::createReg(ARM::SP));
4476  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4477  return MCDisassembler::Fail;
4478  }
4479 
4480  return S;
4481 }
4482 
4484  uint64_t Address, const void *Decoder) {
4485  unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
4486  unsigned flags = fieldFromInstruction(Insn, 0, 3);
4487 
4488  Inst.addOperand(MCOperand::createImm(imod));
4489  Inst.addOperand(MCOperand::createImm(flags));
4490 
4491  return MCDisassembler::Success;
4492 }
4493 
4494 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
4495  uint64_t Address, const void *Decoder) {
4497  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4498  unsigned add = fieldFromInstruction(Insn, 4, 1);
4499 
4500  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
4501  return MCDisassembler::Fail;
4503 
4504  return S;
4505 }
4506 
4508  uint64_t Address, const void *Decoder) {
4510  unsigned Rn = fieldFromInstruction(Insn, 3, 4);
4511  unsigned Qm = fieldFromInstruction(Insn, 0, 3);
4512 
4513  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4514  return MCDisassembler::Fail;
4515  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4516  return MCDisassembler::Fail;
4517 
4518  return S;
4519 }
4520 
4521 template<int shift>
4523  uint64_t Address, const void *Decoder) {
4525  unsigned Qm = fieldFromInstruction(Insn, 8, 3);
4526  int imm = fieldFromInstruction(Insn, 0, 7);
4527 
4528  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4529  return MCDisassembler::Fail;
4530 
4531  if(!fieldFromInstruction(Insn, 7, 1)) {
4532  if (imm == 0)
4533  imm = INT32_MIN; // indicate -0
4534  else
4535  imm *= -1;
4536  }
4537  if (imm != INT32_MIN)
4538  imm *= (1U << shift);
4539  Inst.addOperand(MCOperand::createImm(imm));
4540 
4541  return S;
4542 }
4543 
4544 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
4545  uint64_t Address, const void *Decoder) {
4546  // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
4547  // Note only one trailing zero not two. Also the J1 and J2 values are from
4548  // the encoded instruction. So here change to I1 and I2 values via:
4549  // I1 = NOT(J1 EOR S);
4550  // I2 = NOT(J2 EOR S);
4551  // and build the imm32 with two trailing zeros as documented:
4552  // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
4553  unsigned S = (Val >> 23) & 1;
4554  unsigned J1 = (Val >> 22) & 1;
4555  unsigned J2 = (Val >> 21) & 1;
4556  unsigned I1 = !(J1 ^ S);
4557  unsigned I2 = !(J2 ^ S);
4558  unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4559  int imm32 = SignExtend32<25>(tmp << 1);
4560 
4562  (Address & ~2u) + imm32 + 4,
4563  true, 4, Inst, Decoder))
4564  Inst.addOperand(MCOperand::createImm(imm32));
4565  return MCDisassembler::Success;
4566 }
4567 
4568 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
4569  uint64_t Address, const void *Decoder) {
4570  if (Val == 0xA || Val == 0xB)
4571  return MCDisassembler::Fail;
4572 
4573  const FeatureBitset &featureBits =
4574  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4575 
4576  if (!isValidCoprocessorNumber(Val, featureBits))
4577  return MCDisassembler::Fail;
4578 
4579  Inst.addOperand(MCOperand::createImm(Val));
4580  return MCDisassembler::Success;
4581 }
4582 
4583 static DecodeStatus
4585  uint64_t Address, const void *Decoder) {
4586  const FeatureBitset &FeatureBits =
4587  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4589 
4590  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4591  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4592 
4593  if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail;
4594  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4595  return MCDisassembler::Fail;
4596  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4597  return MCDisassembler::Fail;
4598  return S;
4599 }
4600 
4601 static