LLVM  16.0.0git
ARMDisassembler.cpp
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1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ARMBaseInstrInfo.h"
14 #include "Utils/ARMBaseInfo.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCDecoderOps.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/TargetRegistry.h"
23 #include "llvm/Support/Compiler.h"
27 #include <algorithm>
28 #include <cassert>
29 #include <cstdint>
30 #include <vector>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "arm-disassembler"
35 
37 
38 namespace {
39 
40  // Handles the condition code status of instructions in IT blocks
41  class ITStatus
42  {
43  public:
44  // Returns the condition code for instruction in IT block
45  unsigned getITCC() {
46  unsigned CC = ARMCC::AL;
47  if (instrInITBlock())
48  CC = ITStates.back();
49  return CC;
50  }
51 
52  // Advances the IT block state to the next T or E
53  void advanceITState() {
54  ITStates.pop_back();
55  }
56 
57  // Returns true if the current instruction is in an IT block
58  bool instrInITBlock() {
59  return !ITStates.empty();
60  }
61 
62  // Returns true if current instruction is the last instruction in an IT block
63  bool instrLastInITBlock() {
64  return ITStates.size() == 1;
65  }
66 
67  // Called when decoding an IT instruction. Sets the IT state for
68  // the following instructions that for the IT block. Firstcond
69  // corresponds to the field in the IT instruction encoding; Mask
70  // is in the MCOperand format in which 1 means 'else' and 0 'then'.
71  void setITState(char Firstcond, char Mask) {
72  // (3 - the number of trailing zeros) is the number of then / else.
73  unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
74  unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
75  assert(NumTZ <= 3 && "Invalid IT mask!");
76  // push condition codes onto the stack the correct order for the pops
77  for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
78  unsigned Else = (Mask >> Pos) & 1;
79  ITStates.push_back(CCBits ^ Else);
80  }
81  ITStates.push_back(CCBits);
82  }
83 
84  private:
85  std::vector<unsigned char> ITStates;
86  };
87 
88  class VPTStatus
89  {
90  public:
91  unsigned getVPTPred() {
92  unsigned Pred = ARMVCC::None;
93  if (instrInVPTBlock())
94  Pred = VPTStates.back();
95  return Pred;
96  }
97 
98  void advanceVPTState() {
99  VPTStates.pop_back();
100  }
101 
102  bool instrInVPTBlock() {
103  return !VPTStates.empty();
104  }
105 
106  bool instrLastInVPTBlock() {
107  return VPTStates.size() == 1;
108  }
109 
110  void setVPTState(char Mask) {
111  // (3 - the number of trailing zeros) is the number of then / else.
112  unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
113  assert(NumTZ <= 3 && "Invalid VPT mask!");
114  // push predicates onto the stack the correct order for the pops
115  for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
116  bool T = ((Mask >> Pos) & 1) == 0;
117  if (T)
118  VPTStates.push_back(ARMVCC::Then);
119  else
120  VPTStates.push_back(ARMVCC::Else);
121  }
122  VPTStates.push_back(ARMVCC::Then);
123  }
124 
125  private:
127  };
128 
129 /// ARM disassembler for all ARM platforms.
130 class ARMDisassembler : public MCDisassembler {
131 public:
132  ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
133  MCDisassembler(STI, Ctx) {
134  InstructionEndianness = STI.getFeatureBits()[ARM::ModeBigEndianInstructions]
137  }
138 
139  ~ARMDisassembler() override = default;
140 
141  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
142  ArrayRef<uint8_t> Bytes, uint64_t Address,
143  raw_ostream &CStream) const override;
144 
145  uint64_t suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
146  uint64_t Address) const override;
147 
148 private:
149  DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size,
150  ArrayRef<uint8_t> Bytes, uint64_t Address,
151  raw_ostream &CStream) const;
152 
153  DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,
154  ArrayRef<uint8_t> Bytes, uint64_t Address,
155  raw_ostream &CStream) const;
156 
157  mutable ITStatus ITBlock;
158  mutable VPTStatus VPTBlock;
159 
160  DecodeStatus AddThumbPredicate(MCInst&) const;
161  void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
162 
163  llvm::support::endianness InstructionEndianness;
164 };
165 
166 } // end anonymous namespace
167 
168 // Forward declare these because the autogenerated code will reference them.
169 // Definitions are further down.
170 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
171  uint64_t Address,
172  const MCDisassembler *Decoder);
173 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
174  uint64_t Address,
175  const MCDisassembler *Decoder);
176 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
177  uint64_t Address,
178  const MCDisassembler *Decoder);
179 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
180  uint64_t Address,
181  const MCDisassembler *Decoder);
182 static DecodeStatus
183 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
184  uint64_t Address,
185  const MCDisassembler *Decoder);
186 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
187  uint64_t Address,
188  const MCDisassembler *Decoder);
189 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
190  uint64_t Address,
191  const MCDisassembler *Decoder);
192 static DecodeStatus
193 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
194  const MCDisassembler *Decoder);
195 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
196  uint64_t Address,
197  const MCDisassembler *Decoder);
198 static DecodeStatus
199 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
200  const MCDisassembler *Decoder);
201 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
202  uint64_t Address,
203  const MCDisassembler *Decoder);
204 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
205  uint64_t Address,
206  const MCDisassembler *Decoder);
207 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
208  uint64_t Address,
209  const MCDisassembler *Decoder);
210 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
211  uint64_t Address,
212  const MCDisassembler *Decoder);
213 static DecodeStatus
214 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
215  const MCDisassembler *Decoder);
216 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
217  uint64_t Address,
218  const MCDisassembler *Decoder);
219 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
220  uint64_t Address,
221  const MCDisassembler *Decoder);
222 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
223  uint64_t Address,
224  const MCDisassembler *Decoder);
225 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
226  uint64_t Address,
227  const MCDisassembler *Decoder);
228 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
229  uint64_t Address,
230  const MCDisassembler *Decoder);
231 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
232  uint64_t Address,
233  const MCDisassembler *Decoder);
234 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
235  uint64_t Address,
236  const MCDisassembler *Decoder);
237 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
238  uint64_t Address,
239  const MCDisassembler *Decoder);
240 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
241  uint64_t Address,
242  const MCDisassembler *Decoder);
243 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
244  uint64_t Address,
245  const MCDisassembler *Decoder);
246 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
247  uint64_t Address,
248  const MCDisassembler *Decoder);
249 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
250  uint64_t Address,
251  const MCDisassembler *Decoder);
252 static DecodeStatus
253 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
254  const MCDisassembler *Decoder);
255 
256 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
257  uint64_t Address,
258  const MCDisassembler *Decoder);
259 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
260  uint64_t Address,
261  const MCDisassembler *Decoder);
262 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
263  uint64_t Address,
264  const MCDisassembler *Decoder);
265 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
266  uint64_t Address,
267  const MCDisassembler *Decoder);
268 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
269  uint64_t Address,
270  const MCDisassembler *Decoder);
271 
272 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
273  uint64_t Address,
274  const MCDisassembler *Decoder);
275 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
276  uint64_t Address,
277  const MCDisassembler *Decoder);
278 static DecodeStatus
279 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
280  const MCDisassembler *Decoder);
281 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
282  uint64_t Address,
283  const MCDisassembler *Decoder);
284 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
285  uint64_t Address,
286  const MCDisassembler *Decoder);
287 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
288  uint64_t Address,
289  const MCDisassembler *Decoder);
290 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
291  uint64_t Address,
292  const MCDisassembler *Decoder);
293 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
294  uint64_t Address,
295  const MCDisassembler *Decoder);
296 
297 static DecodeStatus
299  uint64_t Adddress,
300  const MCDisassembler *Decoder);
301 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
302  uint64_t Address,
303  const MCDisassembler *Decoder);
304 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
305  uint64_t Address,
306  const MCDisassembler *Decoder);
307 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
308  uint64_t Address,
309  const MCDisassembler *Decoder);
310 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
311  uint64_t Address,
312  const MCDisassembler *Decoder);
313 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
314  uint64_t Address,
315  const MCDisassembler *Decoder);
316 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
317  uint64_t Address,
318  const MCDisassembler *Decoder);
319 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
320  uint64_t Address,
321  const MCDisassembler *Decoder);
322 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
323  uint64_t Address,
324  const MCDisassembler *Decoder);
326  uint64_t Address,
327  const MCDisassembler *Decoder);
328 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
329  uint64_t Address,
330  const MCDisassembler *Decoder);
331 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
332  uint64_t Address,
333  const MCDisassembler *Decoder);
334 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
335  uint64_t Address,
336  const MCDisassembler *Decoder);
337 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
338  uint64_t Address,
339  const MCDisassembler *Decoder);
340 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
341  uint64_t Address,
342  const MCDisassembler *Decoder);
343 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
344  uint64_t Address,
345  const MCDisassembler *Decoder);
346 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
347  uint64_t Address,
348  const MCDisassembler *Decoder);
349 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
350  uint64_t Address,
351  const MCDisassembler *Decoder);
352 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
353  uint64_t Address,
354  const MCDisassembler *Decoder);
355 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
356  uint64_t Address,
357  const MCDisassembler *Decoder);
358 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
359  uint64_t Address,
360  const MCDisassembler *Decoder);
361 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
362  uint64_t Address,
363  const MCDisassembler *Decoder);
364 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
365  uint64_t Address,
366  const MCDisassembler *Decoder);
367 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
368  uint64_t Address,
369  const MCDisassembler *Decoder);
370 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
371  uint64_t Address,
372  const MCDisassembler *Decoder);
373 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
374  uint64_t Address,
375  const MCDisassembler *Decoder);
376 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
377  uint64_t Address,
378  const MCDisassembler *Decoder);
379 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val,
380  uint64_t Address,
381  const MCDisassembler *Decoder);
382 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val,
383  uint64_t Address,
384  const MCDisassembler *Decoder);
385 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
386  uint64_t Address,
387  const MCDisassembler *Decoder);
388 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
389  uint64_t Address,
390  const MCDisassembler *Decoder);
391 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
392  uint64_t Address,
393  const MCDisassembler *Decoder);
394 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
395  uint64_t Address,
396  const MCDisassembler *Decoder);
397 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
398  uint64_t Address,
399  const MCDisassembler *Decoder);
400 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
401  uint64_t Address,
402  const MCDisassembler *Decoder);
403 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
404  uint64_t Address,
405  const MCDisassembler *Decoder);
406 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
407  uint64_t Address,
408  const MCDisassembler *Decoder);
409 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
410  uint64_t Address,
411  const MCDisassembler *Decoder);
412 template <int shift>
413 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
414  uint64_t Address,
415  const MCDisassembler *Decoder);
416 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
417  uint64_t Address,
418  const MCDisassembler *Decoder);
419 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
420  uint64_t Address,
421  const MCDisassembler *Decoder);
422 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
423  uint64_t Address,
424  const MCDisassembler *Decoder);
425 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address,
426  const MCDisassembler *Decoder);
427 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
428  uint64_t Address,
429  const MCDisassembler *Decoder);
430 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
431  uint64_t Address,
432  const MCDisassembler *Decoder);
433 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
434  uint64_t Address,
435  const MCDisassembler *Decoder);
436 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
437  uint64_t Address,
438  const MCDisassembler *Decoder);
439 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
440  uint64_t Address,
441  const MCDisassembler *Decoder);
442 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
443  uint64_t Address,
444  const MCDisassembler *Decoder);
445 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
446  uint64_t Address,
447  const MCDisassembler *Decoder);
448 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
449  const MCDisassembler *Decoder);
450 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
451  const MCDisassembler *Decoder);
452 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
453  const MCDisassembler *Decoder);
454 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
455  const MCDisassembler *Decoder);
456 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
457  const MCDisassembler *Decoder);
458 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
459  const MCDisassembler *Decoder);
460 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
461  const MCDisassembler *Decoder);
462 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
463  const MCDisassembler *Decoder);
464 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
465  const MCDisassembler *Decoder);
466 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
467  const MCDisassembler *Decoder);
468 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
469  const MCDisassembler *Decoder);
470 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
471  const MCDisassembler *Decoder);
472 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
473  const MCDisassembler *Decoder);
474 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
475  uint64_t Address,
476  const MCDisassembler *Decoder);
477 static DecodeStatus
478 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address,
479  const MCDisassembler *Decoder);
480 
482  uint64_t Address,
483  const MCDisassembler *Decoder);
484 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
485  uint64_t Address,
486  const MCDisassembler *Decoder);
487 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
488  uint64_t Address,
489  const MCDisassembler *Decoder);
490 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
491  uint64_t Address,
492  const MCDisassembler *Decoder);
493 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
494  uint64_t Address,
495  const MCDisassembler *Decoder);
496 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
497  uint64_t Address,
498  const MCDisassembler *Decoder);
499 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
500  uint64_t Address,
501  const MCDisassembler *Decoder);
502 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
503  uint64_t Address,
504  const MCDisassembler *Decoder);
505 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
506  uint64_t Address,
507  const MCDisassembler *Decoder);
508 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
509  uint64_t Address,
510  const MCDisassembler *Decoder);
511 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
512  uint64_t Address,
513  const MCDisassembler *Decoder);
514 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
515  uint64_t Address,
516  const MCDisassembler *Decoder);
517 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
518  const MCDisassembler *Decoder);
519 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
520  uint64_t Address,
521  const MCDisassembler *Decoder);
522 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
523  const MCDisassembler *Decoder);
524 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
525  const MCDisassembler *Decoder);
526 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
527  uint64_t Address,
528  const MCDisassembler *Decoder);
529 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
530  uint64_t Address,
531  const MCDisassembler *Decoder);
532 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val,
533  uint64_t Address,
534  const MCDisassembler *Decoder);
535 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
536  const MCDisassembler *Decoder);
537 template <int shift>
538 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
539  const MCDisassembler *Decoder);
540 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
541  uint64_t Address,
542  const MCDisassembler *Decoder);
543 template <int shift>
544 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
545  uint64_t Address,
546  const MCDisassembler *Decoder);
547 template <int shift, int WriteBack>
548 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
549  uint64_t Address,
550  const MCDisassembler *Decoder);
552  uint64_t Address,
553  const MCDisassembler *Decoder);
555  uint64_t Address,
556  const MCDisassembler *Decoder);
558  uint64_t Address,
559  const MCDisassembler *Decoder);
560 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
561  uint64_t Address,
562  const MCDisassembler *Decoder);
563 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
564  uint64_t Address,
565  const MCDisassembler *Decoder);
566 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
567  uint64_t Address,
568  const MCDisassembler *Decoder);
569 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
570  uint64_t Address,
571  const MCDisassembler *Decoder);
572 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
573  uint64_t Address,
574  const MCDisassembler *Decoder);
575 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
576  const MCDisassembler *Decoder);
577 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
578  uint64_t Address,
579  const MCDisassembler *Decoder);
580 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
581  uint64_t Address,
582  const MCDisassembler *Decoder);
583 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address,
584  const MCDisassembler *Decoder);
585 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
586  uint64_t Address,
587  const MCDisassembler *Decoder);
588 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
589  uint64_t Address,
590  const MCDisassembler *Decoder);
591 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address,
592  const MCDisassembler *Decoder);
593 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
594  uint64_t Address,
595  const MCDisassembler *Decoder);
596 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
597  uint64_t Address,
598  const MCDisassembler *Decoder);
599 
600 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
601  const MCDisassembler *Decoder);
602 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
603  uint64_t Address,
604  const MCDisassembler *Decoder);
605 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
606  uint64_t Address,
607  const MCDisassembler *Decoder);
608 
609 template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
610 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
611  uint64_t Address,
612  const MCDisassembler *Decoder);
613 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
614  uint64_t Address,
615  const MCDisassembler *Decoder);
616 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
617  uint64_t Address,
618  const MCDisassembler *Decoder);
619 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
620  const MCDisassembler *Decoder);
621 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
622  uint64_t Address,
623  const MCDisassembler *Decoder);
624 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
625  const MCDisassembler *Decoder);
626 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
627  uint64_t Address,
628  const MCDisassembler *Decoder);
629 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
630  uint64_t Address,
631  const MCDisassembler *Decoder);
632 static DecodeStatus
633 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
634  const MCDisassembler *Decoder);
635 static DecodeStatus
636 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
637  const MCDisassembler *Decoder);
638 static DecodeStatus
639 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
640  const MCDisassembler *Decoder);
641 static DecodeStatus
642 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
643  const MCDisassembler *Decoder);
644 template <bool Writeback>
645 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
646  uint64_t Address,
647  const MCDisassembler *Decoder);
648 template <int shift>
649 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
650  uint64_t Address,
651  const MCDisassembler *Decoder);
652 template <int shift>
653 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
654  uint64_t Address,
655  const MCDisassembler *Decoder);
656 template <int shift>
657 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
658  uint64_t Address,
659  const MCDisassembler *Decoder);
660 template <unsigned MinLog, unsigned MaxLog>
661 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
662  uint64_t Address,
663  const MCDisassembler *Decoder);
664 template <unsigned start>
665 static DecodeStatus
666 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,
667  const MCDisassembler *Decoder);
668 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
669  uint64_t Address,
670  const MCDisassembler *Decoder);
671 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
672  uint64_t Address,
673  const MCDisassembler *Decoder);
674 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
675  uint64_t Address,
676  const MCDisassembler *Decoder);
677 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
678  uint64_t Address,
679  const MCDisassembler *Decoder);
680 template <bool scalar, OperandDecoder predicate_decoder>
681 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
682  const MCDisassembler *Decoder);
683 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
684  const MCDisassembler *Decoder);
685 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
686  uint64_t Address,
687  const MCDisassembler *Decoder);
688 static DecodeStatus
689 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
690  const MCDisassembler *Decoder);
691 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
692  uint64_t Address,
693  const MCDisassembler *Decoder);
694 
695 #include "ARMGenDisassemblerTables.inc"
696 
698  const MCSubtargetInfo &STI,
699  MCContext &Ctx) {
700  return new ARMDisassembler(STI, Ctx);
701 }
702 
703 // Post-decoding checks
705  uint64_t Address, raw_ostream &CS,
706  uint32_t Insn,
707  DecodeStatus Result) {
708  switch (MI.getOpcode()) {
709  case ARM::HVC: {
710  // HVC is undefined if condition = 0xf otherwise upredictable
711  // if condition != 0xe
712  uint32_t Cond = (Insn >> 28) & 0xF;
713  if (Cond == 0xF)
714  return MCDisassembler::Fail;
715  if (Cond != 0xE)
717  return Result;
718  }
719  case ARM::t2ADDri:
720  case ARM::t2ADDri12:
721  case ARM::t2ADDrr:
722  case ARM::t2ADDrs:
723  case ARM::t2SUBri:
724  case ARM::t2SUBri12:
725  case ARM::t2SUBrr:
726  case ARM::t2SUBrs:
727  if (MI.getOperand(0).getReg() == ARM::SP &&
728  MI.getOperand(1).getReg() != ARM::SP)
730  return Result;
731  default: return Result;
732  }
733 }
734 
735 uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
736  uint64_t Address) const {
737  // In Arm state, instructions are always 4 bytes wide, so there's no
738  // point in skipping any smaller number of bytes if an instruction
739  // can't be decoded.
740  if (!STI.getFeatureBits()[ARM::ModeThumb])
741  return 4;
742 
743  // In a Thumb instruction stream, a halfword is a standalone 2-byte
744  // instruction if and only if its value is less than 0xE800.
745  // Otherwise, it's the first halfword of a 4-byte instruction.
746  //
747  // So, if we can see the upcoming halfword, we can judge on that
748  // basis, and maybe skip a whole 4-byte instruction that we don't
749  // know how to decode, without accidentally trying to interpret its
750  // second half as something else.
751  //
752  // If we don't have the instruction data available, we just have to
753  // recommend skipping the minimum sensible distance, which is 2
754  // bytes.
755  if (Bytes.size() < 2)
756  return 2;
757 
758  uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
759  Bytes.data(), InstructionEndianness);
760  return Insn16 < 0xE800 ? 2 : 4;
761 }
762 
763 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
764  ArrayRef<uint8_t> Bytes,
765  uint64_t Address,
766  raw_ostream &CS) const {
767  if (STI.getFeatureBits()[ARM::ModeThumb])
768  return getThumbInstruction(MI, Size, Bytes, Address, CS);
769  return getARMInstruction(MI, Size, Bytes, Address, CS);
770 }
771 
772 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
773  ArrayRef<uint8_t> Bytes,
774  uint64_t Address,
775  raw_ostream &CS) const {
776  CommentStream = &CS;
777 
778  assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
779  "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
780  "mode!");
781 
782  // We want to read exactly 4 bytes of data.
783  if (Bytes.size() < 4) {
784  Size = 0;
785  return MCDisassembler::Fail;
786  }
787 
788  // Encoded as a 32-bit word in the stream.
789  uint32_t Insn = llvm::support::endian::read<uint32_t>(Bytes.data(),
790  InstructionEndianness);
791 
792  // Calling the auto-generated decoder function.
794  decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
795  if (Result != MCDisassembler::Fail) {
796  Size = 4;
797  return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
798  }
799 
800  struct DecodeTable {
801  const uint8_t *P;
802  bool DecodePred;
803  };
804 
805  const DecodeTable Tables[] = {
806  {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
807  {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
808  {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
809  {DecoderTablev8Crypto32, false},
810  };
811 
812  for (auto Table : Tables) {
813  Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
814  if (Result != MCDisassembler::Fail) {
815  Size = 4;
816  // Add a fake predicate operand, because we share these instruction
817  // definitions with Thumb2 where these instructions are predicable.
818  if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
819  return MCDisassembler::Fail;
820  return Result;
821  }
822  }
823 
824  Result =
825  decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
826  if (Result != MCDisassembler::Fail) {
827  Size = 4;
828  return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
829  }
830 
831  Size = 4;
832  return MCDisassembler::Fail;
833 }
834 
835 namespace llvm {
836 
837 extern const MCInstrDesc ARMInsts[];
838 
839 } // end namespace llvm
840 
841 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
842 /// immediate Value in the MCInst. The immediate Value has had any PC
843 /// adjustment made by the caller. If the instruction is a branch instruction
844 /// then isBranch is true, else false. If the getOpInfo() function was set as
845 /// part of the setupForSymbolicDisassembly() call then that function is called
846 /// to get any symbolic information at the Address for this instruction. If
847 /// that returns non-zero then the symbolic information it returns is used to
848 /// create an MCExpr and that is added as an operand to the MCInst. If
849 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
850 /// Value is done and if a symbol is found an MCExpr is created with that, else
851 /// an MCExpr with Value is created. This function returns true if it adds an
852 /// operand to the MCInst and false otherwise.
853 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
854  bool isBranch, uint64_t InstSize,
855  MCInst &MI,
856  const MCDisassembler *Decoder) {
857  // FIXME: Does it make sense for value to be negative?
858  return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address,
859  isBranch, /*Offset=*/0, /*OpSize=*/0,
860  InstSize);
861 }
862 
863 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
864 /// referenced by a load instruction with the base register that is the Pc.
865 /// These can often be values in a literal pool near the Address of the
866 /// instruction. The Address of the instruction and its immediate Value are
867 /// used as a possible literal pool entry. The SymbolLookUp call back will
868 /// return the name of a symbol referenced by the literal pool's entry if
869 /// the referenced address is that of a symbol. Or it will return a pointer to
870 /// a literal 'C' string if the referenced address of the literal pool's entry
871 /// is an address into a section with 'C' string literals.
873  const MCDisassembler *Decoder) {
874  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
875  Dis->tryAddingPcLoadReferenceComment(Value, Address);
876 }
877 
878 // Thumb1 instructions don't have explicit S bits. Rather, they
879 // implicitly set CPSR. Since it's not represented in the encoding, the
880 // auto-generated decoder won't inject the CPSR operand. We need to fix
881 // that as a post-pass.
882 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
883  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
884  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
885  MCInst::iterator I = MI.begin();
886  for (unsigned i = 0; i < NumOps; ++i, ++I) {
887  if (I == MI.end()) break;
888  if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
889  if (i > 0 && OpInfo[i-1].isPredicate()) continue;
890  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
891  return;
892  }
893  }
894 
895  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
896 }
897 
898 static bool isVectorPredicable(unsigned Opcode) {
899  const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
900  unsigned short NumOps = ARMInsts[Opcode].NumOperands;
901  for (unsigned i = 0; i < NumOps; ++i) {
902  if (ARM::isVpred(OpInfo[i].OperandType))
903  return true;
904  }
905  return false;
906 }
907 
908 // Most Thumb instructions don't have explicit predicates in the
909 // encoding, but rather get their predicates from IT context. We need
910 // to fix up the predicate operands using this context information as a
911 // post-pass.
913 ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
915 
916  const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
917 
918  // A few instructions actually have predicates encoded in them. Don't
919  // try to overwrite it if we're seeing one of those.
920  switch (MI.getOpcode()) {
921  case ARM::tBcc:
922  case ARM::t2Bcc:
923  case ARM::tCBZ:
924  case ARM::tCBNZ:
925  case ARM::tCPS:
926  case ARM::t2CPS3p:
927  case ARM::t2CPS2p:
928  case ARM::t2CPS1p:
929  case ARM::t2CSEL:
930  case ARM::t2CSINC:
931  case ARM::t2CSINV:
932  case ARM::t2CSNEG:
933  case ARM::tMOVSr:
934  case ARM::tSETEND:
935  // Some instructions (mostly conditional branches) are not
936  // allowed in IT blocks.
937  if (ITBlock.instrInITBlock())
938  S = SoftFail;
939  else
940  return Success;
941  break;
942  case ARM::t2HINT:
943  if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
944  S = SoftFail;
945  break;
946  case ARM::tB:
947  case ARM::t2B:
948  case ARM::t2TBB:
949  case ARM::t2TBH:
950  // Some instructions (mostly unconditional branches) can
951  // only appears at the end of, or outside of, an IT.
952  if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
953  S = SoftFail;
954  break;
955  default:
956  break;
957  }
958 
959  // Warn on non-VPT predicable instruction in a VPT block and a VPT
960  // predicable instruction in an IT block
961  if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) ||
962  (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock()))
963  S = SoftFail;
964 
965  // If we're in an IT/VPT block, base the predicate on that. Otherwise,
966  // assume a predicate of AL.
967  unsigned CC = ARMCC::AL;
968  unsigned VCC = ARMVCC::None;
969  if (ITBlock.instrInITBlock()) {
970  CC = ITBlock.getITCC();
971  ITBlock.advanceITState();
972  } else if (VPTBlock.instrInVPTBlock()) {
973  VCC = VPTBlock.getVPTPred();
974  VPTBlock.advanceVPTState();
975  }
976 
977  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
978  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
979 
980  MCInst::iterator CCI = MI.begin();
981  for (unsigned i = 0; i < NumOps; ++i, ++CCI) {
982  if (OpInfo[i].isPredicate() || CCI == MI.end()) break;
983  }
984 
985  if (ARMInsts[MI.getOpcode()].isPredicable()) {
986  CCI = MI.insert(CCI, MCOperand::createImm(CC));
987  ++CCI;
988  if (CC == ARMCC::AL)
989  MI.insert(CCI, MCOperand::createReg(0));
990  else
991  MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
992  } else if (CC != ARMCC::AL) {
993  Check(S, SoftFail);
994  }
995 
996  MCInst::iterator VCCI = MI.begin();
997  unsigned VCCPos;
998  for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
999  if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break;
1000  }
1001 
1002  if (isVectorPredicable(MI.getOpcode())) {
1003  VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
1004  ++VCCI;
1005  if (VCC == ARMVCC::None)
1006  VCCI = MI.insert(VCCI, MCOperand::createReg(0));
1007  else
1008  VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0));
1009  ++VCCI;
1010  VCCI = MI.insert(VCCI, MCOperand::createReg(0));
1011  ++VCCI;
1012  if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
1013  int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint(
1014  VCCPos + 3, MCOI::TIED_TO);
1015  assert(TiedOp >= 0 &&
1016  "Inactive register in vpred_r is not tied to an output!");
1017  // Copy the operand to ensure it's not invalidated when MI grows.
1018  MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp)));
1019  }
1020  } else if (VCC != ARMVCC::None) {
1021  Check(S, SoftFail);
1022  }
1023 
1024  return S;
1025 }
1026 
1027 // Thumb VFP instructions are a special case. Because we share their
1028 // encodings between ARM and Thumb modes, and they are predicable in ARM
1029 // mode, the auto-generated decoder will give them an (incorrect)
1030 // predicate operand. We need to rewrite these operands based on the IT
1031 // context as a post-pass.
1032 void ARMDisassembler::UpdateThumbVFPPredicate(
1033  DecodeStatus &S, MCInst &MI) const {
1034  unsigned CC;
1035  CC = ITBlock.getITCC();
1036  if (CC == 0xF)
1037  CC = ARMCC::AL;
1038  if (ITBlock.instrInITBlock())
1039  ITBlock.advanceITState();
1040  else if (VPTBlock.instrInVPTBlock()) {
1041  CC = VPTBlock.getVPTPred();
1042  VPTBlock.advanceVPTState();
1043  }
1044 
1045  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
1046  MCInst::iterator I = MI.begin();
1047  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
1048  for (unsigned i = 0; i < NumOps; ++i, ++I) {
1049  if (OpInfo[i].isPredicate() ) {
1050  if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
1051  Check(S, SoftFail);
1052  I->setImm(CC);
1053  ++I;
1054  if (CC == ARMCC::AL)
1055  I->setReg(0);
1056  else
1057  I->setReg(ARM::CPSR);
1058  return;
1059  }
1060  }
1061 }
1062 
1063 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
1064  ArrayRef<uint8_t> Bytes,
1065  uint64_t Address,
1066  raw_ostream &CS) const {
1067  CommentStream = &CS;
1068 
1069  assert(STI.getFeatureBits()[ARM::ModeThumb] &&
1070  "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
1071 
1072  // We want to read exactly 2 bytes of data.
1073  if (Bytes.size() < 2) {
1074  Size = 0;
1075  return MCDisassembler::Fail;
1076  }
1077 
1078  uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
1079  Bytes.data(), InstructionEndianness);
1081  decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
1082  if (Result != MCDisassembler::Fail) {
1083  Size = 2;
1084  Check(Result, AddThumbPredicate(MI));
1085  return Result;
1086  }
1087 
1088  Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
1089  STI);
1090  if (Result) {
1091  Size = 2;
1092  bool InITBlock = ITBlock.instrInITBlock();
1093  Check(Result, AddThumbPredicate(MI));
1094  AddThumb1SBit(MI, InITBlock);
1095  return Result;
1096  }
1097 
1098  Result =
1099  decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
1100  if (Result != MCDisassembler::Fail) {
1101  Size = 2;
1102 
1103  // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
1104  // the Thumb predicate.
1105  if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
1107 
1108  Check(Result, AddThumbPredicate(MI));
1109 
1110  // If we find an IT instruction, we need to parse its condition
1111  // code and mask operands so that we can apply them correctly
1112  // to the subsequent instructions.
1113  if (MI.getOpcode() == ARM::t2IT) {
1114  unsigned Firstcond = MI.getOperand(0).getImm();
1115  unsigned Mask = MI.getOperand(1).getImm();
1116  ITBlock.setITState(Firstcond, Mask);
1117 
1118  // An IT instruction that would give a 'NV' predicate is unpredictable.
1119  if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
1120  CS << "unpredictable IT predicate sequence";
1121  }
1122 
1123  return Result;
1124  }
1125 
1126  // We want to read exactly 4 bytes of data.
1127  if (Bytes.size() < 4) {
1128  Size = 0;
1129  return MCDisassembler::Fail;
1130  }
1131 
1132  uint32_t Insn32 =
1133  (uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>(
1134  Bytes.data() + 2, InstructionEndianness);
1135 
1136  Result =
1137  decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
1138  if (Result != MCDisassembler::Fail) {
1139  Size = 4;
1140 
1141  // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
1142  // the VPT predicate.
1143  if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
1145 
1146  Check(Result, AddThumbPredicate(MI));
1147 
1148  if (isVPTOpcode(MI.getOpcode())) {
1149  unsigned Mask = MI.getOperand(0).getImm();
1150  VPTBlock.setVPTState(Mask);
1151  }
1152 
1153  return Result;
1154  }
1155 
1156  Result =
1157  decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
1158  if (Result != MCDisassembler::Fail) {
1159  Size = 4;
1160  bool InITBlock = ITBlock.instrInITBlock();
1161  Check(Result, AddThumbPredicate(MI));
1162  AddThumb1SBit(MI, InITBlock);
1163  return Result;
1164  }
1165 
1166  Result =
1167  decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
1168  if (Result != MCDisassembler::Fail) {
1169  Size = 4;
1170  Check(Result, AddThumbPredicate(MI));
1171  return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result);
1172  }
1173 
1174  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1175  Result =
1176  decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
1177  if (Result != MCDisassembler::Fail) {
1178  Size = 4;
1179  UpdateThumbVFPPredicate(Result, MI);
1180  return Result;
1181  }
1182  }
1183 
1184  Result =
1185  decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
1186  if (Result != MCDisassembler::Fail) {
1187  Size = 4;
1188  return Result;
1189  }
1190 
1191  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1192  Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
1193  STI);
1194  if (Result != MCDisassembler::Fail) {
1195  Size = 4;
1196  Check(Result, AddThumbPredicate(MI));
1197  return Result;
1198  }
1199  }
1200 
1201  if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
1202  uint32_t NEONLdStInsn = Insn32;
1203  NEONLdStInsn &= 0xF0FFFFFF;
1204  NEONLdStInsn |= 0x04000000;
1205  Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
1206  Address, this, STI);
1207  if (Result != MCDisassembler::Fail) {
1208  Size = 4;
1209  Check(Result, AddThumbPredicate(MI));
1210  return Result;
1211  }
1212  }
1213 
1214  if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
1215  uint32_t NEONDataInsn = Insn32;
1216  NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
1217  NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1218  NEONDataInsn |= 0x12000000; // Set bits 28 and 25
1219  Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
1220  Address, this, STI);
1221  if (Result != MCDisassembler::Fail) {
1222  Size = 4;
1223  Check(Result, AddThumbPredicate(MI));
1224  return Result;
1225  }
1226 
1227  uint32_t NEONCryptoInsn = Insn32;
1228  NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
1229  NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1230  NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
1231  Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
1232  Address, this, STI);
1233  if (Result != MCDisassembler::Fail) {
1234  Size = 4;
1235  return Result;
1236  }
1237 
1238  uint32_t NEONv8Insn = Insn32;
1239  NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
1240  Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
1241  this, STI);
1242  if (Result != MCDisassembler::Fail) {
1243  Size = 4;
1244  return Result;
1245  }
1246  }
1247 
1248  uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
1249  const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)
1250  ? DecoderTableThumb2CDE32
1251  : DecoderTableThumb2CoProc32;
1252  Result =
1253  decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI);
1254  if (Result != MCDisassembler::Fail) {
1255  Size = 4;
1256  Check(Result, AddThumbPredicate(MI));
1257  return Result;
1258  }
1259 
1260  Size = 0;
1261  return MCDisassembler::Fail;
1262 }
1263 
1273 }
1274 
1275 static const uint16_t GPRDecoderTable[] = {
1276  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1277  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1278  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1279  ARM::R12, ARM::SP, ARM::LR, ARM::PC
1280 };
1281 
1282 static const uint16_t CLRMGPRDecoderTable[] = {
1283  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1284  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1285  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1286  ARM::R12, 0, ARM::LR, ARM::APSR
1287 };
1288 
1289 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1290  uint64_t Address,
1291  const MCDisassembler *Decoder) {
1292  if (RegNo > 15)
1293  return MCDisassembler::Fail;
1294 
1295  unsigned Register = GPRDecoderTable[RegNo];
1297  return MCDisassembler::Success;
1298 }
1299 
1300 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1301  uint64_t Address,
1302  const MCDisassembler *Decoder) {
1303  if (RegNo > 15)
1304  return MCDisassembler::Fail;
1305 
1306  unsigned Register = CLRMGPRDecoderTable[RegNo];
1307  if (Register == 0)
1308  return MCDisassembler::Fail;
1309 
1311  return MCDisassembler::Success;
1312 }
1313 
1314 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
1315  uint64_t Address,
1316  const MCDisassembler *Decoder) {
1318 
1319  if (RegNo == 15)
1321 
1322  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1323 
1324  return S;
1325 }
1326 
1327 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
1328  uint64_t Address,
1329  const MCDisassembler *Decoder) {
1331 
1332  if (RegNo == 13)
1334 
1335  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1336 
1337  return S;
1338 }
1339 
1340 static DecodeStatus
1341 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1342  const MCDisassembler *Decoder) {
1344 
1345  if (RegNo == 15)
1346  {
1347  Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
1348  return MCDisassembler::Success;
1349  }
1350 
1351  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1352  return S;
1353 }
1354 
1355 static DecodeStatus
1356 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1357  const MCDisassembler *Decoder) {
1359 
1360  if (RegNo == 15)
1361  {
1362  Inst.addOperand(MCOperand::createReg(ARM::ZR));
1363  return MCDisassembler::Success;
1364  }
1365 
1366  if (RegNo == 13)
1368 
1369  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1370  return S;
1371 }
1372 
1373 static DecodeStatus
1374 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1375  const MCDisassembler *Decoder) {
1377  if (RegNo == 13)
1378  return MCDisassembler::Fail;
1379  Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
1380  return S;
1381 }
1382 
1383 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1384  uint64_t Address,
1385  const MCDisassembler *Decoder) {
1386  if (RegNo > 7)
1387  return MCDisassembler::Fail;
1388  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
1389 }
1390 
1391 static const uint16_t GPRPairDecoderTable[] = {
1392  ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1393  ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1394 };
1395 
1396 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
1397  uint64_t Address,
1398  const MCDisassembler *Decoder) {
1400 
1401  // According to the Arm ARM RegNo = 14 is undefined, but we return fail
1402  // rather than SoftFail as there is no GPRPair table entry for index 7.
1403  if (RegNo > 13)
1404  return MCDisassembler::Fail;
1405 
1406  if (RegNo & 1)
1408 
1409  unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1410  Inst.addOperand(MCOperand::createReg(RegisterPair));
1411  return S;
1412 }
1413 
1414 static DecodeStatus
1415 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1416  const MCDisassembler *Decoder) {
1417  if (RegNo > 13)
1418  return MCDisassembler::Fail;
1419 
1420  unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1421  Inst.addOperand(MCOperand::createReg(RegisterPair));
1422 
1423  if ((RegNo & 1) || RegNo > 10)
1424  return MCDisassembler::SoftFail;
1425  return MCDisassembler::Success;
1426 }
1427 
1428 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
1429  uint64_t Address,
1430  const MCDisassembler *Decoder) {
1431  if (RegNo != 13)
1432  return MCDisassembler::Fail;
1433 
1434  unsigned Register = GPRDecoderTable[RegNo];
1436  return MCDisassembler::Success;
1437 }
1438 
1439 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1440  uint64_t Address,
1441  const MCDisassembler *Decoder) {
1442  unsigned Register = 0;
1443  switch (RegNo) {
1444  case 0:
1445  Register = ARM::R0;
1446  break;
1447  case 1:
1448  Register = ARM::R1;
1449  break;
1450  case 2:
1451  Register = ARM::R2;
1452  break;
1453  case 3:
1454  Register = ARM::R3;
1455  break;
1456  case 9:
1457  Register = ARM::R9;
1458  break;
1459  case 12:
1460  Register = ARM::R12;
1461  break;
1462  default:
1463  return MCDisassembler::Fail;
1464  }
1465 
1467  return MCDisassembler::Success;
1468 }
1469 
1470 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1471  uint64_t Address,
1472  const MCDisassembler *Decoder) {
1474 
1475  const FeatureBitset &featureBits =
1476  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1477 
1478  if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1480 
1481  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1482  return S;
1483 }
1484 
1485 static const uint16_t SPRDecoderTable[] = {
1486  ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1487  ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1488  ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1489  ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1490  ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1491  ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1492  ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1493  ARM::S28, ARM::S29, ARM::S30, ARM::S31
1494 };
1495 
1496 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1497  uint64_t Address,
1498  const MCDisassembler *Decoder) {
1499  if (RegNo > 31)
1500  return MCDisassembler::Fail;
1501 
1502  unsigned Register = SPRDecoderTable[RegNo];
1504  return MCDisassembler::Success;
1505 }
1506 
1507 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1508  uint64_t Address,
1509  const MCDisassembler *Decoder) {
1510  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1511 }
1512 
1513 static const uint16_t DPRDecoderTable[] = {
1514  ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1515  ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1516  ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1517  ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1518  ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1519  ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1520  ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1521  ARM::D28, ARM::D29, ARM::D30, ARM::D31
1522 };
1523 
1524 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1525  uint64_t Address,
1526  const MCDisassembler *Decoder) {
1527  const FeatureBitset &featureBits =
1528  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1529 
1530  bool hasD32 = featureBits[ARM::FeatureD32];
1531 
1532  if (RegNo > 31 || (!hasD32 && RegNo > 15))
1533  return MCDisassembler::Fail;
1534 
1535  unsigned Register = DPRDecoderTable[RegNo];
1537  return MCDisassembler::Success;
1538 }
1539 
1540 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1541  uint64_t Address,
1542  const MCDisassembler *Decoder) {
1543  if (RegNo > 7)
1544  return MCDisassembler::Fail;
1545  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1546 }
1547 
1548 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1549  uint64_t Address,
1550  const MCDisassembler *Decoder) {
1551  if (RegNo > 15)
1552  return MCDisassembler::Fail;
1553  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1554 }
1555 
1556 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1557  uint64_t Address,
1558  const MCDisassembler *Decoder) {
1559  if (RegNo > 15)
1560  return MCDisassembler::Fail;
1561  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1562 }
1563 
1564 static const uint16_t QPRDecoderTable[] = {
1565  ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1566  ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1567  ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1568  ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1569 };
1570 
1571 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1572  uint64_t Address,
1573  const MCDisassembler *Decoder) {
1574  if (RegNo > 31 || (RegNo & 1) != 0)
1575  return MCDisassembler::Fail;
1576  RegNo >>= 1;
1577 
1578  unsigned Register = QPRDecoderTable[RegNo];
1580  return MCDisassembler::Success;
1581 }
1582 
1583 static const uint16_t DPairDecoderTable[] = {
1584  ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1585  ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1586  ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1587  ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1588  ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1589  ARM::Q15
1590 };
1591 
1592 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1593  uint64_t Address,
1594  const MCDisassembler *Decoder) {
1595  if (RegNo > 30)
1596  return MCDisassembler::Fail;
1597 
1598  unsigned Register = DPairDecoderTable[RegNo];
1600  return MCDisassembler::Success;
1601 }
1602 
1604  ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1605  ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1606  ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1607  ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1608  ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1609  ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1610  ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1611  ARM::D28_D30, ARM::D29_D31
1612 };
1613 
1614 static DecodeStatus
1615 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1616  const MCDisassembler *Decoder) {
1617  if (RegNo > 29)
1618  return MCDisassembler::Fail;
1619 
1620  unsigned Register = DPairSpacedDecoderTable[RegNo];
1622  return MCDisassembler::Success;
1623 }
1624 
1625 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1626  uint64_t Address,
1627  const MCDisassembler *Decoder) {
1629  if (Val == 0xF) return MCDisassembler::Fail;
1630  // AL predicate is not allowed on Thumb1 branches.
1631  if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1632  return MCDisassembler::Fail;
1633  if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable())
1635  Inst.addOperand(MCOperand::createImm(Val));
1636  if (Val == ARMCC::AL) {
1638  } else
1639  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1640  return S;
1641 }
1642 
1643 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1644  uint64_t Address,
1645  const MCDisassembler *Decoder) {
1646  if (Val)
1647  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1648  else
1650  return MCDisassembler::Success;
1651 }
1652 
1653 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1654  uint64_t Address,
1655  const MCDisassembler *Decoder) {
1657 
1658  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1659  unsigned type = fieldFromInstruction(Val, 5, 2);
1660  unsigned imm = fieldFromInstruction(Val, 7, 5);
1661 
1662  // Register-immediate
1663  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1664  return MCDisassembler::Fail;
1665 
1667  switch (type) {
1668  case 0:
1669  Shift = ARM_AM::lsl;
1670  break;
1671  case 1:
1672  Shift = ARM_AM::lsr;
1673  break;
1674  case 2:
1675  Shift = ARM_AM::asr;
1676  break;
1677  case 3:
1678  Shift = ARM_AM::ror;
1679  break;
1680  }
1681 
1682  if (Shift == ARM_AM::ror && imm == 0)
1683  Shift = ARM_AM::rrx;
1684 
1685  unsigned Op = Shift | (imm << 3);
1687 
1688  return S;
1689 }
1690 
1691 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1692  uint64_t Address,
1693  const MCDisassembler *Decoder) {
1695 
1696  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1697  unsigned type = fieldFromInstruction(Val, 5, 2);
1698  unsigned Rs = fieldFromInstruction(Val, 8, 4);
1699 
1700  // Register-register
1701  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1702  return MCDisassembler::Fail;
1703  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1704  return MCDisassembler::Fail;
1705 
1707  switch (type) {
1708  case 0:
1709  Shift = ARM_AM::lsl;
1710  break;
1711  case 1:
1712  Shift = ARM_AM::lsr;
1713  break;
1714  case 2:
1715  Shift = ARM_AM::asr;
1716  break;
1717  case 3:
1718  Shift = ARM_AM::ror;
1719  break;
1720  }
1721 
1723 
1724  return S;
1725 }
1726 
1727 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1728  uint64_t Address,
1729  const MCDisassembler *Decoder) {
1731 
1732  bool NeedDisjointWriteback = false;
1733  unsigned WritebackReg = 0;
1734  bool CLRM = false;
1735  switch (Inst.getOpcode()) {
1736  default:
1737  break;
1738  case ARM::LDMIA_UPD:
1739  case ARM::LDMDB_UPD:
1740  case ARM::LDMIB_UPD:
1741  case ARM::LDMDA_UPD:
1742  case ARM::t2LDMIA_UPD:
1743  case ARM::t2LDMDB_UPD:
1744  case ARM::t2STMIA_UPD:
1745  case ARM::t2STMDB_UPD:
1746  NeedDisjointWriteback = true;
1747  WritebackReg = Inst.getOperand(0).getReg();
1748  break;
1749  case ARM::t2CLRM:
1750  CLRM = true;
1751  break;
1752  }
1753 
1754  // Empty register lists are not allowed.
1755  if (Val == 0) return MCDisassembler::Fail;
1756  for (unsigned i = 0; i < 16; ++i) {
1757  if (Val & (1 << i)) {
1758  if (CLRM) {
1759  if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
1760  return MCDisassembler::Fail;
1761  }
1762  } else {
1763  if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1764  return MCDisassembler::Fail;
1765  // Writeback not allowed if Rn is in the target list.
1766  if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1768  }
1769  }
1770  }
1771 
1772  return S;
1773 }
1774 
1775 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1776  uint64_t Address,
1777  const MCDisassembler *Decoder) {
1779 
1780  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1781  unsigned regs = fieldFromInstruction(Val, 0, 8);
1782 
1783  // In case of unpredictable encoding, tweak the operands.
1784  if (regs == 0 || (Vd + regs) > 32) {
1785  regs = Vd + regs > 32 ? 32 - Vd : regs;
1786  regs = std::max( 1u, regs);
1788  }
1789 
1790  if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1791  return MCDisassembler::Fail;
1792  for (unsigned i = 0; i < (regs - 1); ++i) {
1793  if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1794  return MCDisassembler::Fail;
1795  }
1796 
1797  return S;
1798 }
1799 
1800 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1801  uint64_t Address,
1802  const MCDisassembler *Decoder) {
1804 
1805  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1806  unsigned regs = fieldFromInstruction(Val, 1, 7);
1807 
1808  // In case of unpredictable encoding, tweak the operands.
1809  if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1810  regs = Vd + regs > 32 ? 32 - Vd : regs;
1811  regs = std::max( 1u, regs);
1812  regs = std::min(16u, regs);
1814  }
1815 
1816  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1817  return MCDisassembler::Fail;
1818  for (unsigned i = 0; i < (regs - 1); ++i) {
1819  if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1820  return MCDisassembler::Fail;
1821  }
1822 
1823  return S;
1824 }
1825 
1826 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1827  uint64_t Address,
1828  const MCDisassembler *Decoder) {
1829  // This operand encodes a mask of contiguous zeros between a specified MSB
1830  // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1831  // the mask of all bits LSB-and-lower, and then xor them to create
1832  // the mask of that's all ones on [msb, lsb]. Finally we not it to
1833  // create the final mask.
1834  unsigned msb = fieldFromInstruction(Val, 5, 5);
1835  unsigned lsb = fieldFromInstruction(Val, 0, 5);
1836 
1838  if (lsb > msb) {
1840  // The check above will cause the warning for the "potentially undefined
1841  // instruction encoding" but we can't build a bad MCOperand value here
1842  // with a lsb > msb or else printing the MCInst will cause a crash.
1843  lsb = msb;
1844  }
1845 
1846  uint32_t msb_mask = 0xFFFFFFFF;
1847  if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1848  uint32_t lsb_mask = (1U << lsb) - 1;
1849 
1850  Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1851  return S;
1852 }
1853 
1855  uint64_t Address,
1856  const MCDisassembler *Decoder) {
1858 
1859  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1860  unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1861  unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1862  unsigned imm = fieldFromInstruction(Insn, 0, 8);
1863  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1864  unsigned U = fieldFromInstruction(Insn, 23, 1);
1865  const FeatureBitset &featureBits =
1866  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1867 
1868  switch (Inst.getOpcode()) {
1869  case ARM::LDC_OFFSET:
1870  case ARM::LDC_PRE:
1871  case ARM::LDC_POST:
1872  case ARM::LDC_OPTION:
1873  case ARM::LDCL_OFFSET:
1874  case ARM::LDCL_PRE:
1875  case ARM::LDCL_POST:
1876  case ARM::LDCL_OPTION:
1877  case ARM::STC_OFFSET:
1878  case ARM::STC_PRE:
1879  case ARM::STC_POST:
1880  case ARM::STC_OPTION:
1881  case ARM::STCL_OFFSET:
1882  case ARM::STCL_PRE:
1883  case ARM::STCL_POST:
1884  case ARM::STCL_OPTION:
1885  case ARM::t2LDC_OFFSET:
1886  case ARM::t2LDC_PRE:
1887  case ARM::t2LDC_POST:
1888  case ARM::t2LDC_OPTION:
1889  case ARM::t2LDCL_OFFSET:
1890  case ARM::t2LDCL_PRE:
1891  case ARM::t2LDCL_POST:
1892  case ARM::t2LDCL_OPTION:
1893  case ARM::t2STC_OFFSET:
1894  case ARM::t2STC_PRE:
1895  case ARM::t2STC_POST:
1896  case ARM::t2STC_OPTION:
1897  case ARM::t2STCL_OFFSET:
1898  case ARM::t2STCL_PRE:
1899  case ARM::t2STCL_POST:
1900  case ARM::t2STCL_OPTION:
1901  case ARM::t2LDC2_OFFSET:
1902  case ARM::t2LDC2L_OFFSET:
1903  case ARM::t2LDC2_PRE:
1904  case ARM::t2LDC2L_PRE:
1905  case ARM::t2STC2_OFFSET:
1906  case ARM::t2STC2L_OFFSET:
1907  case ARM::t2STC2_PRE:
1908  case ARM::t2STC2L_PRE:
1909  case ARM::LDC2_OFFSET:
1910  case ARM::LDC2L_OFFSET:
1911  case ARM::LDC2_PRE:
1912  case ARM::LDC2L_PRE:
1913  case ARM::STC2_OFFSET:
1914  case ARM::STC2L_OFFSET:
1915  case ARM::STC2_PRE:
1916  case ARM::STC2L_PRE:
1917  case ARM::t2LDC2_OPTION:
1918  case ARM::t2STC2_OPTION:
1919  case ARM::t2LDC2_POST:
1920  case ARM::t2LDC2L_POST:
1921  case ARM::t2STC2_POST:
1922  case ARM::t2STC2L_POST:
1923  case ARM::LDC2_POST:
1924  case ARM::LDC2L_POST:
1925  case ARM::STC2_POST:
1926  case ARM::STC2L_POST:
1927  if (coproc == 0xA || coproc == 0xB ||
1928  (featureBits[ARM::HasV8_1MMainlineOps] &&
1929  (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1930  coproc == 0xE || coproc == 0xF)))
1931  return MCDisassembler::Fail;
1932  break;
1933  default:
1934  break;
1935  }
1936 
1937  if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1938  return MCDisassembler::Fail;
1939 
1940  Inst.addOperand(MCOperand::createImm(coproc));
1941  Inst.addOperand(MCOperand::createImm(CRd));
1942  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1943  return MCDisassembler::Fail;
1944 
1945  switch (Inst.getOpcode()) {
1946  case ARM::t2LDC2_OFFSET:
1947  case ARM::t2LDC2L_OFFSET:
1948  case ARM::t2LDC2_PRE:
1949  case ARM::t2LDC2L_PRE:
1950  case ARM::t2STC2_OFFSET:
1951  case ARM::t2STC2L_OFFSET:
1952  case ARM::t2STC2_PRE:
1953  case ARM::t2STC2L_PRE:
1954  case ARM::LDC2_OFFSET:
1955  case ARM::LDC2L_OFFSET:
1956  case ARM::LDC2_PRE:
1957  case ARM::LDC2L_PRE:
1958  case ARM::STC2_OFFSET:
1959  case ARM::STC2L_OFFSET:
1960  case ARM::STC2_PRE:
1961  case ARM::STC2L_PRE:
1962  case ARM::t2LDC_OFFSET:
1963  case ARM::t2LDCL_OFFSET:
1964  case ARM::t2LDC_PRE:
1965  case ARM::t2LDCL_PRE:
1966  case ARM::t2STC_OFFSET:
1967  case ARM::t2STCL_OFFSET:
1968  case ARM::t2STC_PRE:
1969  case ARM::t2STCL_PRE:
1970  case ARM::LDC_OFFSET:
1971  case ARM::LDCL_OFFSET:
1972  case ARM::LDC_PRE:
1973  case ARM::LDCL_PRE:
1974  case ARM::STC_OFFSET:
1975  case ARM::STCL_OFFSET:
1976  case ARM::STC_PRE:
1977  case ARM::STCL_PRE:
1978  imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1979  Inst.addOperand(MCOperand::createImm(imm));
1980  break;
1981  case ARM::t2LDC2_POST:
1982  case ARM::t2LDC2L_POST:
1983  case ARM::t2STC2_POST:
1984  case ARM::t2STC2L_POST:
1985  case ARM::LDC2_POST:
1986  case ARM::LDC2L_POST:
1987  case ARM::STC2_POST:
1988  case ARM::STC2L_POST:
1989  case ARM::t2LDC_POST:
1990  case ARM::t2LDCL_POST:
1991  case ARM::t2STC_POST:
1992  case ARM::t2STCL_POST:
1993  case ARM::LDC_POST:
1994  case ARM::LDCL_POST:
1995  case ARM::STC_POST:
1996  case ARM::STCL_POST:
1997  imm |= U << 8;
1998  [[fallthrough]];
1999  default:
2000  // The 'option' variant doesn't encode 'U' in the immediate since
2001  // the immediate is unsigned [0,255].
2002  Inst.addOperand(MCOperand::createImm(imm));
2003  break;
2004  }
2005 
2006  switch (Inst.getOpcode()) {
2007  case ARM::LDC_OFFSET:
2008  case ARM::LDC_PRE:
2009  case ARM::LDC_POST:
2010  case ARM::LDC_OPTION:
2011  case ARM::LDCL_OFFSET:
2012  case ARM::LDCL_PRE:
2013  case ARM::LDCL_POST:
2014  case ARM::LDCL_OPTION:
2015  case ARM::STC_OFFSET:
2016  case ARM::STC_PRE:
2017  case ARM::STC_POST:
2018  case ARM::STC_OPTION:
2019  case ARM::STCL_OFFSET:
2020  case ARM::STCL_PRE:
2021  case ARM::STCL_POST:
2022  case ARM::STCL_OPTION:
2023  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2024  return MCDisassembler::Fail;
2025  break;
2026  default:
2027  break;
2028  }
2029 
2030  return S;
2031 }
2032 
2033 static DecodeStatus
2035  const MCDisassembler *Decoder) {
2037 
2038  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2039  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
2040  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2041  unsigned imm = fieldFromInstruction(Insn, 0, 12);
2042  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2043  unsigned reg = fieldFromInstruction(Insn, 25, 1);
2044  unsigned P = fieldFromInstruction(Insn, 24, 1);
2045  unsigned W = fieldFromInstruction(Insn, 21, 1);
2046 
2047  // On stores, the writeback operand precedes Rt.
2048  switch (Inst.getOpcode()) {
2049  case ARM::STR_POST_IMM:
2050  case ARM::STR_POST_REG:
2051  case ARM::STRB_POST_IMM:
2052  case ARM::STRB_POST_REG:
2053  case ARM::STRT_POST_REG:
2054  case ARM::STRT_POST_IMM:
2055  case ARM::STRBT_POST_REG:
2056  case ARM::STRBT_POST_IMM:
2057  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2058  return MCDisassembler::Fail;
2059  break;
2060  default:
2061  break;
2062  }
2063 
2064  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2065  return MCDisassembler::Fail;
2066 
2067  // On loads, the writeback operand comes after Rt.
2068  switch (Inst.getOpcode()) {
2069  case ARM::LDR_POST_IMM:
2070  case ARM::LDR_POST_REG:
2071  case ARM::LDRB_POST_IMM:
2072  case ARM::LDRB_POST_REG:
2073  case ARM::LDRBT_POST_REG:
2074  case ARM::LDRBT_POST_IMM:
2075  case ARM::LDRT_POST_REG:
2076  case ARM::LDRT_POST_IMM:
2077  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2078  return MCDisassembler::Fail;
2079  break;
2080  default:
2081  break;
2082  }
2083 
2084  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2085  return MCDisassembler::Fail;
2086 
2088  if (!fieldFromInstruction(Insn, 23, 1))
2089  Op = ARM_AM::sub;
2090 
2091  bool writeback = (P == 0) || (W == 1);
2092  unsigned idx_mode = 0;
2093  if (P && writeback)
2094  idx_mode = ARMII::IndexModePre;
2095  else if (!P && writeback)
2096  idx_mode = ARMII::IndexModePost;
2097 
2098  if (writeback && (Rn == 15 || Rn == Rt))
2099  S = MCDisassembler::SoftFail; // UNPREDICTABLE
2100 
2101  if (reg) {
2102  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2103  return MCDisassembler::Fail;
2105  switch( fieldFromInstruction(Insn, 5, 2)) {
2106  case 0:
2107  Opc = ARM_AM::lsl;
2108  break;
2109  case 1:
2110  Opc = ARM_AM::lsr;
2111  break;
2112  case 2:
2113  Opc = ARM_AM::asr;
2114  break;
2115  case 3:
2116  Opc = ARM_AM::ror;
2117  break;
2118  default:
2119  return MCDisassembler::Fail;
2120  }
2121  unsigned amt = fieldFromInstruction(Insn, 7, 5);
2122  if (Opc == ARM_AM::ror && amt == 0)
2123  Opc = ARM_AM::rrx;
2124  unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
2125 
2126  Inst.addOperand(MCOperand::createImm(imm));
2127  } else {
2129  unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
2131  }
2132 
2133  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2134  return MCDisassembler::Fail;
2135 
2136  return S;
2137 }
2138 
2139 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
2140  uint64_t Address,
2141  const MCDisassembler *Decoder) {
2143 
2144  unsigned Rn = fieldFromInstruction(Val, 13, 4);
2145  unsigned Rm = fieldFromInstruction(Val, 0, 4);
2146  unsigned type = fieldFromInstruction(Val, 5, 2);
2147  unsigned imm = fieldFromInstruction(Val, 7, 5);
2148  unsigned U = fieldFromInstruction(Val, 12, 1);
2149 
2151  switch (type) {
2152  case 0:
2153  ShOp = ARM_AM::lsl;
2154  break;
2155  case 1:
2156  ShOp = ARM_AM::lsr;
2157  break;
2158  case 2:
2159  ShOp = ARM_AM::asr;
2160  break;
2161  case 3:
2162  ShOp = ARM_AM::ror;
2163  break;
2164  }
2165 
2166  if (ShOp == ARM_AM::ror && imm == 0)
2167  ShOp = ARM_AM::rrx;
2168 
2169  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2170  return MCDisassembler::Fail;
2171  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2172  return MCDisassembler::Fail;
2173  unsigned shift;
2174  if (U)
2175  shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
2176  else
2177  shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
2179 
2180  return S;
2181 }
2182 
2184  uint64_t Address,
2185  const MCDisassembler *Decoder) {
2186  if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB)
2187  return MCDisassembler::Fail;
2188 
2189  // The "csync" operand is not encoded into the "tsb" instruction (as this is
2190  // the only available operand), but LLVM expects the instruction to have one
2191  // operand, so we need to add the csync when decoding.
2193  return MCDisassembler::Success;
2194 }
2195 
2197  uint64_t Address,
2198  const MCDisassembler *Decoder) {
2200 
2201  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
2202  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2203  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2204  unsigned type = fieldFromInstruction(Insn, 22, 1);
2205  unsigned imm = fieldFromInstruction(Insn, 8, 4);
2206  unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
2207  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2208  unsigned W = fieldFromInstruction(Insn, 21, 1);
2209  unsigned P = fieldFromInstruction(Insn, 24, 1);
2210  unsigned Rt2 = Rt + 1;
2211 
2212  bool writeback = (W == 1) | (P == 0);
2213 
2214  // For {LD,ST}RD, Rt must be even, else undefined.
2215  switch (Inst.getOpcode()) {
2216  case ARM::STRD:
2217  case ARM::STRD_PRE:
2218  case ARM::STRD_POST:
2219  case ARM::LDRD:
2220  case ARM::LDRD_PRE:
2221  case ARM::LDRD_POST:
2222  if (Rt & 0x1) S = MCDisassembler::SoftFail;
2223  break;
2224  default:
2225  break;
2226  }
2227  switch (Inst.getOpcode()) {
2228  case ARM::STRD:
2229  case ARM::STRD_PRE:
2230  case ARM::STRD_POST:
2231  if (P == 0 && W == 1)
2233 
2234  if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2236  if (type && Rm == 15)
2238  if (Rt2 == 15)
2240  if (!type && fieldFromInstruction(Insn, 8, 4))
2242  break;
2243  case ARM::STRH:
2244  case ARM::STRH_PRE:
2245  case ARM::STRH_POST:
2246  if (Rt == 15)
2248  if (writeback && (Rn == 15 || Rn == Rt))
2250  if (!type && Rm == 15)
2252  break;
2253  case ARM::LDRD:
2254  case ARM::LDRD_PRE:
2255  case ARM::LDRD_POST:
2256  if (type && Rn == 15) {
2257  if (Rt2 == 15)
2259  break;
2260  }
2261  if (P == 0 && W == 1)
2263  if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2265  if (!type && writeback && Rn == 15)
2267  if (writeback && (Rn == Rt || Rn == Rt2))
2269  break;
2270  case ARM::LDRH:
2271  case ARM::LDRH_PRE:
2272  case ARM::LDRH_POST:
2273  if (type && Rn == 15) {
2274  if (Rt == 15)
2276  break;
2277  }
2278  if (Rt == 15)
2280  if (!type && Rm == 15)
2282  if (!type && writeback && (Rn == 15 || Rn == Rt))
2284  break;
2285  case ARM::LDRSH:
2286  case ARM::LDRSH_PRE:
2287  case ARM::LDRSH_POST:
2288  case ARM::LDRSB:
2289  case ARM::LDRSB_PRE:
2290  case ARM::LDRSB_POST:
2291  if (type && Rn == 15) {
2292  if (Rt == 15)
2294  break;
2295  }
2296  if (type && (Rt == 15 || (writeback && Rn == Rt)))
2298  if (!type && (Rt == 15 || Rm == 15))
2300  if (!type && writeback && (Rn == 15 || Rn == Rt))
2302  break;
2303  default:
2304  break;
2305  }
2306 
2307  if (writeback) { // Writeback
2308  if (P)
2309  U |= ARMII::IndexModePre << 9;
2310  else
2311  U |= ARMII::IndexModePost << 9;
2312 
2313  // On stores, the writeback operand precedes Rt.
2314  switch (Inst.getOpcode()) {
2315  case ARM::STRD:
2316  case ARM::STRD_PRE:
2317  case ARM::STRD_POST:
2318  case ARM::STRH:
2319  case ARM::STRH_PRE:
2320  case ARM::STRH_POST:
2321  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2322  return MCDisassembler::Fail;
2323  break;
2324  default:
2325  break;
2326  }
2327  }
2328 
2329  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2330  return MCDisassembler::Fail;
2331  switch (Inst.getOpcode()) {
2332  case ARM::STRD:
2333  case ARM::STRD_PRE:
2334  case ARM::STRD_POST:
2335  case ARM::LDRD:
2336  case ARM::LDRD_PRE:
2337  case ARM::LDRD_POST:
2338  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2339  return MCDisassembler::Fail;
2340  break;
2341  default:
2342  break;
2343  }
2344 
2345  if (writeback) {
2346  // On loads, the writeback operand comes after Rt.
2347  switch (Inst.getOpcode()) {
2348  case ARM::LDRD:
2349  case ARM::LDRD_PRE:
2350  case ARM::LDRD_POST:
2351  case ARM::LDRH:
2352  case ARM::LDRH_PRE:
2353  case ARM::LDRH_POST:
2354  case ARM::LDRSH:
2355  case ARM::LDRSH_PRE:
2356  case ARM::LDRSH_POST:
2357  case ARM::LDRSB:
2358  case ARM::LDRSB_PRE:
2359  case ARM::LDRSB_POST:
2360  case ARM::LDRHTr:
2361  case ARM::LDRSBTr:
2362  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2363  return MCDisassembler::Fail;
2364  break;
2365  default:
2366  break;
2367  }
2368  }
2369 
2370  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2371  return MCDisassembler::Fail;
2372 
2373  if (type) {
2375  Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2376  } else {
2377  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2378  return MCDisassembler::Fail;
2380  }
2381 
2382  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2383  return MCDisassembler::Fail;
2384 
2385  return S;
2386 }
2387 
2389  uint64_t Address,
2390  const MCDisassembler *Decoder) {
2392 
2393  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2394  unsigned mode = fieldFromInstruction(Insn, 23, 2);
2395 
2396  switch (mode) {
2397  case 0:
2398  mode = ARM_AM::da;
2399  break;
2400  case 1:
2401  mode = ARM_AM::ia;
2402  break;
2403  case 2:
2404  mode = ARM_AM::db;
2405  break;
2406  case 3:
2407  mode = ARM_AM::ib;
2408  break;
2409  }
2410 
2412  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2413  return MCDisassembler::Fail;
2414 
2415  return S;
2416 }
2417 
2419  uint64_t Address,
2420  const MCDisassembler *Decoder) {
2422 
2423  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2424  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2425  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2426  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2427 
2428  if (pred == 0xF)
2429  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2430 
2431  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2432  return MCDisassembler::Fail;
2433  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2434  return MCDisassembler::Fail;
2435  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2436  return MCDisassembler::Fail;
2437  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2438  return MCDisassembler::Fail;
2439  return S;
2440 }
2441 
2442 static DecodeStatus
2444  uint64_t Address,
2445  const MCDisassembler *Decoder) {
2447 
2448  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2449  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2450  unsigned reglist = fieldFromInstruction(Insn, 0, 16);
2451 
2452  if (pred == 0xF) {
2453  // Ambiguous with RFE and SRS
2454  switch (Inst.getOpcode()) {
2455  case ARM::LDMDA:
2456  Inst.setOpcode(ARM::RFEDA);
2457  break;
2458  case ARM::LDMDA_UPD:
2459  Inst.setOpcode(ARM::RFEDA_UPD);
2460  break;
2461  case ARM::LDMDB:
2462  Inst.setOpcode(ARM::RFEDB);
2463  break;
2464  case ARM::LDMDB_UPD:
2465  Inst.setOpcode(ARM::RFEDB_UPD);
2466  break;
2467  case ARM::LDMIA:
2468  Inst.setOpcode(ARM::RFEIA);
2469  break;
2470  case ARM::LDMIA_UPD:
2471  Inst.setOpcode(ARM::RFEIA_UPD);
2472  break;
2473  case ARM::LDMIB:
2474  Inst.setOpcode(ARM::RFEIB);
2475  break;
2476  case ARM::LDMIB_UPD:
2477  Inst.setOpcode(ARM::RFEIB_UPD);
2478  break;
2479  case ARM::STMDA:
2480  Inst.setOpcode(ARM::SRSDA);
2481  break;
2482  case ARM::STMDA_UPD:
2483  Inst.setOpcode(ARM::SRSDA_UPD);
2484  break;
2485  case ARM::STMDB:
2486  Inst.setOpcode(ARM::SRSDB);
2487  break;
2488  case ARM::STMDB_UPD:
2489  Inst.setOpcode(ARM::SRSDB_UPD);
2490  break;
2491  case ARM::STMIA:
2492  Inst.setOpcode(ARM::SRSIA);
2493  break;
2494  case ARM::STMIA_UPD:
2495  Inst.setOpcode(ARM::SRSIA_UPD);
2496  break;
2497  case ARM::STMIB:
2498  Inst.setOpcode(ARM::SRSIB);
2499  break;
2500  case ARM::STMIB_UPD:
2501  Inst.setOpcode(ARM::SRSIB_UPD);
2502  break;
2503  default:
2504  return MCDisassembler::Fail;
2505  }
2506 
2507  // For stores (which become SRS's, the only operand is the mode.
2508  if (fieldFromInstruction(Insn, 20, 1) == 0) {
2509  // Check SRS encoding constraints
2510  if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
2511  fieldFromInstruction(Insn, 20, 1) == 0))
2512  return MCDisassembler::Fail;
2513 
2514  Inst.addOperand(
2515  MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
2516  return S;
2517  }
2518 
2519  return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
2520  }
2521 
2522  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2523  return MCDisassembler::Fail;
2524  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2525  return MCDisassembler::Fail; // Tied
2526  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2527  return MCDisassembler::Fail;
2528  if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
2529  return MCDisassembler::Fail;
2530 
2531  return S;
2532 }
2533 
2534 // Check for UNPREDICTABLE predicated ESB instruction
2536  uint64_t Address,
2537  const MCDisassembler *Decoder) {
2538  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2539  unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
2540  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2541  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2542 
2544 
2545  Inst.addOperand(MCOperand::createImm(imm8));
2546 
2547  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2548  return MCDisassembler::Fail;
2549 
2550  // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
2551  // so all predicates should be allowed.
2552  if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2554 
2555  return S;
2556 }
2557 
2559  uint64_t Address,
2560  const MCDisassembler *Decoder) {
2561  unsigned imod = fieldFromInstruction(Insn, 18, 2);
2562  unsigned M = fieldFromInstruction(Insn, 17, 1);
2563  unsigned iflags = fieldFromInstruction(Insn, 6, 3);
2564  unsigned mode = fieldFromInstruction(Insn, 0, 5);
2565 
2567 
2568  // This decoder is called from multiple location that do not check
2569  // the full encoding is valid before they do.
2570  if (fieldFromInstruction(Insn, 5, 1) != 0 ||
2571  fieldFromInstruction(Insn, 16, 1) != 0 ||
2572  fieldFromInstruction(Insn, 20, 8) != 0x10)
2573  return MCDisassembler::Fail;
2574 
2575  // imod == '01' --> UNPREDICTABLE
2576  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2577  // return failure here. The '01' imod value is unprintable, so there's
2578  // nothing useful we could do even if we returned UNPREDICTABLE.
2579 
2580  if (imod == 1) return MCDisassembler::Fail;
2581 
2582  if (imod && M) {
2583  Inst.setOpcode(ARM::CPS3p);
2584  Inst.addOperand(MCOperand::createImm(imod));
2585  Inst.addOperand(MCOperand::createImm(iflags));
2587  } else if (imod && !M) {
2588  Inst.setOpcode(ARM::CPS2p);
2589  Inst.addOperand(MCOperand::createImm(imod));
2590  Inst.addOperand(MCOperand::createImm(iflags));
2592  } else if (!imod && M) {
2593  Inst.setOpcode(ARM::CPS1p);
2595  if (iflags) S = MCDisassembler::SoftFail;
2596  } else {
2597  // imod == '00' && M == '0' --> UNPREDICTABLE
2598  Inst.setOpcode(ARM::CPS1p);
2601  }
2602 
2603  return S;
2604 }
2605 
2607  uint64_t Address,
2608  const MCDisassembler *Decoder) {
2609  unsigned imod = fieldFromInstruction(Insn, 9, 2);
2610  unsigned M = fieldFromInstruction(Insn, 8, 1);
2611  unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2612  unsigned mode = fieldFromInstruction(Insn, 0, 5);
2613 
2615 
2616  // imod == '01' --> UNPREDICTABLE
2617  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2618  // return failure here. The '01' imod value is unprintable, so there's
2619  // nothing useful we could do even if we returned UNPREDICTABLE.
2620 
2621  if (imod == 1) return MCDisassembler::Fail;
2622 
2623  if (imod && M) {
2624  Inst.setOpcode(ARM::t2CPS3p);
2625  Inst.addOperand(MCOperand::createImm(imod));
2626  Inst.addOperand(MCOperand::createImm(iflags));
2628  } else if (imod && !M) {
2629  Inst.setOpcode(ARM::t2CPS2p);
2630  Inst.addOperand(MCOperand::createImm(imod));
2631  Inst.addOperand(MCOperand::createImm(iflags));
2633  } else if (!imod && M) {
2634  Inst.setOpcode(ARM::t2CPS1p);
2636  if (iflags) S = MCDisassembler::SoftFail;
2637  } else {
2638  // imod == '00' && M == '0' --> this is a HINT instruction
2639  int imm = fieldFromInstruction(Insn, 0, 8);
2640  // HINT are defined only for immediate in [0..4]
2641  if(imm > 4) return MCDisassembler::Fail;
2642  Inst.setOpcode(ARM::t2HINT);
2643  Inst.addOperand(MCOperand::createImm(imm));
2644  }
2645 
2646  return S;
2647 }
2648 
2649 static DecodeStatus
2651  const MCDisassembler *Decoder) {
2652  unsigned imm = fieldFromInstruction(Insn, 0, 8);
2653 
2654  unsigned Opcode = ARM::t2HINT;
2655 
2656  if (imm == 0x0D) {
2657  Opcode = ARM::t2PACBTI;
2658  } else if (imm == 0x1D) {
2659  Opcode = ARM::t2PAC;
2660  } else if (imm == 0x2D) {
2661  Opcode = ARM::t2AUT;
2662  } else if (imm == 0x0F) {
2663  Opcode = ARM::t2BTI;
2664  }
2665 
2666  Inst.setOpcode(Opcode);
2667  if (Opcode == ARM::t2HINT) {
2668  Inst.addOperand(MCOperand::createImm(imm));
2669  }
2670 
2671  return MCDisassembler::Success;
2672 }
2673 
2675  uint64_t Address,
2676  const MCDisassembler *Decoder) {
2678 
2679  unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2680  unsigned imm = 0;
2681 
2682  imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2683  imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2684  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2685  imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2686 
2687  if (Inst.getOpcode() == ARM::t2MOVTi16)
2688  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2689  return MCDisassembler::Fail;
2690  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2691  return MCDisassembler::Fail;
2692 
2693  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2694  Inst.addOperand(MCOperand::createImm(imm));
2695 
2696  return S;
2697 }
2698 
2700  uint64_t Address,
2701  const MCDisassembler *Decoder) {
2703 
2704  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2705  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2706  unsigned imm = 0;
2707 
2708  imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2709  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2710 
2711  if (Inst.getOpcode() == ARM::MOVTi16)
2712  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2713  return MCDisassembler::Fail;
2714 
2715  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2716  return MCDisassembler::Fail;
2717 
2718  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2719  Inst.addOperand(MCOperand::createImm(imm));
2720 
2721  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2722  return MCDisassembler::Fail;
2723 
2724  return S;
2725 }
2726 
2728  uint64_t Address,
2729  const MCDisassembler *Decoder) {
2731 
2732  unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2733  unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2734  unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2735  unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2736  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2737 
2738  if (pred == 0xF)
2739  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2740 
2741  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2742  return MCDisassembler::Fail;
2743  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2744  return MCDisassembler::Fail;
2745  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2746  return MCDisassembler::Fail;
2747  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2748  return MCDisassembler::Fail;
2749 
2750  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2751  return MCDisassembler::Fail;
2752 
2753  return S;
2754 }
2755 
2757  uint64_t Address,
2758  const MCDisassembler *Decoder) {
2760 
2761  unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2762  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2763  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2764 
2765  if (Pred == 0xF)
2766  return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2767 
2768  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2769  return MCDisassembler::Fail;
2770  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2771  return MCDisassembler::Fail;
2772  if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2773  return MCDisassembler::Fail;
2774 
2775  return S;
2776 }
2777 
2779  uint64_t Address,
2780  const MCDisassembler *Decoder) {
2782 
2783  unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2784 
2785  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2786  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2787 
2788  if (!FeatureBits[ARM::HasV8_1aOps] ||
2789  !FeatureBits[ARM::HasV8Ops])
2790  return MCDisassembler::Fail;
2791 
2792  // Decoder can be called from DecodeTST, which does not check the full
2793  // encoding is valid.
2794  if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2795  fieldFromInstruction(Insn, 4,4) != 0)
2796  return MCDisassembler::Fail;
2797  if (fieldFromInstruction(Insn, 10,10) != 0 ||
2798  fieldFromInstruction(Insn, 0,4) != 0)
2800 
2801  Inst.setOpcode(ARM::SETPAN);
2803 
2804  return S;
2805 }
2806 
2808  uint64_t Address,
2809  const MCDisassembler *Decoder) {
2811 
2812  unsigned add = fieldFromInstruction(Val, 12, 1);
2813  unsigned imm = fieldFromInstruction(Val, 0, 12);
2814  unsigned Rn = fieldFromInstruction(Val, 13, 4);
2815 
2816  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2817  return MCDisassembler::Fail;
2818 
2819  if (!add) imm *= -1;
2820  if (imm == 0 && !add) imm = INT32_MIN;
2821  Inst.addOperand(MCOperand::createImm(imm));
2822  if (Rn == 15)
2823  tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2824 
2825  return S;
2826 }
2827 
2828 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2829  uint64_t Address,
2830  const MCDisassembler *Decoder) {
2832 
2833  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2834  // U == 1 to add imm, 0 to subtract it.
2835  unsigned U = fieldFromInstruction(Val, 8, 1);
2836  unsigned imm = fieldFromInstruction(Val, 0, 8);
2837 
2838  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2839  return MCDisassembler::Fail;
2840 
2841  if (U)
2843  else
2845 
2846  return S;
2847 }
2848 
2850  uint64_t Address,
2851  const MCDisassembler *Decoder) {
2853 
2854  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2855  // U == 1 to add imm, 0 to subtract it.
2856  unsigned U = fieldFromInstruction(Val, 8, 1);
2857  unsigned imm = fieldFromInstruction(Val, 0, 8);
2858 
2859  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2860  return MCDisassembler::Fail;
2861 
2862  if (U)
2864  else
2866 
2867  return S;
2868 }
2869 
2870 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2871  uint64_t Address,
2872  const MCDisassembler *Decoder) {
2873  return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2874 }
2875 
2877  uint64_t Address,
2878  const MCDisassembler *Decoder) {
2880 
2881  // Note the J1 and J2 values are from the encoded instruction. So here
2882  // change them to I1 and I2 values via as documented:
2883  // I1 = NOT(J1 EOR S);
2884  // I2 = NOT(J2 EOR S);
2885  // and build the imm32 with one trailing zero as documented:
2886  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2887  unsigned S = fieldFromInstruction(Insn, 26, 1);
2888  unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2889  unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2890  unsigned I1 = !(J1 ^ S);
2891  unsigned I2 = !(J2 ^ S);
2892  unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2893  unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2894  unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2895  int imm32 = SignExtend32<25>(tmp << 1);
2896  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2897  true, 4, Inst, Decoder))
2898  Inst.addOperand(MCOperand::createImm(imm32));
2899 
2900  return Status;
2901 }
2902 
2904  uint64_t Address,
2905  const MCDisassembler *Decoder) {
2907 
2908  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2909  unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2910 
2911  if (pred == 0xF) {
2912  Inst.setOpcode(ARM::BLXi);
2913  imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2914  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2915  true, 4, Inst, Decoder))
2916  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2917  return S;
2918  }
2919 
2920  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2921  true, 4, Inst, Decoder))
2922  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2923 
2924  // We already have BL_pred for BL w/ predicate, no need to add addition
2925  // predicate opreands for BL
2926  if (Inst.getOpcode() != ARM::BL)
2927  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2928  return MCDisassembler::Fail;
2929 
2930  return S;
2931 }
2932 
2933 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2934  uint64_t Address,
2935  const MCDisassembler *Decoder) {
2937 
2938  unsigned Rm = fieldFromInstruction(Val, 0, 4);
2939  unsigned align = fieldFromInstruction(Val, 4, 2);
2940 
2941  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2942  return MCDisassembler::Fail;
2943  if (!align)
2945  else
2947 
2948  return S;
2949 }
2950 
2952  uint64_t Address,
2953  const MCDisassembler *Decoder) {
2955 
2956  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2957  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2958  unsigned wb = fieldFromInstruction(Insn, 16, 4);
2959  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2960  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2961  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2962 
2963  // First output register
2964  switch (Inst.getOpcode()) {
2965  case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2966  case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2967  case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2968  case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2969  case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2970  case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2971  case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2972  case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2973  case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2974  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2975  return MCDisassembler::Fail;
2976  break;
2977  case ARM::VLD2b16:
2978  case ARM::VLD2b32:
2979  case ARM::VLD2b8:
2980  case ARM::VLD2b16wb_fixed:
2981  case ARM::VLD2b16wb_register:
2982  case ARM::VLD2b32wb_fixed:
2983  case ARM::VLD2b32wb_register:
2984  case ARM::VLD2b8wb_fixed:
2985  case ARM::VLD2b8wb_register:
2986  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2987  return MCDisassembler::Fail;
2988  break;
2989  default:
2990  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2991  return MCDisassembler::Fail;
2992  }
2993 
2994  // Second output register
2995  switch (Inst.getOpcode()) {
2996  case ARM::VLD3d8:
2997  case ARM::VLD3d16:
2998  case ARM::VLD3d32:
2999  case ARM::VLD3d8_UPD:
3000  case ARM::VLD3d16_UPD:
3001  case ARM::VLD3d32_UPD:
3002  case ARM::VLD4d8:
3003  case ARM::VLD4d16:
3004  case ARM::VLD4d32:
3005  case ARM::VLD4d8_UPD:
3006  case ARM::VLD4d16_UPD:
3007  case ARM::VLD4d32_UPD:
3008  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
3009  return MCDisassembler::Fail;
3010  break;
3011  case ARM::VLD3q8:
3012  case ARM::VLD3q16:
3013  case ARM::VLD3q32:
3014  case ARM::VLD3q8_UPD:
3015  case ARM::VLD3q16_UPD:
3016  case ARM::VLD3q32_UPD:
3017  case ARM::VLD4q8:
3018  case ARM::VLD4q16:
3019  case ARM::VLD4q32:
3020  case ARM::VLD4q8_UPD:
3021  case ARM::VLD4q16_UPD:
3022  case ARM::VLD4q32_UPD:
3023  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3024  return MCDisassembler::Fail;
3025  break;
3026  default:
3027  break;
3028  }
3029 
3030  // Third output register
3031  switch(Inst.getOpcode()) {
3032  case ARM::VLD3d8:
3033  case ARM::VLD3d16:
3034  case ARM::VLD3d32:
3035  case ARM::VLD3d8_UPD:
3036  case ARM::VLD3d16_UPD:
3037  case ARM::VLD3d32_UPD:
3038  case ARM::VLD4d8:
3039  case ARM::VLD4d16:
3040  case ARM::VLD4d32:
3041  case ARM::VLD4d8_UPD:
3042  case ARM::VLD4d16_UPD:
3043  case ARM::VLD4d32_UPD:
3044  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3045  return MCDisassembler::Fail;
3046  break;
3047  case ARM::VLD3q8:
3048  case ARM::VLD3q16:
3049  case ARM::VLD3q32:
3050  case ARM::VLD3q8_UPD:
3051  case ARM::VLD3q16_UPD:
3052  case ARM::VLD3q32_UPD:
3053  case ARM::VLD4q8:
3054  case ARM::VLD4q16:
3055  case ARM::VLD4q32:
3056  case ARM::VLD4q8_UPD:
3057  case ARM::VLD4q16_UPD:
3058  case ARM::VLD4q32_UPD:
3059  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
3060  return MCDisassembler::Fail;
3061  break;
3062  default:
3063  break;
3064  }
3065 
3066  // Fourth output register
3067  switch (Inst.getOpcode()) {
3068  case ARM::VLD4d8:
3069  case ARM::VLD4d16:
3070  case ARM::VLD4d32:
3071  case ARM::VLD4d8_UPD:
3072  case ARM::VLD4d16_UPD:
3073  case ARM::VLD4d32_UPD:
3074  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
3075  return MCDisassembler::Fail;
3076  break;
3077  case ARM::VLD4q8:
3078  case ARM::VLD4q16:
3079  case ARM::VLD4q32:
3080  case ARM::VLD4q8_UPD:
3081  case ARM::VLD4q16_UPD:
3082  case ARM::VLD4q32_UPD:
3083  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
3084  return MCDisassembler::Fail;
3085  break;
3086  default:
3087  break;
3088  }
3089 
3090  // Writeback operand
3091  switch (Inst.getOpcode()) {
3092  case ARM::VLD1d8wb_fixed:
3093  case ARM::VLD1d16wb_fixed:
3094  case ARM::VLD1d32wb_fixed:
3095  case ARM::VLD1d64wb_fixed:
3096  case ARM::VLD1d8wb_register:
3097  case ARM::VLD1d16wb_register:
3098  case ARM::VLD1d32wb_register:
3099  case ARM::VLD1d64wb_register:
3100  case ARM::VLD1q8wb_fixed:
3101  case ARM::VLD1q16wb_fixed:
3102  case ARM::VLD1q32wb_fixed:
3103  case ARM::VLD1q64wb_fixed:
3104  case ARM::VLD1q8wb_register:
3105  case ARM::VLD1q16wb_register:
3106  case ARM::VLD1q32wb_register:
3107  case ARM::VLD1q64wb_register:
3108  case ARM::VLD1d8Twb_fixed:
3109  case ARM::VLD1d8Twb_register:
3110  case ARM::VLD1d16Twb_fixed:
3111  case ARM::VLD1d16Twb_register:
3112  case ARM::VLD1d32Twb_fixed:
3113  case ARM::VLD1d32Twb_register:
3114  case ARM::VLD1d64Twb_fixed:
3115  case ARM::VLD1d64Twb_register:
3116  case ARM::VLD1d8Qwb_fixed:
3117  case ARM::VLD1d8Qwb_register:
3118  case ARM::VLD1d16Qwb_fixed:
3119  case ARM::VLD1d16Qwb_register:
3120  case ARM::VLD1d32Qwb_fixed:
3121  case ARM::VLD1d32Qwb_register:
3122  case ARM::VLD1d64Qwb_fixed:
3123  case ARM::VLD1d64Qwb_register:
3124  case ARM::VLD2d8wb_fixed:
3125  case ARM::VLD2d16wb_fixed:
3126  case ARM::VLD2d32wb_fixed:
3127  case ARM::VLD2q8wb_fixed:
3128  case ARM::VLD2q16wb_fixed:
3129  case ARM::VLD2q32wb_fixed:
3130  case ARM::VLD2d8wb_register:
3131  case ARM::VLD2d16wb_register:
3132  case ARM::VLD2d32wb_register:
3133  case ARM::VLD2q8wb_register:
3134  case ARM::VLD2q16wb_register:
3135  case ARM::VLD2q32wb_register:
3136  case ARM::VLD2b8wb_fixed:
3137  case ARM::VLD2b16wb_fixed:
3138  case ARM::VLD2b32wb_fixed:
3139  case ARM::VLD2b8wb_register:
3140  case ARM::VLD2b16wb_register:
3141  case ARM::VLD2b32wb_register:
3143  break;
3144  case ARM::VLD3d8_UPD:
3145  case ARM::VLD3d16_UPD:
3146  case ARM::VLD3d32_UPD:
3147  case ARM::VLD3q8_UPD:
3148  case ARM::VLD3q16_UPD:
3149  case ARM::VLD3q32_UPD:
3150  case ARM::VLD4d8_UPD:
3151  case ARM::VLD4d16_UPD:
3152  case ARM::VLD4d32_UPD:
3153  case ARM::VLD4q8_UPD:
3154  case ARM::VLD4q16_UPD:
3155  case ARM::VLD4q32_UPD:
3156  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3157  return MCDisassembler::Fail;
3158  break;
3159  default:
3160  break;
3161  }
3162 
3163  // AddrMode6 Base (register+alignment)
3164  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3165  return MCDisassembler::Fail;
3166 
3167  // AddrMode6 Offset (register)
3168  switch (Inst.getOpcode()) {
3169  default:
3170  // The below have been updated to have explicit am6offset split
3171  // between fixed and register offset. For those instructions not
3172  // yet updated, we need to add an additional reg0 operand for the
3173  // fixed variant.
3174  //
3175  // The fixed offset encodes as Rm == 0xd, so we check for that.
3176  if (Rm == 0xd) {
3178  break;
3179  }
3180  // Fall through to handle the register offset variant.
3181  [[fallthrough]];
3182  case ARM::VLD1d8wb_fixed:
3183  case ARM::VLD1d16wb_fixed:
3184  case ARM::VLD1d32wb_fixed:
3185  case ARM::VLD1d64wb_fixed:
3186  case ARM::VLD1d8Twb_fixed:
3187  case ARM::VLD1d16Twb_fixed:
3188  case ARM::VLD1d32Twb_fixed:
3189  case ARM::VLD1d64Twb_fixed:
3190  case ARM::VLD1d8Qwb_fixed:
3191  case ARM::VLD1d16Qwb_fixed:
3192  case ARM::VLD1d32Qwb_fixed:
3193  case ARM::VLD1d64Qwb_fixed:
3194  case ARM::VLD1d8wb_register:
3195  case ARM::VLD1d16wb_register:
3196  case ARM::VLD1d32wb_register:
3197  case ARM::VLD1d64wb_register:
3198  case ARM::VLD1q8wb_fixed:
3199  case ARM::VLD1q16wb_fixed:
3200  case ARM::VLD1q32wb_fixed:
3201  case ARM::VLD1q64wb_fixed:
3202  case ARM::VLD1q8wb_register:
3203  case ARM::VLD1q16wb_register:
3204  case ARM::VLD1q32wb_register:
3205  case ARM::VLD1q64wb_register:
3206  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3207  // variant encodes Rm == 0xf. Anything else is a register offset post-
3208  // increment and we need to add the register operand to the instruction.
3209  if (Rm != 0xD && Rm != 0xF &&
3210  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3211  return MCDisassembler::Fail;
3212  break;
3213  case ARM::VLD2d8wb_fixed:
3214  case ARM::VLD2d16wb_fixed:
3215  case ARM::VLD2d32wb_fixed:
3216  case ARM::VLD2b8wb_fixed:
3217  case ARM::VLD2b16wb_fixed:
3218  case ARM::VLD2b32wb_fixed:
3219  case ARM::VLD2q8wb_fixed:
3220  case ARM::VLD2q16wb_fixed:
3221  case ARM::VLD2q32wb_fixed:
3222  break;
3223  }
3224 
3225  return S;
3226 }
3227 
3229  uint64_t Address,
3230  const MCDisassembler *Decoder) {
3231  unsigned type = fieldFromInstruction(Insn, 8, 4);
3232  unsigned align = fieldFromInstruction(Insn, 4, 2);
3233  if (type == 6 && (align & 2)) return MCDisassembler::Fail;
3234  if (type == 7 && (align & 2)) return MCDisassembler::Fail;
3235  if (type == 10 && align == 3) return MCDisassembler::Fail;
3236 
3237  unsigned load = fieldFromInstruction(Insn, 21, 1);
3238  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3239  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3240 }
3241 
3243  uint64_t Address,
3244  const MCDisassembler *Decoder) {
3245  unsigned size = fieldFromInstruction(Insn, 6, 2);
3246  if (size == 3) return MCDisassembler::Fail;
3247 
3248  unsigned type = fieldFromInstruction(Insn, 8, 4);
3249  unsigned align = fieldFromInstruction(Insn, 4, 2);
3250  if (type == 8 && align == 3) return MCDisassembler::Fail;
3251  if (type == 9 && align == 3) return MCDisassembler::Fail;
3252 
3253  unsigned load = fieldFromInstruction(Insn, 21, 1);
3254  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3255  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3256 }
3257 
3259  uint64_t Address,
3260  const MCDisassembler *Decoder) {
3261  unsigned size = fieldFromInstruction(Insn, 6, 2);
3262  if (size == 3) return MCDisassembler::Fail;
3263 
3264  unsigned align = fieldFromInstruction(Insn, 4, 2);
3265  if (align & 2) return MCDisassembler::Fail;
3266 
3267  unsigned load = fieldFromInstruction(Insn, 21, 1);
3268  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3269  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3270 }
3271 
3273  uint64_t Address,
3274  const MCDisassembler *Decoder) {
3275  unsigned size = fieldFromInstruction(Insn, 6, 2);
3276  if (size == 3) return MCDisassembler::Fail;
3277 
3278  unsigned load = fieldFromInstruction(Insn, 21, 1);
3279  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3280  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3281 }
3282 
3284  uint64_t Address,
3285  const MCDisassembler *Decoder) {
3287 
3288  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3289  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3290  unsigned wb = fieldFromInstruction(Insn, 16, 4);
3291  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3292  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
3293  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3294 
3295  // Writeback Operand
3296  switch (Inst.getOpcode()) {
3297  case ARM::VST1d8wb_fixed:
3298  case ARM::VST1d16wb_fixed:
3299  case ARM::VST1d32wb_fixed:
3300  case ARM::VST1d64wb_fixed:
3301  case ARM::VST1d8wb_register:
3302  case ARM::VST1d16wb_register:
3303  case ARM::VST1d32wb_register:
3304  case ARM::VST1d64wb_register:
3305  case ARM::VST1q8wb_fixed:
3306  case ARM::VST1q16wb_fixed:
3307  case ARM::VST1q32wb_fixed:
3308  case ARM::VST1q64wb_fixed:
3309  case ARM::VST1q8wb_register:
3310  case ARM::VST1q16wb_register:
3311  case ARM::VST1q32wb_register:
3312  case ARM::VST1q64wb_register:
3313  case ARM::VST1d8Twb_fixed:
3314  case ARM::VST1d16Twb_fixed:
3315  case ARM::VST1d32Twb_fixed:
3316  case ARM::VST1d64Twb_fixed:
3317  case ARM::VST1d8Twb_register:
3318  case ARM::VST1d16Twb_register:
3319  case ARM::VST1d32Twb_register:
3320  case ARM::VST1d64Twb_register:
3321  case ARM::VST1d8Qwb_fixed:
3322  case ARM::VST1d16Qwb_fixed:
3323  case ARM::VST1d32Qwb_fixed:
3324  case ARM::VST1d64Qwb_fixed:
3325  case ARM::VST1d8Qwb_register:
3326  case ARM::VST1d16Qwb_register:
3327  case ARM::VST1d32Qwb_register:
3328  case ARM::VST1d64Qwb_register:
3329  case ARM::VST2d8wb_fixed:
3330  case ARM::VST2d16wb_fixed:
3331  case ARM::VST2d32wb_fixed:
3332  case ARM::VST2d8wb_register:
3333  case ARM::VST2d16wb_register:
3334  case ARM::VST2d32wb_register:
3335  case ARM::VST2q8wb_fixed:
3336  case ARM::VST2q16wb_fixed:
3337  case ARM::VST2q32wb_fixed:
3338  case ARM::VST2q8wb_register:
3339  case ARM::VST2q16wb_register:
3340  case ARM::VST2q32wb_register:
3341  case ARM::VST2b8wb_fixed:
3342  case ARM::VST2b16wb_fixed:
3343  case ARM::VST2b32wb_fixed:
3344  case ARM::VST2b8wb_register:
3345  case ARM::VST2b16wb_register:
3346  case ARM::VST2b32wb_register:
3347  if (Rm == 0xF)
3348  return MCDisassembler::Fail;
3350  break;
3351  case ARM::VST3d8_UPD:
3352  case ARM::VST3d16_UPD:
3353  case ARM::VST3d32_UPD:
3354  case ARM::VST3q8_UPD:
3355  case ARM::VST3q16_UPD:
3356  case ARM::VST3q32_UPD:
3357  case ARM::VST4d8_UPD:
3358  case ARM::VST4d16_UPD:
3359  case ARM::VST4d32_UPD:
3360  case ARM::VST4q8_UPD:
3361  case ARM::VST4q16_UPD:
3362  case ARM::VST4q32_UPD:
3363  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3364  return MCDisassembler::Fail;
3365  break;
3366  default:
3367  break;
3368  }
3369 
3370  // AddrMode6 Base (register+alignment)
3371  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3372  return MCDisassembler::Fail;
3373 
3374  // AddrMode6 Offset (register)
3375  switch (Inst.getOpcode()) {
3376  default:
3377  if (Rm == 0xD)
3379  else if (Rm != 0xF) {
3380  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3381  return MCDisassembler::Fail;
3382  }
3383  break;
3384  case ARM::VST1d8wb_fixed:
3385  case ARM::VST1d16wb_fixed:
3386  case ARM::VST1d32wb_fixed:
3387  case ARM::VST1d64wb_fixed:
3388  case ARM::VST1q8wb_fixed:
3389  case ARM::VST1q16wb_fixed:
3390  case ARM::VST1q32wb_fixed:
3391  case ARM::VST1q64wb_fixed:
3392  case ARM::VST1d8Twb_fixed:
3393  case ARM::VST1d16Twb_fixed:
3394  case ARM::VST1d32Twb_fixed:
3395  case ARM::VST1d64Twb_fixed:
3396  case ARM::VST1d8Qwb_fixed:
3397  case ARM::VST1d16Qwb_fixed:
3398  case ARM::VST1d32Qwb_fixed:
3399  case ARM::VST1d64Qwb_fixed:
3400  case ARM::VST2d8wb_fixed:
3401  case ARM::VST2d16wb_fixed:
3402  case ARM::VST2d32wb_fixed:
3403  case ARM::VST2q8wb_fixed:
3404  case ARM::VST2q16wb_fixed:
3405  case ARM::VST2q32wb_fixed:
3406  case ARM::VST2b8wb_fixed:
3407  case ARM::VST2b16wb_fixed:
3408  case ARM::VST2b32wb_fixed:
3409  break;
3410  }
3411 
3412  // First input register
3413  switch (Inst.getOpcode()) {
3414  case ARM::VST1q16:
3415  case ARM::VST1q32:
3416  case ARM::VST1q64:
3417  case ARM::VST1q8:
3418  case ARM::VST1q16wb_fixed:
3419  case ARM::VST1q16wb_register:
3420  case ARM::VST1q32wb_fixed:
3421  case ARM::VST1q32wb_register:
3422  case ARM::VST1q64wb_fixed:
3423  case ARM::VST1q64wb_register:
3424  case ARM::VST1q8wb_fixed:
3425  case ARM::VST1q8wb_register:
3426  case ARM::VST2d16:
3427  case ARM::VST2d32:
3428  case ARM::VST2d8:
3429  case ARM::VST2d16wb_fixed:
3430  case ARM::VST2d16wb_register:
3431  case ARM::VST2d32wb_fixed:
3432  case ARM::VST2d32wb_register:
3433  case ARM::VST2d8wb_fixed:
3434  case ARM::VST2d8wb_register:
3435  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3436  return MCDisassembler::Fail;
3437  break;
3438  case ARM::VST2b16:
3439  case ARM::VST2b32:
3440  case ARM::VST2b8:
3441  case ARM::VST2b16wb_fixed:
3442  case ARM::VST2b16wb_register:
3443  case ARM::VST2b32wb_fixed:
3444  case ARM::VST2b32wb_register:
3445  case ARM::VST2b8wb_fixed:
3446  case ARM::VST2b8wb_register:
3447  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3448  return MCDisassembler::Fail;
3449  break;
3450  default:
3451  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3452  return MCDisassembler::Fail;
3453  }
3454 
3455  // Second input register
3456  switch (Inst.getOpcode()) {
3457  case ARM::VST3d8:
3458  case ARM::VST3d16:
3459  case ARM::VST3d32:
3460  case ARM::VST3d8_UPD:
3461  case ARM::VST3d16_UPD:
3462  case ARM::VST3d32_UPD:
3463  case ARM::VST4d8:
3464  case ARM::VST4d16:
3465  case ARM::VST4d32:
3466  case ARM::VST4d8_UPD:
3467  case ARM::VST4d16_UPD:
3468  case ARM::VST4d32_UPD:
3469  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
3470  return MCDisassembler::Fail;
3471  break;
3472  case ARM::VST3q8:
3473  case ARM::VST3q16:
3474  case ARM::VST3q32:
3475  case ARM::VST3q8_UPD:
3476  case ARM::VST3q16_UPD:
3477  case ARM::VST3q32_UPD:
3478  case ARM::VST4q8:
3479  case ARM::VST4q16:
3480  case ARM::VST4q32:
3481  case ARM::VST4q8_UPD:
3482  case ARM::VST4q16_UPD:
3483  case ARM::VST4q32_UPD:
3484  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3485  return MCDisassembler::Fail;
3486  break;
3487  default:
3488  break;
3489  }
3490 
3491  // Third input register
3492  switch (Inst.getOpcode()) {
3493  case ARM::VST3d8:
3494  case ARM::VST3d16:
3495  case ARM::VST3d32:
3496  case ARM::VST3d8_UPD:
3497  case ARM::VST3d16_UPD:
3498  case ARM::VST3d32_UPD:
3499  case ARM::VST4d8:
3500  case ARM::VST4d16:
3501  case ARM::VST4d32:
3502  case ARM::VST4d8_UPD:
3503  case ARM::VST4d16_UPD:
3504  case ARM::VST4d32_UPD:
3505  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3506  return MCDisassembler::Fail;
3507  break;
3508  case ARM::VST3q8:
3509  case ARM::VST3q16:
3510  case ARM::VST3q32:
3511  case ARM::VST3q8_UPD:
3512  case ARM::VST3q16_UPD:
3513  case ARM::VST3q32_UPD:
3514  case ARM::VST4q8:
3515  case ARM::VST4q16:
3516  case ARM::VST4q32:
3517  case ARM::VST4q8_UPD:
3518  case ARM::VST4q16_UPD:
3519  case ARM::VST4q32_UPD:
3520  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
3521  return MCDisassembler::Fail;
3522  break;
3523  default:
3524  break;
3525  }
3526 
3527  // Fourth input register
3528  switch (Inst.getOpcode()) {
3529  case ARM::VST4d8:
3530  case ARM::VST4d16:
3531  case ARM::VST4d32:
3532  case ARM::VST4d8_UPD:
3533  case ARM::VST4d16_UPD:
3534  case ARM::VST4d32_UPD:
3535  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
3536  return MCDisassembler::Fail;
3537  break;
3538  case ARM::VST4q8:
3539  case ARM::VST4q16:
3540  case ARM::VST4q32:
3541  case ARM::VST4q8_UPD:
3542  case ARM::VST4q16_UPD:
3543  case ARM::VST4q32_UPD:
3544  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
3545  return MCDisassembler::Fail;
3546  break;
3547  default:
3548  break;
3549  }
3550 
3551  return S;
3552 }
3553 
3555  uint64_t Address,
3556  const MCDisassembler *Decoder) {
3558 
3559  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3560  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3561  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3562  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3563  unsigned align = fieldFromInstruction(Insn, 4, 1);
3564  unsigned size = fieldFromInstruction(Insn, 6, 2);
3565 
3566  if (size == 0 && align == 1)
3567  return MCDisassembler::Fail;
3568  align *= (1 << size);
3569 
3570  switch (Inst.getOpcode()) {
3571  case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
3572  case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
3573  case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
3574  case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
3575  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3576  return MCDisassembler::Fail;
3577  break;
3578  default:
3579  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3580  return MCDisassembler::Fail;
3581  break;
3582  }
3583  if (Rm != 0xF) {
3584  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3585  return MCDisassembler::Fail;
3586  }
3587 
3588  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3589  return MCDisassembler::Fail;
3591 
3592  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3593  // variant encodes Rm == 0xf. Anything else is a register offset post-
3594  // increment and we need to add the register operand to the instruction.
3595  if (Rm != 0xD && Rm != 0xF &&
3596  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3597  return MCDisassembler::Fail;
3598 
3599  return S;
3600 }
3601 
3603  uint64_t Address,
3604  const MCDisassembler *Decoder) {
3606 
3607  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3608  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3609  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3610  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3611  unsigned align = fieldFromInstruction(Insn, 4, 1);
3612  unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
3613  align *= 2*size;
3614 
3615  switch (Inst.getOpcode()) {
3616  case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
3617  case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
3618  case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
3619  case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
3620  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3621  return MCDisassembler::Fail;
3622  break;
3623  case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
3624  case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
3625  case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
3626  case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3627  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3628  return MCDisassembler::Fail;
3629  break;
3630  default:
3631  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3632  return MCDisassembler::Fail;
3633  break;
3634  }
3635 
3636  if (Rm != 0xF)
3638 
3639  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3640  return MCDisassembler::Fail;
3642 
3643  if (Rm != 0xD && Rm != 0xF) {
3644  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3645  return MCDisassembler::Fail;
3646  }
3647 
3648  return S;
3649 }
3650 
3652  uint64_t Address,
3653  const MCDisassembler *Decoder) {
3655 
3656  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3657  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3658  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3659  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3660  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3661 
3662  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3663  return MCDisassembler::Fail;
3664  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3665  return MCDisassembler::Fail;
3666  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3667  return MCDisassembler::Fail;
3668  if (Rm != 0xF) {
3669  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3670  return MCDisassembler::Fail;
3671  }
3672 
3673  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3674  return MCDisassembler::Fail;
3676 
3677  if (Rm == 0xD)
3679  else if (Rm != 0xF) {
3680  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3681  return MCDisassembler::Fail;
3682  }
3683 
3684  return S;
3685 }
3686 
3688  uint64_t Address,
3689  const MCDisassembler *Decoder) {
3691 
3692  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3693  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3694  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3695  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3696  unsigned size = fieldFromInstruction(Insn, 6, 2);
3697  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3698  unsigned align = fieldFromInstruction(Insn, 4, 1);
3699 
3700  if (size == 0x3) {
3701  if (align == 0)
3702  return MCDisassembler::Fail;
3703  align = 16;
3704  } else {
3705  if (size == 2) {
3706  align *= 8;
3707  } else {
3708  size = 1 << size;
3709  align *= 4*size;
3710  }
3711  }
3712 
3713  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3714  return MCDisassembler::Fail;
3715  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3716  return MCDisassembler::Fail;
3717  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3718  return MCDisassembler::Fail;
3719  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3720  return MCDisassembler::Fail;
3721  if (Rm != 0xF) {
3722  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3723  return MCDisassembler::Fail;
3724  }
3725 
3726  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3727  return MCDisassembler::Fail;
3729 
3730  if (Rm == 0xD)
3732  else if (Rm != 0xF) {
3733  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3734  return MCDisassembler::Fail;
3735  }
3736 
3737  return S;
3738 }
3739 
3741  uint64_t Address,
3742  const MCDisassembler *Decoder) {
3744 
3745  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3746  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3747  unsigned imm = fieldFromInstruction(Insn, 0, 4);
3748  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3749  imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3750  imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3751  imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3752  unsigned Q = fieldFromInstruction(Insn, 6, 1);
3753 
3754  if (Q) {
3755  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3756  return MCDisassembler::Fail;
3757  } else {
3758  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3759  return MCDisassembler::Fail;
3760  }
3761 
3762  Inst.addOperand(MCOperand::createImm(imm));
3763 
3764  switch (Inst.getOpcode()) {
3765  case ARM::VORRiv4i16:
3766  case ARM::VORRiv2i32:
3767  case ARM::VBICiv4i16:
3768  case ARM::VBICiv2i32:
3769  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3770  return MCDisassembler::Fail;
3771  break;
3772  case ARM::VORRiv8i16:
3773  case ARM::VORRiv4i32:
3774  case ARM::VBICiv8i16:
3775  case ARM::VBICiv4i32:
3776  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3777  return MCDisassembler::Fail;
3778  break;
3779  default:
3780  break;
3781  }
3782 
3783  return S;
3784 }
3785 
3787  uint64_t Address,
3788  const MCDisassembler *Decoder) {
3790 
3791  unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
3792  fieldFromInstruction(Insn, 13, 3));
3793  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
3794  unsigned imm = fieldFromInstruction(Insn, 0, 4);
3795  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3796  imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3797  imm |= cmode << 8;
3798  imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3799 
3800  if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3801  return MCDisassembler::Fail;
3802 
3803  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3804  return MCDisassembler::Fail;
3805 
3806  Inst.addOperand(MCOperand::createImm(imm));
3807 
3811 
3812  return S;
3813 }
3814 
3816  uint64_t Address,
3817  const MCDisassembler *Decoder) {
3819 
3820  unsigned Qd = fieldFromInstruction(Insn, 13, 3);
3821  Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
3822  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3823  return MCDisassembler::Fail;
3824  Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3825 
3826  unsigned Qn = fieldFromInstruction(Insn, 17, 3);
3827  Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
3828  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
3829  return MCDisassembler::Fail;
3830  unsigned Qm = fieldFromInstruction(Insn, 1, 3);
3831  Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
3832  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3833  return MCDisassembler::Fail;
3834  if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
3835  Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3836  Inst.addOperand(MCOperand::createImm(Qd));
3837 
3838  return S;
3839 }
3840 
3842  uint64_t Address,
3843  const MCDisassembler *Decoder) {
3845 
3846  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3847  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3848  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3849  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3850  unsigned size = fieldFromInstruction(Insn, 18, 2);
3851 
3852  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3853  return MCDisassembler::Fail;
3854  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3855  return MCDisassembler::Fail;
3856  Inst.addOperand(MCOperand::createImm(8 << size));
3857 
3858  return S;
3859 }
3860 
3861 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3862  uint64_t Address,
3863  const MCDisassembler *Decoder) {
3864  Inst.addOperand(MCOperand::createImm(8 - Val));
3865  return MCDisassembler::Success;
3866 }
3867 
3868 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3869  uint64_t Address,
3870  const MCDisassembler *Decoder) {
3871  Inst.addOperand(MCOperand::createImm(16 - Val));
3872  return MCDisassembler::Success;
3873 }
3874 
3875 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3876  uint64_t Address,
3877  const MCDisassembler *Decoder) {
3878  Inst.addOperand(MCOperand::createImm(32 - Val));
3879  return MCDisassembler::Success;
3880 }
3881 
3882 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3883  uint64_t Address,
3884  const MCDisassembler *Decoder) {
3885  Inst.addOperand(MCOperand::createImm(64 - Val));
3886  return MCDisassembler::Success;
3887 }
3888 
3890  uint64_t Address,
3891  const MCDisassembler *Decoder) {
3893 
3894  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3895  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3896  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3897  Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3898  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3899  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3900  unsigned op = fieldFromInstruction(Insn, 6, 1);
3901 
3902  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3903  return MCDisassembler::Fail;
3904  if (op) {
3905  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3906  return MCDisassembler::Fail; // Writeback
3907  }
3908 
3909  switch (Inst.getOpcode()) {
3910  case ARM::VTBL2:
3911  case ARM::VTBX2:
3912  if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3913  return MCDisassembler::Fail;
3914  break;
3915  default:
3916  if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3917  return MCDisassembler::Fail;
3918  }
3919 
3920  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3921  return MCDisassembler::Fail;
3922 
3923  return S;
3924 }
3925 
3927  uint64_t Address,
3928  const MCDisassembler *Decoder) {
3930 
3931  unsigned dst = fieldFromInstruction(Insn, 8, 3);
3932  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3933 
3934  if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3935  return MCDisassembler::Fail;
3936 
3937  switch(Inst.getOpcode()) {
3938  default:
3939  return MCDisassembler::Fail;
3940  case ARM::tADR:
3941  break; // tADR does not explicitly represent the PC as an operand.
3942  case ARM::tADDrSPi:
3943  Inst.addOperand(MCOperand::createReg(ARM::SP));
3944  break;
3945  }
3946 
3947  Inst.addOperand(MCOperand::createImm(imm));
3948  return S;
3949 }
3950 
3951 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3952  uint64_t Address,
3953  const MCDisassembler *Decoder) {
3954  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3955  true, 2, Inst, Decoder))
3956  Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3957  return MCDisassembler::Success;
3958 }
3959 
3960 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3961  uint64_t Address,
3962  const MCDisassembler *Decoder) {
3963  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3964  true, 4, Inst, Decoder))
3965  Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3966  return MCDisassembler::Success;
3967 }
3968 
3969 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3970  uint64_t Address,
3971  const MCDisassembler *Decoder) {
3972  if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3973  true, 2, Inst, Decoder))
3974  Inst.addOperand(MCOperand::createImm(Val << 1));
3975  return MCDisassembler::Success;
3976 }
3977 
3978 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3979  uint64_t Address,
3980  const MCDisassembler *Decoder) {
3982 
3983  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3984  unsigned Rm = fieldFromInstruction(Val, 3, 3);
3985 
3986  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3987  return MCDisassembler::Fail;
3988  if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3989  return MCDisassembler::Fail;
3990 
3991  return S;
3992 }
3993 
3994 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3995  uint64_t Address,
3996  const MCDisassembler *Decoder) {
3998 
3999  unsigned Rn = fieldFromInstruction(Val, 0, 3);
4000  unsigned imm = fieldFromInstruction(Val, 3, 5);
4001 
4002  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4003  return MCDisassembler::Fail;
4004  Inst.addOperand(MCOperand::createImm(imm));
4005 
4006  return S;
4007 }
4008 
4009 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
4010  uint64_t Address,
4011  const MCDisassembler *Decoder) {
4012  unsigned imm = Val << 2;
4013 
4014  Inst.addOperand(MCOperand::createImm(imm));
4015  tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
4016 
4017  return MCDisassembler::Success;
4018 }
4019 
4020 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
4021  uint64_t Address,
4022  const MCDisassembler *Decoder) {
4023  Inst.addOperand(MCOperand::createReg(ARM::SP));
4024  Inst.addOperand(MCOperand::createImm(Val));
4025 
4026  return MCDisassembler::Success;
4027 }
4028 
4029 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
4030  uint64_t Address,
4031  const MCDisassembler *Decoder) {
4033 
4034  unsigned Rn = fieldFromInstruction(Val, 6, 4);
4035  unsigned Rm = fieldFromInstruction(Val, 2, 4);
4036  unsigned imm = fieldFromInstruction(Val, 0, 2);
4037 
4038  // Thumb stores cannot use PC as dest register.
4039  switch (Inst.getOpcode()) {
4040  case ARM::t2STRHs:
4041  case ARM::t2STRBs:
4042  case ARM::t2STRs:
4043  if (Rn == 15)
4044  return MCDisassembler::Fail;
4045  break;
4046  default:
4047  break;
4048  }
4049 
4050  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4051  return MCDisassembler::Fail;
4052  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4053  return MCDisassembler::Fail;
4054  Inst.addOperand(MCOperand::createImm(imm));
4055 
4056  return S;
4057 }
4058 
4060  uint64_t Address,
4061  const MCDisassembler *Decoder) {
4063 
4064  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4065  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4066 
4067  const FeatureBitset &featureBits =
4068  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4069 
4070  bool hasMP = featureBits[ARM::FeatureMP];
4071  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4072 
4073  if (Rn == 15) {
4074  switch (Inst.getOpcode()) {
4075  case ARM::t2LDRBs:
4076  Inst.setOpcode(ARM::t2LDRBpci);
4077  break;
4078  case ARM::t2LDRHs:
4079  Inst.setOpcode(ARM::t2LDRHpci);
4080  break;
4081  case ARM::t2LDRSHs:
4082  Inst.setOpcode(ARM::t2LDRSHpci);
4083  break;
4084  case ARM::t2LDRSBs:
4085  Inst.setOpcode(ARM::t2LDRSBpci);
4086  break;
4087  case ARM::t2LDRs:
4088  Inst.setOpcode(ARM::t2LDRpci);
4089  break;
4090  case ARM::t2PLDs:
4091  Inst.setOpcode(ARM::t2PLDpci);
4092  break;
4093  case ARM::t2PLIs:
4094  Inst.setOpcode(ARM::t2PLIpci);
4095  break;
4096  default:
4097  return MCDisassembler::Fail;
4098  }
4099 
4100  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4101  }
4102 
4103  if (Rt == 15) {
4104  switch (Inst.getOpcode()) {
4105  case ARM::t2LDRSHs:
4106  return MCDisassembler::Fail;
4107  case ARM::t2LDRHs:
4108  Inst.setOpcode(ARM::t2PLDWs);
4109  break;
4110  case ARM::t2LDRSBs:
4111  Inst.setOpcode(ARM::t2PLIs);
4112  break;
4113  default:
4114  break;
4115  }
4116  }
4117 
4118  switch (Inst.getOpcode()) {
4119  case ARM::t2PLDs:
4120  break;
4121  case ARM::t2PLIs:
4122  if (!hasV7Ops)
4123  return MCDisassembler::Fail;
4124  break;
4125  case ARM::t2PLDWs:
4126  if (!hasV7Ops || !hasMP)
4127  return MCDisassembler::Fail;
4128  break;
4129  default:
4130  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4131  return MCDisassembler::Fail;
4132  }
4133 
4134  unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
4135  addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
4136  addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
4137  if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
4138  return MCDisassembler::Fail;
4139 
4140  return S;
4141 }
4142 
4143 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
4144  uint64_t Address,
4145  const MCDisassembler *Decoder) {
4147 
4148  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4149  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4150  unsigned U = fieldFromInstruction(Insn, 9, 1);
4151  unsigned imm = fieldFromInstruction(Insn, 0, 8);
4152  imm |= (U << 8);
4153  imm |= (Rn << 9);
4154  unsigned add = fieldFromInstruction(Insn, 9, 1);
4155 
4156  const FeatureBitset &featureBits =
4157  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4158 
4159  bool hasMP = featureBits[ARM::FeatureMP];
4160  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4161 
4162  if (Rn == 15) {
4163  switch (Inst.getOpcode()) {
4164  case ARM::t2LDRi8:
4165  Inst.setOpcode(ARM::t2LDRpci);
4166  break;
4167  case ARM::t2LDRBi8:
4168  Inst.setOpcode(ARM::t2LDRBpci);
4169  break;
4170  case ARM::t2LDRSBi8:
4171  Inst.setOpcode(ARM::t2LDRSBpci);
4172  break;
4173  case ARM::t2LDRHi8:
4174  Inst.setOpcode(ARM::t2LDRHpci);
4175  break;
4176  case ARM::t2LDRSHi8:
4177  Inst.setOpcode(ARM::t2LDRSHpci);
4178  break;
4179  case ARM::t2PLDi8:
4180  Inst.setOpcode(ARM::t2PLDpci);
4181  break;
4182  case ARM::t2PLIi8:
4183  Inst.setOpcode(ARM::t2PLIpci);
4184  break;
4185  default:
4186  return MCDisassembler::Fail;
4187  }
4188  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4189  }
4190 
4191  if (Rt == 15) {
4192  switch (Inst.getOpcode()) {
4193  case ARM::t2LDRSHi8:
4194  return MCDisassembler::Fail;
4195  case ARM::t2LDRHi8:
4196  if (!add)
4197  Inst.setOpcode(ARM::t2PLDWi8);
4198  break;
4199  case ARM::t2LDRSBi8:
4200  Inst.setOpcode(ARM::t2PLIi8);
4201  break;
4202  default:
4203  break;
4204  }
4205  }
4206 
4207  switch (Inst.getOpcode()) {
4208  case ARM::t2PLDi8:
4209  break;
4210  case ARM::t2PLIi8:
4211  if (!hasV7Ops)
4212  return MCDisassembler::Fail;
4213  break;
4214  case ARM::t2PLDWi8:
4215  if (!hasV7Ops || !hasMP)
4216  return MCDisassembler::Fail;
4217  break;
4218  default:
4219  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4220  return MCDisassembler::Fail;
4221  }
4222 
4223  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4224  return MCDisassembler::Fail;
4225  return S;
4226 }
4227 
4229  uint64_t Address,
4230  const MCDisassembler *Decoder) {
4232 
4233  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4234  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4235  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4236  imm |= (Rn << 13);
4237 
4238  const FeatureBitset &featureBits =
4239  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4240 
4241  bool hasMP = featureBits[ARM::FeatureMP];
4242  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4243 
4244  if (Rn == 15) {
4245  switch (Inst.getOpcode()) {
4246  case ARM::t2LDRi12:
4247  Inst.setOpcode(ARM::t2LDRpci);
4248  break;
4249  case ARM::t2LDRHi12:
4250  Inst.setOpcode(ARM::t2LDRHpci);
4251  break;
4252  case ARM::t2LDRSHi12:
4253  Inst.setOpcode(ARM::t2LDRSHpci);
4254  break;
4255  case ARM::t2LDRBi12:
4256  Inst.setOpcode(ARM::t2LDRBpci);
4257  break;
4258  case ARM::t2LDRSBi12:
4259  Inst.setOpcode(ARM::t2LDRSBpci);
4260  break;
4261  case ARM::t2PLDi12:
4262  Inst.setOpcode(ARM::t2PLDpci);
4263  break;
4264  case ARM::t2PLIi12:
4265  Inst.setOpcode(ARM::t2PLIpci);
4266  break;
4267  default:
4268  return MCDisassembler::Fail;
4269  }
4270  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4271  }
4272 
4273  if (Rt == 15) {
4274  switch (Inst.getOpcode()) {
4275  case ARM::t2LDRSHi12:
4276  return MCDisassembler::Fail;
4277  case ARM::t2LDRHi12:
4278  Inst.setOpcode(ARM::t2PLDWi12);
4279  break;
4280  case ARM::t2LDRSBi12:
4281  Inst.setOpcode(ARM::t2PLIi12);
4282  break;
4283  default:
4284  break;
4285  }
4286  }
4287 
4288  switch (Inst.getOpcode()) {
4289  case ARM::t2PLDi12:
4290  break;
4291  case ARM::t2PLIi12:
4292  if (!hasV7Ops)
4293  return MCDisassembler::Fail;
4294  break;
4295  case ARM::t2PLDWi12:
4296  if (!hasV7Ops || !hasMP)
4297  return MCDisassembler::Fail;
4298  break;
4299  default:
4300  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4301  return MCDisassembler::Fail;
4302  }
4303 
4304  if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
4305  return MCDisassembler::Fail;
4306  return S;
4307 }
4308 
4309 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
4310  const MCDisassembler *Decoder) {
4312 
4313  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4314  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4315  unsigned imm = fieldFromInstruction(Insn, 0, 8);
4316  imm |= (Rn << 9);
4317 
4318  if (Rn == 15) {
4319  switch (Inst.getOpcode()) {
4320  case ARM::t2LDRT:
4321  Inst.setOpcode(ARM::t2LDRpci);
4322  break;
4323  case ARM::t2LDRBT:
4324  Inst.setOpcode(ARM::t2LDRBpci);
4325  break;
4326  case ARM::t2LDRHT:
4327  Inst.setOpcode(ARM::t2LDRHpci);
4328  break;
4329  case ARM::t2LDRSBT:
4330  Inst.setOpcode(ARM::t2LDRSBpci);
4331  break;
4332  case ARM::t2LDRSHT:
4333  Inst.setOpcode(ARM::t2LDRSHpci);
4334  break;
4335  default:
4336  return MCDisassembler::Fail;
4337  }
4338  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4339  }
4340 
4341  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4342  return MCDisassembler::Fail;
4343  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4344  return MCDisassembler::Fail;
4345  return S;
4346 }
4347 
4349  uint64_t Address,
4350  const MCDisassembler *Decoder) {
4352 
4353  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4354  unsigned U = fieldFromInstruction(Insn, 23, 1);
4355  int imm = fieldFromInstruction(Insn, 0, 12);
4356 
4357  const FeatureBitset &featureBits =
4358  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4359 
4360  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4361 
4362  if (Rt == 15) {
4363  switch (Inst.getOpcode()) {
4364  case ARM::t2LDRBpci:
4365  case ARM::t2LDRHpci:
4366  Inst.setOpcode(ARM::t2PLDpci);
4367  break;
4368  case ARM::t2LDRSBpci:
4369  Inst.setOpcode(ARM::t2PLIpci);
4370  break;
4371  case ARM::t2LDRSHpci:
4372  return MCDisassembler::Fail;
4373  default:
4374  break;
4375  }
4376  }
4377 
4378  switch(Inst.getOpcode()) {
4379  case ARM::t2PLDpci:
4380  break;
4381  case ARM::t2PLIpci:
4382  if (!hasV7Ops)
4383  return MCDisassembler::Fail;
4384  break;
4385  default:
4386  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4387  return MCDisassembler::Fail;
4388  }
4389 
4390  if (!U) {
4391  // Special case for #-0.
4392  if (imm == 0)
4393  imm = INT32_MIN;
4394  else
4395  imm = -imm;
4396  }
4397  Inst.addOperand(MCOperand::createImm(imm));
4398 
4399  return S;
4400 }
4401 
4402 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
4403  const MCDisassembler *Decoder) {
4404  if (Val == 0)
4405  Inst.addOperand(MCOperand::createImm(INT32_MIN));
4406  else {
4407  int imm = Val & 0xFF;
4408 
4409  if (!(Val & 0x100)) imm *= -1;
4410  Inst.addOperand(MCOperand::createImm(imm * 4));
4411  }
4412 
4413  return MCDisassembler::Success;
4414 }
4415 
4416 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
4417  const MCDisassembler *Decoder) {
4418  if (Val == 0)
4419  Inst.addOperand(MCOperand::createImm(INT32_MIN));
4420  else {
4421  int imm = Val & 0x7F;
4422 
4423  if (!(Val & 0x80))
4424  imm *= -1;
4425  Inst.addOperand(MCOperand::createImm(imm * 4));
4426  }
4427 
4428  return MCDisassembler::Success;
4429 }
4430 
4431 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
4432  uint64_t Address,
4433  const MCDisassembler *Decoder) {
4435 
4436  unsigned Rn = fieldFromInstruction(Val, 9, 4);
4437  unsigned imm = fieldFromInstruction(Val, 0, 9);
4438 
4439  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4440  return MCDisassembler::Fail;
4441  if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
4442  return MCDisassembler::Fail;
4443 
4444  return S;
4445 }
4446 
4447 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
4448  uint64_t Address,
4449  const MCDisassembler *Decoder) {
4451 
4452  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4453  unsigned imm = fieldFromInstruction(Val, 0, 8);
4454 
4455  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4456  return MCDisassembler::Fail;
4457  if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
4458  return MCDisassembler::Fail;
4459 
4460  return S;
4461 }
4462 
4464  uint64_t Address,
4465  const MCDisassembler *Decoder) {
4467 
4468  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4469  unsigned imm = fieldFromInstruction(Val, 0, 8);
4470 
4471  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4472  return MCDisassembler::Fail;
4473 
4474  Inst.addOperand(MCOperand::createImm(imm));
4475 
4476  return S;
4477 }
4478 
4479 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
4480  const MCDisassembler *Decoder) {
4481  int imm = Val & 0xFF;
4482  if (Val == 0)
4483  imm = INT32_MIN;
4484  else if (!(Val & 0x100))
4485  imm *= -1;
4486  Inst.addOperand(MCOperand::createImm(imm));
4487 
4488  return MCDisassembler::Success;
4489 }
4490 
4491 template <int shift>
4492 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
4493  const MCDisassembler *Decoder) {
4494  int imm = Val & 0x7F;
4495  if (Val == 0)
4496  imm = INT32_MIN;
4497  else if (!(Val & 0x80))
4498  imm *= -1;
4499  if (imm != INT32_MIN)
4500  imm *= (1U << shift);
4501  Inst.addOperand(MCOperand::createImm(imm));
4502 
4503  return MCDisassembler::Success;
4504 }
4505 
4506 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
4507  uint64_t Address,
4508  const MCDisassembler *Decoder) {
4510 
4511  unsigned Rn = fieldFromInstruction(Val, 9, 4);
4512  unsigned imm = fieldFromInstruction(Val, 0, 9);
4513 
4514  // Thumb stores cannot use PC as dest register.
4515  switch (Inst.getOpcode()) {
4516  case ARM::t2STRT:
4517  case ARM::t2STRBT:
4518  case ARM::t2STRHT:
4519  case ARM::t2STRi8:
4520  case ARM::t2STRHi8:
4521  case ARM::t2STRBi8:
4522  if (Rn == 15)
4523  return MCDisassembler::Fail;
4524  break;
4525  default:
4526  break;
4527  }
4528 
4529  // Some instructions always use an additive offset.
4530  switch (Inst.getOpcode()) {
4531  case ARM::t2LDRT:
4532  case ARM::t2LDRBT:
4533  case ARM::t2LDRHT:
4534  case ARM::t2LDRSBT:
4535  case ARM::t2LDRSHT:
4536  case ARM::t2STRT:
4537  case ARM::t2STRBT:
4538  case ARM::t2STRHT:
4539  imm |= 0x100;
4540  break;
4541  default:
4542  break;
4543  }
4544 
4545  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4546  return MCDisassembler::Fail;
4547  if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
4548  return MCDisassembler::Fail;
4549 
4550  return S;
4551 }
4552 
4553 template <int shift>
4554 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
4555  uint64_t Address,
4556  const MCDisassembler *Decoder) {
4558 
4559  unsigned Rn = fieldFromInstruction(Val, 8, 3);
4560  unsigned imm = fieldFromInstruction(Val, 0, 8);
4561 
4562  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4563  return MCDisassembler::Fail;
4564  if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4565  return MCDisassembler::Fail;
4566 
4567  return S;
4568 }
4569 
4570 template <int shift, int WriteBack>
4571 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
4572  uint64_t Address,
4573  const MCDisassembler *Decoder) {
4575 
4576  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4577  unsigned imm = fieldFromInstruction(Val, 0, 8);
4578  if (WriteBack) {
4579  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4580  return MCDisassembler::Fail;
4581  } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4582  return MCDisassembler::Fail;
4583  if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4584  return MCDisassembler::Fail;
4585 
4586  return S;
4587 }
4588 
4589 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
4590  uint64_t Address,
4591  const MCDisassembler *Decoder) {
4593 
4594  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4595  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4596  unsigned addr = fieldFromInstruction(Insn, 0, 8);
4597  addr |= fieldFromInstruction(Insn, 9, 1) << 8;
4598  addr |= Rn << 9;
4599  unsigned load = fieldFromInstruction(Insn, 20, 1);
4600 
4601  if (Rn == 15) {
4602  switch (Inst.getOpcode()) {
4603  case ARM::t2LDR_PRE:
4604  case ARM::t2LDR_POST:
4605  Inst.setOpcode(ARM::t2LDRpci);
4606  break;
4607  case ARM::t2LDRB_PRE:
4608  case ARM::t2LDRB_POST:
4609  Inst.setOpcode(ARM::t2LDRBpci);
4610  break;
4611  case ARM::t2LDRH_PRE:
4612  case ARM::t2LDRH_POST:
4613  Inst.setOpcode(ARM::t2LDRHpci);
4614  break;
4615  case ARM::t2LDRSB_PRE:
4616  case ARM::t2LDRSB_POST:
4617  if (Rt == 15)
4618  Inst.setOpcode(ARM::t2PLIpci);
4619  else
4620  Inst.setOpcode(ARM::t2LDRSBpci);
4621  break;
4622  case ARM::t2LDRSH_PRE:
4623  case ARM::t2LDRSH_POST:
4624  Inst.setOpcode(ARM::t2LDRSHpci);
4625  break;
4626  default:
4627  return MCDisassembler::Fail;
4628  }
4629  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4630  }
4631 
4632  if (!load) {
4633  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4634  return MCDisassembler::Fail;
4635  }
4636 
4637  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4638  return MCDisassembler::Fail;
4639 
4640  if (load) {
4641  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4642  return MCDisassembler::Fail;
4643  }
4644 
4645  if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
4646  return MCDisassembler::Fail;
4647 
4648  return S;
4649 }
4650 
4651 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
4652  uint64_t Address,
4653  const MCDisassembler *Decoder) {
4655 
4656  unsigned Rn = fieldFromInstruction(Val, 13, 4);
4657  unsigned imm = fieldFromInstruction(Val, 0, 12);
4658 
4659  // Thumb stores cannot use PC as dest register.
4660  switch (Inst.getOpcode()) {
4661  case ARM::t2STRi12:
4662  case ARM::t2STRBi12:
4663  case ARM::t2STRHi12:
4664  if (Rn == 15)
4665  return MCDisassembler::Fail;
4666  break;
4667  default:
4668  break;
4669  }
4670 
4671  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4672  return MCDisassembler::Fail;
4673  Inst.addOperand(MCOperand::createImm(imm));
4674 
4675  return S;
4676 }
4677 
4679  uint64_t Address,
4680  const MCDisassembler *Decoder) {
4681  unsigned imm = fieldFromInstruction(Insn, 0, 7);
4682 
4683  Inst.addOperand(MCOperand::createReg(ARM::SP));
4684  Inst.addOperand(MCOperand::createReg(ARM::SP));
4685  Inst.addOperand(MCOperand::createImm(imm));
4686 
4687  return MCDisassembler::Success;
4688 }
4689 
4691  uint64_t Address,
4692  const MCDisassembler *Decoder) {
4694 
4695  if (Inst.getOpcode() == ARM::tADDrSP) {
4696  unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
4697  Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
4698 
4699  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4700  return MCDisassembler::Fail;
4701  Inst.addOperand(MCOperand::createReg(ARM::SP));
4702  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4703  return MCDisassembler::Fail;
4704  } else if (Inst.getOpcode() == ARM::tADDspr) {
4705  unsigned Rm = fieldFromInstruction(Insn, 3, 4);
4706 
4707  Inst.addOperand(MCOperand::createReg(ARM::SP));
4708  Inst.addOperand(MCOperand::createReg(ARM::SP));
4709  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4710  return MCDisassembler::Fail;
4711  }
4712 
4713  return S;
4714 }
4715 
4717  uint64_t Address,
4718  const MCDisassembler *Decoder) {
4719  unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
4720  unsigned flags = fieldFromInstruction(Insn, 0, 3);
4721 
4722  Inst.addOperand(MCOperand::createImm(imod));
4723  Inst.addOperand(MCOperand::createImm(flags));
4724 
4725  return MCDisassembler::Success;
4726 }
4727 
4728 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
4729  uint64_t Address,
4730  const MCDisassembler *Decoder) {
4732  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4733  unsigned add = fieldFromInstruction(Insn, 4, 1);
4734 
4735  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
4736  return MCDisassembler::Fail;
4738 
4739  return S;
4740 }
4741 
4743  uint64_t Address,
4744  const MCDisassembler *Decoder) {
4746  unsigned Rn = fieldFromInstruction(Insn, 3, 4);
4747  unsigned Qm = fieldFromInstruction(Insn, 0, 3);
4748 
4749  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4750  return MCDisassembler::Fail;
4751  if (!Check(