LLVM  15.0.0git
ARMDisassembler.cpp
Go to the documentation of this file.
1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ARMBaseInstrInfo.h"
14 #include "Utils/ARMBaseInfo.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCDecoderOps.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/TargetRegistry.h"
23 #include "llvm/Support/Compiler.h"
27 #include <algorithm>
28 #include <cassert>
29 #include <cstdint>
30 #include <vector>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "arm-disassembler"
35 
37 
38 namespace {
39 
40  // Handles the condition code status of instructions in IT blocks
41  class ITStatus
42  {
43  public:
44  // Returns the condition code for instruction in IT block
45  unsigned getITCC() {
46  unsigned CC = ARMCC::AL;
47  if (instrInITBlock())
48  CC = ITStates.back();
49  return CC;
50  }
51 
52  // Advances the IT block state to the next T or E
53  void advanceITState() {
54  ITStates.pop_back();
55  }
56 
57  // Returns true if the current instruction is in an IT block
58  bool instrInITBlock() {
59  return !ITStates.empty();
60  }
61 
62  // Returns true if current instruction is the last instruction in an IT block
63  bool instrLastInITBlock() {
64  return ITStates.size() == 1;
65  }
66 
67  // Called when decoding an IT instruction. Sets the IT state for
68  // the following instructions that for the IT block. Firstcond
69  // corresponds to the field in the IT instruction encoding; Mask
70  // is in the MCOperand format in which 1 means 'else' and 0 'then'.
71  void setITState(char Firstcond, char Mask) {
72  // (3 - the number of trailing zeros) is the number of then / else.
73  unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
74  unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
75  assert(NumTZ <= 3 && "Invalid IT mask!");
76  // push condition codes onto the stack the correct order for the pops
77  for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
78  unsigned Else = (Mask >> Pos) & 1;
79  ITStates.push_back(CCBits ^ Else);
80  }
81  ITStates.push_back(CCBits);
82  }
83 
84  private:
85  std::vector<unsigned char> ITStates;
86  };
87 
88  class VPTStatus
89  {
90  public:
91  unsigned getVPTPred() {
92  unsigned Pred = ARMVCC::None;
93  if (instrInVPTBlock())
94  Pred = VPTStates.back();
95  return Pred;
96  }
97 
98  void advanceVPTState() {
99  VPTStates.pop_back();
100  }
101 
102  bool instrInVPTBlock() {
103  return !VPTStates.empty();
104  }
105 
106  bool instrLastInVPTBlock() {
107  return VPTStates.size() == 1;
108  }
109 
110  void setVPTState(char Mask) {
111  // (3 - the number of trailing zeros) is the number of then / else.
112  unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
113  assert(NumTZ <= 3 && "Invalid VPT mask!");
114  // push predicates onto the stack the correct order for the pops
115  for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
116  bool T = ((Mask >> Pos) & 1) == 0;
117  if (T)
118  VPTStates.push_back(ARMVCC::Then);
119  else
120  VPTStates.push_back(ARMVCC::Else);
121  }
122  VPTStates.push_back(ARMVCC::Then);
123  }
124 
125  private:
127  };
128 
129 /// ARM disassembler for all ARM platforms.
130 class ARMDisassembler : public MCDisassembler {
131 public:
132  ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
133  MCDisassembler(STI, Ctx) {
134  }
135 
136  ~ARMDisassembler() override = default;
137 
138  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
139  ArrayRef<uint8_t> Bytes, uint64_t Address,
140  raw_ostream &CStream) const override;
141 
142 private:
143  DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size,
144  ArrayRef<uint8_t> Bytes, uint64_t Address,
145  raw_ostream &CStream) const;
146 
147  DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,
148  ArrayRef<uint8_t> Bytes, uint64_t Address,
149  raw_ostream &CStream) const;
150 
151  mutable ITStatus ITBlock;
152  mutable VPTStatus VPTBlock;
153 
154  DecodeStatus AddThumbPredicate(MCInst&) const;
155  void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
156 };
157 
158 } // end anonymous namespace
159 
160 static bool Check(DecodeStatus &Out, DecodeStatus In) {
161  switch (In) {
163  // Out stays the same.
164  return true;
166  Out = In;
167  return true;
169  Out = In;
170  return false;
171  }
172  llvm_unreachable("Invalid DecodeStatus!");
173 }
174 
175 // Forward declare these because the autogenerated code will reference them.
176 // Definitions are further down.
177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
178  uint64_t Address,
179  const MCDisassembler *Decoder);
180 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
181  uint64_t Address,
182  const MCDisassembler *Decoder);
183 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
184  uint64_t Address,
185  const MCDisassembler *Decoder);
186 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
187  uint64_t Address,
188  const MCDisassembler *Decoder);
189 static DecodeStatus
190 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
191  uint64_t Address,
192  const MCDisassembler *Decoder);
193 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
194  uint64_t Address,
195  const MCDisassembler *Decoder);
196 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
197  uint64_t Address,
198  const MCDisassembler *Decoder);
199 static DecodeStatus
200 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
201  const MCDisassembler *Decoder);
202 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
203  uint64_t Address,
204  const MCDisassembler *Decoder);
205 static DecodeStatus
206 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
207  const MCDisassembler *Decoder);
208 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
209  uint64_t Address,
210  const MCDisassembler *Decoder);
211 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
212  uint64_t Address,
213  const MCDisassembler *Decoder);
214 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
215  uint64_t Address,
216  const MCDisassembler *Decoder);
217 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
218  uint64_t Address,
219  const MCDisassembler *Decoder);
220 static DecodeStatus
221 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
222  const MCDisassembler *Decoder);
223 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
224  uint64_t Address,
225  const MCDisassembler *Decoder);
226 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
227  uint64_t Address,
228  const MCDisassembler *Decoder);
229 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
230  uint64_t Address,
231  const MCDisassembler *Decoder);
232 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
233  uint64_t Address,
234  const MCDisassembler *Decoder);
235 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
236  uint64_t Address,
237  const MCDisassembler *Decoder);
238 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
239  uint64_t Address,
240  const MCDisassembler *Decoder);
241 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
242  uint64_t Address,
243  const MCDisassembler *Decoder);
244 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
245  uint64_t Address,
246  const MCDisassembler *Decoder);
247 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
248  uint64_t Address,
249  const MCDisassembler *Decoder);
250 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
251  uint64_t Address,
252  const MCDisassembler *Decoder);
253 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
254  uint64_t Address,
255  const MCDisassembler *Decoder);
256 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
257  uint64_t Address,
258  const MCDisassembler *Decoder);
259 static DecodeStatus
260 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
261  const MCDisassembler *Decoder);
262 
263 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
264  uint64_t Address,
265  const MCDisassembler *Decoder);
266 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
267  uint64_t Address,
268  const MCDisassembler *Decoder);
269 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
270  uint64_t Address,
271  const MCDisassembler *Decoder);
272 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
273  uint64_t Address,
274  const MCDisassembler *Decoder);
275 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
276  uint64_t Address,
277  const MCDisassembler *Decoder);
278 
279 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
280  uint64_t Address,
281  const MCDisassembler *Decoder);
282 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
283  uint64_t Address,
284  const MCDisassembler *Decoder);
285 static DecodeStatus
286 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
287  const MCDisassembler *Decoder);
288 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
289  uint64_t Address,
290  const MCDisassembler *Decoder);
291 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
292  uint64_t Address,
293  const MCDisassembler *Decoder);
294 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
295  uint64_t Address,
296  const MCDisassembler *Decoder);
297 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
298  uint64_t Address,
299  const MCDisassembler *Decoder);
300 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
301  uint64_t Address,
302  const MCDisassembler *Decoder);
303 
304 static DecodeStatus
306  uint64_t Adddress,
307  const MCDisassembler *Decoder);
308 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
309  uint64_t Address,
310  const MCDisassembler *Decoder);
311 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
312  uint64_t Address,
313  const MCDisassembler *Decoder);
314 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
315  uint64_t Address,
316  const MCDisassembler *Decoder);
317 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
318  uint64_t Address,
319  const MCDisassembler *Decoder);
320 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
321  uint64_t Address,
322  const MCDisassembler *Decoder);
323 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
324  uint64_t Address,
325  const MCDisassembler *Decoder);
326 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
327  uint64_t Address,
328  const MCDisassembler *Decoder);
329 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
330  uint64_t Address,
331  const MCDisassembler *Decoder);
333  uint64_t Address,
334  const MCDisassembler *Decoder);
335 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
336  uint64_t Address,
337  const MCDisassembler *Decoder);
338 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
339  uint64_t Address,
340  const MCDisassembler *Decoder);
341 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
342  uint64_t Address,
343  const MCDisassembler *Decoder);
344 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
345  uint64_t Address,
346  const MCDisassembler *Decoder);
347 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
348  uint64_t Address,
349  const MCDisassembler *Decoder);
350 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
351  uint64_t Address,
352  const MCDisassembler *Decoder);
353 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
354  uint64_t Address,
355  const MCDisassembler *Decoder);
356 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
357  uint64_t Address,
358  const MCDisassembler *Decoder);
359 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
360  uint64_t Address,
361  const MCDisassembler *Decoder);
362 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
363  uint64_t Address,
364  const MCDisassembler *Decoder);
365 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
366  uint64_t Address,
367  const MCDisassembler *Decoder);
368 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
369  uint64_t Address,
370  const MCDisassembler *Decoder);
371 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
372  uint64_t Address,
373  const MCDisassembler *Decoder);
374 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
375  uint64_t Address,
376  const MCDisassembler *Decoder);
377 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
378  uint64_t Address,
379  const MCDisassembler *Decoder);
380 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
381  uint64_t Address,
382  const MCDisassembler *Decoder);
383 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
384  uint64_t Address,
385  const MCDisassembler *Decoder);
386 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val,
387  uint64_t Address,
388  const MCDisassembler *Decoder);
389 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val,
390  uint64_t Address,
391  const MCDisassembler *Decoder);
392 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
393  uint64_t Address,
394  const MCDisassembler *Decoder);
395 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
396  uint64_t Address,
397  const MCDisassembler *Decoder);
398 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
399  uint64_t Address,
400  const MCDisassembler *Decoder);
401 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
402  uint64_t Address,
403  const MCDisassembler *Decoder);
404 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
405  uint64_t Address,
406  const MCDisassembler *Decoder);
407 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
408  uint64_t Address,
409  const MCDisassembler *Decoder);
410 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
411  uint64_t Address,
412  const MCDisassembler *Decoder);
413 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
414  uint64_t Address,
415  const MCDisassembler *Decoder);
416 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
417  uint64_t Address,
418  const MCDisassembler *Decoder);
419 template <int shift>
420 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
421  uint64_t Address,
422  const MCDisassembler *Decoder);
423 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
424  uint64_t Address,
425  const MCDisassembler *Decoder);
426 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
427  uint64_t Address,
428  const MCDisassembler *Decoder);
429 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
430  uint64_t Address,
431  const MCDisassembler *Decoder);
432 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address,
433  const MCDisassembler *Decoder);
434 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
435  uint64_t Address,
436  const MCDisassembler *Decoder);
437 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
438  uint64_t Address,
439  const MCDisassembler *Decoder);
440 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
441  uint64_t Address,
442  const MCDisassembler *Decoder);
443 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
444  uint64_t Address,
445  const MCDisassembler *Decoder);
446 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
447  uint64_t Address,
448  const MCDisassembler *Decoder);
449 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
450  uint64_t Address,
451  const MCDisassembler *Decoder);
452 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
453  uint64_t Address,
454  const MCDisassembler *Decoder);
455 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
456  const MCDisassembler *Decoder);
457 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
458  const MCDisassembler *Decoder);
459 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
460  const MCDisassembler *Decoder);
461 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
462  const MCDisassembler *Decoder);
463 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
464  const MCDisassembler *Decoder);
465 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
466  const MCDisassembler *Decoder);
467 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
468  const MCDisassembler *Decoder);
469 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
470  const MCDisassembler *Decoder);
471 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
472  const MCDisassembler *Decoder);
473 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
474  const MCDisassembler *Decoder);
475 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
476  const MCDisassembler *Decoder);
477 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
478  const MCDisassembler *Decoder);
479 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
480  const MCDisassembler *Decoder);
481 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
482  uint64_t Address,
483  const MCDisassembler *Decoder);
484 static DecodeStatus
485 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address,
486  const MCDisassembler *Decoder);
487 
489  uint64_t Address,
490  const MCDisassembler *Decoder);
491 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
492  uint64_t Address,
493  const MCDisassembler *Decoder);
494 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
495  uint64_t Address,
496  const MCDisassembler *Decoder);
497 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
498  uint64_t Address,
499  const MCDisassembler *Decoder);
500 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
501  uint64_t Address,
502  const MCDisassembler *Decoder);
503 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
504  uint64_t Address,
505  const MCDisassembler *Decoder);
506 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
507  uint64_t Address,
508  const MCDisassembler *Decoder);
509 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
510  uint64_t Address,
511  const MCDisassembler *Decoder);
512 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
513  uint64_t Address,
514  const MCDisassembler *Decoder);
515 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
516  uint64_t Address,
517  const MCDisassembler *Decoder);
518 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
519  uint64_t Address,
520  const MCDisassembler *Decoder);
521 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
522  uint64_t Address,
523  const MCDisassembler *Decoder);
524 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
525  const MCDisassembler *Decoder);
526 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
527  uint64_t Address,
528  const MCDisassembler *Decoder);
529 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
530  const MCDisassembler *Decoder);
531 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
532  const MCDisassembler *Decoder);
533 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
534  uint64_t Address,
535  const MCDisassembler *Decoder);
536 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
537  uint64_t Address,
538  const MCDisassembler *Decoder);
539 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val,
540  uint64_t Address,
541  const MCDisassembler *Decoder);
542 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
543  const MCDisassembler *Decoder);
544 template <int shift>
545 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
546  const MCDisassembler *Decoder);
547 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
548  uint64_t Address,
549  const MCDisassembler *Decoder);
550 template <int shift>
551 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
552  uint64_t Address,
553  const MCDisassembler *Decoder);
554 template <int shift, int WriteBack>
555 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
556  uint64_t Address,
557  const MCDisassembler *Decoder);
559  uint64_t Address,
560  const MCDisassembler *Decoder);
562  uint64_t Address,
563  const MCDisassembler *Decoder);
565  uint64_t Address,
566  const MCDisassembler *Decoder);
567 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
568  uint64_t Address,
569  const MCDisassembler *Decoder);
570 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
571  uint64_t Address,
572  const MCDisassembler *Decoder);
573 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
574  uint64_t Address,
575  const MCDisassembler *Decoder);
576 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
577  uint64_t Address,
578  const MCDisassembler *Decoder);
579 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
580  uint64_t Address,
581  const MCDisassembler *Decoder);
582 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
583  const MCDisassembler *Decoder);
584 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
585  uint64_t Address,
586  const MCDisassembler *Decoder);
587 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
588  uint64_t Address,
589  const MCDisassembler *Decoder);
590 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address,
591  const MCDisassembler *Decoder);
592 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
593  uint64_t Address,
594  const MCDisassembler *Decoder);
595 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
596  uint64_t Address,
597  const MCDisassembler *Decoder);
598 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address,
599  const MCDisassembler *Decoder);
600 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
601  uint64_t Address,
602  const MCDisassembler *Decoder);
603 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
604  uint64_t Address,
605  const MCDisassembler *Decoder);
606 
607 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
608  const MCDisassembler *Decoder);
609 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
610  uint64_t Address,
611  const MCDisassembler *Decoder);
612 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
613  uint64_t Address,
614  const MCDisassembler *Decoder);
615 
616 template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
617 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
618  uint64_t Address,
619  const MCDisassembler *Decoder);
620 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
621  uint64_t Address,
622  const MCDisassembler *Decoder);
623 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
624  uint64_t Address,
625  const MCDisassembler *Decoder);
626 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
627  const MCDisassembler *Decoder);
628 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
629  uint64_t Address,
630  const MCDisassembler *Decoder);
631 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
632  const MCDisassembler *Decoder);
633 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
634  uint64_t Address,
635  const MCDisassembler *Decoder);
636 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
637  uint64_t Address,
638  const MCDisassembler *Decoder);
639 static DecodeStatus
640 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
641  const MCDisassembler *Decoder);
642 static DecodeStatus
643 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
644  const MCDisassembler *Decoder);
645 static DecodeStatus
646 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
647  const MCDisassembler *Decoder);
648 static DecodeStatus
649 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
650  const MCDisassembler *Decoder);
651 template <bool Writeback>
652 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
653  uint64_t Address,
654  const MCDisassembler *Decoder);
655 template <int shift>
656 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
657  uint64_t Address,
658  const MCDisassembler *Decoder);
659 template <int shift>
660 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
661  uint64_t Address,
662  const MCDisassembler *Decoder);
663 template <int shift>
664 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
665  uint64_t Address,
666  const MCDisassembler *Decoder);
667 template <unsigned MinLog, unsigned MaxLog>
668 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
669  uint64_t Address,
670  const MCDisassembler *Decoder);
671 template <unsigned start>
672 static DecodeStatus
673 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,
674  const MCDisassembler *Decoder);
675 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
676  uint64_t Address,
677  const MCDisassembler *Decoder);
678 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
679  uint64_t Address,
680  const MCDisassembler *Decoder);
681 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
682  uint64_t Address,
683  const MCDisassembler *Decoder);
684 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
685  uint64_t Address,
686  const MCDisassembler *Decoder);
687 template <bool scalar, OperandDecoder predicate_decoder>
688 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
689  const MCDisassembler *Decoder);
690 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
691  const MCDisassembler *Decoder);
692 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
693  uint64_t Address,
694  const MCDisassembler *Decoder);
695 static DecodeStatus
696 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
697  const MCDisassembler *Decoder);
698 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
699  uint64_t Address,
700  const MCDisassembler *Decoder);
701 
702 #include "ARMGenDisassemblerTables.inc"
703 
705  const MCSubtargetInfo &STI,
706  MCContext &Ctx) {
707  return new ARMDisassembler(STI, Ctx);
708 }
709 
710 // Post-decoding checks
712  uint64_t Address, raw_ostream &CS,
713  uint32_t Insn,
714  DecodeStatus Result) {
715  switch (MI.getOpcode()) {
716  case ARM::HVC: {
717  // HVC is undefined if condition = 0xf otherwise upredictable
718  // if condition != 0xe
719  uint32_t Cond = (Insn >> 28) & 0xF;
720  if (Cond == 0xF)
721  return MCDisassembler::Fail;
722  if (Cond != 0xE)
724  return Result;
725  }
726  case ARM::t2ADDri:
727  case ARM::t2ADDri12:
728  case ARM::t2ADDrr:
729  case ARM::t2ADDrs:
730  case ARM::t2SUBri:
731  case ARM::t2SUBri12:
732  case ARM::t2SUBrr:
733  case ARM::t2SUBrs:
734  if (MI.getOperand(0).getReg() == ARM::SP &&
735  MI.getOperand(1).getReg() != ARM::SP)
737  return Result;
738  default: return Result;
739  }
740 }
741 
742 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
743  ArrayRef<uint8_t> Bytes,
744  uint64_t Address,
745  raw_ostream &CS) const {
746  if (STI.getFeatureBits()[ARM::ModeThumb])
747  return getThumbInstruction(MI, Size, Bytes, Address, CS);
748  return getARMInstruction(MI, Size, Bytes, Address, CS);
749 }
750 
751 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
752  ArrayRef<uint8_t> Bytes,
753  uint64_t Address,
754  raw_ostream &CS) const {
755  CommentStream = &CS;
756 
757  assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
758  "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
759  "mode!");
760 
761  // We want to read exactly 4 bytes of data.
762  if (Bytes.size() < 4) {
763  Size = 0;
764  return MCDisassembler::Fail;
765  }
766 
767  // Encoded as a small-endian 32-bit word in the stream.
768  uint32_t Insn =
769  (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
770 
771  // Calling the auto-generated decoder function.
773  decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
774  if (Result != MCDisassembler::Fail) {
775  Size = 4;
776  return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
777  }
778 
779  struct DecodeTable {
780  const uint8_t *P;
781  bool DecodePred;
782  };
783 
784  const DecodeTable Tables[] = {
785  {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
786  {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
787  {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
788  {DecoderTablev8Crypto32, false},
789  };
790 
791  for (auto Table : Tables) {
792  Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
793  if (Result != MCDisassembler::Fail) {
794  Size = 4;
795  // Add a fake predicate operand, because we share these instruction
796  // definitions with Thumb2 where these instructions are predicable.
797  if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
798  return MCDisassembler::Fail;
799  return Result;
800  }
801  }
802 
803  Result =
804  decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
805  if (Result != MCDisassembler::Fail) {
806  Size = 4;
807  return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
808  }
809 
810  Size = 4;
811  return MCDisassembler::Fail;
812 }
813 
814 namespace llvm {
815 
816 extern const MCInstrDesc ARMInsts[];
817 
818 } // end namespace llvm
819 
820 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
821 /// immediate Value in the MCInst. The immediate Value has had any PC
822 /// adjustment made by the caller. If the instruction is a branch instruction
823 /// then isBranch is true, else false. If the getOpInfo() function was set as
824 /// part of the setupForSymbolicDisassembly() call then that function is called
825 /// to get any symbolic information at the Address for this instruction. If
826 /// that returns non-zero then the symbolic information it returns is used to
827 /// create an MCExpr and that is added as an operand to the MCInst. If
828 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
829 /// Value is done and if a symbol is found an MCExpr is created with that, else
830 /// an MCExpr with Value is created. This function returns true if it adds an
831 /// operand to the MCInst and false otherwise.
832 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
833  bool isBranch, uint64_t InstSize,
834  MCInst &MI,
835  const MCDisassembler *Decoder) {
836  // FIXME: Does it make sense for value to be negative?
837  return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address,
838  isBranch, /*Offset=*/0, /*OpSize=*/0,
839  InstSize);
840 }
841 
842 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
843 /// referenced by a load instruction with the base register that is the Pc.
844 /// These can often be values in a literal pool near the Address of the
845 /// instruction. The Address of the instruction and its immediate Value are
846 /// used as a possible literal pool entry. The SymbolLookUp call back will
847 /// return the name of a symbol referenced by the literal pool's entry if
848 /// the referenced address is that of a symbol. Or it will return a pointer to
849 /// a literal 'C' string if the referenced address of the literal pool's entry
850 /// is an address into a section with 'C' string literals.
852  const MCDisassembler *Decoder) {
853  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
854  Dis->tryAddingPcLoadReferenceComment(Value, Address);
855 }
856 
857 // Thumb1 instructions don't have explicit S bits. Rather, they
858 // implicitly set CPSR. Since it's not represented in the encoding, the
859 // auto-generated decoder won't inject the CPSR operand. We need to fix
860 // that as a post-pass.
861 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
862  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
863  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
864  MCInst::iterator I = MI.begin();
865  for (unsigned i = 0; i < NumOps; ++i, ++I) {
866  if (I == MI.end()) break;
867  if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
868  if (i > 0 && OpInfo[i-1].isPredicate()) continue;
869  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
870  return;
871  }
872  }
873 
874  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
875 }
876 
877 static bool isVectorPredicable(unsigned Opcode) {
878  const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
879  unsigned short NumOps = ARMInsts[Opcode].NumOperands;
880  for (unsigned i = 0; i < NumOps; ++i) {
881  if (ARM::isVpred(OpInfo[i].OperandType))
882  return true;
883  }
884  return false;
885 }
886 
887 // Most Thumb instructions don't have explicit predicates in the
888 // encoding, but rather get their predicates from IT context. We need
889 // to fix up the predicate operands using this context information as a
890 // post-pass.
892 ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
894 
895  const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
896 
897  // A few instructions actually have predicates encoded in them. Don't
898  // try to overwrite it if we're seeing one of those.
899  switch (MI.getOpcode()) {
900  case ARM::tBcc:
901  case ARM::t2Bcc:
902  case ARM::tCBZ:
903  case ARM::tCBNZ:
904  case ARM::tCPS:
905  case ARM::t2CPS3p:
906  case ARM::t2CPS2p:
907  case ARM::t2CPS1p:
908  case ARM::t2CSEL:
909  case ARM::t2CSINC:
910  case ARM::t2CSINV:
911  case ARM::t2CSNEG:
912  case ARM::tMOVSr:
913  case ARM::tSETEND:
914  // Some instructions (mostly conditional branches) are not
915  // allowed in IT blocks.
916  if (ITBlock.instrInITBlock())
917  S = SoftFail;
918  else
919  return Success;
920  break;
921  case ARM::t2HINT:
922  if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
923  S = SoftFail;
924  break;
925  case ARM::tB:
926  case ARM::t2B:
927  case ARM::t2TBB:
928  case ARM::t2TBH:
929  // Some instructions (mostly unconditional branches) can
930  // only appears at the end of, or outside of, an IT.
931  if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
932  S = SoftFail;
933  break;
934  default:
935  break;
936  }
937 
938  // Warn on non-VPT predicable instruction in a VPT block and a VPT
939  // predicable instruction in an IT block
940  if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) ||
941  (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock()))
942  S = SoftFail;
943 
944  // If we're in an IT/VPT block, base the predicate on that. Otherwise,
945  // assume a predicate of AL.
946  unsigned CC = ARMCC::AL;
947  unsigned VCC = ARMVCC::None;
948  if (ITBlock.instrInITBlock()) {
949  CC = ITBlock.getITCC();
950  ITBlock.advanceITState();
951  } else if (VPTBlock.instrInVPTBlock()) {
952  VCC = VPTBlock.getVPTPred();
953  VPTBlock.advanceVPTState();
954  }
955 
956  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
957  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
958 
959  MCInst::iterator CCI = MI.begin();
960  for (unsigned i = 0; i < NumOps; ++i, ++CCI) {
961  if (OpInfo[i].isPredicate() || CCI == MI.end()) break;
962  }
963 
964  if (ARMInsts[MI.getOpcode()].isPredicable()) {
965  CCI = MI.insert(CCI, MCOperand::createImm(CC));
966  ++CCI;
967  if (CC == ARMCC::AL)
968  MI.insert(CCI, MCOperand::createReg(0));
969  else
970  MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
971  } else if (CC != ARMCC::AL) {
972  Check(S, SoftFail);
973  }
974 
975  MCInst::iterator VCCI = MI.begin();
976  unsigned VCCPos;
977  for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
978  if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break;
979  }
980 
981  if (isVectorPredicable(MI.getOpcode())) {
982  VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
983  ++VCCI;
984  if (VCC == ARMVCC::None)
985  VCCI = MI.insert(VCCI, MCOperand::createReg(0));
986  else
987  VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0));
988  ++VCCI;
989  VCCI = MI.insert(VCCI, MCOperand::createReg(0));
990  ++VCCI;
991  if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
992  int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint(
993  VCCPos + 3, MCOI::TIED_TO);
994  assert(TiedOp >= 0 &&
995  "Inactive register in vpred_r is not tied to an output!");
996  // Copy the operand to ensure it's not invalidated when MI grows.
997  MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp)));
998  }
999  } else if (VCC != ARMVCC::None) {
1000  Check(S, SoftFail);
1001  }
1002 
1003  return S;
1004 }
1005 
1006 // Thumb VFP instructions are a special case. Because we share their
1007 // encodings between ARM and Thumb modes, and they are predicable in ARM
1008 // mode, the auto-generated decoder will give them an (incorrect)
1009 // predicate operand. We need to rewrite these operands based on the IT
1010 // context as a post-pass.
1011 void ARMDisassembler::UpdateThumbVFPPredicate(
1012  DecodeStatus &S, MCInst &MI) const {
1013  unsigned CC;
1014  CC = ITBlock.getITCC();
1015  if (CC == 0xF)
1016  CC = ARMCC::AL;
1017  if (ITBlock.instrInITBlock())
1018  ITBlock.advanceITState();
1019  else if (VPTBlock.instrInVPTBlock()) {
1020  CC = VPTBlock.getVPTPred();
1021  VPTBlock.advanceVPTState();
1022  }
1023 
1024  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
1025  MCInst::iterator I = MI.begin();
1026  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
1027  for (unsigned i = 0; i < NumOps; ++i, ++I) {
1028  if (OpInfo[i].isPredicate() ) {
1029  if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
1030  Check(S, SoftFail);
1031  I->setImm(CC);
1032  ++I;
1033  if (CC == ARMCC::AL)
1034  I->setReg(0);
1035  else
1036  I->setReg(ARM::CPSR);
1037  return;
1038  }
1039  }
1040 }
1041 
1042 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
1043  ArrayRef<uint8_t> Bytes,
1044  uint64_t Address,
1045  raw_ostream &CS) const {
1046  CommentStream = &CS;
1047 
1048  assert(STI.getFeatureBits()[ARM::ModeThumb] &&
1049  "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
1050 
1051  // We want to read exactly 2 bytes of data.
1052  if (Bytes.size() < 2) {
1053  Size = 0;
1054  return MCDisassembler::Fail;
1055  }
1056 
1057  uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
1059  decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
1060  if (Result != MCDisassembler::Fail) {
1061  Size = 2;
1062  Check(Result, AddThumbPredicate(MI));
1063  return Result;
1064  }
1065 
1066  Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
1067  STI);
1068  if (Result) {
1069  Size = 2;
1070  bool InITBlock = ITBlock.instrInITBlock();
1071  Check(Result, AddThumbPredicate(MI));
1072  AddThumb1SBit(MI, InITBlock);
1073  return Result;
1074  }
1075 
1076  Result =
1077  decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
1078  if (Result != MCDisassembler::Fail) {
1079  Size = 2;
1080 
1081  // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
1082  // the Thumb predicate.
1083  if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
1085 
1086  Check(Result, AddThumbPredicate(MI));
1087 
1088  // If we find an IT instruction, we need to parse its condition
1089  // code and mask operands so that we can apply them correctly
1090  // to the subsequent instructions.
1091  if (MI.getOpcode() == ARM::t2IT) {
1092  unsigned Firstcond = MI.getOperand(0).getImm();
1093  unsigned Mask = MI.getOperand(1).getImm();
1094  ITBlock.setITState(Firstcond, Mask);
1095 
1096  // An IT instruction that would give a 'NV' predicate is unpredictable.
1097  if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
1098  CS << "unpredictable IT predicate sequence";
1099  }
1100 
1101  return Result;
1102  }
1103 
1104  // We want to read exactly 4 bytes of data.
1105  if (Bytes.size() < 4) {
1106  Size = 0;
1107  return MCDisassembler::Fail;
1108  }
1109 
1110  uint32_t Insn32 =
1111  (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
1112 
1113  Result =
1114  decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
1115  if (Result != MCDisassembler::Fail) {
1116  Size = 4;
1117 
1118  // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
1119  // the VPT predicate.
1120  if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
1122 
1123  Check(Result, AddThumbPredicate(MI));
1124 
1125  if (isVPTOpcode(MI.getOpcode())) {
1126  unsigned Mask = MI.getOperand(0).getImm();
1127  VPTBlock.setVPTState(Mask);
1128  }
1129 
1130  return Result;
1131  }
1132 
1133  Result =
1134  decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
1135  if (Result != MCDisassembler::Fail) {
1136  Size = 4;
1137  bool InITBlock = ITBlock.instrInITBlock();
1138  Check(Result, AddThumbPredicate(MI));
1139  AddThumb1SBit(MI, InITBlock);
1140  return Result;
1141  }
1142 
1143  Result =
1144  decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
1145  if (Result != MCDisassembler::Fail) {
1146  Size = 4;
1147  Check(Result, AddThumbPredicate(MI));
1148  return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result);
1149  }
1150 
1151  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1152  Result =
1153  decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
1154  if (Result != MCDisassembler::Fail) {
1155  Size = 4;
1156  UpdateThumbVFPPredicate(Result, MI);
1157  return Result;
1158  }
1159  }
1160 
1161  Result =
1162  decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
1163  if (Result != MCDisassembler::Fail) {
1164  Size = 4;
1165  return Result;
1166  }
1167 
1168  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1169  Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
1170  STI);
1171  if (Result != MCDisassembler::Fail) {
1172  Size = 4;
1173  Check(Result, AddThumbPredicate(MI));
1174  return Result;
1175  }
1176  }
1177 
1178  if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
1179  uint32_t NEONLdStInsn = Insn32;
1180  NEONLdStInsn &= 0xF0FFFFFF;
1181  NEONLdStInsn |= 0x04000000;
1182  Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
1183  Address, this, STI);
1184  if (Result != MCDisassembler::Fail) {
1185  Size = 4;
1186  Check(Result, AddThumbPredicate(MI));
1187  return Result;
1188  }
1189  }
1190 
1191  if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
1192  uint32_t NEONDataInsn = Insn32;
1193  NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
1194  NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1195  NEONDataInsn |= 0x12000000; // Set bits 28 and 25
1196  Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
1197  Address, this, STI);
1198  if (Result != MCDisassembler::Fail) {
1199  Size = 4;
1200  Check(Result, AddThumbPredicate(MI));
1201  return Result;
1202  }
1203 
1204  uint32_t NEONCryptoInsn = Insn32;
1205  NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
1206  NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1207  NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
1208  Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
1209  Address, this, STI);
1210  if (Result != MCDisassembler::Fail) {
1211  Size = 4;
1212  return Result;
1213  }
1214 
1215  uint32_t NEONv8Insn = Insn32;
1216  NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
1217  Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
1218  this, STI);
1219  if (Result != MCDisassembler::Fail) {
1220  Size = 4;
1221  return Result;
1222  }
1223  }
1224 
1225  uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
1226  const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)
1227  ? DecoderTableThumb2CDE32
1228  : DecoderTableThumb2CoProc32;
1229  Result =
1230  decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI);
1231  if (Result != MCDisassembler::Fail) {
1232  Size = 4;
1233  Check(Result, AddThumbPredicate(MI));
1234  return Result;
1235  }
1236 
1237  Size = 0;
1238  return MCDisassembler::Fail;
1239 }
1240 
1250 }
1251 
1252 static const uint16_t GPRDecoderTable[] = {
1253  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1254  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1255  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1256  ARM::R12, ARM::SP, ARM::LR, ARM::PC
1257 };
1258 
1259 static const uint16_t CLRMGPRDecoderTable[] = {
1260  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1261  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1262  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1263  ARM::R12, 0, ARM::LR, ARM::APSR
1264 };
1265 
1266 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1267  uint64_t Address,
1268  const MCDisassembler *Decoder) {
1269  if (RegNo > 15)
1270  return MCDisassembler::Fail;
1271 
1272  unsigned Register = GPRDecoderTable[RegNo];
1274  return MCDisassembler::Success;
1275 }
1276 
1277 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1278  uint64_t Address,
1279  const MCDisassembler *Decoder) {
1280  if (RegNo > 15)
1281  return MCDisassembler::Fail;
1282 
1283  unsigned Register = CLRMGPRDecoderTable[RegNo];
1284  if (Register == 0)
1285  return MCDisassembler::Fail;
1286 
1288  return MCDisassembler::Success;
1289 }
1290 
1291 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
1292  uint64_t Address,
1293  const MCDisassembler *Decoder) {
1295 
1296  if (RegNo == 15)
1298 
1299  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1300 
1301  return S;
1302 }
1303 
1304 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
1305  uint64_t Address,
1306  const MCDisassembler *Decoder) {
1308 
1309  if (RegNo == 13)
1311 
1312  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1313 
1314  return S;
1315 }
1316 
1317 static DecodeStatus
1318 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1319  const MCDisassembler *Decoder) {
1321 
1322  if (RegNo == 15)
1323  {
1324  Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
1325  return MCDisassembler::Success;
1326  }
1327 
1328  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1329  return S;
1330 }
1331 
1332 static DecodeStatus
1333 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1334  const MCDisassembler *Decoder) {
1336 
1337  if (RegNo == 15)
1338  {
1339  Inst.addOperand(MCOperand::createReg(ARM::ZR));
1340  return MCDisassembler::Success;
1341  }
1342 
1343  if (RegNo == 13)
1345 
1346  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1347  return S;
1348 }
1349 
1350 static DecodeStatus
1351 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1352  const MCDisassembler *Decoder) {
1354  if (RegNo == 13)
1355  return MCDisassembler::Fail;
1356  Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
1357  return S;
1358 }
1359 
1360 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1361  uint64_t Address,
1362  const MCDisassembler *Decoder) {
1363  if (RegNo > 7)
1364  return MCDisassembler::Fail;
1365  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
1366 }
1367 
1368 static const uint16_t GPRPairDecoderTable[] = {
1369  ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1370  ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1371 };
1372 
1373 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
1374  uint64_t Address,
1375  const MCDisassembler *Decoder) {
1377 
1378  // According to the Arm ARM RegNo = 14 is undefined, but we return fail
1379  // rather than SoftFail as there is no GPRPair table entry for index 7.
1380  if (RegNo > 13)
1381  return MCDisassembler::Fail;
1382 
1383  if (RegNo & 1)
1385 
1386  unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1387  Inst.addOperand(MCOperand::createReg(RegisterPair));
1388  return S;
1389 }
1390 
1391 static DecodeStatus
1392 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1393  const MCDisassembler *Decoder) {
1394  if (RegNo > 13)
1395  return MCDisassembler::Fail;
1396 
1397  unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1398  Inst.addOperand(MCOperand::createReg(RegisterPair));
1399 
1400  if ((RegNo & 1) || RegNo > 10)
1401  return MCDisassembler::SoftFail;
1402  return MCDisassembler::Success;
1403 }
1404 
1405 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
1406  uint64_t Address,
1407  const MCDisassembler *Decoder) {
1408  if (RegNo != 13)
1409  return MCDisassembler::Fail;
1410 
1411  unsigned Register = GPRDecoderTable[RegNo];
1413  return MCDisassembler::Success;
1414 }
1415 
1416 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1417  uint64_t Address,
1418  const MCDisassembler *Decoder) {
1419  unsigned Register = 0;
1420  switch (RegNo) {
1421  case 0:
1422  Register = ARM::R0;
1423  break;
1424  case 1:
1425  Register = ARM::R1;
1426  break;
1427  case 2:
1428  Register = ARM::R2;
1429  break;
1430  case 3:
1431  Register = ARM::R3;
1432  break;
1433  case 9:
1434  Register = ARM::R9;
1435  break;
1436  case 12:
1437  Register = ARM::R12;
1438  break;
1439  default:
1440  return MCDisassembler::Fail;
1441  }
1442 
1444  return MCDisassembler::Success;
1445 }
1446 
1447 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1448  uint64_t Address,
1449  const MCDisassembler *Decoder) {
1451 
1452  const FeatureBitset &featureBits =
1453  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1454 
1455  if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1457 
1458  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1459  return S;
1460 }
1461 
1462 static const uint16_t SPRDecoderTable[] = {
1463  ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1464  ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1465  ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1466  ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1467  ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1468  ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1469  ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1470  ARM::S28, ARM::S29, ARM::S30, ARM::S31
1471 };
1472 
1473 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1474  uint64_t Address,
1475  const MCDisassembler *Decoder) {
1476  if (RegNo > 31)
1477  return MCDisassembler::Fail;
1478 
1479  unsigned Register = SPRDecoderTable[RegNo];
1481  return MCDisassembler::Success;
1482 }
1483 
1484 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1485  uint64_t Address,
1486  const MCDisassembler *Decoder) {
1487  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1488 }
1489 
1490 static const uint16_t DPRDecoderTable[] = {
1491  ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1492  ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1493  ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1494  ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1495  ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1496  ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1497  ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1498  ARM::D28, ARM::D29, ARM::D30, ARM::D31
1499 };
1500 
1501 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1502  uint64_t Address,
1503  const MCDisassembler *Decoder) {
1504  const FeatureBitset &featureBits =
1505  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1506 
1507  bool hasD32 = featureBits[ARM::FeatureD32];
1508 
1509  if (RegNo > 31 || (!hasD32 && RegNo > 15))
1510  return MCDisassembler::Fail;
1511 
1512  unsigned Register = DPRDecoderTable[RegNo];
1514  return MCDisassembler::Success;
1515 }
1516 
1517 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1518  uint64_t Address,
1519  const MCDisassembler *Decoder) {
1520  if (RegNo > 7)
1521  return MCDisassembler::Fail;
1522  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1523 }
1524 
1525 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1526  uint64_t Address,
1527  const MCDisassembler *Decoder) {
1528  if (RegNo > 15)
1529  return MCDisassembler::Fail;
1530  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1531 }
1532 
1533 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1534  uint64_t Address,
1535  const MCDisassembler *Decoder) {
1536  if (RegNo > 15)
1537  return MCDisassembler::Fail;
1538  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1539 }
1540 
1541 static const uint16_t QPRDecoderTable[] = {
1542  ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1543  ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1544  ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1545  ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1546 };
1547 
1548 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1549  uint64_t Address,
1550  const MCDisassembler *Decoder) {
1551  if (RegNo > 31 || (RegNo & 1) != 0)
1552  return MCDisassembler::Fail;
1553  RegNo >>= 1;
1554 
1555  unsigned Register = QPRDecoderTable[RegNo];
1557  return MCDisassembler::Success;
1558 }
1559 
1560 static const uint16_t DPairDecoderTable[] = {
1561  ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1562  ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1563  ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1564  ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1565  ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1566  ARM::Q15
1567 };
1568 
1569 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1570  uint64_t Address,
1571  const MCDisassembler *Decoder) {
1572  if (RegNo > 30)
1573  return MCDisassembler::Fail;
1574 
1575  unsigned Register = DPairDecoderTable[RegNo];
1577  return MCDisassembler::Success;
1578 }
1579 
1581  ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1582  ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1583  ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1584  ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1585  ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1586  ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1587  ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1588  ARM::D28_D30, ARM::D29_D31
1589 };
1590 
1591 static DecodeStatus
1592 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1593  const MCDisassembler *Decoder) {
1594  if (RegNo > 29)
1595  return MCDisassembler::Fail;
1596 
1597  unsigned Register = DPairSpacedDecoderTable[RegNo];
1599  return MCDisassembler::Success;
1600 }
1601 
1602 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1603  uint64_t Address,
1604  const MCDisassembler *Decoder) {
1606  if (Val == 0xF) return MCDisassembler::Fail;
1607  // AL predicate is not allowed on Thumb1 branches.
1608  if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1609  return MCDisassembler::Fail;
1610  if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable())
1612  Inst.addOperand(MCOperand::createImm(Val));
1613  if (Val == ARMCC::AL) {
1615  } else
1616  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1617  return S;
1618 }
1619 
1620 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1621  uint64_t Address,
1622  const MCDisassembler *Decoder) {
1623  if (Val)
1624  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1625  else
1627  return MCDisassembler::Success;
1628 }
1629 
1630 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1631  uint64_t Address,
1632  const MCDisassembler *Decoder) {
1634 
1635  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1636  unsigned type = fieldFromInstruction(Val, 5, 2);
1637  unsigned imm = fieldFromInstruction(Val, 7, 5);
1638 
1639  // Register-immediate
1640  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1641  return MCDisassembler::Fail;
1642 
1644  switch (type) {
1645  case 0:
1646  Shift = ARM_AM::lsl;
1647  break;
1648  case 1:
1649  Shift = ARM_AM::lsr;
1650  break;
1651  case 2:
1652  Shift = ARM_AM::asr;
1653  break;
1654  case 3:
1655  Shift = ARM_AM::ror;
1656  break;
1657  }
1658 
1659  if (Shift == ARM_AM::ror && imm == 0)
1660  Shift = ARM_AM::rrx;
1661 
1662  unsigned Op = Shift | (imm << 3);
1664 
1665  return S;
1666 }
1667 
1668 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1669  uint64_t Address,
1670  const MCDisassembler *Decoder) {
1672 
1673  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1674  unsigned type = fieldFromInstruction(Val, 5, 2);
1675  unsigned Rs = fieldFromInstruction(Val, 8, 4);
1676 
1677  // Register-register
1678  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1679  return MCDisassembler::Fail;
1680  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1681  return MCDisassembler::Fail;
1682 
1684  switch (type) {
1685  case 0:
1686  Shift = ARM_AM::lsl;
1687  break;
1688  case 1:
1689  Shift = ARM_AM::lsr;
1690  break;
1691  case 2:
1692  Shift = ARM_AM::asr;
1693  break;
1694  case 3:
1695  Shift = ARM_AM::ror;
1696  break;
1697  }
1698 
1700 
1701  return S;
1702 }
1703 
1704 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1705  uint64_t Address,
1706  const MCDisassembler *Decoder) {
1708 
1709  bool NeedDisjointWriteback = false;
1710  unsigned WritebackReg = 0;
1711  bool CLRM = false;
1712  switch (Inst.getOpcode()) {
1713  default:
1714  break;
1715  case ARM::LDMIA_UPD:
1716  case ARM::LDMDB_UPD:
1717  case ARM::LDMIB_UPD:
1718  case ARM::LDMDA_UPD:
1719  case ARM::t2LDMIA_UPD:
1720  case ARM::t2LDMDB_UPD:
1721  case ARM::t2STMIA_UPD:
1722  case ARM::t2STMDB_UPD:
1723  NeedDisjointWriteback = true;
1724  WritebackReg = Inst.getOperand(0).getReg();
1725  break;
1726  case ARM::t2CLRM:
1727  CLRM = true;
1728  break;
1729  }
1730 
1731  // Empty register lists are not allowed.
1732  if (Val == 0) return MCDisassembler::Fail;
1733  for (unsigned i = 0; i < 16; ++i) {
1734  if (Val & (1 << i)) {
1735  if (CLRM) {
1736  if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
1737  return MCDisassembler::Fail;
1738  }
1739  } else {
1740  if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1741  return MCDisassembler::Fail;
1742  // Writeback not allowed if Rn is in the target list.
1743  if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1745  }
1746  }
1747  }
1748 
1749  return S;
1750 }
1751 
1752 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1753  uint64_t Address,
1754  const MCDisassembler *Decoder) {
1756 
1757  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1758  unsigned regs = fieldFromInstruction(Val, 0, 8);
1759 
1760  // In case of unpredictable encoding, tweak the operands.
1761  if (regs == 0 || (Vd + regs) > 32) {
1762  regs = Vd + regs > 32 ? 32 - Vd : regs;
1763  regs = std::max( 1u, regs);
1765  }
1766 
1767  if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1768  return MCDisassembler::Fail;
1769  for (unsigned i = 0; i < (regs - 1); ++i) {
1770  if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1771  return MCDisassembler::Fail;
1772  }
1773 
1774  return S;
1775 }
1776 
1777 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1778  uint64_t Address,
1779  const MCDisassembler *Decoder) {
1781 
1782  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1783  unsigned regs = fieldFromInstruction(Val, 1, 7);
1784 
1785  // In case of unpredictable encoding, tweak the operands.
1786  if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1787  regs = Vd + regs > 32 ? 32 - Vd : regs;
1788  regs = std::max( 1u, regs);
1789  regs = std::min(16u, regs);
1791  }
1792 
1793  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1794  return MCDisassembler::Fail;
1795  for (unsigned i = 0; i < (regs - 1); ++i) {
1796  if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1797  return MCDisassembler::Fail;
1798  }
1799 
1800  return S;
1801 }
1802 
1803 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1804  uint64_t Address,
1805  const MCDisassembler *Decoder) {
1806  // This operand encodes a mask of contiguous zeros between a specified MSB
1807  // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1808  // the mask of all bits LSB-and-lower, and then xor them to create
1809  // the mask of that's all ones on [msb, lsb]. Finally we not it to
1810  // create the final mask.
1811  unsigned msb = fieldFromInstruction(Val, 5, 5);
1812  unsigned lsb = fieldFromInstruction(Val, 0, 5);
1813 
1815  if (lsb > msb) {
1817  // The check above will cause the warning for the "potentially undefined
1818  // instruction encoding" but we can't build a bad MCOperand value here
1819  // with a lsb > msb or else printing the MCInst will cause a crash.
1820  lsb = msb;
1821  }
1822 
1823  uint32_t msb_mask = 0xFFFFFFFF;
1824  if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1825  uint32_t lsb_mask = (1U << lsb) - 1;
1826 
1827  Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1828  return S;
1829 }
1830 
1832  uint64_t Address,
1833  const MCDisassembler *Decoder) {
1835 
1836  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1837  unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1838  unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1839  unsigned imm = fieldFromInstruction(Insn, 0, 8);
1840  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1841  unsigned U = fieldFromInstruction(Insn, 23, 1);
1842  const FeatureBitset &featureBits =
1843  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1844 
1845  switch (Inst.getOpcode()) {
1846  case ARM::LDC_OFFSET:
1847  case ARM::LDC_PRE:
1848  case ARM::LDC_POST:
1849  case ARM::LDC_OPTION:
1850  case ARM::LDCL_OFFSET:
1851  case ARM::LDCL_PRE:
1852  case ARM::LDCL_POST:
1853  case ARM::LDCL_OPTION:
1854  case ARM::STC_OFFSET:
1855  case ARM::STC_PRE:
1856  case ARM::STC_POST:
1857  case ARM::STC_OPTION:
1858  case ARM::STCL_OFFSET:
1859  case ARM::STCL_PRE:
1860  case ARM::STCL_POST:
1861  case ARM::STCL_OPTION:
1862  case ARM::t2LDC_OFFSET:
1863  case ARM::t2LDC_PRE:
1864  case ARM::t2LDC_POST:
1865  case ARM::t2LDC_OPTION:
1866  case ARM::t2LDCL_OFFSET:
1867  case ARM::t2LDCL_PRE:
1868  case ARM::t2LDCL_POST:
1869  case ARM::t2LDCL_OPTION:
1870  case ARM::t2STC_OFFSET:
1871  case ARM::t2STC_PRE:
1872  case ARM::t2STC_POST:
1873  case ARM::t2STC_OPTION:
1874  case ARM::t2STCL_OFFSET:
1875  case ARM::t2STCL_PRE:
1876  case ARM::t2STCL_POST:
1877  case ARM::t2STCL_OPTION:
1878  case ARM::t2LDC2_OFFSET:
1879  case ARM::t2LDC2L_OFFSET:
1880  case ARM::t2LDC2_PRE:
1881  case ARM::t2LDC2L_PRE:
1882  case ARM::t2STC2_OFFSET:
1883  case ARM::t2STC2L_OFFSET:
1884  case ARM::t2STC2_PRE:
1885  case ARM::t2STC2L_PRE:
1886  case ARM::LDC2_OFFSET:
1887  case ARM::LDC2L_OFFSET:
1888  case ARM::LDC2_PRE:
1889  case ARM::LDC2L_PRE:
1890  case ARM::STC2_OFFSET:
1891  case ARM::STC2L_OFFSET:
1892  case ARM::STC2_PRE:
1893  case ARM::STC2L_PRE:
1894  case ARM::t2LDC2_OPTION:
1895  case ARM::t2STC2_OPTION:
1896  case ARM::t2LDC2_POST:
1897  case ARM::t2LDC2L_POST:
1898  case ARM::t2STC2_POST:
1899  case ARM::t2STC2L_POST:
1900  case ARM::LDC2_POST:
1901  case ARM::LDC2L_POST:
1902  case ARM::STC2_POST:
1903  case ARM::STC2L_POST:
1904  if (coproc == 0xA || coproc == 0xB ||
1905  (featureBits[ARM::HasV8_1MMainlineOps] &&
1906  (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1907  coproc == 0xE || coproc == 0xF)))
1908  return MCDisassembler::Fail;
1909  break;
1910  default:
1911  break;
1912  }
1913 
1914  if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1915  return MCDisassembler::Fail;
1916 
1917  Inst.addOperand(MCOperand::createImm(coproc));
1918  Inst.addOperand(MCOperand::createImm(CRd));
1919  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1920  return MCDisassembler::Fail;
1921 
1922  switch (Inst.getOpcode()) {
1923  case ARM::t2LDC2_OFFSET:
1924  case ARM::t2LDC2L_OFFSET:
1925  case ARM::t2LDC2_PRE:
1926  case ARM::t2LDC2L_PRE:
1927  case ARM::t2STC2_OFFSET:
1928  case ARM::t2STC2L_OFFSET:
1929  case ARM::t2STC2_PRE:
1930  case ARM::t2STC2L_PRE:
1931  case ARM::LDC2_OFFSET:
1932  case ARM::LDC2L_OFFSET:
1933  case ARM::LDC2_PRE:
1934  case ARM::LDC2L_PRE:
1935  case ARM::STC2_OFFSET:
1936  case ARM::STC2L_OFFSET:
1937  case ARM::STC2_PRE:
1938  case ARM::STC2L_PRE:
1939  case ARM::t2LDC_OFFSET:
1940  case ARM::t2LDCL_OFFSET:
1941  case ARM::t2LDC_PRE:
1942  case ARM::t2LDCL_PRE:
1943  case ARM::t2STC_OFFSET:
1944  case ARM::t2STCL_OFFSET:
1945  case ARM::t2STC_PRE:
1946  case ARM::t2STCL_PRE:
1947  case ARM::LDC_OFFSET:
1948  case ARM::LDCL_OFFSET:
1949  case ARM::LDC_PRE:
1950  case ARM::LDCL_PRE:
1951  case ARM::STC_OFFSET:
1952  case ARM::STCL_OFFSET:
1953  case ARM::STC_PRE:
1954  case ARM::STCL_PRE:
1955  imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1956  Inst.addOperand(MCOperand::createImm(imm));
1957  break;
1958  case ARM::t2LDC2_POST:
1959  case ARM::t2LDC2L_POST:
1960  case ARM::t2STC2_POST:
1961  case ARM::t2STC2L_POST:
1962  case ARM::LDC2_POST:
1963  case ARM::LDC2L_POST:
1964  case ARM::STC2_POST:
1965  case ARM::STC2L_POST:
1966  case ARM::t2LDC_POST:
1967  case ARM::t2LDCL_POST:
1968  case ARM::t2STC_POST:
1969  case ARM::t2STCL_POST:
1970  case ARM::LDC_POST:
1971  case ARM::LDCL_POST:
1972  case ARM::STC_POST:
1973  case ARM::STCL_POST:
1974  imm |= U << 8;
1976  default:
1977  // The 'option' variant doesn't encode 'U' in the immediate since
1978  // the immediate is unsigned [0,255].
1979  Inst.addOperand(MCOperand::createImm(imm));
1980  break;
1981  }
1982 
1983  switch (Inst.getOpcode()) {
1984  case ARM::LDC_OFFSET:
1985  case ARM::LDC_PRE:
1986  case ARM::LDC_POST:
1987  case ARM::LDC_OPTION:
1988  case ARM::LDCL_OFFSET:
1989  case ARM::LDCL_PRE:
1990  case ARM::LDCL_POST:
1991  case ARM::LDCL_OPTION:
1992  case ARM::STC_OFFSET:
1993  case ARM::STC_PRE:
1994  case ARM::STC_POST:
1995  case ARM::STC_OPTION:
1996  case ARM::STCL_OFFSET:
1997  case ARM::STCL_PRE:
1998  case ARM::STCL_POST:
1999  case ARM::STCL_OPTION:
2000  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2001  return MCDisassembler::Fail;
2002  break;
2003  default:
2004  break;
2005  }
2006 
2007  return S;
2008 }
2009 
2010 static DecodeStatus
2012  const MCDisassembler *Decoder) {
2014 
2015  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2016  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
2017  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2018  unsigned imm = fieldFromInstruction(Insn, 0, 12);
2019  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2020  unsigned reg = fieldFromInstruction(Insn, 25, 1);
2021  unsigned P = fieldFromInstruction(Insn, 24, 1);
2022  unsigned W = fieldFromInstruction(Insn, 21, 1);
2023 
2024  // On stores, the writeback operand precedes Rt.
2025  switch (Inst.getOpcode()) {
2026  case ARM::STR_POST_IMM:
2027  case ARM::STR_POST_REG:
2028  case ARM::STRB_POST_IMM:
2029  case ARM::STRB_POST_REG:
2030  case ARM::STRT_POST_REG:
2031  case ARM::STRT_POST_IMM:
2032  case ARM::STRBT_POST_REG:
2033  case ARM::STRBT_POST_IMM:
2034  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2035  return MCDisassembler::Fail;
2036  break;
2037  default:
2038  break;
2039  }
2040 
2041  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2042  return MCDisassembler::Fail;
2043 
2044  // On loads, the writeback operand comes after Rt.
2045  switch (Inst.getOpcode()) {
2046  case ARM::LDR_POST_IMM:
2047  case ARM::LDR_POST_REG:
2048  case ARM::LDRB_POST_IMM:
2049  case ARM::LDRB_POST_REG:
2050  case ARM::LDRBT_POST_REG:
2051  case ARM::LDRBT_POST_IMM:
2052  case ARM::LDRT_POST_REG:
2053  case ARM::LDRT_POST_IMM:
2054  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2055  return MCDisassembler::Fail;
2056  break;
2057  default:
2058  break;
2059  }
2060 
2061  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2062  return MCDisassembler::Fail;
2063 
2065  if (!fieldFromInstruction(Insn, 23, 1))
2066  Op = ARM_AM::sub;
2067 
2068  bool writeback = (P == 0) || (W == 1);
2069  unsigned idx_mode = 0;
2070  if (P && writeback)
2071  idx_mode = ARMII::IndexModePre;
2072  else if (!P && writeback)
2073  idx_mode = ARMII::IndexModePost;
2074 
2075  if (writeback && (Rn == 15 || Rn == Rt))
2076  S = MCDisassembler::SoftFail; // UNPREDICTABLE
2077 
2078  if (reg) {
2079  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2080  return MCDisassembler::Fail;
2082  switch( fieldFromInstruction(Insn, 5, 2)) {
2083  case 0:
2084  Opc = ARM_AM::lsl;
2085  break;
2086  case 1:
2087  Opc = ARM_AM::lsr;
2088  break;
2089  case 2:
2090  Opc = ARM_AM::asr;
2091  break;
2092  case 3:
2093  Opc = ARM_AM::ror;
2094  break;
2095  default:
2096  return MCDisassembler::Fail;
2097  }
2098  unsigned amt = fieldFromInstruction(Insn, 7, 5);
2099  if (Opc == ARM_AM::ror && amt == 0)
2100  Opc = ARM_AM::rrx;
2101  unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
2102 
2103  Inst.addOperand(MCOperand::createImm(imm));
2104  } else {
2106  unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
2108  }
2109 
2110  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2111  return MCDisassembler::Fail;
2112 
2113  return S;
2114 }
2115 
2116 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
2117  uint64_t Address,
2118  const MCDisassembler *Decoder) {
2120 
2121  unsigned Rn = fieldFromInstruction(Val, 13, 4);
2122  unsigned Rm = fieldFromInstruction(Val, 0, 4);
2123  unsigned type = fieldFromInstruction(Val, 5, 2);
2124  unsigned imm = fieldFromInstruction(Val, 7, 5);
2125  unsigned U = fieldFromInstruction(Val, 12, 1);
2126 
2128  switch (type) {
2129  case 0:
2130  ShOp = ARM_AM::lsl;
2131  break;
2132  case 1:
2133  ShOp = ARM_AM::lsr;
2134  break;
2135  case 2:
2136  ShOp = ARM_AM::asr;
2137  break;
2138  case 3:
2139  ShOp = ARM_AM::ror;
2140  break;
2141  }
2142 
2143  if (ShOp == ARM_AM::ror && imm == 0)
2144  ShOp = ARM_AM::rrx;
2145 
2146  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2147  return MCDisassembler::Fail;
2148  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2149  return MCDisassembler::Fail;
2150  unsigned shift;
2151  if (U)
2152  shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
2153  else
2154  shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
2156 
2157  return S;
2158 }
2159 
2161  uint64_t Address,
2162  const MCDisassembler *Decoder) {
2163  if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB)
2164  return MCDisassembler::Fail;
2165 
2166  // The "csync" operand is not encoded into the "tsb" instruction (as this is
2167  // the only available operand), but LLVM expects the instruction to have one
2168  // operand, so we need to add the csync when decoding.
2170  return MCDisassembler::Success;
2171 }
2172 
2174  uint64_t Address,
2175  const MCDisassembler *Decoder) {
2177 
2178  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
2179  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2180  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2181  unsigned type = fieldFromInstruction(Insn, 22, 1);
2182  unsigned imm = fieldFromInstruction(Insn, 8, 4);
2183  unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
2184  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2185  unsigned W = fieldFromInstruction(Insn, 21, 1);
2186  unsigned P = fieldFromInstruction(Insn, 24, 1);
2187  unsigned Rt2 = Rt + 1;
2188 
2189  bool writeback = (W == 1) | (P == 0);
2190 
2191  // For {LD,ST}RD, Rt must be even, else undefined.
2192  switch (Inst.getOpcode()) {
2193  case ARM::STRD:
2194  case ARM::STRD_PRE:
2195  case ARM::STRD_POST:
2196  case ARM::LDRD:
2197  case ARM::LDRD_PRE:
2198  case ARM::LDRD_POST:
2199  if (Rt & 0x1) S = MCDisassembler::SoftFail;
2200  break;
2201  default:
2202  break;
2203  }
2204  switch (Inst.getOpcode()) {
2205  case ARM::STRD:
2206  case ARM::STRD_PRE:
2207  case ARM::STRD_POST:
2208  if (P == 0 && W == 1)
2210 
2211  if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2213  if (type && Rm == 15)
2215  if (Rt2 == 15)
2217  if (!type && fieldFromInstruction(Insn, 8, 4))
2219  break;
2220  case ARM::STRH:
2221  case ARM::STRH_PRE:
2222  case ARM::STRH_POST:
2223  if (Rt == 15)
2225  if (writeback && (Rn == 15 || Rn == Rt))
2227  if (!type && Rm == 15)
2229  break;
2230  case ARM::LDRD:
2231  case ARM::LDRD_PRE:
2232  case ARM::LDRD_POST:
2233  if (type && Rn == 15) {
2234  if (Rt2 == 15)
2236  break;
2237  }
2238  if (P == 0 && W == 1)
2240  if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2242  if (!type && writeback && Rn == 15)
2244  if (writeback && (Rn == Rt || Rn == Rt2))
2246  break;
2247  case ARM::LDRH:
2248  case ARM::LDRH_PRE:
2249  case ARM::LDRH_POST:
2250  if (type && Rn == 15) {
2251  if (Rt == 15)
2253  break;
2254  }
2255  if (Rt == 15)
2257  if (!type && Rm == 15)
2259  if (!type && writeback && (Rn == 15 || Rn == Rt))
2261  break;
2262  case ARM::LDRSH:
2263  case ARM::LDRSH_PRE:
2264  case ARM::LDRSH_POST:
2265  case ARM::LDRSB:
2266  case ARM::LDRSB_PRE:
2267  case ARM::LDRSB_POST:
2268  if (type && Rn == 15) {
2269  if (Rt == 15)
2271  break;
2272  }
2273  if (type && (Rt == 15 || (writeback && Rn == Rt)))
2275  if (!type && (Rt == 15 || Rm == 15))
2277  if (!type && writeback && (Rn == 15 || Rn == Rt))
2279  break;
2280  default:
2281  break;
2282  }
2283 
2284  if (writeback) { // Writeback
2285  if (P)
2286  U |= ARMII::IndexModePre << 9;
2287  else
2288  U |= ARMII::IndexModePost << 9;
2289 
2290  // On stores, the writeback operand precedes Rt.
2291  switch (Inst.getOpcode()) {
2292  case ARM::STRD:
2293  case ARM::STRD_PRE:
2294  case ARM::STRD_POST:
2295  case ARM::STRH:
2296  case ARM::STRH_PRE:
2297  case ARM::STRH_POST:
2298  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2299  return MCDisassembler::Fail;
2300  break;
2301  default:
2302  break;
2303  }
2304  }
2305 
2306  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2307  return MCDisassembler::Fail;
2308  switch (Inst.getOpcode()) {
2309  case ARM::STRD:
2310  case ARM::STRD_PRE:
2311  case ARM::STRD_POST:
2312  case ARM::LDRD:
2313  case ARM::LDRD_PRE:
2314  case ARM::LDRD_POST:
2315  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2316  return MCDisassembler::Fail;
2317  break;
2318  default:
2319  break;
2320  }
2321 
2322  if (writeback) {
2323  // On loads, the writeback operand comes after Rt.
2324  switch (Inst.getOpcode()) {
2325  case ARM::LDRD:
2326  case ARM::LDRD_PRE:
2327  case ARM::LDRD_POST:
2328  case ARM::LDRH:
2329  case ARM::LDRH_PRE:
2330  case ARM::LDRH_POST:
2331  case ARM::LDRSH:
2332  case ARM::LDRSH_PRE:
2333  case ARM::LDRSH_POST:
2334  case ARM::LDRSB:
2335  case ARM::LDRSB_PRE:
2336  case ARM::LDRSB_POST:
2337  case ARM::LDRHTr:
2338  case ARM::LDRSBTr:
2339  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2340  return MCDisassembler::Fail;
2341  break;
2342  default:
2343  break;
2344  }
2345  }
2346 
2347  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2348  return MCDisassembler::Fail;
2349 
2350  if (type) {
2352  Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2353  } else {
2354  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2355  return MCDisassembler::Fail;
2357  }
2358 
2359  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2360  return MCDisassembler::Fail;
2361 
2362  return S;
2363 }
2364 
2366  uint64_t Address,
2367  const MCDisassembler *Decoder) {
2369 
2370  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2371  unsigned mode = fieldFromInstruction(Insn, 23, 2);
2372 
2373  switch (mode) {
2374  case 0:
2375  mode = ARM_AM::da;
2376  break;
2377  case 1:
2378  mode = ARM_AM::ia;
2379  break;
2380  case 2:
2381  mode = ARM_AM::db;
2382  break;
2383  case 3:
2384  mode = ARM_AM::ib;
2385  break;
2386  }
2387 
2389  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2390  return MCDisassembler::Fail;
2391 
2392  return S;
2393 }
2394 
2396  uint64_t Address,
2397  const MCDisassembler *Decoder) {
2399 
2400  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2401  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2402  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2403  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2404 
2405  if (pred == 0xF)
2406  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2407 
2408  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2409  return MCDisassembler::Fail;
2410  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2411  return MCDisassembler::Fail;
2412  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2413  return MCDisassembler::Fail;
2414  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2415  return MCDisassembler::Fail;
2416  return S;
2417 }
2418 
2419 static DecodeStatus
2421  uint64_t Address,
2422  const MCDisassembler *Decoder) {
2424 
2425  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2426  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2427  unsigned reglist = fieldFromInstruction(Insn, 0, 16);
2428 
2429  if (pred == 0xF) {
2430  // Ambiguous with RFE and SRS
2431  switch (Inst.getOpcode()) {
2432  case ARM::LDMDA:
2433  Inst.setOpcode(ARM::RFEDA);
2434  break;
2435  case ARM::LDMDA_UPD:
2436  Inst.setOpcode(ARM::RFEDA_UPD);
2437  break;
2438  case ARM::LDMDB:
2439  Inst.setOpcode(ARM::RFEDB);
2440  break;
2441  case ARM::LDMDB_UPD:
2442  Inst.setOpcode(ARM::RFEDB_UPD);
2443  break;
2444  case ARM::LDMIA:
2445  Inst.setOpcode(ARM::RFEIA);
2446  break;
2447  case ARM::LDMIA_UPD:
2448  Inst.setOpcode(ARM::RFEIA_UPD);
2449  break;
2450  case ARM::LDMIB:
2451  Inst.setOpcode(ARM::RFEIB);
2452  break;
2453  case ARM::LDMIB_UPD:
2454  Inst.setOpcode(ARM::RFEIB_UPD);
2455  break;
2456  case ARM::STMDA:
2457  Inst.setOpcode(ARM::SRSDA);
2458  break;
2459  case ARM::STMDA_UPD:
2460  Inst.setOpcode(ARM::SRSDA_UPD);
2461  break;
2462  case ARM::STMDB:
2463  Inst.setOpcode(ARM::SRSDB);
2464  break;
2465  case ARM::STMDB_UPD:
2466  Inst.setOpcode(ARM::SRSDB_UPD);
2467  break;
2468  case ARM::STMIA:
2469  Inst.setOpcode(ARM::SRSIA);
2470  break;
2471  case ARM::STMIA_UPD:
2472  Inst.setOpcode(ARM::SRSIA_UPD);
2473  break;
2474  case ARM::STMIB:
2475  Inst.setOpcode(ARM::SRSIB);
2476  break;
2477  case ARM::STMIB_UPD:
2478  Inst.setOpcode(ARM::SRSIB_UPD);
2479  break;
2480  default:
2481  return MCDisassembler::Fail;
2482  }
2483 
2484  // For stores (which become SRS's, the only operand is the mode.
2485  if (fieldFromInstruction(Insn, 20, 1) == 0) {
2486  // Check SRS encoding constraints
2487  if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
2488  fieldFromInstruction(Insn, 20, 1) == 0))
2489  return MCDisassembler::Fail;
2490 
2491  Inst.addOperand(
2492  MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
2493  return S;
2494  }
2495 
2496  return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
2497  }
2498 
2499  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2500  return MCDisassembler::Fail;
2501  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2502  return MCDisassembler::Fail; // Tied
2503  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2504  return MCDisassembler::Fail;
2505  if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
2506  return MCDisassembler::Fail;
2507 
2508  return S;
2509 }
2510 
2511 // Check for UNPREDICTABLE predicated ESB instruction
2513  uint64_t Address,
2514  const MCDisassembler *Decoder) {
2515  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2516  unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
2517  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2518  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2519 
2521 
2522  Inst.addOperand(MCOperand::createImm(imm8));
2523 
2524  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2525  return MCDisassembler::Fail;
2526 
2527  // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
2528  // so all predicates should be allowed.
2529  if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2531 
2532  return S;
2533 }
2534 
2536  uint64_t Address,
2537  const MCDisassembler *Decoder) {
2538  unsigned imod = fieldFromInstruction(Insn, 18, 2);
2539  unsigned M = fieldFromInstruction(Insn, 17, 1);
2540  unsigned iflags = fieldFromInstruction(Insn, 6, 3);
2541  unsigned mode = fieldFromInstruction(Insn, 0, 5);
2542 
2544 
2545  // This decoder is called from multiple location that do not check
2546  // the full encoding is valid before they do.
2547  if (fieldFromInstruction(Insn, 5, 1) != 0 ||
2548  fieldFromInstruction(Insn, 16, 1) != 0 ||
2549  fieldFromInstruction(Insn, 20, 8) != 0x10)
2550  return MCDisassembler::Fail;
2551 
2552  // imod == '01' --> UNPREDICTABLE
2553  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2554  // return failure here. The '01' imod value is unprintable, so there's
2555  // nothing useful we could do even if we returned UNPREDICTABLE.
2556 
2557  if (imod == 1) return MCDisassembler::Fail;
2558 
2559  if (imod && M) {
2560  Inst.setOpcode(ARM::CPS3p);
2561  Inst.addOperand(MCOperand::createImm(imod));
2562  Inst.addOperand(MCOperand::createImm(iflags));
2564  } else if (imod && !M) {
2565  Inst.setOpcode(ARM::CPS2p);
2566  Inst.addOperand(MCOperand::createImm(imod));
2567  Inst.addOperand(MCOperand::createImm(iflags));
2569  } else if (!imod && M) {
2570  Inst.setOpcode(ARM::CPS1p);
2572  if (iflags) S = MCDisassembler::SoftFail;
2573  } else {
2574  // imod == '00' && M == '0' --> UNPREDICTABLE
2575  Inst.setOpcode(ARM::CPS1p);
2578  }
2579 
2580  return S;
2581 }
2582 
2584  uint64_t Address,
2585  const MCDisassembler *Decoder) {
2586  unsigned imod = fieldFromInstruction(Insn, 9, 2);
2587  unsigned M = fieldFromInstruction(Insn, 8, 1);
2588  unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2589  unsigned mode = fieldFromInstruction(Insn, 0, 5);
2590 
2592 
2593  // imod == '01' --> UNPREDICTABLE
2594  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2595  // return failure here. The '01' imod value is unprintable, so there's
2596  // nothing useful we could do even if we returned UNPREDICTABLE.
2597 
2598  if (imod == 1) return MCDisassembler::Fail;
2599 
2600  if (imod && M) {
2601  Inst.setOpcode(ARM::t2CPS3p);
2602  Inst.addOperand(MCOperand::createImm(imod));
2603  Inst.addOperand(MCOperand::createImm(iflags));
2605  } else if (imod && !M) {
2606  Inst.setOpcode(ARM::t2CPS2p);
2607  Inst.addOperand(MCOperand::createImm(imod));
2608  Inst.addOperand(MCOperand::createImm(iflags));
2610  } else if (!imod && M) {
2611  Inst.setOpcode(ARM::t2CPS1p);
2613  if (iflags) S = MCDisassembler::SoftFail;
2614  } else {
2615  // imod == '00' && M == '0' --> this is a HINT instruction
2616  int imm = fieldFromInstruction(Insn, 0, 8);
2617  // HINT are defined only for immediate in [0..4]
2618  if(imm > 4) return MCDisassembler::Fail;
2619  Inst.setOpcode(ARM::t2HINT);
2620  Inst.addOperand(MCOperand::createImm(imm));
2621  }
2622 
2623  return S;
2624 }
2625 
2626 static DecodeStatus
2628  const MCDisassembler *Decoder) {
2629  unsigned imm = fieldFromInstruction(Insn, 0, 8);
2630 
2631  unsigned Opcode = ARM::t2HINT;
2632 
2633  if (imm == 0x0D) {
2634  Opcode = ARM::t2PACBTI;
2635  } else if (imm == 0x1D) {
2636  Opcode = ARM::t2PAC;
2637  } else if (imm == 0x2D) {
2638  Opcode = ARM::t2AUT;
2639  } else if (imm == 0x0F) {
2640  Opcode = ARM::t2BTI;
2641  }
2642 
2643  Inst.setOpcode(Opcode);
2644  if (Opcode == ARM::t2HINT) {
2645  Inst.addOperand(MCOperand::createImm(imm));
2646  }
2647 
2648  return MCDisassembler::Success;
2649 }
2650 
2652  uint64_t Address,
2653  const MCDisassembler *Decoder) {
2655 
2656  unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2657  unsigned imm = 0;
2658 
2659  imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2660  imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2661  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2662  imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2663 
2664  if (Inst.getOpcode() == ARM::t2MOVTi16)
2665  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2666  return MCDisassembler::Fail;
2667  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2668  return MCDisassembler::Fail;
2669 
2670  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2671  Inst.addOperand(MCOperand::createImm(imm));
2672 
2673  return S;
2674 }
2675 
2677  uint64_t Address,
2678  const MCDisassembler *Decoder) {
2680 
2681  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2682  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2683  unsigned imm = 0;
2684 
2685  imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2686  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2687 
2688  if (Inst.getOpcode() == ARM::MOVTi16)
2689  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2690  return MCDisassembler::Fail;
2691 
2692  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2693  return MCDisassembler::Fail;
2694 
2695  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2696  Inst.addOperand(MCOperand::createImm(imm));
2697 
2698  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2699  return MCDisassembler::Fail;
2700 
2701  return S;
2702 }
2703 
2705  uint64_t Address,
2706  const MCDisassembler *Decoder) {
2708 
2709  unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2710  unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2711  unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2712  unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2713  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2714 
2715  if (pred == 0xF)
2716  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2717 
2718  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2719  return MCDisassembler::Fail;
2720  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2721  return MCDisassembler::Fail;
2722  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2723  return MCDisassembler::Fail;
2724  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2725  return MCDisassembler::Fail;
2726 
2727  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2728  return MCDisassembler::Fail;
2729 
2730  return S;
2731 }
2732 
2734  uint64_t Address,
2735  const MCDisassembler *Decoder) {
2737 
2738  unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2739  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2740  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2741 
2742  if (Pred == 0xF)
2743  return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2744 
2745  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2746  return MCDisassembler::Fail;
2747  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2748  return MCDisassembler::Fail;
2749  if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2750  return MCDisassembler::Fail;
2751 
2752  return S;
2753 }
2754 
2756  uint64_t Address,
2757  const MCDisassembler *Decoder) {
2759 
2760  unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2761 
2762  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2763  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2764 
2765  if (!FeatureBits[ARM::HasV8_1aOps] ||
2766  !FeatureBits[ARM::HasV8Ops])
2767  return MCDisassembler::Fail;
2768 
2769  // Decoder can be called from DecodeTST, which does not check the full
2770  // encoding is valid.
2771  if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2772  fieldFromInstruction(Insn, 4,4) != 0)
2773  return MCDisassembler::Fail;
2774  if (fieldFromInstruction(Insn, 10,10) != 0 ||
2775  fieldFromInstruction(Insn, 0,4) != 0)
2777 
2778  Inst.setOpcode(ARM::SETPAN);
2780 
2781  return S;
2782 }
2783 
2785  uint64_t Address,
2786  const MCDisassembler *Decoder) {
2788 
2789  unsigned add = fieldFromInstruction(Val, 12, 1);
2790  unsigned imm = fieldFromInstruction(Val, 0, 12);
2791  unsigned Rn = fieldFromInstruction(Val, 13, 4);
2792 
2793  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2794  return MCDisassembler::Fail;
2795 
2796  if (!add) imm *= -1;
2797  if (imm == 0 && !add) imm = INT32_MIN;
2798  Inst.addOperand(MCOperand::createImm(imm));
2799  if (Rn == 15)
2800  tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2801 
2802  return S;
2803 }
2804 
2805 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2806  uint64_t Address,
2807  const MCDisassembler *Decoder) {
2809 
2810  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2811  // U == 1 to add imm, 0 to subtract it.
2812  unsigned U = fieldFromInstruction(Val, 8, 1);
2813  unsigned imm = fieldFromInstruction(Val, 0, 8);
2814 
2815  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2816  return MCDisassembler::Fail;
2817 
2818  if (U)
2820  else
2822 
2823  return S;
2824 }
2825 
2827  uint64_t Address,
2828  const MCDisassembler *Decoder) {
2830 
2831  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2832  // U == 1 to add imm, 0 to subtract it.
2833  unsigned U = fieldFromInstruction(Val, 8, 1);
2834  unsigned imm = fieldFromInstruction(Val, 0, 8);
2835 
2836  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2837  return MCDisassembler::Fail;
2838 
2839  if (U)
2841  else
2843 
2844  return S;
2845 }
2846 
2847 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2848  uint64_t Address,
2849  const MCDisassembler *Decoder) {
2850  return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2851 }
2852 
2854  uint64_t Address,
2855  const MCDisassembler *Decoder) {
2857 
2858  // Note the J1 and J2 values are from the encoded instruction. So here
2859  // change them to I1 and I2 values via as documented:
2860  // I1 = NOT(J1 EOR S);
2861  // I2 = NOT(J2 EOR S);
2862  // and build the imm32 with one trailing zero as documented:
2863  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2864  unsigned S = fieldFromInstruction(Insn, 26, 1);
2865  unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2866  unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2867  unsigned I1 = !(J1 ^ S);
2868  unsigned I2 = !(J2 ^ S);
2869  unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2870  unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2871  unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2872  int imm32 = SignExtend32<25>(tmp << 1);
2873  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2874  true, 4, Inst, Decoder))
2875  Inst.addOperand(MCOperand::createImm(imm32));
2876 
2877  return Status;
2878 }
2879 
2881  uint64_t Address,
2882  const MCDisassembler *Decoder) {
2884 
2885  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2886  unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2887 
2888  if (pred == 0xF) {
2889  Inst.setOpcode(ARM::BLXi);
2890  imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2891  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2892  true, 4, Inst, Decoder))
2893  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2894  return S;
2895  }
2896 
2897  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2898  true, 4, Inst, Decoder))
2899  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2900 
2901  // We already have BL_pred for BL w/ predicate, no need to add addition
2902  // predicate opreands for BL
2903  if (Inst.getOpcode() != ARM::BL)
2904  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2905  return MCDisassembler::Fail;
2906 
2907  return S;
2908 }
2909 
2910 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2911  uint64_t Address,
2912  const MCDisassembler *Decoder) {
2914 
2915  unsigned Rm = fieldFromInstruction(Val, 0, 4);
2916  unsigned align = fieldFromInstruction(Val, 4, 2);
2917 
2918  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2919  return MCDisassembler::Fail;
2920  if (!align)
2922  else
2924 
2925  return S;
2926 }
2927 
2929  uint64_t Address,
2930  const MCDisassembler *Decoder) {
2932 
2933  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2934  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2935  unsigned wb = fieldFromInstruction(Insn, 16, 4);
2936  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2937  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2938  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2939 
2940  // First output register
2941  switch (Inst.getOpcode()) {
2942  case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2943  case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2944  case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2945  case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2946  case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2947  case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2948  case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2949  case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2950  case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2951  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2952  return MCDisassembler::Fail;
2953  break;
2954  case ARM::VLD2b16:
2955  case ARM::VLD2b32:
2956  case ARM::VLD2b8:
2957  case ARM::VLD2b16wb_fixed:
2958  case ARM::VLD2b16wb_register:
2959  case ARM::VLD2b32wb_fixed:
2960  case ARM::VLD2b32wb_register:
2961  case ARM::VLD2b8wb_fixed:
2962  case ARM::VLD2b8wb_register:
2963  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2964  return MCDisassembler::Fail;
2965  break;
2966  default:
2967  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2968  return MCDisassembler::Fail;
2969  }
2970 
2971  // Second output register
2972  switch (Inst.getOpcode()) {
2973  case ARM::VLD3d8:
2974  case ARM::VLD3d16:
2975  case ARM::VLD3d32:
2976  case ARM::VLD3d8_UPD:
2977  case ARM::VLD3d16_UPD:
2978  case ARM::VLD3d32_UPD:
2979  case ARM::VLD4d8:
2980  case ARM::VLD4d16:
2981  case ARM::VLD4d32:
2982  case ARM::VLD4d8_UPD:
2983  case ARM::VLD4d16_UPD:
2984  case ARM::VLD4d32_UPD:
2985  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2986  return MCDisassembler::Fail;
2987  break;
2988  case ARM::VLD3q8:
2989  case ARM::VLD3q16:
2990  case ARM::VLD3q32:
2991  case ARM::VLD3q8_UPD:
2992  case ARM::VLD3q16_UPD:
2993  case ARM::VLD3q32_UPD:
2994  case ARM::VLD4q8:
2995  case ARM::VLD4q16:
2996  case ARM::VLD4q32:
2997  case ARM::VLD4q8_UPD:
2998  case ARM::VLD4q16_UPD:
2999  case ARM::VLD4q32_UPD:
3000  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3001  return MCDisassembler::Fail;
3002  break;
3003  default:
3004  break;
3005  }
3006 
3007  // Third output register
3008  switch(Inst.getOpcode()) {
3009  case ARM::VLD3d8:
3010  case ARM::VLD3d16:
3011  case ARM::VLD3d32:
3012  case ARM::VLD3d8_UPD:
3013  case ARM::VLD3d16_UPD:
3014  case ARM::VLD3d32_UPD:
3015  case ARM::VLD4d8:
3016  case ARM::VLD4d16:
3017  case ARM::VLD4d32:
3018  case ARM::VLD4d8_UPD:
3019  case ARM::VLD4d16_UPD:
3020  case ARM::VLD4d32_UPD:
3021  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3022  return MCDisassembler::Fail;
3023  break;
3024  case ARM::VLD3q8:
3025  case ARM::VLD3q16:
3026  case ARM::VLD3q32:
3027  case ARM::VLD3q8_UPD:
3028  case ARM::VLD3q16_UPD:
3029  case ARM::VLD3q32_UPD:
3030  case ARM::VLD4q8:
3031  case ARM::VLD4q16:
3032  case ARM::VLD4q32:
3033  case ARM::VLD4q8_UPD:
3034  case ARM::VLD4q16_UPD:
3035  case ARM::VLD4q32_UPD:
3036  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
3037  return MCDisassembler::Fail;
3038  break;
3039  default:
3040  break;
3041  }
3042 
3043  // Fourth output register
3044  switch (Inst.getOpcode()) {
3045  case ARM::VLD4d8:
3046  case ARM::VLD4d16:
3047  case ARM::VLD4d32:
3048  case ARM::VLD4d8_UPD:
3049  case ARM::VLD4d16_UPD:
3050  case ARM::VLD4d32_UPD:
3051  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
3052  return MCDisassembler::Fail;
3053  break;
3054  case ARM::VLD4q8:
3055  case ARM::VLD4q16:
3056  case ARM::VLD4q32:
3057  case ARM::VLD4q8_UPD:
3058  case ARM::VLD4q16_UPD:
3059  case ARM::VLD4q32_UPD:
3060  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
3061  return MCDisassembler::Fail;
3062  break;
3063  default:
3064  break;
3065  }
3066 
3067  // Writeback operand
3068  switch (Inst.getOpcode()) {
3069  case ARM::VLD1d8wb_fixed:
3070  case ARM::VLD1d16wb_fixed:
3071  case ARM::VLD1d32wb_fixed:
3072  case ARM::VLD1d64wb_fixed:
3073  case ARM::VLD1d8wb_register:
3074  case ARM::VLD1d16wb_register:
3075  case ARM::VLD1d32wb_register:
3076  case ARM::VLD1d64wb_register:
3077  case ARM::VLD1q8wb_fixed:
3078  case ARM::VLD1q16wb_fixed:
3079  case ARM::VLD1q32wb_fixed:
3080  case ARM::VLD1q64wb_fixed:
3081  case ARM::VLD1q8wb_register:
3082  case ARM::VLD1q16wb_register:
3083  case ARM::VLD1q32wb_register:
3084  case ARM::VLD1q64wb_register:
3085  case ARM::VLD1d8Twb_fixed:
3086  case ARM::VLD1d8Twb_register:
3087  case ARM::VLD1d16Twb_fixed:
3088  case ARM::VLD1d16Twb_register:
3089  case ARM::VLD1d32Twb_fixed:
3090  case ARM::VLD1d32Twb_register:
3091  case ARM::VLD1d64Twb_fixed:
3092  case ARM::VLD1d64Twb_register:
3093  case ARM::VLD1d8Qwb_fixed:
3094  case ARM::VLD1d8Qwb_register:
3095  case ARM::VLD1d16Qwb_fixed:
3096  case ARM::VLD1d16Qwb_register:
3097  case ARM::VLD1d32Qwb_fixed:
3098  case ARM::VLD1d32Qwb_register:
3099  case ARM::VLD1d64Qwb_fixed:
3100  case ARM::VLD1d64Qwb_register:
3101  case ARM::VLD2d8wb_fixed:
3102  case ARM::VLD2d16wb_fixed:
3103  case ARM::VLD2d32wb_fixed:
3104  case ARM::VLD2q8wb_fixed:
3105  case ARM::VLD2q16wb_fixed:
3106  case ARM::VLD2q32wb_fixed:
3107  case ARM::VLD2d8wb_register:
3108  case ARM::VLD2d16wb_register:
3109  case ARM::VLD2d32wb_register:
3110  case ARM::VLD2q8wb_register:
3111  case ARM::VLD2q16wb_register:
3112  case ARM::VLD2q32wb_register:
3113  case ARM::VLD2b8wb_fixed:
3114  case ARM::VLD2b16wb_fixed:
3115  case ARM::VLD2b32wb_fixed:
3116  case ARM::VLD2b8wb_register:
3117  case ARM::VLD2b16wb_register:
3118  case ARM::VLD2b32wb_register:
3120  break;
3121  case ARM::VLD3d8_UPD:
3122  case ARM::VLD3d16_UPD:
3123  case ARM::VLD3d32_UPD:
3124  case ARM::VLD3q8_UPD:
3125  case ARM::VLD3q16_UPD:
3126  case ARM::VLD3q32_UPD:
3127  case ARM::VLD4d8_UPD:
3128  case ARM::VLD4d16_UPD:
3129  case ARM::VLD4d32_UPD:
3130  case ARM::VLD4q8_UPD:
3131  case ARM::VLD4q16_UPD:
3132  case ARM::VLD4q32_UPD:
3133  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3134  return MCDisassembler::Fail;
3135  break;
3136  default:
3137  break;
3138  }
3139 
3140  // AddrMode6 Base (register+alignment)
3141  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3142  return MCDisassembler::Fail;
3143 
3144  // AddrMode6 Offset (register)
3145  switch (Inst.getOpcode()) {
3146  default:
3147  // The below have been updated to have explicit am6offset split
3148  // between fixed and register offset. For those instructions not
3149  // yet updated, we need to add an additional reg0 operand for the
3150  // fixed variant.
3151  //
3152  // The fixed offset encodes as Rm == 0xd, so we check for that.
3153  if (Rm == 0xd) {
3155  break;
3156  }
3157  // Fall through to handle the register offset variant.
3159  case ARM::VLD1d8wb_fixed:
3160  case ARM::VLD1d16wb_fixed:
3161  case ARM::VLD1d32wb_fixed:
3162  case ARM::VLD1d64wb_fixed:
3163  case ARM::VLD1d8Twb_fixed:
3164  case ARM::VLD1d16Twb_fixed:
3165  case ARM::VLD1d32Twb_fixed:
3166  case ARM::VLD1d64Twb_fixed:
3167  case ARM::VLD1d8Qwb_fixed:
3168  case ARM::VLD1d16Qwb_fixed:
3169  case ARM::VLD1d32Qwb_fixed:
3170  case ARM::VLD1d64Qwb_fixed:
3171  case ARM::VLD1d8wb_register:
3172  case ARM::VLD1d16wb_register:
3173  case ARM::VLD1d32wb_register:
3174  case ARM::VLD1d64wb_register:
3175  case ARM::VLD1q8wb_fixed:
3176  case ARM::VLD1q16wb_fixed:
3177  case ARM::VLD1q32wb_fixed:
3178  case ARM::VLD1q64wb_fixed:
3179  case ARM::VLD1q8wb_register:
3180  case ARM::VLD1q16wb_register:
3181  case ARM::VLD1q32wb_register:
3182  case ARM::VLD1q64wb_register:
3183  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3184  // variant encodes Rm == 0xf. Anything else is a register offset post-
3185  // increment and we need to add the register operand to the instruction.
3186  if (Rm != 0xD && Rm != 0xF &&
3187  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3188  return MCDisassembler::Fail;
3189  break;
3190  case ARM::VLD2d8wb_fixed:
3191  case ARM::VLD2d16wb_fixed:
3192  case ARM::VLD2d32wb_fixed:
3193  case ARM::VLD2b8wb_fixed:
3194  case ARM::VLD2b16wb_fixed:
3195  case ARM::VLD2b32wb_fixed:
3196  case ARM::VLD2q8wb_fixed:
3197  case ARM::VLD2q16wb_fixed:
3198  case ARM::VLD2q32wb_fixed:
3199  break;
3200  }
3201 
3202  return S;
3203 }
3204 
3206  uint64_t Address,
3207  const MCDisassembler *Decoder) {
3208  unsigned type = fieldFromInstruction(Insn, 8, 4);
3209  unsigned align = fieldFromInstruction(Insn, 4, 2);
3210  if (type == 6 && (align & 2)) return MCDisassembler::Fail;
3211  if (type == 7 && (align & 2)) return MCDisassembler::Fail;
3212  if (type == 10 && align == 3) return MCDisassembler::Fail;
3213 
3214  unsigned load = fieldFromInstruction(Insn, 21, 1);
3215  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3216  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3217 }
3218 
3220  uint64_t Address,
3221  const MCDisassembler *Decoder) {
3222  unsigned size = fieldFromInstruction(Insn, 6, 2);
3223  if (size == 3) return MCDisassembler::Fail;
3224 
3225  unsigned type = fieldFromInstruction(Insn, 8, 4);
3226  unsigned align = fieldFromInstruction(Insn, 4, 2);
3227  if (type == 8 && align == 3) return MCDisassembler::Fail;
3228  if (type == 9 && align == 3) return MCDisassembler::Fail;
3229 
3230  unsigned load = fieldFromInstruction(Insn, 21, 1);
3231  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3232  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3233 }
3234 
3236  uint64_t Address,
3237  const MCDisassembler *Decoder) {
3238  unsigned size = fieldFromInstruction(Insn, 6, 2);
3239  if (size == 3) return MCDisassembler::Fail;
3240 
3241  unsigned align = fieldFromInstruction(Insn, 4, 2);
3242  if (align & 2) return MCDisassembler::Fail;
3243 
3244  unsigned load = fieldFromInstruction(Insn, 21, 1);
3245  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3246  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3247 }
3248 
3250  uint64_t Address,
3251  const MCDisassembler *Decoder) {
3252  unsigned size = fieldFromInstruction(Insn, 6, 2);
3253  if (size == 3) return MCDisassembler::Fail;
3254 
3255  unsigned load = fieldFromInstruction(Insn, 21, 1);
3256  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3257  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3258 }
3259 
3261  uint64_t Address,
3262  const MCDisassembler *Decoder) {
3264 
3265  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3266  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3267  unsigned wb = fieldFromInstruction(Insn, 16, 4);
3268  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3269  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
3270  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3271 
3272  // Writeback Operand
3273  switch (Inst.getOpcode()) {
3274  case ARM::VST1d8wb_fixed:
3275  case ARM::VST1d16wb_fixed:
3276  case ARM::VST1d32wb_fixed:
3277  case ARM::VST1d64wb_fixed:
3278  case ARM::VST1d8wb_register:
3279  case ARM::VST1d16wb_register:
3280  case ARM::VST1d32wb_register:
3281  case ARM::VST1d64wb_register:
3282  case ARM::VST1q8wb_fixed:
3283  case ARM::VST1q16wb_fixed:
3284  case ARM::VST1q32wb_fixed:
3285  case ARM::VST1q64wb_fixed:
3286  case ARM::VST1q8wb_register:
3287  case ARM::VST1q16wb_register:
3288  case ARM::VST1q32wb_register:
3289  case ARM::VST1q64wb_register:
3290  case ARM::VST1d8Twb_fixed:
3291  case ARM::VST1d16Twb_fixed:
3292  case ARM::VST1d32Twb_fixed:
3293  case ARM::VST1d64Twb_fixed:
3294  case ARM::VST1d8Twb_register:
3295  case ARM::VST1d16Twb_register:
3296  case ARM::VST1d32Twb_register:
3297  case ARM::VST1d64Twb_register:
3298  case ARM::VST1d8Qwb_fixed:
3299  case ARM::VST1d16Qwb_fixed:
3300  case ARM::VST1d32Qwb_fixed:
3301  case ARM::VST1d64Qwb_fixed:
3302  case ARM::VST1d8Qwb_register:
3303  case ARM::VST1d16Qwb_register:
3304  case ARM::VST1d32Qwb_register:
3305  case ARM::VST1d64Qwb_register:
3306  case ARM::VST2d8wb_fixed:
3307  case ARM::VST2d16wb_fixed:
3308  case ARM::VST2d32wb_fixed:
3309  case ARM::VST2d8wb_register:
3310  case ARM::VST2d16wb_register:
3311  case ARM::VST2d32wb_register:
3312  case ARM::VST2q8wb_fixed:
3313  case ARM::VST2q16wb_fixed:
3314  case ARM::VST2q32wb_fixed:
3315  case ARM::VST2q8wb_register:
3316  case ARM::VST2q16wb_register:
3317  case ARM::VST2q32wb_register:
3318  case ARM::VST2b8wb_fixed:
3319  case ARM::VST2b16wb_fixed:
3320  case ARM::VST2b32wb_fixed:
3321  case ARM::VST2b8wb_register:
3322  case ARM::VST2b16wb_register:
3323  case ARM::VST2b32wb_register:
3324  if (Rm == 0xF)
3325  return MCDisassembler::Fail;
3327  break;
3328  case ARM::VST3d8_UPD:
3329  case ARM::VST3d16_UPD:
3330  case ARM::VST3d32_UPD:
3331  case ARM::VST3q8_UPD:
3332  case ARM::VST3q16_UPD:
3333  case ARM::VST3q32_UPD:
3334  case ARM::VST4d8_UPD:
3335  case ARM::VST4d16_UPD:
3336  case ARM::VST4d32_UPD:
3337  case ARM::VST4q8_UPD:
3338  case ARM::VST4q16_UPD:
3339  case ARM::VST4q32_UPD:
3340  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3341  return MCDisassembler::Fail;
3342  break;
3343  default:
3344  break;
3345  }
3346 
3347  // AddrMode6 Base (register+alignment)
3348  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3349  return MCDisassembler::Fail;
3350 
3351  // AddrMode6 Offset (register)
3352  switch (Inst.getOpcode()) {
3353  default:
3354  if (Rm == 0xD)
3356  else if (Rm != 0xF) {
3357  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3358  return MCDisassembler::Fail;
3359  }
3360  break;
3361  case ARM::VST1d8wb_fixed:
3362  case ARM::VST1d16wb_fixed:
3363  case ARM::VST1d32wb_fixed:
3364  case ARM::VST1d64wb_fixed:
3365  case ARM::VST1q8wb_fixed:
3366  case ARM::VST1q16wb_fixed:
3367  case ARM::VST1q32wb_fixed:
3368  case ARM::VST1q64wb_fixed:
3369  case ARM::VST1d8Twb_fixed:
3370  case ARM::VST1d16Twb_fixed:
3371  case ARM::VST1d32Twb_fixed:
3372  case ARM::VST1d64Twb_fixed:
3373  case ARM::VST1d8Qwb_fixed:
3374  case ARM::VST1d16Qwb_fixed:
3375  case ARM::VST1d32Qwb_fixed:
3376  case ARM::VST1d64Qwb_fixed:
3377  case ARM::VST2d8wb_fixed:
3378  case ARM::VST2d16wb_fixed:
3379  case ARM::VST2d32wb_fixed:
3380  case ARM::VST2q8wb_fixed:
3381  case ARM::VST2q16wb_fixed:
3382  case ARM::VST2q32wb_fixed:
3383  case ARM::VST2b8wb_fixed:
3384  case ARM::VST2b16wb_fixed:
3385  case ARM::VST2b32wb_fixed:
3386  break;
3387  }
3388 
3389  // First input register
3390  switch (Inst.getOpcode()) {
3391  case ARM::VST1q16:
3392  case ARM::VST1q32:
3393  case ARM::VST1q64:
3394  case ARM::VST1q8:
3395  case ARM::VST1q16wb_fixed:
3396  case ARM::VST1q16wb_register:
3397  case ARM::VST1q32wb_fixed:
3398  case ARM::VST1q32wb_register:
3399  case ARM::VST1q64wb_fixed:
3400  case ARM::VST1q64wb_register:
3401  case ARM::VST1q8wb_fixed:
3402  case ARM::VST1q8wb_register:
3403  case ARM::VST2d16:
3404  case ARM::VST2d32:
3405  case ARM::VST2d8:
3406  case ARM::VST2d16wb_fixed:
3407  case ARM::VST2d16wb_register:
3408  case ARM::VST2d32wb_fixed:
3409  case ARM::VST2d32wb_register:
3410  case ARM::VST2d8wb_fixed:
3411  case ARM::VST2d8wb_register:
3412  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3413  return MCDisassembler::Fail;
3414  break;
3415  case ARM::VST2b16:
3416  case ARM::VST2b32:
3417  case ARM::VST2b8:
3418  case ARM::VST2b16wb_fixed:
3419  case ARM::VST2b16wb_register:
3420  case ARM::VST2b32wb_fixed:
3421  case ARM::VST2b32wb_register:
3422  case ARM::VST2b8wb_fixed:
3423  case ARM::VST2b8wb_register:
3424  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3425  return MCDisassembler::Fail;
3426  break;
3427  default:
3428  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3429  return MCDisassembler::Fail;
3430  }
3431 
3432  // Second input register
3433  switch (Inst.getOpcode()) {
3434  case ARM::VST3d8:
3435  case ARM::VST3d16:
3436  case ARM::VST3d32:
3437  case ARM::VST3d8_UPD:
3438  case ARM::VST3d16_UPD:
3439  case ARM::VST3d32_UPD:
3440  case ARM::VST4d8:
3441  case ARM::VST4d16:
3442  case ARM::VST4d32:
3443  case ARM::VST4d8_UPD:
3444  case ARM::VST4d16_UPD:
3445  case ARM::VST4d32_UPD:
3446  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
3447  return MCDisassembler::Fail;
3448  break;
3449  case ARM::VST3q8:
3450  case ARM::VST3q16:
3451  case ARM::VST3q32:
3452  case ARM::VST3q8_UPD:
3453  case ARM::VST3q16_UPD:
3454  case ARM::VST3q32_UPD:
3455  case ARM::VST4q8:
3456  case ARM::VST4q16:
3457  case ARM::VST4q32:
3458  case ARM::VST4q8_UPD:
3459  case ARM::VST4q16_UPD:
3460  case ARM::VST4q32_UPD:
3461  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3462  return MCDisassembler::Fail;
3463  break;
3464  default:
3465  break;
3466  }
3467 
3468  // Third input register
3469  switch (Inst.getOpcode()) {
3470  case ARM::VST3d8:
3471  case ARM::VST3d16:
3472  case ARM::VST3d32:
3473  case ARM::VST3d8_UPD:
3474  case ARM::VST3d16_UPD:
3475  case ARM::VST3d32_UPD:
3476  case ARM::VST4d8:
3477  case ARM::VST4d16:
3478  case ARM::VST4d32:
3479  case ARM::VST4d8_UPD:
3480  case ARM::VST4d16_UPD:
3481  case ARM::VST4d32_UPD:
3482  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3483  return MCDisassembler::Fail;
3484  break;
3485  case ARM::VST3q8:
3486  case ARM::VST3q16:
3487  case ARM::VST3q32:
3488  case ARM::VST3q8_UPD:
3489  case ARM::VST3q16_UPD:
3490  case ARM::VST3q32_UPD:
3491  case ARM::VST4q8:
3492  case ARM::VST4q16:
3493  case ARM::VST4q32:
3494  case ARM::VST4q8_UPD:
3495  case ARM::VST4q16_UPD:
3496  case ARM::VST4q32_UPD:
3497  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
3498  return MCDisassembler::Fail;
3499  break;
3500  default:
3501  break;
3502  }
3503 
3504  // Fourth input register
3505  switch (Inst.getOpcode()) {
3506  case ARM::VST4d8:
3507  case ARM::VST4d16:
3508  case ARM::VST4d32:
3509  case ARM::VST4d8_UPD:
3510  case ARM::VST4d16_UPD:
3511  case ARM::VST4d32_UPD:
3512  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
3513  return MCDisassembler::Fail;
3514  break;
3515  case ARM::VST4q8:
3516  case ARM::VST4q16:
3517  case ARM::VST4q32:
3518  case ARM::VST4q8_UPD:
3519  case ARM::VST4q16_UPD:
3520  case ARM::VST4q32_UPD:
3521  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
3522  return MCDisassembler::Fail;
3523  break;
3524  default:
3525  break;
3526  }
3527 
3528  return S;
3529 }
3530 
3532  uint64_t Address,
3533  const MCDisassembler *Decoder) {
3535 
3536  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3537  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3538  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3539  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3540  unsigned align = fieldFromInstruction(Insn, 4, 1);
3541  unsigned size = fieldFromInstruction(Insn, 6, 2);
3542 
3543  if (size == 0 && align == 1)
3544  return MCDisassembler::Fail;
3545  align *= (1 << size);
3546 
3547  switch (Inst.getOpcode()) {
3548  case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
3549  case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
3550  case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
3551  case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
3552  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3553  return MCDisassembler::Fail;
3554  break;
3555  default:
3556  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3557  return MCDisassembler::Fail;
3558  break;
3559  }
3560  if (Rm != 0xF) {
3561  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3562  return MCDisassembler::Fail;
3563  }
3564 
3565  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3566  return MCDisassembler::Fail;
3568 
3569  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3570  // variant encodes Rm == 0xf. Anything else is a register offset post-
3571  // increment and we need to add the register operand to the instruction.
3572  if (Rm != 0xD && Rm != 0xF &&
3573  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3574  return MCDisassembler::Fail;
3575 
3576  return S;
3577 }
3578 
3580  uint64_t Address,
3581  const MCDisassembler *Decoder) {
3583 
3584  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3585  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3586  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3587  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3588  unsigned align = fieldFromInstruction(Insn, 4, 1);
3589  unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
3590  align *= 2*size;
3591 
3592  switch (Inst.getOpcode()) {
3593  case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
3594  case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
3595  case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
3596  case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
3597  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3598  return MCDisassembler::Fail;
3599  break;
3600  case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
3601  case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
3602  case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
3603  case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3604  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3605  return MCDisassembler::Fail;
3606  break;
3607  default:
3608  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3609  return MCDisassembler::Fail;
3610  break;
3611  }
3612 
3613  if (Rm != 0xF)
3615 
3616  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3617  return MCDisassembler::Fail;
3619 
3620  if (Rm != 0xD && Rm != 0xF) {
3621  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3622  return MCDisassembler::Fail;
3623  }
3624 
3625  return S;
3626 }
3627 
3629  uint64_t Address,
3630  const MCDisassembler *Decoder) {
3632 
3633  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3634  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3635  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3636  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3637  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3638 
3639  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3640  return MCDisassembler::Fail;
3641  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3642  return MCDisassembler::Fail;
3643  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3644  return MCDisassembler::Fail;
3645  if (Rm != 0xF) {
3646  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3647  return MCDisassembler::Fail;
3648  }
3649 
3650  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3651  return MCDisassembler::Fail;
3653 
3654  if (Rm == 0xD)
3656  else if (Rm != 0xF) {
3657  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3658  return MCDisassembler::Fail;
3659  }
3660 
3661  return S;
3662 }
3663 
3665  uint64_t Address,
3666  const MCDisassembler *Decoder) {
3668 
3669  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3670  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3671  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3672  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3673  unsigned size = fieldFromInstruction(Insn, 6, 2);
3674  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3675  unsigned align = fieldFromInstruction(Insn, 4, 1);
3676 
3677  if (size == 0x3) {
3678  if (align == 0)
3679  return MCDisassembler::Fail;
3680  align = 16;
3681  } else {
3682  if (size == 2) {
3683  align *= 8;
3684  } else {
3685  size = 1 << size;
3686  align *= 4*size;
3687  }
3688  }
3689 
3690  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3691  return MCDisassembler::Fail;
3692  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3693  return MCDisassembler::Fail;
3694  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3695  return MCDisassembler::Fail;
3696  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3697  return MCDisassembler::Fail;
3698  if (Rm != 0xF) {
3699  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3700  return MCDisassembler::Fail;
3701  }
3702 
3703  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3704  return MCDisassembler::Fail;
3706 
3707  if (Rm == 0xD)
3709  else if (Rm != 0xF) {
3710  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3711  return MCDisassembler::Fail;
3712  }
3713 
3714  return S;
3715 }
3716 
3718  uint64_t Address,
3719  const MCDisassembler *Decoder) {
3721 
3722  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3723  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3724  unsigned imm = fieldFromInstruction(Insn, 0, 4);
3725  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3726  imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3727  imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3728  imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3729  unsigned Q = fieldFromInstruction(Insn, 6, 1);
3730 
3731  if (Q) {
3732  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3733  return MCDisassembler::Fail;
3734  } else {
3735  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3736  return MCDisassembler::Fail;
3737  }
3738 
3739  Inst.addOperand(MCOperand::createImm(imm));
3740 
3741  switch (Inst.getOpcode()) {
3742  case ARM::VORRiv4i16:
3743  case ARM::VORRiv2i32:
3744  case ARM::VBICiv4i16:
3745  case ARM::VBICiv2i32:
3746  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3747  return MCDisassembler::Fail;
3748  break;
3749  case ARM::VORRiv8i16:
3750  case ARM::VORRiv4i32:
3751  case ARM::VBICiv8i16:
3752  case ARM::VBICiv4i32:
3753  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3754  return MCDisassembler::Fail;
3755  break;
3756  default:
3757  break;
3758  }
3759 
3760  return S;
3761 }
3762 
3764  uint64_t Address,
3765  const MCDisassembler *Decoder) {
3767 
3768  unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
3769  fieldFromInstruction(Insn, 13, 3));
3770  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
3771  unsigned imm = fieldFromInstruction(Insn, 0, 4);
3772  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3773  imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3774  imm |= cmode << 8;
3775  imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3776 
3777  if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3778  return MCDisassembler::Fail;
3779 
3780  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3781  return MCDisassembler::Fail;
3782 
3783  Inst.addOperand(MCOperand::createImm(imm));
3784 
3788 
3789  return S;
3790 }
3791 
3793  uint64_t Address,
3794  const MCDisassembler *Decoder) {
3796 
3797  unsigned Qd = fieldFromInstruction(Insn, 13, 3);
3798  Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
3799  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3800  return MCDisassembler::Fail;
3801  Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3802 
3803  unsigned Qn = fieldFromInstruction(Insn, 17, 3);
3804  Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
3805  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
3806  return MCDisassembler::Fail;
3807  unsigned Qm = fieldFromInstruction(Insn, 1, 3);
3808  Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
3809  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3810  return MCDisassembler::Fail;
3811  if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
3812  Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3813  Inst.addOperand(MCOperand::createImm(Qd));
3814 
3815  return S;
3816 }
3817 
3819  uint64_t Address,
3820  const MCDisassembler *Decoder) {
3822 
3823  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3824  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3825  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3826  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3827  unsigned size = fieldFromInstruction(Insn, 18, 2);
3828 
3829  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3830  return MCDisassembler::Fail;
3831  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3832  return MCDisassembler::Fail;
3833  Inst.addOperand(MCOperand::createImm(8 << size));
3834 
3835  return S;
3836 }
3837 
3838 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3839  uint64_t Address,
3840  const MCDisassembler *Decoder) {
3841  Inst.addOperand(MCOperand::createImm(8 - Val));
3842  return MCDisassembler::Success;
3843 }
3844 
3845 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3846  uint64_t Address,
3847  const MCDisassembler *Decoder) {
3848  Inst.addOperand(MCOperand::createImm(16 - Val));
3849  return MCDisassembler::Success;
3850 }
3851 
3852 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3853  uint64_t Address,
3854  const MCDisassembler *Decoder) {
3855  Inst.addOperand(MCOperand::createImm(32 - Val));
3856  return MCDisassembler::Success;
3857 }
3858 
3859 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3860  uint64_t Address,
3861  const MCDisassembler *Decoder) {
3862  Inst.addOperand(MCOperand::createImm(64 - Val));
3863  return MCDisassembler::Success;
3864 }
3865 
3867  uint64_t Address,
3868  const MCDisassembler *Decoder) {
3870 
3871  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3872  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3873  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3874  Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3875  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3876  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3877  unsigned op = fieldFromInstruction(Insn, 6, 1);
3878 
3879  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3880  return MCDisassembler::Fail;
3881  if (op) {
3882  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3883  return MCDisassembler::Fail; // Writeback
3884  }
3885 
3886  switch (Inst.getOpcode()) {
3887  case ARM::VTBL2:
3888  case ARM::VTBX2:
3889  if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3890  return MCDisassembler::Fail;
3891  break;
3892  default:
3893  if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3894  return MCDisassembler::Fail;
3895  }
3896 
3897  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3898  return MCDisassembler::Fail;
3899 
3900  return S;
3901 }
3902 
3904  uint64_t Address,
3905  const MCDisassembler *Decoder) {
3907 
3908  unsigned dst = fieldFromInstruction(Insn, 8, 3);
3909  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3910 
3911  if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3912  return MCDisassembler::Fail;
3913 
3914  switch(Inst.getOpcode()) {
3915  default:
3916  return MCDisassembler::Fail;
3917  case ARM::tADR:
3918  break; // tADR does not explicitly represent the PC as an operand.
3919  case ARM::tADDrSPi:
3920  Inst.addOperand(MCOperand::createReg(ARM::SP));
3921  break;
3922  }
3923 
3924  Inst.addOperand(MCOperand::createImm(imm));
3925  return S;
3926 }
3927 
3928 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3929  uint64_t Address,
3930  const MCDisassembler *Decoder) {
3931  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3932  true, 2, Inst, Decoder))
3933  Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3934  return MCDisassembler::Success;
3935 }
3936 
3937 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3938  uint64_t Address,
3939  const MCDisassembler *Decoder) {
3940  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3941  true, 4, Inst, Decoder))
3942  Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3943  return MCDisassembler::Success;
3944 }
3945 
3946 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3947  uint64_t Address,
3948  const MCDisassembler *Decoder) {
3949  if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3950  true, 2, Inst, Decoder))
3951  Inst.addOperand(MCOperand::createImm(Val << 1));
3952  return MCDisassembler::Success;
3953 }
3954 
3955 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3956  uint64_t Address,
3957  const MCDisassembler *Decoder) {
3959 
3960  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3961  unsigned Rm = fieldFromInstruction(Val, 3, 3);
3962 
3963  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3964  return MCDisassembler::Fail;
3965  if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3966  return MCDisassembler::Fail;
3967 
3968  return S;
3969 }
3970 
3971 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3972  uint64_t Address,
3973  const MCDisassembler *Decoder) {
3975 
3976  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3977  unsigned imm = fieldFromInstruction(Val, 3, 5);
3978 
3979  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3980  return MCDisassembler::Fail;
3981  Inst.addOperand(MCOperand::createImm(imm));
3982 
3983  return S;
3984 }
3985 
3986 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3987  uint64_t Address,
3988  const MCDisassembler *Decoder) {
3989  unsigned imm = Val << 2;
3990 
3991  Inst.addOperand(MCOperand::createImm(imm));
3992  tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3993 
3994  return MCDisassembler::Success;
3995 }
3996 
3997 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3998  uint64_t Address,
3999  const MCDisassembler *Decoder) {
4000  Inst.addOperand(MCOperand::createReg(ARM::SP));
4001  Inst.addOperand(MCOperand::createImm(Val));
4002 
4003  return MCDisassembler::Success;
4004 }
4005 
4006 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
4007  uint64_t Address,
4008  const MCDisassembler *Decoder) {
4010 
4011  unsigned Rn = fieldFromInstruction(Val, 6, 4);
4012  unsigned Rm = fieldFromInstruction(Val, 2, 4);
4013  unsigned imm = fieldFromInstruction(Val, 0, 2);
4014 
4015  // Thumb stores cannot use PC as dest register.
4016  switch (Inst.getOpcode()) {
4017  case ARM::t2STRHs:
4018  case ARM::t2STRBs:
4019  case ARM::t2STRs:
4020  if (Rn == 15)
4021  return MCDisassembler::Fail;
4022  break;
4023  default:
4024  break;
4025  }
4026 
4027  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4028  return MCDisassembler::Fail;
4029  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4030  return MCDisassembler::Fail;
4031  Inst.addOperand(MCOperand::createImm(imm));
4032 
4033  return S;
4034 }
4035 
4037  uint64_t Address,
4038  const MCDisassembler *Decoder) {
4040 
4041  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4042  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4043 
4044  const FeatureBitset &featureBits =
4045  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4046 
4047  bool hasMP = featureBits[ARM::FeatureMP];
4048  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4049 
4050  if (Rn == 15) {
4051  switch (Inst.getOpcode()) {
4052  case ARM::t2LDRBs:
4053  Inst.setOpcode(ARM::t2LDRBpci);
4054  break;
4055  case ARM::t2LDRHs:
4056  Inst.setOpcode(ARM::t2LDRHpci);
4057  break;
4058  case ARM::t2LDRSHs:
4059  Inst.setOpcode(ARM::t2LDRSHpci);
4060  break;
4061  case ARM::t2LDRSBs:
4062  Inst.setOpcode(ARM::t2LDRSBpci);
4063  break;
4064  case ARM::t2LDRs:
4065  Inst.setOpcode(ARM::t2LDRpci);
4066  break;
4067  case ARM::t2PLDs:
4068  Inst.setOpcode(ARM::t2PLDpci);
4069  break;
4070  case ARM::t2PLIs:
4071  Inst.setOpcode(ARM::t2PLIpci);
4072  break;
4073  default:
4074  return MCDisassembler::Fail;
4075  }
4076 
4077  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4078  }
4079 
4080  if (Rt == 15) {
4081  switch (Inst.getOpcode()) {
4082  case ARM::t2LDRSHs:
4083  return MCDisassembler::Fail;
4084  case ARM::t2LDRHs:
4085  Inst.setOpcode(ARM::t2PLDWs);
4086  break;
4087  case ARM::t2LDRSBs:
4088  Inst.setOpcode(ARM::t2PLIs);
4089  break;
4090  default:
4091  break;
4092  }
4093  }
4094 
4095  switch (Inst.getOpcode()) {
4096  case ARM::t2PLDs:
4097  break;
4098  case ARM::t2PLIs:
4099  if (!hasV7Ops)
4100  return MCDisassembler::Fail;
4101  break;
4102  case ARM::t2PLDWs:
4103  if (!hasV7Ops || !hasMP)
4104  return MCDisassembler::Fail;
4105  break;
4106  default:
4107  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4108  return MCDisassembler::Fail;
4109  }
4110 
4111  unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
4112  addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
4113  addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
4114  if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
4115  return MCDisassembler::Fail;
4116 
4117  return S;
4118 }
4119 
4120 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
4121  uint64_t Address,
4122  const MCDisassembler *Decoder) {
4124 
4125  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4126  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4127  unsigned U = fieldFromInstruction(Insn, 9, 1);
4128  unsigned imm = fieldFromInstruction(Insn, 0, 8);
4129  imm |= (U << 8);
4130  imm |= (Rn << 9);
4131  unsigned add = fieldFromInstruction(Insn, 9, 1);
4132 
4133  const FeatureBitset &featureBits =
4134  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4135 
4136  bool hasMP = featureBits[ARM::FeatureMP];
4137  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4138 
4139  if (Rn == 15) {
4140  switch (Inst.getOpcode()) {
4141  case ARM::t2LDRi8:
4142  Inst.setOpcode(ARM::t2LDRpci);
4143  break;
4144  case ARM::t2LDRBi8:
4145  Inst.setOpcode(ARM::t2LDRBpci);
4146  break;
4147  case ARM::t2LDRSBi8:
4148  Inst.setOpcode(ARM::t2LDRSBpci);
4149  break;
4150  case ARM::t2LDRHi8:
4151  Inst.setOpcode(ARM::t2LDRHpci);
4152  break;
4153  case ARM::t2LDRSHi8:
4154  Inst.setOpcode(ARM::t2LDRSHpci);
4155  break;
4156  case ARM::t2PLDi8:
4157  Inst.setOpcode(ARM::t2PLDpci);
4158  break;
4159  case ARM::t2PLIi8:
4160  Inst.setOpcode(ARM::t2PLIpci);
4161  break;
4162  default:
4163  return MCDisassembler::Fail;
4164  }
4165  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4166  }
4167 
4168  if (Rt == 15) {
4169  switch (Inst.getOpcode()) {
4170  case ARM::t2LDRSHi8:
4171  return MCDisassembler::Fail;
4172  case ARM::t2LDRHi8:
4173  if (!add)
4174  Inst.setOpcode(ARM::t2PLDWi8);
4175  break;
4176  case ARM::t2LDRSBi8:
4177  Inst.setOpcode(ARM::t2PLIi8);
4178  break;
4179  default:
4180  break;
4181  }
4182  }
4183 
4184  switch (Inst.getOpcode()) {
4185  case ARM::t2PLDi8:
4186  break;
4187  case ARM::t2PLIi8:
4188  if (!hasV7Ops)
4189  return MCDisassembler::Fail;
4190  break;
4191  case ARM::t2PLDWi8:
4192  if (!hasV7Ops || !hasMP)
4193  return MCDisassembler::Fail;
4194  break;
4195  default:
4196  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4197  return MCDisassembler::Fail;
4198  }
4199 
4200  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4201  return MCDisassembler::Fail;
4202  return S;
4203 }
4204 
4206  uint64_t Address,
4207  const MCDisassembler *Decoder) {
4209 
4210  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4211  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4212  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4213  imm |= (Rn << 13);
4214 
4215  const FeatureBitset &featureBits =
4216  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4217 
4218  bool hasMP = featureBits[ARM::FeatureMP];
4219  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4220 
4221  if (Rn == 15) {
4222  switch (Inst.getOpcode()) {
4223  case ARM::t2LDRi12:
4224  Inst.setOpcode(ARM::t2LDRpci);
4225  break;
4226  case ARM::t2LDRHi12:
4227  Inst.setOpcode(ARM::t2LDRHpci);
4228  break;
4229  case ARM::t2LDRSHi12:
4230  Inst.setOpcode(ARM::t2LDRSHpci);
4231  break;
4232  case ARM::t2LDRBi12:
4233  Inst.setOpcode(ARM::t2LDRBpci);
4234  break;
4235  case ARM::t2LDRSBi12:
4236  Inst.setOpcode(ARM::t2LDRSBpci);
4237  break;
4238  case ARM::t2PLDi12:
4239  Inst.setOpcode(ARM::t2PLDpci);
4240  break;
4241  case ARM::t2PLIi12:
4242  Inst.setOpcode(ARM::t2PLIpci);
4243  break;
4244  default:
4245  return MCDisassembler::Fail;
4246  }
4247  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4248  }
4249 
4250  if (Rt == 15) {
4251  switch (Inst.getOpcode()) {
4252  case ARM::t2LDRSHi12:
4253  return MCDisassembler::Fail;
4254  case ARM::t2LDRHi12:
4255  Inst.setOpcode(ARM::t2PLDWi12);
4256  break;
4257  case ARM::t2LDRSBi12:
4258  Inst.setOpcode(ARM::t2PLIi12);
4259  break;
4260  default:
4261  break;
4262  }
4263  }
4264 
4265  switch (Inst.getOpcode()) {
4266  case ARM::t2PLDi12:
4267  break;
4268  case ARM::t2PLIi12:
4269  if (!hasV7Ops)
4270  return MCDisassembler::Fail;
4271  break;
4272  case ARM::t2PLDWi12:
4273  if (!hasV7Ops || !hasMP)
4274  return MCDisassembler::Fail;
4275  break;
4276  default:
4277  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4278  return MCDisassembler::Fail;
4279  }
4280 
4281  if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
4282  return MCDisassembler::Fail;
4283  return S;
4284 }
4285 
4286 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
4287  const MCDisassembler *Decoder) {
4289 
4290  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4291  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4292  unsigned imm = fieldFromInstruction(Insn, 0, 8);
4293  imm |= (Rn << 9);
4294 
4295  if (Rn == 15) {
4296  switch (Inst.getOpcode()) {
4297  case ARM::t2LDRT:
4298  Inst.setOpcode(ARM::t2LDRpci);
4299  break;
4300  case ARM::t2LDRBT:
4301  Inst.setOpcode(ARM::t2LDRBpci);
4302  break;
4303  case ARM::t2LDRHT:
4304  Inst.setOpcode(ARM::t2LDRHpci);
4305  break;
4306  case ARM::t2LDRSBT:
4307  Inst.setOpcode(ARM::t2LDRSBpci);
4308  break;
4309  case ARM::t2LDRSHT:
4310  Inst.setOpcode(ARM::t2LDRSHpci);
4311  break;
4312  default:
4313  return MCDisassembler::Fail;
4314  }
4315  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4316  }
4317 
4318  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4319  return MCDisassembler::Fail;
4320  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4321  return MCDisassembler::Fail;
4322  return S;
4323 }
4324 
4326  uint64_t Address,
4327  const MCDisassembler *Decoder) {
4329 
4330  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4331  unsigned U = fieldFromInstruction(Insn, 23, 1);
4332  int imm = fieldFromInstruction(Insn, 0, 12);
4333 
4334  const FeatureBitset &featureBits =
4335  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4336 
4337  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4338 
4339  if (Rt == 15) {
4340  switch (Inst.getOpcode()) {
4341  case ARM::t2LDRBpci:
4342  case ARM::t2LDRHpci:
4343  Inst.setOpcode(ARM::t2PLDpci);
4344  break;
4345  case ARM::t2LDRSBpci:
4346  Inst.setOpcode(ARM::t2PLIpci);
4347  break;
4348  case ARM::t2LDRSHpci:
4349  return MCDisassembler::Fail;
4350  default:
4351  break;
4352  }
4353  }
4354 
4355  switch(Inst.getOpcode()) {
4356  case ARM::t2PLDpci:
4357  break;
4358  case ARM::t2PLIpci:
4359  if (!hasV7Ops)
4360  return MCDisassembler::Fail;
4361  break;
4362  default:
4363  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4364  return MCDisassembler::Fail;
4365  }
4366 
4367  if (!U) {
4368  // Special case for #-0.
4369  if (imm == 0)
4370  imm = INT32_MIN;
4371  else
4372  imm = -imm;
4373  }
4374  Inst.addOperand(MCOperand::createImm(imm));
4375 
4376  return S;
4377 }
4378 
4379 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
4380  const MCDisassembler *Decoder) {
4381  if (Val == 0)
4382  Inst.addOperand(MCOperand::createImm(INT32_MIN));
4383  else {
4384  int imm = Val & 0xFF;
4385 
4386  if (!(Val & 0x100)) imm *= -1;
4387  Inst.addOperand(MCOperand::createImm(imm * 4));
4388  }
4389 
4390  return MCDisassembler::Success;
4391 }
4392 
4393 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
4394  const MCDisassembler *Decoder) {
4395  if (Val == 0)
4396  Inst.addOperand(MCOperand::createImm(INT32_MIN));
4397  else {
4398  int imm = Val & 0x7F;
4399 
4400  if (!(Val & 0x80))
4401  imm *= -1;
4402  Inst.addOperand(MCOperand::createImm(imm * 4));
4403  }
4404 
4405  return MCDisassembler::Success;
4406 }
4407 
4408 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
4409  uint64_t Address,
4410  const MCDisassembler *Decoder) {
4412 
4413  unsigned Rn = fieldFromInstruction(Val, 9, 4);
4414  unsigned imm = fieldFromInstruction(Val, 0, 9);
4415 
4416  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4417  return MCDisassembler::Fail;
4418  if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
4419  return MCDisassembler::Fail;
4420 
4421  return S;
4422 }
4423 
4424 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
4425  uint64_t Address,
4426  const MCDisassembler *Decoder) {
4428 
4429  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4430  unsigned imm = fieldFromInstruction(Val, 0, 8);
4431 
4432  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4433  return MCDisassembler::Fail;
4434  if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
4435  return MCDisassembler::Fail;
4436 
4437  return S;
4438 }
4439 
4441  uint64_t Address,
4442  const MCDisassembler *Decoder) {
4444 
4445  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4446  unsigned imm = fieldFromInstruction(Val, 0, 8);
4447 
4448  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4449  return MCDisassembler::Fail;
4450 
4451  Inst.addOperand(MCOperand::createImm(imm));
4452 
4453  return S;
4454 }
4455 
4456 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
4457  const MCDisassembler *Decoder) {
4458  int imm = Val & 0xFF;
4459  if (Val == 0)
4460  imm = INT32_MIN;
4461  else if (!(Val & 0x100))
4462  imm *= -1;
4463  Inst.addOperand(MCOperand::createImm(imm));
4464 
4465  return MCDisassembler::Success;
4466 }
4467 
4468 template <int shift>
4469 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
4470  const MCDisassembler *Decoder) {
4471  int imm = Val & 0x7F;
4472  if (Val == 0)
4473  imm = INT32_MIN;
4474  else if (!(Val & 0x80))
4475  imm *= -1;
4476  if (imm != INT32_MIN)
4477  imm *= (1U << shift);
4478  Inst.addOperand(MCOperand::createImm(imm));
4479 
4480  return MCDisassembler::Success;
4481 }
4482 
4483 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
4484  uint64_t Address,
4485  const MCDisassembler *Decoder) {
4487 
4488  unsigned Rn = fieldFromInstruction(Val, 9, 4);
4489  unsigned imm = fieldFromInstruction(Val, 0, 9);
4490 
4491  // Thumb stores cannot use PC as dest register.
4492  switch (Inst.getOpcode()) {
4493  case ARM::t2STRT:
4494  case ARM::t2STRBT:
4495  case ARM::t2STRHT:
4496  case ARM::t2STRi8:
4497  case ARM::t2STRHi8:
4498  case ARM::t2STRBi8:
4499  if (Rn == 15)
4500  return MCDisassembler::Fail;
4501  break;
4502  default:
4503  break;
4504  }
4505 
4506  // Some instructions always use an additive offset.
4507  switch (Inst.getOpcode()) {
4508  case ARM::t2LDRT:
4509  case ARM::t2LDRBT:
4510  case ARM::t2LDRHT:
4511  case ARM::t2LDRSBT:
4512  case ARM::t2LDRSHT:
4513  case ARM::t2STRT:
4514  case ARM::t2STRBT:
4515  case ARM::t2STRHT:
4516  imm |= 0x100;
4517  break;
4518  default:
4519  break;
4520  }
4521 
4522  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4523  return MCDisassembler::Fail;
4524  if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
4525  return MCDisassembler::Fail;
4526 
4527  return S;
4528 }
4529 
4530 template <int shift>
4531 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
4532  uint64_t Address,
4533  const MCDisassembler *Decoder) {
4535 
4536  unsigned Rn = fieldFromInstruction(Val, 8, 3);
4537  unsigned imm = fieldFromInstruction(Val, 0, 8);
4538 
4539  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4540  return MCDisassembler::Fail;
4541  if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4542  return MCDisassembler::Fail;
4543 
4544  return S;
4545 }
4546 
4547 template <int shift, int WriteBack>
4548 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
4549  uint64_t Address,
4550  const MCDisassembler *Decoder) {
4552 
4553  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4554  unsigned imm = fieldFromInstruction(Val, 0, 8);
4555  if (WriteBack) {
4556  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4557  return MCDisassembler::Fail;
4558  } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4559  return MCDisassembler::Fail;
4560  if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4561  return MCDisassembler::Fail;
4562 
4563  return S;
4564 }
4565 
4566 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
4567  uint64_t Address,
4568  const MCDisassembler *Decoder) {
4570 
4571  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4572  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4573  unsigned addr = fieldFromInstruction(Insn, 0, 8);
4574  addr |= fieldFromInstruction(Insn, 9, 1) << 8;
4575  addr |= Rn << 9;
4576  unsigned load = fieldFromInstruction(Insn, 20, 1);
4577 
4578  if (Rn == 15) {
4579  switch (Inst.getOpcode()) {
4580  case ARM::t2LDR_PRE:
4581  case ARM::t2LDR_POST:
4582  Inst.setOpcode(ARM::t2LDRpci);
4583  break;
4584  case ARM::t2LDRB_PRE:
4585  case ARM::t2LDRB_POST:
4586  Inst.setOpcode(ARM::t2LDRBpci);
4587  break;
4588  case ARM::t2LDRH_PRE:
4589  case ARM::t2LDRH_POST:
4590  Inst.setOpcode(ARM::t2LDRHpci);
4591  break;
4592  case ARM::t2LDRSB_PRE:
4593  case ARM::t2LDRSB_POST:
4594  if (Rt == 15)
4595  Inst.setOpcode(ARM::t2PLIpci);
4596  else
4597  Inst.setOpcode(ARM::t2LDRSBpci);
4598  break;
4599  case ARM::t2LDRSH_PRE:
4600  case ARM::t2LDRSH_POST:
4601  Inst.setOpcode(ARM::t2LDRSHpci);
4602  break;
4603  default:
4604  return MCDisassembler::Fail;
4605  }
4606  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4607  }
4608 
4609  if (!load) {
4610  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4611  return MCDisassembler::Fail;
4612  }
4613 
4614  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4615  return MCDisassembler::Fail;
4616 
4617  if (load) {
4618  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4619  return MCDisassembler::Fail;
4620  }
4621 
4622  if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
4623  return MCDisassembler::Fail;
4624 
4625  return S;
4626 }
4627 
4628 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
4629  uint64_t Address,
4630  const MCDisassembler *Decoder) {
4632 
4633  unsigned Rn = fieldFromInstruction(Val, 13, 4);
4634  unsigned imm = fieldFromInstruction(Val, 0, 12);
4635 
4636  // Thumb stores cannot use PC as dest register.
4637  switch (Inst.getOpcode()) {
4638  case ARM::t2STRi12:
4639  case ARM::t2STRBi12:
4640  case ARM::t2STRHi12:
4641  if (Rn == 15)
4642  return MCDisassembler::Fail;
4643  break;
4644  default:
4645  break;
4646  }
4647 
4648  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4649  return MCDisassembler::Fail;
4650  Inst.addOperand(MCOperand::createImm(imm));
4651 
4652  return S;
4653 }
4654 
4656  uint64_t Address,
4657  const MCDisassembler *Decoder) {
4658  unsigned imm = fieldFromInstruction(Insn, 0, 7);
4659 
4660  Inst.addOperand(MCOperand::createReg(ARM::SP));
4661  Inst.addOperand(MCOperand::createReg(ARM::SP));
4662  Inst.addOperand(MCOperand::createImm(imm));
4663 
4664  return MCDisassembler::Success;
4665 }
4666 
4668  uint64_t Address,
4669  const MCDisassembler *Decoder) {
4671 
4672  if (Inst.getOpcode() == ARM::tADDrSP) {
4673  unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
4674  Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
4675 
4676  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4677  return MCDisassembler::Fail;
4678  Inst.addOperand(MCOperand::createReg(ARM::SP));
4679  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4680  return MCDisassembler::Fail;
4681  } else if (Inst.getOpcode() == ARM::tADDspr) {
4682  unsigned Rm = fieldFromInstruction(Insn, 3, 4);
4683 
4684  Inst.addOperand(MCOperand::createReg(ARM::SP));
4685  Inst.addOperand(MCOperand::createReg(ARM::SP));
4686  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4687  return MCDisassembler::Fail;
4688  }
4689 
4690  return S;
4691 }
4692 
4694  uint64_t Address,
4695  const MCDisassembler *Decoder) {
4696  unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
4697  unsigned flags = fieldFromInstruction(Insn, 0, 3);
4698 
4699  Inst.addOperand(MCOperand::createImm(imod));
4700  Inst.addOperand(MCOperand::createImm(flags));
4701 
4702  return MCDisassembler::Success;
4703 }
4704 
4705 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
4706  uint64_t Address,
4707  const MCDisassembler *Decoder) {
4709  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4710  unsigned add = fieldFromInstruction(Insn, 4, 1);
4711 
4712  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
4713  return MCDisassembler::Fail;
4715 
4716  return S;
4717 }
4718 
4720  uint64_t Address,
4721  const MCDisassembler *Decoder) {
4723  unsigned Rn = fieldFromInstruction(Insn, 3, 4);
4724  unsigned Qm = fieldFromInstruction(Insn, 0, 3);
4725 
4726  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4727  return MCDisassembler::Fail;
4728  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4729  return MCDisassembler::Fail;
4730 
4731  return S;
4732 }
4733 
4734 template <int shift>
4736  uint64_t Address,
4737  const MCDisassembler *Decoder) {
4739  unsigned Qm = fieldFromInstruction(Insn, 8, 3);
4740  int imm = fieldFromInstruction(Insn, 0, 7);
4741