LLVM  16.0.0git
LegalizeTypes.h
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1 //===-- LegalizeTypes.h - DAG Type Legalizer class definition ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the DAGTypeLegalizer class. This is a private interface
10 // shared between the code that implements the SelectionDAG::LegalizeTypes
11 // method.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_LEGALIZETYPES_H
16 #define LLVM_LIB_CODEGEN_SELECTIONDAG_LEGALIZETYPES_H
17 
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/TargetLowering.h"
21 #include "llvm/Support/Compiler.h"
22 
23 namespace llvm {
24 
25 //===----------------------------------------------------------------------===//
26 /// This takes an arbitrary SelectionDAG as input and hacks on it until only
27 /// value types the target machine can handle are left. This involves promoting
28 /// small sizes to large sizes or splitting up large values into small values.
29 ///
30 class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
31  const TargetLowering &TLI;
32  SelectionDAG &DAG;
33 public:
34  /// This pass uses the NodeId on the SDNodes to hold information about the
35  /// state of the node. The enum has all the values.
36  enum NodeIdFlags {
37  /// All operands have been processed, so this node is ready to be handled.
38  ReadyToProcess = 0,
39 
40  /// This is a new node, not before seen, that was created in the process of
41  /// legalizing some other node.
42  NewNode = -1,
43 
44  /// This node's ID needs to be set to the number of its unprocessed
45  /// operands.
46  Unanalyzed = -2,
47 
48  /// This is a node that has already been processed.
49  Processed = -3
50 
51  // 1+ - This is a node which has this many unprocessed operands.
52  };
53 private:
54 
55  /// This is a bitvector that contains two bits for each simple value type,
56  /// where the two bits correspond to the LegalizeAction enum from
57  /// TargetLowering. This can be queried with "getTypeAction(VT)".
58  TargetLowering::ValueTypeActionImpl ValueTypeActions;
59 
60  /// Return how we should legalize values of this type.
61  TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const {
62  return TLI.getTypeAction(*DAG.getContext(), VT);
63  }
64 
65  /// Return true if this type is legal on this target.
66  bool isTypeLegal(EVT VT) const {
67  return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
68  }
69 
70  /// Return true if this is a simple legal type.
71  bool isSimpleLegalType(EVT VT) const {
72  return VT.isSimple() && TLI.isTypeLegal(VT);
73  }
74 
75  EVT getSetCCResultType(EVT VT) const {
76  return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
77  }
78 
79  /// Pretend all of this node's results are legal.
80  bool IgnoreNodeResults(SDNode *N) const {
81  return N->getOpcode() == ISD::TargetConstant ||
82  N->getOpcode() == ISD::Register;
83  }
84 
85  // Bijection from SDValue to unique id. As each created node gets a
86  // new id we do not need to worry about reuse expunging. Should we
87  // run out of ids, we can do a one time expensive compactifcation.
88  typedef unsigned TableId;
89 
90  TableId NextValueId = 1;
91 
92  SmallDenseMap<SDValue, TableId, 8> ValueToIdMap;
93  SmallDenseMap<TableId, SDValue, 8> IdToValueMap;
94 
95  /// For integer nodes that are below legal width, this map indicates what
96  /// promoted value to use.
97  SmallDenseMap<TableId, TableId, 8> PromotedIntegers;
98 
99  /// For integer nodes that need to be expanded this map indicates which
100  /// operands are the expanded version of the input.
101  SmallDenseMap<TableId, std::pair<TableId, TableId>, 8> ExpandedIntegers;
102 
103  /// For floating-point nodes converted to integers of the same size, this map
104  /// indicates the converted value to use.
105  SmallDenseMap<TableId, TableId, 8> SoftenedFloats;
106 
107  /// For floating-point nodes that have a smaller precision than the smallest
108  /// supported precision, this map indicates what promoted value to use.
109  SmallDenseMap<TableId, TableId, 8> PromotedFloats;
110 
111  /// For floating-point nodes that have a smaller precision than the smallest
112  /// supported precision, this map indicates the converted value to use.
113  SmallDenseMap<TableId, TableId, 8> SoftPromotedHalfs;
114 
115  /// For float nodes that need to be expanded this map indicates which operands
116  /// are the expanded version of the input.
117  SmallDenseMap<TableId, std::pair<TableId, TableId>, 8> ExpandedFloats;
118 
119  /// For nodes that are <1 x ty>, this map indicates the scalar value of type
120  /// 'ty' to use.
121  SmallDenseMap<TableId, TableId, 8> ScalarizedVectors;
122 
123  /// For nodes that need to be split this map indicates which operands are the
124  /// expanded version of the input.
125  SmallDenseMap<TableId, std::pair<TableId, TableId>, 8> SplitVectors;
126 
127  /// For vector nodes that need to be widened, indicates the widened value to
128  /// use.
129  SmallDenseMap<TableId, TableId, 8> WidenedVectors;
130 
131  /// For values that have been replaced with another, indicates the replacement
132  /// value to use.
133  SmallDenseMap<TableId, TableId, 8> ReplacedValues;
134 
135  /// This defines a worklist of nodes to process. In order to be pushed onto
136  /// this worklist, all operands of a node must have already been processed.
137  SmallVector<SDNode*, 128> Worklist;
138 
139  TableId getTableId(SDValue V) {
140  assert(V.getNode() && "Getting TableId on SDValue()");
141 
142  auto I = ValueToIdMap.find(V);
143  if (I != ValueToIdMap.end()) {
144  // replace if there's been a shift.
145  RemapId(I->second);
146  assert(I->second && "All Ids should be nonzero");
147  return I->second;
148  }
149  // Add if it's not there.
150  ValueToIdMap.insert(std::make_pair(V, NextValueId));
151  IdToValueMap.insert(std::make_pair(NextValueId, V));
152  ++NextValueId;
153  assert(NextValueId != 0 &&
154  "Ran out of Ids. Increase id type size or add compactification");
155  return NextValueId - 1;
156  }
157 
158  const SDValue &getSDValue(TableId &Id) {
159  RemapId(Id);
160  assert(Id && "TableId should be non-zero");
161  auto I = IdToValueMap.find(Id);
162  assert(I != IdToValueMap.end() && "cannot find Id in map");
163  return I->second;
164  }
165 
166 public:
167  explicit DAGTypeLegalizer(SelectionDAG &dag)
168  : TLI(dag.getTargetLoweringInfo()), DAG(dag),
169  ValueTypeActions(TLI.getValueTypeActions()) {
170  static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
171  "Too many value types for ValueTypeActions to hold!");
172  }
173 
174  /// This is the main entry point for the type legalizer. This does a
175  /// top-down traversal of the dag, legalizing types as it goes. Returns
176  /// "true" if it made any changes.
177  bool run();
178 
179  void NoteDeletion(SDNode *Old, SDNode *New) {
180  assert(Old != New && "node replaced with self");
181  for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
182  TableId NewId = getTableId(SDValue(New, i));
183  TableId OldId = getTableId(SDValue(Old, i));
184 
185  if (OldId != NewId) {
186  ReplacedValues[OldId] = NewId;
187 
188  // Delete Node from tables. We cannot do this when OldId == NewId,
189  // because NewId can still have table references to it in
190  // ReplacedValues.
191  IdToValueMap.erase(OldId);
192  PromotedIntegers.erase(OldId);
193  ExpandedIntegers.erase(OldId);
194  SoftenedFloats.erase(OldId);
195  PromotedFloats.erase(OldId);
196  SoftPromotedHalfs.erase(OldId);
197  ExpandedFloats.erase(OldId);
198  ScalarizedVectors.erase(OldId);
199  SplitVectors.erase(OldId);
200  WidenedVectors.erase(OldId);
201  }
202 
203  ValueToIdMap.erase(SDValue(Old, i));
204  }
205  }
206 
207  SelectionDAG &getDAG() const { return DAG; }
208 
209 private:
210  SDNode *AnalyzeNewNode(SDNode *N);
211  void AnalyzeNewValue(SDValue &Val);
212  void PerformExpensiveChecks();
213  void RemapId(TableId &Id);
214  void RemapValue(SDValue &V);
215 
216  // Common routines.
217  SDValue BitConvertToInteger(SDValue Op);
218  SDValue BitConvertVectorToIntegerVector(SDValue Op);
219  SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
220  bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult);
221  bool CustomWidenLowerNode(SDNode *N, EVT VT);
222 
223  /// Replace each result of the given MERGE_VALUES node with the corresponding
224  /// input operand, except for the result 'ResNo', for which the corresponding
225  /// input operand is returned.
226  SDValue DisintegrateMERGE_VALUES(SDNode *N, unsigned ResNo);
227 
228  SDValue JoinIntegers(SDValue Lo, SDValue Hi);
229 
230  std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
231 
232  SDValue PromoteTargetBoolean(SDValue Bool, EVT ValVT);
233 
234  void ReplaceValueWith(SDValue From, SDValue To);
235  void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
236  void SplitInteger(SDValue Op, EVT LoVT, EVT HiVT,
237  SDValue &Lo, SDValue &Hi);
238 
239  //===--------------------------------------------------------------------===//
240  // Integer Promotion Support: LegalizeIntegerTypes.cpp
241  //===--------------------------------------------------------------------===//
242 
243  /// Given a processed operand Op which was promoted to a larger integer type,
244  /// this returns the promoted value. The low bits of the promoted value
245  /// corresponding to the original type are exactly equal to Op.
246  /// The extra bits contain rubbish, so the promoted value may need to be zero-
247  /// or sign-extended from the original type before it is usable (the helpers
248  /// SExtPromotedInteger and ZExtPromotedInteger can do this for you).
249  /// For example, if Op is an i16 and was promoted to an i32, then this method
250  /// returns an i32, the lower 16 bits of which coincide with Op, and the upper
251  /// 16 bits of which contain rubbish.
252  SDValue GetPromotedInteger(SDValue Op) {
253  TableId &PromotedId = PromotedIntegers[getTableId(Op)];
254  SDValue PromotedOp = getSDValue(PromotedId);
255  assert(PromotedOp.getNode() && "Operand wasn't promoted?");
256  return PromotedOp;
257  }
258  void SetPromotedInteger(SDValue Op, SDValue Result);
259 
260  /// Get a promoted operand and sign extend it to the final size.
261  SDValue SExtPromotedInteger(SDValue Op) {
262  EVT OldVT = Op.getValueType();
263  SDLoc dl(Op);
264  Op = GetPromotedInteger(Op);
265  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
266  DAG.getValueType(OldVT));
267  }
268 
269  /// Get a promoted operand and zero extend it to the final size.
270  SDValue ZExtPromotedInteger(SDValue Op) {
271  EVT OldVT = Op.getValueType();
272  SDLoc dl(Op);
273  Op = GetPromotedInteger(Op);
274  return DAG.getZeroExtendInReg(Op, dl, OldVT);
275  }
276 
277  // Get a promoted operand and sign or zero extend it to the final size
278  // (depending on TargetLoweringInfo::isSExtCheaperThanZExt). For a given
279  // subtarget and type, the choice of sign or zero-extension will be
280  // consistent.
281  SDValue SExtOrZExtPromotedInteger(SDValue Op) {
282  EVT OldVT = Op.getValueType();
283  SDLoc DL(Op);
284  Op = GetPromotedInteger(Op);
285  if (TLI.isSExtCheaperThanZExt(OldVT, Op.getValueType()))
286  return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), Op,
287  DAG.getValueType(OldVT));
288  return DAG.getZeroExtendInReg(Op, DL, OldVT);
289  }
290 
291  // Promote the given operand V (vector or scalar) according to N's specific
292  // reduction kind. N must be an integer VECREDUCE_* or VP_REDUCE_*. Returns
293  // the nominal extension opcode (ISD::(ANY|ZERO|SIGN)_EXTEND) and the
294  // promoted value.
295  SDValue PromoteIntOpVectorReduction(SDNode *N, SDValue V);
296 
297  // Integer Result Promotion.
298  void PromoteIntegerResult(SDNode *N, unsigned ResNo);
299  SDValue PromoteIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
300  SDValue PromoteIntRes_AssertSext(SDNode *N);
301  SDValue PromoteIntRes_AssertZext(SDNode *N);
302  SDValue PromoteIntRes_Atomic0(AtomicSDNode *N);
303  SDValue PromoteIntRes_Atomic1(AtomicSDNode *N);
304  SDValue PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N, unsigned ResNo);
305  SDValue PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N);
306  SDValue PromoteIntRes_INSERT_SUBVECTOR(SDNode *N);
307  SDValue PromoteIntRes_VECTOR_REVERSE(SDNode *N);
308  SDValue PromoteIntRes_VECTOR_SHUFFLE(SDNode *N);
309  SDValue PromoteIntRes_VECTOR_SPLICE(SDNode *N);
310  SDValue PromoteIntRes_BUILD_VECTOR(SDNode *N);
311  SDValue PromoteIntRes_ScalarOp(SDNode *N);
312  SDValue PromoteIntRes_STEP_VECTOR(SDNode *N);
313  SDValue PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N);
314  SDValue PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N);
315  SDValue PromoteIntRes_CONCAT_VECTORS(SDNode *N);
316  SDValue PromoteIntRes_BITCAST(SDNode *N);
317  SDValue PromoteIntRes_BSWAP(SDNode *N);
318  SDValue PromoteIntRes_BITREVERSE(SDNode *N);
319  SDValue PromoteIntRes_BUILD_PAIR(SDNode *N);
320  SDValue PromoteIntRes_Constant(SDNode *N);
321  SDValue PromoteIntRes_CTLZ(SDNode *N);
322  SDValue PromoteIntRes_CTPOP_PARITY(SDNode *N);
323  SDValue PromoteIntRes_CTTZ(SDNode *N);
324  SDValue PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N);
325  SDValue PromoteIntRes_FP_TO_XINT(SDNode *N);
326  SDValue PromoteIntRes_FP_TO_XINT_SAT(SDNode *N);
327  SDValue PromoteIntRes_FP_TO_FP16(SDNode *N);
328  SDValue PromoteIntRes_FREEZE(SDNode *N);
329  SDValue PromoteIntRes_INT_EXTEND(SDNode *N);
330  SDValue PromoteIntRes_LOAD(LoadSDNode *N);
331  SDValue PromoteIntRes_MLOAD(MaskedLoadSDNode *N);
332  SDValue PromoteIntRes_MGATHER(MaskedGatherSDNode *N);
333  SDValue PromoteIntRes_Overflow(SDNode *N);
334  SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo);
335  SDValue PromoteIntRes_Select(SDNode *N);
336  SDValue PromoteIntRes_SELECT_CC(SDNode *N);
337  SDValue PromoteIntRes_SETCC(SDNode *N);
338  SDValue PromoteIntRes_SHL(SDNode *N);
339  SDValue PromoteIntRes_SimpleIntBinOp(SDNode *N);
340  SDValue PromoteIntRes_ZExtIntBinOp(SDNode *N);
341  SDValue PromoteIntRes_SExtIntBinOp(SDNode *N);
342  SDValue PromoteIntRes_UMINUMAX(SDNode *N);
343  SDValue PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N);
344  SDValue PromoteIntRes_SRA(SDNode *N);
345  SDValue PromoteIntRes_SRL(SDNode *N);
346  SDValue PromoteIntRes_TRUNCATE(SDNode *N);
347  SDValue PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo);
348  SDValue PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo);
349  SDValue PromoteIntRes_SADDSUBO_CARRY(SDNode *N, unsigned ResNo);
350  SDValue PromoteIntRes_UNDEF(SDNode *N);
351  SDValue PromoteIntRes_VAARG(SDNode *N);
352  SDValue PromoteIntRes_VSCALE(SDNode *N);
353  SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
354  SDValue PromoteIntRes_ADDSUBSHLSAT(SDNode *N);
355  SDValue PromoteIntRes_MULFIX(SDNode *N);
356  SDValue PromoteIntRes_DIVFIX(SDNode *N);
357  SDValue PromoteIntRes_FLT_ROUNDS(SDNode *N);
358  SDValue PromoteIntRes_VECREDUCE(SDNode *N);
359  SDValue PromoteIntRes_VP_REDUCE(SDNode *N);
360  SDValue PromoteIntRes_ABS(SDNode *N);
361  SDValue PromoteIntRes_Rotate(SDNode *N);
362  SDValue PromoteIntRes_FunnelShift(SDNode *N);
363  SDValue PromoteIntRes_IS_FPCLASS(SDNode *N);
364 
365  // Integer Operand Promotion.
366  bool PromoteIntegerOperand(SDNode *N, unsigned OpNo);
367  SDValue PromoteIntOp_ANY_EXTEND(SDNode *N);
368  SDValue PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N);
369  SDValue PromoteIntOp_BITCAST(SDNode *N);
370  SDValue PromoteIntOp_BUILD_PAIR(SDNode *N);
371  SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);
372  SDValue PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo);
373  SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N);
374  SDValue PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo);
375  SDValue PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N);
376  SDValue PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N);
377  SDValue PromoteIntOp_INSERT_SUBVECTOR(SDNode *N);
378  SDValue PromoteIntOp_CONCAT_VECTORS(SDNode *N);
379  SDValue PromoteIntOp_ScalarOp(SDNode *N);
380  SDValue PromoteIntOp_SELECT(SDNode *N, unsigned OpNo);
381  SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
382  SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
383  SDValue PromoteIntOp_Shift(SDNode *N);
384  SDValue PromoteIntOp_FunnelShift(SDNode *N);
385  SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
386  SDValue PromoteIntOp_SINT_TO_FP(SDNode *N);
387  SDValue PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N);
388  SDValue PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo);
389  SDValue PromoteIntOp_TRUNCATE(SDNode *N);
390  SDValue PromoteIntOp_UINT_TO_FP(SDNode *N);
391  SDValue PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N);
392  SDValue PromoteIntOp_ZERO_EXTEND(SDNode *N);
393  SDValue PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
394  SDValue PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo);
395  SDValue PromoteIntOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
396  SDValue PromoteIntOp_MGATHER(MaskedGatherSDNode *N, unsigned OpNo);
397  SDValue PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo);
398  SDValue PromoteIntOp_FRAMERETURNADDR(SDNode *N);
399  SDValue PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo);
400  SDValue PromoteIntOp_FIX(SDNode *N);
401  SDValue PromoteIntOp_FPOWI(SDNode *N);
402  SDValue PromoteIntOp_VECREDUCE(SDNode *N);
403  SDValue PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo);
404  SDValue PromoteIntOp_SET_ROUNDING(SDNode *N);
405  SDValue PromoteIntOp_STACKMAP(SDNode *N, unsigned OpNo);
406  SDValue PromoteIntOp_PATCHPOINT(SDNode *N, unsigned OpNo);
407  SDValue PromoteIntOp_VP_STRIDED(SDNode *N, unsigned OpNo);
408 
409  void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
410 
411  //===--------------------------------------------------------------------===//
412  // Integer Expansion Support: LegalizeIntegerTypes.cpp
413  //===--------------------------------------------------------------------===//
414 
415  /// Given a processed operand Op which was expanded into two integers of half
416  /// the size, this returns the two halves. The low bits of Op are exactly
417  /// equal to the bits of Lo; the high bits exactly equal Hi.
418  /// For example, if Op is an i64 which was expanded into two i32's, then this
419  /// method returns the two i32's, with Lo being equal to the lower 32 bits of
420  /// Op, and Hi being equal to the upper 32 bits.
421  void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
422  void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi);
423 
424  // Integer Result Expansion.
425  void ExpandIntegerResult(SDNode *N, unsigned ResNo);
426  void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
427  void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValue &Hi);
428  void ExpandIntRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi);
429  void ExpandIntRes_Constant (SDNode *N, SDValue &Lo, SDValue &Hi);
430  void ExpandIntRes_ABS (SDNode *N, SDValue &Lo, SDValue &Hi);
431  void ExpandIntRes_CTLZ (SDNode *N, SDValue &Lo, SDValue &Hi);
432  void ExpandIntRes_CTPOP (SDNode *N, SDValue &Lo, SDValue &Hi);
433  void ExpandIntRes_CTTZ (SDNode *N, SDValue &Lo, SDValue &Hi);
434  void ExpandIntRes_LOAD (LoadSDNode *N, SDValue &Lo, SDValue &Hi);
435  void ExpandIntRes_READCYCLECOUNTER (SDNode *N, SDValue &Lo, SDValue &Hi);
436  void ExpandIntRes_SIGN_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
437  void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDValue &Lo, SDValue &Hi);
438  void ExpandIntRes_TRUNCATE (SDNode *N, SDValue &Lo, SDValue &Hi);
439  void ExpandIntRes_ZERO_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
440  void ExpandIntRes_FLT_ROUNDS (SDNode *N, SDValue &Lo, SDValue &Hi);
441  void ExpandIntRes_FP_TO_SINT (SDNode *N, SDValue &Lo, SDValue &Hi);
442  void ExpandIntRes_FP_TO_UINT (SDNode *N, SDValue &Lo, SDValue &Hi);
443  void ExpandIntRes_FP_TO_XINT_SAT (SDNode *N, SDValue &Lo, SDValue &Hi);
444  void ExpandIntRes_LLROUND_LLRINT (SDNode *N, SDValue &Lo, SDValue &Hi);
445 
446  void ExpandIntRes_Logical (SDNode *N, SDValue &Lo, SDValue &Hi);
447  void ExpandIntRes_ADDSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
448  void ExpandIntRes_ADDSUBC (SDNode *N, SDValue &Lo, SDValue &Hi);
449  void ExpandIntRes_ADDSUBE (SDNode *N, SDValue &Lo, SDValue &Hi);
450  void ExpandIntRes_ADDSUBCARRY (SDNode *N, SDValue &Lo, SDValue &Hi);
451  void ExpandIntRes_SADDSUBO_CARRY (SDNode *N, SDValue &Lo, SDValue &Hi);
452  void ExpandIntRes_BITREVERSE (SDNode *N, SDValue &Lo, SDValue &Hi);
453  void ExpandIntRes_BSWAP (SDNode *N, SDValue &Lo, SDValue &Hi);
454  void ExpandIntRes_PARITY (SDNode *N, SDValue &Lo, SDValue &Hi);
455  void ExpandIntRes_MUL (SDNode *N, SDValue &Lo, SDValue &Hi);
456  void ExpandIntRes_SDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
457  void ExpandIntRes_SREM (SDNode *N, SDValue &Lo, SDValue &Hi);
458  void ExpandIntRes_UDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
459  void ExpandIntRes_UREM (SDNode *N, SDValue &Lo, SDValue &Hi);
460  void ExpandIntRes_Shift (SDNode *N, SDValue &Lo, SDValue &Hi);
461 
462  void ExpandIntRes_MINMAX (SDNode *N, SDValue &Lo, SDValue &Hi);
463 
464  void ExpandIntRes_SADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
465  void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
466  void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi);
467  void ExpandIntRes_ADDSUBSAT (SDNode *N, SDValue &Lo, SDValue &Hi);
468  void ExpandIntRes_SHLSAT (SDNode *N, SDValue &Lo, SDValue &Hi);
469  void ExpandIntRes_MULFIX (SDNode *N, SDValue &Lo, SDValue &Hi);
470  void ExpandIntRes_DIVFIX (SDNode *N, SDValue &Lo, SDValue &Hi);
471 
472  void ExpandIntRes_ATOMIC_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
473  void ExpandIntRes_VECREDUCE (SDNode *N, SDValue &Lo, SDValue &Hi);
474 
475  void ExpandIntRes_Rotate (SDNode *N, SDValue &Lo, SDValue &Hi);
476  void ExpandIntRes_FunnelShift (SDNode *N, SDValue &Lo, SDValue &Hi);
477 
478  void ExpandIntRes_VSCALE (SDNode *N, SDValue &Lo, SDValue &Hi);
479 
480  void ExpandShiftByConstant(SDNode *N, const APInt &Amt,
481  SDValue &Lo, SDValue &Hi);
482  bool ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
483  bool ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
484 
485  // Integer Operand Expansion.
486  bool ExpandIntegerOperand(SDNode *N, unsigned OpNo);
487  SDValue ExpandIntOp_BR_CC(SDNode *N);
488  SDValue ExpandIntOp_SELECT_CC(SDNode *N);
489  SDValue ExpandIntOp_SETCC(SDNode *N);
490  SDValue ExpandIntOp_SETCCCARRY(SDNode *N);
491  SDValue ExpandIntOp_Shift(SDNode *N);
492  SDValue ExpandIntOp_SINT_TO_FP(SDNode *N);
493  SDValue ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
494  SDValue ExpandIntOp_TRUNCATE(SDNode *N);
495  SDValue ExpandIntOp_UINT_TO_FP(SDNode *N);
496  SDValue ExpandIntOp_RETURNADDR(SDNode *N);
497  SDValue ExpandIntOp_ATOMIC_STORE(SDNode *N);
498  SDValue ExpandIntOp_SPLAT_VECTOR(SDNode *N);
499  SDValue ExpandIntOp_STACKMAP(SDNode *N, unsigned OpNo);
500  SDValue ExpandIntOp_PATCHPOINT(SDNode *N, unsigned OpNo);
501  SDValue ExpandIntOp_VP_STRIDED(SDNode *N, unsigned OpNo);
502 
503  void IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
504  ISD::CondCode &CCCode, const SDLoc &dl);
505 
506  //===--------------------------------------------------------------------===//
507  // Float to Integer Conversion Support: LegalizeFloatTypes.cpp
508  //===--------------------------------------------------------------------===//
509 
510  /// GetSoftenedFloat - Given a processed operand Op which was converted to an
511  /// integer of the same size, this returns the integer. The integer contains
512  /// exactly the same bits as Op - only the type changed. For example, if Op
513  /// is an f32 which was softened to an i32, then this method returns an i32,
514  /// the bits of which coincide with those of Op
515  SDValue GetSoftenedFloat(SDValue Op) {
516  TableId Id = getTableId(Op);
517  auto Iter = SoftenedFloats.find(Id);
518  if (Iter == SoftenedFloats.end()) {
519  assert(isSimpleLegalType(Op.getValueType()) &&
520  "Operand wasn't converted to integer?");
521  return Op;
522  }
523  SDValue SoftenedOp = getSDValue(Iter->second);
524  assert(SoftenedOp.getNode() && "Unconverted op in SoftenedFloats?");
525  return SoftenedOp;
526  }
527  void SetSoftenedFloat(SDValue Op, SDValue Result);
528 
529  // Convert Float Results to Integer.
530  void SoftenFloatResult(SDNode *N, unsigned ResNo);
531  SDValue SoftenFloatRes_Unary(SDNode *N, RTLIB::Libcall LC);
532  SDValue SoftenFloatRes_Binary(SDNode *N, RTLIB::Libcall LC);
533  SDValue SoftenFloatRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
534  SDValue SoftenFloatRes_ARITH_FENCE(SDNode *N);
535  SDValue SoftenFloatRes_BITCAST(SDNode *N);
536  SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
537  SDValue SoftenFloatRes_ConstantFP(SDNode *N);
538  SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo);
539  SDValue SoftenFloatRes_FABS(SDNode *N);
540  SDValue SoftenFloatRes_FMINNUM(SDNode *N);
541  SDValue SoftenFloatRes_FMAXNUM(SDNode *N);
542  SDValue SoftenFloatRes_FADD(SDNode *N);
543  SDValue SoftenFloatRes_FCBRT(SDNode *N);
544  SDValue SoftenFloatRes_FCEIL(SDNode *N);
545  SDValue SoftenFloatRes_FCOPYSIGN(SDNode *N);
546  SDValue SoftenFloatRes_FCOS(SDNode *N);
547  SDValue SoftenFloatRes_FDIV(SDNode *N);
548  SDValue SoftenFloatRes_FEXP(SDNode *N);
549  SDValue SoftenFloatRes_FEXP2(SDNode *N);
550  SDValue SoftenFloatRes_FFLOOR(SDNode *N);
551  SDValue SoftenFloatRes_FLOG(SDNode *N);
552  SDValue SoftenFloatRes_FLOG2(SDNode *N);
553  SDValue SoftenFloatRes_FLOG10(SDNode *N);
554  SDValue SoftenFloatRes_FMA(SDNode *N);
555  SDValue SoftenFloatRes_FMUL(SDNode *N);
556  SDValue SoftenFloatRes_FNEARBYINT(SDNode *N);
557  SDValue SoftenFloatRes_FNEG(SDNode *N);
558  SDValue SoftenFloatRes_FP_EXTEND(SDNode *N);
559  SDValue SoftenFloatRes_FP16_TO_FP(SDNode *N);
560  SDValue SoftenFloatRes_FP_ROUND(SDNode *N);
561  SDValue SoftenFloatRes_FPOW(SDNode *N);
562  SDValue SoftenFloatRes_FPOWI(SDNode *N);
563  SDValue SoftenFloatRes_FREEZE(SDNode *N);
564  SDValue SoftenFloatRes_FREM(SDNode *N);
565  SDValue SoftenFloatRes_FRINT(SDNode *N);
566  SDValue SoftenFloatRes_FROUND(SDNode *N);
567  SDValue SoftenFloatRes_FROUNDEVEN(SDNode *N);
568  SDValue SoftenFloatRes_FSIN(SDNode *N);
569  SDValue SoftenFloatRes_FSQRT(SDNode *N);
570  SDValue SoftenFloatRes_FSUB(SDNode *N);
571  SDValue SoftenFloatRes_FTRUNC(SDNode *N);
572  SDValue SoftenFloatRes_LOAD(SDNode *N);
573  SDValue SoftenFloatRes_SELECT(SDNode *N);
574  SDValue SoftenFloatRes_SELECT_CC(SDNode *N);
575  SDValue SoftenFloatRes_UNDEF(SDNode *N);
576  SDValue SoftenFloatRes_VAARG(SDNode *N);
577  SDValue SoftenFloatRes_XINT_TO_FP(SDNode *N);
578  SDValue SoftenFloatRes_VECREDUCE(SDNode *N);
579  SDValue SoftenFloatRes_VECREDUCE_SEQ(SDNode *N);
580 
581  // Convert Float Operand to Integer.
582  bool SoftenFloatOperand(SDNode *N, unsigned OpNo);
583  SDValue SoftenFloatOp_Unary(SDNode *N, RTLIB::Libcall LC);
584  SDValue SoftenFloatOp_BITCAST(SDNode *N);
585  SDValue SoftenFloatOp_BR_CC(SDNode *N);
586  SDValue SoftenFloatOp_FP_ROUND(SDNode *N);
587  SDValue SoftenFloatOp_FP_TO_XINT(SDNode *N);
588  SDValue SoftenFloatOp_FP_TO_XINT_SAT(SDNode *N);
589  SDValue SoftenFloatOp_LROUND(SDNode *N);
590  SDValue SoftenFloatOp_LLROUND(SDNode *N);
591  SDValue SoftenFloatOp_LRINT(SDNode *N);
592  SDValue SoftenFloatOp_LLRINT(SDNode *N);
593  SDValue SoftenFloatOp_SELECT_CC(SDNode *N);
594  SDValue SoftenFloatOp_SETCC(SDNode *N);
595  SDValue SoftenFloatOp_STORE(SDNode *N, unsigned OpNo);
596  SDValue SoftenFloatOp_FCOPYSIGN(SDNode *N);
597 
598  //===--------------------------------------------------------------------===//
599  // Float Expansion Support: LegalizeFloatTypes.cpp
600  //===--------------------------------------------------------------------===//
601 
602  /// Given a processed operand Op which was expanded into two floating-point
603  /// values of half the size, this returns the two halves.
604  /// The low bits of Op are exactly equal to the bits of Lo; the high bits
605  /// exactly equal Hi. For example, if Op is a ppcf128 which was expanded
606  /// into two f64's, then this method returns the two f64's, with Lo being
607  /// equal to the lower 64 bits of Op, and Hi to the upper 64 bits.
608  void GetExpandedFloat(SDValue Op, SDValue &Lo, SDValue &Hi);
609  void SetExpandedFloat(SDValue Op, SDValue Lo, SDValue Hi);
610 
611  // Float Result Expansion.
612  void ExpandFloatResult(SDNode *N, unsigned ResNo);
613  void ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, SDValue &Hi);
614  void ExpandFloatRes_Unary(SDNode *N, RTLIB::Libcall LC,
615  SDValue &Lo, SDValue &Hi);
616  void ExpandFloatRes_Binary(SDNode *N, RTLIB::Libcall LC,
617  SDValue &Lo, SDValue &Hi);
618  void ExpandFloatRes_FABS (SDNode *N, SDValue &Lo, SDValue &Hi);
619  void ExpandFloatRes_FMINNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
620  void ExpandFloatRes_FMAXNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
621  void ExpandFloatRes_FADD (SDNode *N, SDValue &Lo, SDValue &Hi);
622  void ExpandFloatRes_FCBRT (SDNode *N, SDValue &Lo, SDValue &Hi);
623  void ExpandFloatRes_FCEIL (SDNode *N, SDValue &Lo, SDValue &Hi);
624  void ExpandFloatRes_FCOPYSIGN (SDNode *N, SDValue &Lo, SDValue &Hi);
625  void ExpandFloatRes_FCOS (SDNode *N, SDValue &Lo, SDValue &Hi);
626  void ExpandFloatRes_FDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
627  void ExpandFloatRes_FEXP (SDNode *N, SDValue &Lo, SDValue &Hi);
628  void ExpandFloatRes_FEXP2 (SDNode *N, SDValue &Lo, SDValue &Hi);
629  void ExpandFloatRes_FFLOOR (SDNode *N, SDValue &Lo, SDValue &Hi);
630  void ExpandFloatRes_FLOG (SDNode *N, SDValue &Lo, SDValue &Hi);
631  void ExpandFloatRes_FLOG2 (SDNode *N, SDValue &Lo, SDValue &Hi);
632  void ExpandFloatRes_FLOG10 (SDNode *N, SDValue &Lo, SDValue &Hi);
633  void ExpandFloatRes_FMA (SDNode *N, SDValue &Lo, SDValue &Hi);
634  void ExpandFloatRes_FMUL (SDNode *N, SDValue &Lo, SDValue &Hi);
635  void ExpandFloatRes_FNEARBYINT(SDNode *N, SDValue &Lo, SDValue &Hi);
636  void ExpandFloatRes_FNEG (SDNode *N, SDValue &Lo, SDValue &Hi);
637  void ExpandFloatRes_FP_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
638  void ExpandFloatRes_FPOW (SDNode *N, SDValue &Lo, SDValue &Hi);
639  void ExpandFloatRes_FPOWI (SDNode *N, SDValue &Lo, SDValue &Hi);
640  void ExpandFloatRes_FREEZE (SDNode *N, SDValue &Lo, SDValue &Hi);
641  void ExpandFloatRes_FREM (SDNode *N, SDValue &Lo, SDValue &Hi);
642  void ExpandFloatRes_FRINT (SDNode *N, SDValue &Lo, SDValue &Hi);
643  void ExpandFloatRes_FROUND (SDNode *N, SDValue &Lo, SDValue &Hi);
644  void ExpandFloatRes_FROUNDEVEN(SDNode *N, SDValue &Lo, SDValue &Hi);
645  void ExpandFloatRes_FSIN (SDNode *N, SDValue &Lo, SDValue &Hi);
646  void ExpandFloatRes_FSQRT (SDNode *N, SDValue &Lo, SDValue &Hi);
647  void ExpandFloatRes_FSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
648  void ExpandFloatRes_FTRUNC (SDNode *N, SDValue &Lo, SDValue &Hi);
649  void ExpandFloatRes_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
650  void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi);
651 
652  // Float Operand Expansion.
653  bool ExpandFloatOperand(SDNode *N, unsigned OpNo);
654  SDValue ExpandFloatOp_BR_CC(SDNode *N);
655  SDValue ExpandFloatOp_FCOPYSIGN(SDNode *N);
656  SDValue ExpandFloatOp_FP_ROUND(SDNode *N);
657  SDValue ExpandFloatOp_FP_TO_XINT(SDNode *N);
658  SDValue ExpandFloatOp_LROUND(SDNode *N);
659  SDValue ExpandFloatOp_LLROUND(SDNode *N);
660  SDValue ExpandFloatOp_LRINT(SDNode *N);
661  SDValue ExpandFloatOp_LLRINT(SDNode *N);
662  SDValue ExpandFloatOp_SELECT_CC(SDNode *N);
663  SDValue ExpandFloatOp_SETCC(SDNode *N);
664  SDValue ExpandFloatOp_STORE(SDNode *N, unsigned OpNo);
665 
666  void FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
667  ISD::CondCode &CCCode, const SDLoc &dl,
668  SDValue &Chain, bool IsSignaling = false);
669 
670  //===--------------------------------------------------------------------===//
671  // Float promotion support: LegalizeFloatTypes.cpp
672  //===--------------------------------------------------------------------===//
673 
674  SDValue GetPromotedFloat(SDValue Op) {
675  TableId &PromotedId = PromotedFloats[getTableId(Op)];
676  SDValue PromotedOp = getSDValue(PromotedId);
677  assert(PromotedOp.getNode() && "Operand wasn't promoted?");
678  return PromotedOp;
679  }
680  void SetPromotedFloat(SDValue Op, SDValue Result);
681 
682  void PromoteFloatResult(SDNode *N, unsigned ResNo);
683  SDValue PromoteFloatRes_BITCAST(SDNode *N);
684  SDValue PromoteFloatRes_BinOp(SDNode *N);
685  SDValue PromoteFloatRes_ConstantFP(SDNode *N);
686  SDValue PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N);
687  SDValue PromoteFloatRes_FCOPYSIGN(SDNode *N);
688  SDValue PromoteFloatRes_FMAD(SDNode *N);
689  SDValue PromoteFloatRes_FPOWI(SDNode *N);
690  SDValue PromoteFloatRes_FP_ROUND(SDNode *N);
691  SDValue PromoteFloatRes_LOAD(SDNode *N);
692  SDValue PromoteFloatRes_SELECT(SDNode *N);
693  SDValue PromoteFloatRes_SELECT_CC(SDNode *N);
694  SDValue PromoteFloatRes_UnaryOp(SDNode *N);
695  SDValue PromoteFloatRes_UNDEF(SDNode *N);
696  SDValue BitcastToInt_ATOMIC_SWAP(SDNode *N);
697  SDValue PromoteFloatRes_XINT_TO_FP(SDNode *N);
698  SDValue PromoteFloatRes_VECREDUCE(SDNode *N);
699  SDValue PromoteFloatRes_VECREDUCE_SEQ(SDNode *N);
700 
701  bool PromoteFloatOperand(SDNode *N, unsigned OpNo);
702  SDValue PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo);
703  SDValue PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo);
704  SDValue PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo);
705  SDValue PromoteFloatOp_FP_TO_XINT(SDNode *N, unsigned OpNo);
706  SDValue PromoteFloatOp_FP_TO_XINT_SAT(SDNode *N, unsigned OpNo);
707  SDValue PromoteFloatOp_STORE(SDNode *N, unsigned OpNo);
708  SDValue PromoteFloatOp_SELECT_CC(SDNode *N, unsigned OpNo);
709  SDValue PromoteFloatOp_SETCC(SDNode *N, unsigned OpNo);
710 
711  //===--------------------------------------------------------------------===//
712  // Half soft promotion support: LegalizeFloatTypes.cpp
713  //===--------------------------------------------------------------------===//
714 
715  SDValue GetSoftPromotedHalf(SDValue Op) {
716  TableId &PromotedId = SoftPromotedHalfs[getTableId(Op)];
717  SDValue PromotedOp = getSDValue(PromotedId);
718  assert(PromotedOp.getNode() && "Operand wasn't promoted?");
719  return PromotedOp;
720  }
721  void SetSoftPromotedHalf(SDValue Op, SDValue Result);
722 
723  void SoftPromoteHalfResult(SDNode *N, unsigned ResNo);
724  SDValue SoftPromoteHalfRes_BinOp(SDNode *N);
725  SDValue SoftPromoteHalfRes_BITCAST(SDNode *N);
726  SDValue SoftPromoteHalfRes_ConstantFP(SDNode *N);
727  SDValue SoftPromoteHalfRes_EXTRACT_VECTOR_ELT(SDNode *N);
728  SDValue SoftPromoteHalfRes_FCOPYSIGN(SDNode *N);
729  SDValue SoftPromoteHalfRes_FMAD(SDNode *N);
730  SDValue SoftPromoteHalfRes_FPOWI(SDNode *N);
731  SDValue SoftPromoteHalfRes_FP_ROUND(SDNode *N);
732  SDValue SoftPromoteHalfRes_LOAD(SDNode *N);
733  SDValue SoftPromoteHalfRes_SELECT(SDNode *N);
734  SDValue SoftPromoteHalfRes_SELECT_CC(SDNode *N);
735  SDValue SoftPromoteHalfRes_UnaryOp(SDNode *N);
736  SDValue SoftPromoteHalfRes_XINT_TO_FP(SDNode *N);
737  SDValue SoftPromoteHalfRes_UNDEF(SDNode *N);
738  SDValue SoftPromoteHalfRes_VECREDUCE(SDNode *N);
739  SDValue SoftPromoteHalfRes_VECREDUCE_SEQ(SDNode *N);
740 
741  bool SoftPromoteHalfOperand(SDNode *N, unsigned OpNo);
742  SDValue SoftPromoteHalfOp_BITCAST(SDNode *N);
743  SDValue SoftPromoteHalfOp_FCOPYSIGN(SDNode *N, unsigned OpNo);
744  SDValue SoftPromoteHalfOp_FP_EXTEND(SDNode *N);
745  SDValue SoftPromoteHalfOp_FP_TO_XINT(SDNode *N);
746  SDValue SoftPromoteHalfOp_FP_TO_XINT_SAT(SDNode *N);
747  SDValue SoftPromoteHalfOp_SETCC(SDNode *N);
748  SDValue SoftPromoteHalfOp_SELECT_CC(SDNode *N, unsigned OpNo);
749  SDValue SoftPromoteHalfOp_STORE(SDNode *N, unsigned OpNo);
750  SDValue SoftPromoteHalfOp_STACKMAP(SDNode *N, unsigned OpNo);
751  SDValue SoftPromoteHalfOp_PATCHPOINT(SDNode *N, unsigned OpNo);
752 
753  //===--------------------------------------------------------------------===//
754  // Scalarization Support: LegalizeVectorTypes.cpp
755  //===--------------------------------------------------------------------===//
756 
757  /// Given a processed one-element vector Op which was scalarized to its
758  /// element type, this returns the element. For example, if Op is a v1i32,
759  /// Op = < i32 val >, this method returns val, an i32.
760  SDValue GetScalarizedVector(SDValue Op) {
761  TableId &ScalarizedId = ScalarizedVectors[getTableId(Op)];
762  SDValue ScalarizedOp = getSDValue(ScalarizedId);
763  assert(ScalarizedOp.getNode() && "Operand wasn't scalarized?");
764  return ScalarizedOp;
765  }
766  void SetScalarizedVector(SDValue Op, SDValue Result);
767 
768  // Vector Result Scalarization: <1 x ty> -> ty.
769  void ScalarizeVectorResult(SDNode *N, unsigned ResNo);
770  SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
771  SDValue ScalarizeVecRes_BinOp(SDNode *N);
772  SDValue ScalarizeVecRes_TernaryOp(SDNode *N);
773  SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
774  SDValue ScalarizeVecRes_StrictFPOp(SDNode *N);
775  SDValue ScalarizeVecRes_OverflowOp(SDNode *N, unsigned ResNo);
776  SDValue ScalarizeVecRes_InregOp(SDNode *N);
777  SDValue ScalarizeVecRes_VecInregOp(SDNode *N);
778 
779  SDValue ScalarizeVecRes_BITCAST(SDNode *N);
780  SDValue ScalarizeVecRes_BUILD_VECTOR(SDNode *N);
781  SDValue ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N);
782  SDValue ScalarizeVecRes_FP_ROUND(SDNode *N);
783  SDValue ScalarizeVecRes_FPOWI(SDNode *N);
784  SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
785  SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
786  SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
787  SDValue ScalarizeVecRes_VSELECT(SDNode *N);
788  SDValue ScalarizeVecRes_SELECT(SDNode *N);
789  SDValue ScalarizeVecRes_SELECT_CC(SDNode *N);
790  SDValue ScalarizeVecRes_SETCC(SDNode *N);
791  SDValue ScalarizeVecRes_UNDEF(SDNode *N);
792  SDValue ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
793  SDValue ScalarizeVecRes_FP_TO_XINT_SAT(SDNode *N);
794  SDValue ScalarizeVecRes_IS_FPCLASS(SDNode *N);
795 
796  SDValue ScalarizeVecRes_FIX(SDNode *N);
797 
798  // Vector Operand Scalarization: <1 x ty> -> ty.
799  bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
800  SDValue ScalarizeVecOp_BITCAST(SDNode *N);
801  SDValue ScalarizeVecOp_UnaryOp(SDNode *N);
802  SDValue ScalarizeVecOp_UnaryOp_StrictFP(SDNode *N);
803  SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N);
804  SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
805  SDValue ScalarizeVecOp_VSELECT(SDNode *N);
806  SDValue ScalarizeVecOp_VSETCC(SDNode *N);
807  SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo);
808  SDValue ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo);
809  SDValue ScalarizeVecOp_STRICT_FP_ROUND(SDNode *N, unsigned OpNo);
810  SDValue ScalarizeVecOp_FP_EXTEND(SDNode *N);
811  SDValue ScalarizeVecOp_STRICT_FP_EXTEND(SDNode *N);
812  SDValue ScalarizeVecOp_VECREDUCE(SDNode *N);
813  SDValue ScalarizeVecOp_VECREDUCE_SEQ(SDNode *N);
814 
815  //===--------------------------------------------------------------------===//
816  // Vector Splitting Support: LegalizeVectorTypes.cpp
817  //===--------------------------------------------------------------------===//
818 
819  /// Given a processed vector Op which was split into vectors of half the size,
820  /// this method returns the halves. The first elements of Op coincide with the
821  /// elements of Lo; the remaining elements of Op coincide with the elements of
822  /// Hi: Op is what you would get by concatenating Lo and Hi.
823  /// For example, if Op is a v8i32 that was split into two v4i32's, then this
824  /// method returns the two v4i32's, with Lo corresponding to the first 4
825  /// elements of Op, and Hi to the last 4 elements.
826  void GetSplitVector(SDValue Op, SDValue &Lo, SDValue &Hi);
827  void SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi);
828 
829  /// Split mask operator of a VP intrinsic.
830  std::pair<SDValue, SDValue> SplitMask(SDValue Mask);
831 
832  /// Split mask operator of a VP intrinsic in a given location.
833  std::pair<SDValue, SDValue> SplitMask(SDValue Mask, const SDLoc &DL);
834 
835  // Helper function for incrementing the pointer when splitting
836  // memory operations
837  void IncrementPointer(MemSDNode *N, EVT MemVT, MachinePointerInfo &MPI,
838  SDValue &Ptr, uint64_t *ScaledOffset = nullptr);
839 
840  // Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>.
841  void SplitVectorResult(SDNode *N, unsigned ResNo);
842  void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi);
843  void SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
844  void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
845  void SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo, SDValue &Hi);
846  void SplitVecRes_InregOp(SDNode *N, SDValue &Lo, SDValue &Hi);
847  void SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo, SDValue &Hi);
848  void SplitVecRes_StrictFPOp(SDNode *N, SDValue &Lo, SDValue &Hi);
849  void SplitVecRes_OverflowOp(SDNode *N, unsigned ResNo,
850  SDValue &Lo, SDValue &Hi);
851 
852  void SplitVecRes_FIX(SDNode *N, SDValue &Lo, SDValue &Hi);
853 
854  void SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi);
855  void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
856  void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi);
857  void SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
858  void SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
859  void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
860  void SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi);
861  void SplitVecRes_IS_FPCLASS(SDNode *N, SDValue &Lo, SDValue &Hi);
862  void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
863  void SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi);
864  void SplitVecRes_VP_LOAD(VPLoadSDNode *LD, SDValue &Lo, SDValue &Hi);
865  void SplitVecRes_VP_STRIDED_LOAD(VPStridedLoadSDNode *SLD, SDValue &Lo,
866  SDValue &Hi);
867  void SplitVecRes_MLOAD(MaskedLoadSDNode *MLD, SDValue &Lo, SDValue &Hi);
868  void SplitVecRes_Gather(MemSDNode *VPGT, SDValue &Lo, SDValue &Hi,
869  bool SplitSETCC = false);
870  void SplitVecRes_ScalarOp(SDNode *N, SDValue &Lo, SDValue &Hi);
871  void SplitVecRes_STEP_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
872  void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
873  void SplitVecRes_VECTOR_REVERSE(SDNode *N, SDValue &Lo, SDValue &Hi);
874  void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
875  SDValue &Hi);
876  void SplitVecRes_VECTOR_SPLICE(SDNode *N, SDValue &Lo, SDValue &Hi);
877  void SplitVecRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi);
878  void SplitVecRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo, SDValue &Hi);
879 
880  // Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
881  bool SplitVectorOperand(SDNode *N, unsigned OpNo);
882  SDValue SplitVecOp_VSELECT(SDNode *N, unsigned OpNo);
883  SDValue SplitVecOp_VECREDUCE(SDNode *N, unsigned OpNo);
884  SDValue SplitVecOp_VECREDUCE_SEQ(SDNode *N);
885  SDValue SplitVecOp_VP_REDUCE(SDNode *N, unsigned OpNo);
886  SDValue SplitVecOp_UnaryOp(SDNode *N);
887  SDValue SplitVecOp_TruncateHelper(SDNode *N);
888 
889  SDValue SplitVecOp_BITCAST(SDNode *N);
890  SDValue SplitVecOp_INSERT_SUBVECTOR(SDNode *N, unsigned OpNo);
891  SDValue SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
892  SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
893  SDValue SplitVecOp_ExtVecInRegOp(SDNode *N);
894  SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
895  SDValue SplitVecOp_VP_STORE(VPStoreSDNode *N, unsigned OpNo);
896  SDValue SplitVecOp_VP_STRIDED_STORE(VPStridedStoreSDNode *N, unsigned OpNo);
897  SDValue SplitVecOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
898  SDValue SplitVecOp_Scatter(MemSDNode *N, unsigned OpNo);
899  SDValue SplitVecOp_Gather(MemSDNode *MGT, unsigned OpNo);
900  SDValue SplitVecOp_CONCAT_VECTORS(SDNode *N);
901  SDValue SplitVecOp_VSETCC(SDNode *N);
902  SDValue SplitVecOp_FP_ROUND(SDNode *N);
903  SDValue SplitVecOp_FCOPYSIGN(SDNode *N);
904  SDValue SplitVecOp_FP_TO_XINT_SAT(SDNode *N);
905 
906  //===--------------------------------------------------------------------===//
907  // Vector Widening Support: LegalizeVectorTypes.cpp
908  //===--------------------------------------------------------------------===//
909 
910  /// Given a processed vector Op which was widened into a larger vector, this
911  /// method returns the larger vector. The elements of the returned vector
912  /// consist of the elements of Op followed by elements containing rubbish.
913  /// For example, if Op is a v2i32 that was widened to a v4i32, then this
914  /// method returns a v4i32 for which the first two elements are the same as
915  /// those of Op, while the last two elements contain rubbish.
916  SDValue GetWidenedVector(SDValue Op) {
917  TableId &WidenedId = WidenedVectors[getTableId(Op)];
918  SDValue WidenedOp = getSDValue(WidenedId);
919  assert(WidenedOp.getNode() && "Operand wasn't widened?");
920  return WidenedOp;
921  }
922  void SetWidenedVector(SDValue Op, SDValue Result);
923 
924  /// Given a mask Mask, returns the larger vector into which Mask was widened.
925  SDValue GetWidenedMask(SDValue Mask, ElementCount EC) {
926  // For VP operations, we must also widen the mask. Note that the mask type
927  // may not actually need widening, leading it be split along with the VP
928  // operation.
929  // FIXME: This could lead to an infinite split/widen loop. We only handle
930  // the case where the mask needs widening to an identically-sized type as
931  // the vector inputs.
932  assert(getTypeAction(Mask.getValueType()) ==
933  TargetLowering::TypeWidenVector &&
934  "Unable to widen binary VP op");
935  Mask = GetWidenedVector(Mask);
936  assert(Mask.getValueType().getVectorElementCount() == EC &&
937  "Unable to widen binary VP op");
938  return Mask;
939  }
940 
941  // Widen Vector Result Promotion.
942  void WidenVectorResult(SDNode *N, unsigned ResNo);
943  SDValue WidenVecRes_MERGE_VALUES(SDNode* N, unsigned ResNo);
944  SDValue WidenVecRes_BITCAST(SDNode* N);
945  SDValue WidenVecRes_BUILD_VECTOR(SDNode* N);
946  SDValue WidenVecRes_CONCAT_VECTORS(SDNode* N);
947  SDValue WidenVecRes_EXTEND_VECTOR_INREG(SDNode* N);
948  SDValue WidenVecRes_EXTRACT_SUBVECTOR(SDNode* N);
949  SDValue WidenVecRes_INSERT_SUBVECTOR(SDNode *N);
950  SDValue WidenVecRes_INSERT_VECTOR_ELT(SDNode* N);
951  SDValue WidenVecRes_LOAD(SDNode* N);
952  SDValue WidenVecRes_VP_LOAD(VPLoadSDNode *N);
953  SDValue WidenVecRes_VP_STRIDED_LOAD(VPStridedLoadSDNode *N);
954  SDValue WidenVecRes_MLOAD(MaskedLoadSDNode* N);
955  SDValue WidenVecRes_MGATHER(MaskedGatherSDNode* N);
956  SDValue WidenVecRes_VP_GATHER(VPGatherSDNode* N);
957  SDValue WidenVecRes_ScalarOp(SDNode* N);
958  SDValue WidenVecRes_Select(SDNode *N);
959  SDValue WidenVSELECTMask(SDNode *N);
960  SDValue WidenVecRes_SELECT_CC(SDNode* N);
961  SDValue WidenVecRes_SETCC(SDNode* N);
962  SDValue WidenVecRes_STRICT_FSETCC(SDNode* N);
963  SDValue WidenVecRes_UNDEF(SDNode *N);
964  SDValue WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N);
965  SDValue WidenVecRes_VECTOR_REVERSE(SDNode *N);
966 
967  SDValue WidenVecRes_Ternary(SDNode *N);
968  SDValue WidenVecRes_Binary(SDNode *N);
969  SDValue WidenVecRes_BinaryCanTrap(SDNode *N);
970  SDValue WidenVecRes_BinaryWithExtraScalarOp(SDNode *N);
971  SDValue WidenVecRes_StrictFP(SDNode *N);
972  SDValue WidenVecRes_OverflowOp(SDNode *N, unsigned ResNo);
973  SDValue WidenVecRes_Convert(SDNode *N);
974  SDValue WidenVecRes_Convert_StrictFP(SDNode *N);
975  SDValue WidenVecRes_FP_TO_XINT_SAT(SDNode *N);
976  SDValue WidenVecRes_FCOPYSIGN(SDNode *N);
977  SDValue WidenVecRes_IS_FPCLASS(SDNode *N);
978  SDValue WidenVecRes_POWI(SDNode *N);
979  SDValue WidenVecRes_Unary(SDNode *N);
980  SDValue WidenVecRes_InregOp(SDNode *N);
981 
982  // Widen Vector Operand.
983  bool WidenVectorOperand(SDNode *N, unsigned OpNo);
984  SDValue WidenVecOp_BITCAST(SDNode *N);
985  SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
986  SDValue WidenVecOp_EXTEND(SDNode *N);
987  SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
988  SDValue WidenVecOp_INSERT_SUBVECTOR(SDNode *N);
989  SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
990  SDValue WidenVecOp_STORE(SDNode* N);
991  SDValue WidenVecOp_VP_STORE(SDNode *N, unsigned OpNo);
992  SDValue WidenVecOp_VP_STRIDED_STORE(SDNode *N, unsigned OpNo);
993  SDValue WidenVecOp_MSTORE(SDNode* N, unsigned OpNo);
994  SDValue WidenVecOp_MGATHER(SDNode* N, unsigned OpNo);
995  SDValue WidenVecOp_MSCATTER(SDNode* N, unsigned OpNo);
996  SDValue WidenVecOp_VP_SCATTER(SDNode* N, unsigned OpNo);
997  SDValue WidenVecOp_SETCC(SDNode* N);
998  SDValue WidenVecOp_STRICT_FSETCC(SDNode* N);
999  SDValue WidenVecOp_VSELECT(SDNode *N);
1000 
1001  SDValue WidenVecOp_Convert(SDNode *N);
1002  SDValue WidenVecOp_FP_TO_XINT_SAT(SDNode *N);
1003  SDValue WidenVecOp_FCOPYSIGN(SDNode *N);
1004  SDValue WidenVecOp_IS_FPCLASS(SDNode *N);
1005  SDValue WidenVecOp_VECREDUCE(SDNode *N);
1006  SDValue WidenVecOp_VECREDUCE_SEQ(SDNode *N);
1007  SDValue WidenVecOp_VP_REDUCE(SDNode *N);
1008 
1009  /// Helper function to generate a set of operations to perform
1010  /// a vector operation for a wider type.
1011  ///
1012  SDValue UnrollVectorOp_StrictFP(SDNode *N, unsigned ResNE);
1013 
1014  //===--------------------------------------------------------------------===//
1015  // Vector Widening Utilities Support: LegalizeVectorTypes.cpp
1016  //===--------------------------------------------------------------------===//
1017 
1018  /// Helper function to generate a set of loads to load a vector with a
1019  /// resulting wider type. It takes:
1020  /// LdChain: list of chains for the load to be generated.
1021  /// Ld: load to widen
1022  SDValue GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
1023  LoadSDNode *LD);
1024 
1025  /// Helper function to generate a set of extension loads to load a vector with
1026  /// a resulting wider type. It takes:
1027  /// LdChain: list of chains for the load to be generated.
1028  /// Ld: load to widen
1029  /// ExtType: extension element type
1030  SDValue GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
1031  LoadSDNode *LD, ISD::LoadExtType ExtType);
1032 
1033  /// Helper function to generate a set of stores to store a widen vector into
1034  /// non-widen memory. Returns true if successful, false otherwise.
1035  /// StChain: list of chains for the stores we have generated
1036  /// ST: store of a widen value
1037  bool GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain, StoreSDNode *ST);
1038 
1039  /// Modifies a vector input (widen or narrows) to a vector of NVT. The
1040  /// input vector must have the same element type as NVT.
1041  /// When FillWithZeroes is "on" the vector will be widened with zeroes.
1042  /// By default, the vector will be widened with undefined values.
1043  SDValue ModifyToType(SDValue InOp, EVT NVT, bool FillWithZeroes = false);
1044 
1045  /// Return a mask of vector type MaskVT to replace InMask. Also adjust
1046  /// MaskVT to ToMaskVT if needed with vector extension or truncation.
1047  SDValue convertMask(SDValue InMask, EVT MaskVT, EVT ToMaskVT);
1048 
1049  //===--------------------------------------------------------------------===//
1050  // Generic Splitting: LegalizeTypesGeneric.cpp
1051  //===--------------------------------------------------------------------===//
1052 
1053  // Legalization methods which only use that the illegal type is split into two
1054  // not necessarily identical types. As such they can be used for splitting
1055  // vectors and expanding integers and floats.
1056 
1057  void GetSplitOp(SDValue Op, SDValue &Lo, SDValue &Hi) {
1058  if (Op.getValueType().isVector())
1059  GetSplitVector(Op, Lo, Hi);
1060  else if (Op.getValueType().isInteger())
1061  GetExpandedInteger(Op, Lo, Hi);
1062  else
1063  GetExpandedFloat(Op, Lo, Hi);
1064  }
1065 
1066  /// Use ISD::EXTRACT_ELEMENT nodes to extract the low and high parts of the
1067  /// given value.
1068  void GetPairElements(SDValue Pair, SDValue &Lo, SDValue &Hi);
1069 
1070  // Generic Result Splitting.
1071  void SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1072  SDValue &Lo, SDValue &Hi);
1073  void SplitRes_ARITH_FENCE (SDNode *N, SDValue &Lo, SDValue &Hi);
1074  void SplitRes_Select (SDNode *N, SDValue &Lo, SDValue &Hi);
1075  void SplitRes_SELECT_CC (SDNode *N, SDValue &Lo, SDValue &Hi);
1076  void SplitRes_UNDEF (SDNode *N, SDValue &Lo, SDValue &Hi);
1077  void SplitRes_FREEZE (SDNode *N, SDValue &Lo, SDValue &Hi);
1078 
1079  //===--------------------------------------------------------------------===//
1080  // Generic Expansion: LegalizeTypesGeneric.cpp
1081  //===--------------------------------------------------------------------===//
1082 
1083  // Legalization methods which only use that the illegal type is split into two
1084  // identical types of half the size, and that the Lo/Hi part is stored first
1085  // in memory on little/big-endian machines, followed by the Hi/Lo part. As
1086  // such they can be used for expanding integers and floats.
1087 
1088  void GetExpandedOp(SDValue Op, SDValue &Lo, SDValue &Hi) {
1089  if (Op.getValueType().isInteger())
1090  GetExpandedInteger(Op, Lo, Hi);
1091  else
1092  GetExpandedFloat(Op, Lo, Hi);
1093  }
1094 
1095 
1096  /// This function will split the integer \p Op into \p NumElements
1097  /// operations of type \p EltVT and store them in \p Ops.
1098  void IntegerToVector(SDValue Op, unsigned NumElements,
1099  SmallVectorImpl<SDValue> &Ops, EVT EltVT);
1100 
1101  // Generic Result Expansion.
1102  void ExpandRes_MERGE_VALUES (SDNode *N, unsigned ResNo,
1103  SDValue &Lo, SDValue &Hi);
1104  void ExpandRes_BITCAST (SDNode *N, SDValue &Lo, SDValue &Hi);
1105  void ExpandRes_BUILD_PAIR (SDNode *N, SDValue &Lo, SDValue &Hi);
1106  void ExpandRes_EXTRACT_ELEMENT (SDNode *N, SDValue &Lo, SDValue &Hi);
1107  void ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
1108  void ExpandRes_NormalLoad (SDNode *N, SDValue &Lo, SDValue &Hi);
1109  void ExpandRes_VAARG (SDNode *N, SDValue &Lo, SDValue &Hi);
1110 
1111  // Generic Operand Expansion.
1112  SDValue ExpandOp_BITCAST (SDNode *N);
1113  SDValue ExpandOp_BUILD_VECTOR (SDNode *N);
1114  SDValue ExpandOp_EXTRACT_ELEMENT (SDNode *N);
1115  SDValue ExpandOp_INSERT_VECTOR_ELT(SDNode *N);
1116  SDValue ExpandOp_SCALAR_TO_VECTOR (SDNode *N);
1117  SDValue ExpandOp_NormalStore (SDNode *N, unsigned OpNo);
1118 };
1119 
1120 } // end namespace llvm.
1121 
1122 #endif
i
i
Definition: README.txt:29
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:159
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1859
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
DenseMap.h
llvm::SelectionDAG::getZeroExtendInReg
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
Definition: SelectionDAG.cpp:1436
llvm::DAGTypeLegalizer::NodeIdFlags
NodeIdFlags
This pass uses the NodeId on the SDNodes to hold information about the state of the node.
Definition: LegalizeTypes.h:36
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
SelectionDAG.h
llvm::DAGTypeLegalizer::getDAG
SelectionDAG & getDAG() const
Definition: LegalizeTypes.h:207
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:479
llvm::DAGTypeLegalizer
This takes an arbitrary SelectionDAG as input and hacks on it until only value types the target machi...
Definition: LegalizeTypes.h:30
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1404
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
TargetLowering.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:781
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::DAGTypeLegalizer::NoteDeletion
void NoteDeletion(SDNode *Old, SDNode *New)
Definition: LegalizeTypes.h:179
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3506
llvm::TargetLoweringBase::ValueTypeActionImpl
Definition: TargetLowering.h:945
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:213
llvm::dxil::PointerTypeAnalysis::run
PointerTypeMap run(const Module &M)
Compute the PointerTypeMap for the module M.
Definition: PointerTypeAnalysis.cpp:189
llvm::ISD::Register
@ Register
Definition: ISDOpcodes.h:74
llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction
LegalizeTypeAction getTypeAction(MVT VT) const
Definition: TargetLowering.h:956
uint64_t
llvm::MVT::MAX_ALLOWED_VALUETYPE
@ MAX_ALLOWED_VALUETYPE
Definition: MachineValueType.h:302
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:9133
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1424
Compiler.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
LLVM_LIBRARY_VISIBILITY
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library,...
Definition: Compiler.h:126
Node
Definition: ItaniumDemangle.h:156
llvm::TargetLoweringBase::TypeLegal
@ TypeLegal
Definition: TargetLowering.h:206
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:351
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:469
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::ISD::TargetConstant
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
Definition: ISDOpcodes.h:158
llvm::SDNode::getNumValues
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Definition: SelectionDAGNodes.h:983
N
#define N
llvm::MVT::LAST_VALUETYPE
@ LAST_VALUETYPE
Definition: MachineValueType.h:296
llvm::DAGTypeLegalizer::DAGTypeLegalizer
DAGTypeLegalizer(SelectionDAG &dag)
Definition: LegalizeTypes.h:167
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:244
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