LLVM  14.0.0git
MCRegisterInfo.cpp
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1 //===- MC/MCRegisterInfo.cpp - Target Register Description ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements MCRegisterInfo functions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/MC/MCRegisterInfo.h"
14 #include "llvm/ADT/DenseMap.h"
15 #include "llvm/ADT/Twine.h"
17 #include <algorithm>
18 #include <cassert>
19 #include <cstdint>
20 
21 using namespace llvm;
22 
25  const MCRegisterClass *RC) const {
26  for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
27  if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
28  return *Supers;
29  return 0;
30 }
31 
33  assert(Idx && Idx < getNumSubRegIndices() &&
34  "This is not a subregister index");
35  // Get a pointer to the corresponding SubRegIndices list. This list has the
36  // name of each sub-register in the same order as MCSubRegIterator.
37  const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
38  for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
39  if (*SRI == Idx)
40  return *Subs;
41  return 0;
42 }
43 
45  MCRegister SubReg) const {
46  assert(SubReg && SubReg < getNumRegs() && "This is not a register");
47  // Get a pointer to the corresponding SubRegIndices list. This list has the
48  // name of each sub-register in the same order as MCSubRegIterator.
49  const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
50  for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
51  if (*Subs == SubReg)
52  return *SRI;
53  return 0;
54 }
55 
56 unsigned MCRegisterInfo::getSubRegIdxSize(unsigned Idx) const {
57  assert(Idx && Idx < getNumSubRegIndices() &&
58  "This is not a subregister index");
59  return SubRegIdxRanges[Idx].Size;
60 }
61 
62 unsigned MCRegisterInfo::getSubRegIdxOffset(unsigned Idx) const {
63  assert(Idx && Idx < getNumSubRegIndices() &&
64  "This is not a subregister index");
65  return SubRegIdxRanges[Idx].Offset;
66 }
67 
68 int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
69  const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
70  unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize;
71 
72  if (!M)
73  return -1;
74  DwarfLLVMRegPair Key = { RegNum, 0 };
76  if (I == M+Size || I->FromReg != RegNum)
77  return -1;
78  return I->ToReg;
79 }
80 
82  bool isEH) const {
83  const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
84  unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize;
85 
86  if (!M)
87  return None;
88  DwarfLLVMRegPair Key = { RegNum, 0 };
90  if (I != M + Size && I->FromReg == RegNum)
91  return I->ToReg;
92  return None;
93 }
94 
96  // On ELF platforms, DWARF EH register numbers are the same as DWARF
97  // other register numbers. On Darwin x86, they differ and so need to be
98  // mapped. The .cfi_* directives accept integer literals as well as
99  // register names and should generate exactly what the assembly code
100  // asked for, so there might be DWARF/EH register numbers that don't have
101  // a corresponding LLVM register number at all. So if we can't map the
102  // EH register number to an LLVM register number, assume it's just a
103  // valid DWARF register number as is.
104  if (Optional<unsigned> LRegNum = getLLVMRegNum(RegNum, true))
105  return getDwarfRegNum(*LRegNum, false);
106  return RegNum;
107 }
108 
110  const DenseMap<MCRegister, int>::const_iterator I = L2SEHRegs.find(RegNum);
111  if (I == L2SEHRegs.end()) return (int)RegNum;
112  return I->second;
113 }
114 
116  if (L2CVRegs.empty())
117  report_fatal_error("target does not implement codeview register mapping");
118  const DenseMap<MCRegister, int>::const_iterator I = L2CVRegs.find(RegNum);
119  if (I == L2CVRegs.end())
120  report_fatal_error("unknown codeview register " + (RegNum < getNumRegs()
121  ? getName(RegNum)
122  : Twine(RegNum)));
123  return I->second;
124 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum
int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const
Map a target EH register number to an equivalent DWARF register number.
Definition: MCRegisterInfo.cpp:95
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::lower_bound
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1657
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:24
ErrorHandling.h
llvm::MCRegisterInfo::getDwarfRegNum
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
Definition: MCRegisterInfo.cpp:68
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::DenseMapIterator
Definition: DenseMap.h:56
DenseMap.h
llvm::Optional< unsigned >
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition: MCRegisterInfo.h:68
llvm::MCRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: MCRegisterInfo.cpp:32
llvm::MCRegisterInfo::getNumSubRegIndices
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
Definition: MCRegisterInfo.h:498
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
llvm::MCRegisterInfo::getSEHRegNum
int getSEHRegNum(MCRegister RegNum) const
Map a target register to an equivalent SEH register number.
Definition: MCRegisterInfo.cpp:109
Twine.h
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:481
llvm::MCRegisterInfo::getSubRegIndex
unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
Definition: MCRegisterInfo.cpp:44
llvm::MCRegisterInfo::SubRegCoveredBits::Size
uint16_t Size
Definition: MCRegisterInfo.h:152
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::None
const NoneType None
Definition: None.h:23
llvm::MCRegisterInfo::DwarfLLVMRegPair
DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be performed with a binary se...
Definition: MCRegisterInfo.h:141
llvm::MCRegisterInfo::getLLVMRegNum
Optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
Definition: MCRegisterInfo.cpp:81
I
#define I(x, y, z)
Definition: MD5.cpp:59
MCRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
llvm::MCRegisterInfo::get
const MCRegisterDesc & get(MCRegister RegNo) const
Provide a get method, equivalent to [], but more useful with a pointer to this object.
Definition: MCRegisterInfo.h:454
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
uint16_t
llvm::MCSubRegIterator
MCSubRegIterator enumerates all sub-registers of Reg.
Definition: MCRegisterInfo.h:594
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::MCRegisterDesc::SubRegIndices
uint32_t SubRegIndices
Definition: MCRegisterInfo.h:112
llvm::MCRegisterInfo::getSubRegIdxOffset
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
Definition: MCRegisterInfo.cpp:62
llvm::MCRegisterInfo::getCodeViewRegNum
int getCodeViewRegNum(MCRegister RegNum) const
Map a target register to an equivalent CodeView register number.
Definition: MCRegisterInfo.cpp:115
llvm::MCRegisterInfo::SubRegCoveredBits::Offset
uint16_t Offset
Definition: MCRegisterInfo.h:151
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::MCRegisterInfo::getSubRegIdxSize
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
Definition: MCRegisterInfo.cpp:56