MCRegisterClass - Base class of TargetRegisterClass. More...

#include "llvm/MC/MCRegisterInfo.h"

Public Types
using	iterator = const MCPhysReg*
using	const_iterator = const MCPhysReg*

Public Member Functions
unsigned	getID () const
	getID() - Return the register class ID number.
iterator	begin () const
	begin/end - Return all of the registers in this class.
iterator	end () const
unsigned	getNumRegs () const
	getNumRegs - Return the number of registers in this class.
MCRegister	getRegister (unsigned i) const
	getRegister - Return the specified register in the class.
ArrayRef< MCPhysReg >	getRegisters () const
bool	contains (MCRegister Reg) const
	contains - Return true if the specified register is included in this register class.
bool	contains (MCRegister Reg1, MCRegister Reg2) const
	contains - Return true if both registers are in this class.
unsigned	getSizeInBits () const
	Return the size of the physical register in bits if we are able to determine it.
uint8_t	getCopyCost () const
	getCopyCost - Return the cost of copying a value between two registers in this class.
bool	expensiveOrImpossibleToCopy () const
bool	isAllocatable () const
	isAllocatable - Return true if this register class may be used to create virtual registers.
bool	isBaseClass () const
	Return true if this register class has a defined BaseClassOrder.
bool	hasSubClass (const MCRegisterClass *RC) const
	Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
bool	hasSubClassEq (const MCRegisterClass *RC) const
	Returns true if RC is a sub-class of or equal to this class.
bool	hasSuperClass (const MCRegisterClass *RC) const
	Return true if the specified MCRegisterClass is a proper super-class of this MCRegisterClass.
bool	hasSuperClassEq (const MCRegisterClass *RC) const
	Returns true if RC is a super-class of or equal to this class.
const uint32_t *	getSubClassMask () const
	Returns a bit vector of subclasses, including this one.
const uint32_t *	getSuperRegClassMaskOffsets () const
	Returns the relative offsets of this class's super-register class bit masks, one per entry of getSuperRegIndices().
const uint32_t *	getSuperRegClassMaskAt (uint32_t Offset) const
	Returns the bit mask of register classes that the sub-register index belonging to Offset projects into this class, where Offset is an entry of getSuperRegClassMaskOffsets().
const uint16_t *	getSuperRegIndices () const
	Returns a 0-terminated list of sub-register indices that project some super-register class into this register class.
ArrayRef< unsigned >	superclasses () const
	Returns a list of super-classes.
LaneBitmask	getLaneMask () const
	Returns the combination of all lane masks of register in this class.

Public Attributes
const uint32_t	RegsOff
	Relative offset to MCPhysReg array.
const uint32_t	RegSetOff
	Relative offset to uint8_t array.
const uint32_t	NameIdx
const uint32_t	RegSizeInBits
const uint16_t	RegsSize
const MCPhysReg	RegSetBegin
	Register denoted by first bit in RegSet.
const uint16_t	RegSetSize
const uint16_t	ID
const uint8_t	CopyCost
const bool	Allocatable
const bool	BaseClass
const uint32_t	SubClassMaskOff
	Relative offset to uint32_t array.
const uint32_t	SuperRegMaskOffsetsOff
	Relative offset to a uint32_t array holding, for each entry of getSuperRegIndices(), the relative offset of that entry's bit mask.
const uint32_t	SuperRegIndicesOff
	Relative offset to MCPhysReg array.
const LaneBitmask	LaneMask
const uint8_t	AllocationPriority
	Classes with a higher priority value are assigned first by register allocators using a greedy heuristic.
const bool	GlobalPriority
const uint8_t	TSFlags
	Configurable target specific flags.
const uint8_t	SpillStackID
const bool	HasDisjunctSubRegs
	Whether the class supports two (or more) disjunct subregister indices.
const bool	CoveredBySubRegs
	Whether a combination of subregisters can cover every register in the class.
const uint32_t	SuperClassesOff
	Relative offset to unsigned array.
const uint16_t	SuperClassesSize

Detailed Description

MCRegisterClass - Base class of TargetRegisterClass.

Definition at line 37 of file MCRegisterInfo.h.

Member Typedef Documentation

◆ const_iterator

using llvm::MCRegisterClass::const_iterator = const MCPhysReg*

Definition at line 40 of file MCRegisterInfo.h.

◆ iterator

using llvm::MCRegisterClass::iterator = const MCPhysReg*

Definition at line 39 of file MCRegisterInfo.h.

Member Function Documentation

◆ begin()

iterator llvm::MCRegisterClass::begin ( ) const

inline

begin/end - Return all of the registers in this class.

Definition at line 86 of file MCRegisterInfo.h.

References RegsOff.

Referenced by allocateSGPR32InputImpl(), end(), llvm::HexagonBlockRanges::expandToSubRegs(), getRegister(), getRegisters(), getRegistersForValue(), and getRegistersForValue().

◆ contains() [1/2]

bool llvm::MCRegisterClass::contains ( MCRegister Reg ) const

inline

contains - Return true if the specified register is included in this register class.

This does not include virtual registers.

Definition at line 109 of file MCRegisterInfo.h.

References Reg, RegSetBegin, RegSetOff, and RegSetSize.

Referenced by addHints(), llvm::MachineFunction::addLiveIn(), llvm::SIRegisterInfo::buildSpillLoadStore(), canFoldCopy(), CheckVGPROverflow(), llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters(), llvm::PPCInstrInfo::ClobbersPredicate(), contains(), llvm::AMDGPUDisassembler::convertTrue16OpSel(), llvm::VirtRegAuxInfo::copyHint(), llvm::SIInstrInfo::copyPhysReg(), cvtVOP3DstOpSelOnly(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), estimateRSStackSizeLimit(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::foldImmediate(), llvm::R600InstrInfo::getIndirectIndexBegin(), getLargestFPRegisterOrZero(), llvm::M68kRegisterInfo::getMatchingMegaReg(), llvm::MCRegisterInfo::getMatchingSuperReg(), llvm::AArch64RegisterInfo::getRegAllocationHints(), llvm::ARMBaseRegisterInfo::getRegAllocationHints(), llvm::PPCRegisterInfo::getRegAllocationHints(), llvm::X86RegisterInfo::getRegAllocationHints(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::AMDGPU::getVGPRPhysRegClass(), llvm::PPCInstrInfo::insertSelect(), IsAGPROperand(), llvm::SIInstrInfo::isLegalRegOperand(), isMemOperand(), llvm::HexagonMCInstrInfo::isPredReg(), llvm::AMDGPU::isRsrcIndexReg(), llvm::AMDGPU::isSGPR(), isValidVOPDSrc(), matchAliasCondition(), llvm::MIPS_MC::matchRegisterName(), llvm::ARMInstPrinter::printInst(), llvm::SIFrameLowering::restoreCalleeSavedRegisters(), llvm::rewriteT2FrameIndex(), llvm::CoalescerPair::setRegisters(), llvm::SystemZRegisterInfo::shouldCoalesce(), UpdateOperandRegClass(), and llvm::SIInstrInfo::verifyInstruction().

◆ contains() [2/2]

bool llvm::MCRegisterClass::contains	(	MCRegister	Reg1,
		MCRegister	Reg2 ) const

inline

contains - Return true if both registers are in this class.

Definition at line 120 of file MCRegisterInfo.h.

References contains().

◆ end()

iterator llvm::MCRegisterClass::end ( ) const

inline

Definition at line 90 of file MCRegisterInfo.h.

References begin(), and RegsSize.

Referenced by getRegistersForValue(), and getRegistersForValue().

◆ expensiveOrImpossibleToCopy()

bool llvm::MCRegisterClass::expensiveOrImpossibleToCopy ( ) const

inline

Returns: true if register class is very expensive to copy e.g. status flag register classes.

Definition at line 137 of file MCRegisterInfo.h.

References CopyCost.

Referenced by CheckForPhysRegDependency().

◆ getCopyCost()

uint8_t llvm::MCRegisterClass::getCopyCost ( ) const

inline

getCopyCost - Return the cost of copying a value between two registers in this class.

A negative number means the register class is very expensive to copy e.g. status flag register classes.

Definition at line 133 of file MCRegisterInfo.h.

References CopyCost.

Referenced by CheckForPhysRegDependency().

◆ getID()

unsigned llvm::MCRegisterClass::getID ( ) const

inline

getID() - Return the register class ID number.

Definition at line 82 of file MCRegisterInfo.h.

References ID.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::HexagonEvaluator::composeWithSubRegIndex(), llvm::X86RegisterInfo::constrainRegClassToNonRex2(), llvm::RegisterBank::covers(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::SITargetLowering::finalizeLowering(), llvm::HexagonRegisterInfo::getCallerSavedRegs(), llvm::WebAssembly::getCopyOpcodeForRegClass(), GetCostForDef(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::HexagonRegisterInfo::getHexagonSubRegIndex(), llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), llvm::SIRegisterInfo::getNumUsedPhysRegs(), llvm::AArch64RegisterInfo::getRegAllocationHints(), llvm::X86RegisterInfo::getRegAllocationHints(), llvm::AArch64RegisterBankInfo::getRegBankFromRegClass(), llvm::PPCRegisterBankInfo::getRegBankFromRegClass(), llvm::RISCVRegisterBankInfo::getRegBankFromRegClass(), llvm::SPIRVRegisterBankInfo::getRegBankFromRegClass(), llvm::AMDGPU::getRegBitWidth(), llvm::TargetRegisterInfo::getRegClassInfo(), getRegForPrinting(), llvm::AArch64RegisterInfo::getRegPressureLimit(), llvm::ARMBaseRegisterInfo::getRegPressureLimit(), llvm::MipsRegisterInfo::getRegPressureLimit(), llvm::PPCRegisterInfo::getRegPressureLimit(), llvm::SIRegisterInfo::getRegPressureLimit(), llvm::X86RegisterInfo::getRegPressureLimit(), llvm::AMDGPU::getVGPRWithMSBs(), hasSubClassEq(), INITIALIZE_PASS(), llvm::X86RegisterInfo::isNonRex2RegClass(), isTileRegister(), llvm::X86RegisterInfo::isTileRegisterClass(), IsWritingToVCCR(), llvm::WebAssemblyMCInstLower::lower(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::AMDGPUDAGToDAGISel::Select(), llvm::AArch64RegisterInfo::shouldCoalesce(), and llvm::HexagonRegisterInfo::shouldCoalesce().

◆ getLaneMask()

LaneBitmask llvm::MCRegisterClass::getLaneMask ( ) const

inline

Returns the combination of all lane masks of register in this class.

The lane masks of the registers are the combination of all lane masks of their subregisters. Returns 1 if there are no subregisters.

Definition at line 233 of file MCRegisterInfo.h.

References LaneMask.

Referenced by llvm::ScheduleDAGInstrs::getLaneMaskForMO(), and llvm::MachineRegisterInfo::getMaxLaneMaskForVReg().

◆ getNumRegs()

unsigned llvm::MCRegisterClass::getNumRegs ( ) const

inline

getNumRegs - Return the number of registers in this class.

Definition at line 94 of file MCRegisterInfo.h.

References RegsSize.

Referenced by llvm::RegisterClassInfo::computePSetLimit(), constrainRegClass(), llvm::R600InstrInfo::getIndirectIndexBegin(), llvm::M68kRegisterInfo::getMaximalPhysRegClass(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), getRegister(), llvm::M68kRegisterInfo::getRegisterOrder(), and llvm::SystemZRegisterInfo::shouldCoalesce().

◆ getRegister()

MCRegister llvm::MCRegisterClass::getRegister ( unsigned i ) const

inline

getRegister - Return the specified register in the class.

Definition at line 98 of file MCRegisterInfo.h.

References assert(), begin(), and getNumRegs().

Referenced by llvm::AMDGPUDisassembler::convertTrue16OpSel(), llvm::R600InstrInfo::getIndirectIndexBegin(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), getRegForPrinting(), llvm::MipsTargetLowering::getRegisterByName(), llvm::M68kRegisterInfo::getRegisterOrder(), llvm::AMDGPU::getVGPRWithMSBs(), and llvm::tryFoldSPUpdateIntoPushPop().

◆ getRegisters()

ArrayRef< MCPhysReg > llvm::MCRegisterClass::getRegisters ( ) const

inline

Definition at line 103 of file MCRegisterInfo.h.

References llvm::ArrayRef(), begin(), and RegsSize.

Referenced by llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR(), llvm::RegAllocBase::getErrorAssignment(), llvm::SIRegisterInfo::getNumUsedPhysRegs(), and llvm::TargetRegisterInfo::getRawAllocationOrder().

◆ getSizeInBits()

unsigned llvm::MCRegisterClass::getSizeInBits ( ) const

inline

Return the size of the physical register in bits if we are able to determine it.

This always returns zero for registers of targets that use HW modes, as we need more information to determine the size of registers in such cases. Use TargetRegisterInfo to cover them.

Definition at line 128 of file MCRegisterInfo.h.

References RegSizeInBits.

Referenced by CheckVGPROverflow().

◆ getSubClassMask()

const uint32_t * llvm::MCRegisterClass::getSubClassMask ( ) const

inline

Returns a bit vector of subclasses, including this one.

The vector is indexed by class IDs.

To use it, consider the returned array as a chunk of memory that contains an array of bits of size NumRegClasses. Each 32-bit chunk contains a bitset of the ID of the subclasses in big-endian style. I.e., the representation of the memory from left to right at the bit level looks like: [31 30 ... 1 0] [ 63 62 ... 33 32] ... [ XXX NumRegClasses NumRegClasses - 1 ... ] Where the number represents the class ID and XXX bits that should be ignored.

See the implementation of hasSubClassEq for an example of how it can be used.

Definition at line 187 of file MCRegisterInfo.h.

References SubClassMaskOff.

Referenced by llvm::TargetRegisterInfo::getAllocatableClass(), and hasSubClassEq().

◆ getSuperRegClassMaskAt()

const uint32_t * llvm::MCRegisterClass::getSuperRegClassMaskAt ( uint32_t Offset ) const

inline

Returns the bit mask of register classes that the sub-register index belonging to Offset projects into this class, where Offset is an entry of getSuperRegClassMaskOffsets().

Definition at line 204 of file MCRegisterInfo.h.

References llvm::Offset.

◆ getSuperRegClassMaskOffsets()

const uint32_t * llvm::MCRegisterClass::getSuperRegClassMaskOffsets ( ) const

inline

Returns the relative offsets of this class's super-register class bit masks, one per entry of getSuperRegIndices().

Identical masks are stored once and shared, so the masks of one class are not contiguous and cannot be reached by striding. Resolve an entry with getSuperRegClassMaskAt().

Definition at line 196 of file MCRegisterInfo.h.

References SuperRegMaskOffsetsOff.

◆ getSuperRegIndices()

const uint16_t * llvm::MCRegisterClass::getSuperRegIndices ( ) const

inline

Returns a 0-terminated list of sub-register indices that project some super-register class into this register class.

The list has an entry for each Idx such that:

There exists SuperRC where: For all Reg in SuperRC: this->contains(Reg:Idx)

Definition at line 216 of file MCRegisterInfo.h.

References SuperRegIndicesOff.

◆ hasSubClass()

bool llvm::MCRegisterClass::hasSubClass ( const MCRegisterClass * RC ) const

inline

Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.

Definition at line 150 of file MCRegisterInfo.h.

References hasSubClassEq().

Referenced by foldSimpleCrossClassCopies(), getCommonMinimalPhysRegClass(), llvm::M68kRegisterInfo::getMaximalPhysRegClass(), and hasSuperClass().

◆ hasSubClassEq()

bool llvm::MCRegisterClass::hasSubClassEq ( const MCRegisterClass * RC ) const

inline

Returns true if RC is a sub-class of or equal to this class.

Definition at line 155 of file MCRegisterInfo.h.

References getID(), getSubClassMask(), and ID.

Referenced by llvm::MachineFunction::addLiveIn(), canFoldCopy(), llvm::SIRegisterInfo::getCompatibleSubRegClass(), hasSubClass(), hasSuperClassEq(), llvm::PPCInstrInfo::promoteInstr32To64ForElimEXTSW(), UpdateOperandRegClass(), and llvm::RegisterBank::verify().

◆ hasSuperClass()

bool llvm::MCRegisterClass::hasSuperClass ( const MCRegisterClass * RC ) const

inline

Return true if the specified MCRegisterClass is a proper super-class of this MCRegisterClass.

Definition at line 162 of file MCRegisterInfo.h.

References hasSubClass().

◆ hasSuperClassEq()

bool llvm::MCRegisterClass::hasSuperClassEq ( const MCRegisterClass * RC ) const

inline

Returns true if RC is a super-class of or equal to this class.

Definition at line 167 of file MCRegisterInfo.h.

References hasSubClassEq().

Referenced by llvm::AArch64InstrInfo::emitLdStWithAddr(), llvm::SIInstrInfo::foldMemoryOperandImpl(), llvm::PPCInstrInfo::getOperandLatency(), isFPR64(), isFRClass(), isGPR64(), isGRClass(), llvm::SIRegisterInfo::isProperlyAlignedRC(), isVKClass(), llvm::Thumb1InstrInfo::loadRegFromStackSlot(), and llvm::SystemZRegisterInfo::shouldCoalesce().

◆ isAllocatable()

bool llvm::MCRegisterClass::isAllocatable ( ) const

inline

isAllocatable - Return true if this register class may be used to create virtual registers.

Definition at line 143 of file MCRegisterInfo.h.

References Allocatable.

Referenced by llvm::MachineRegisterInfo::createVirtualRegister(), llvm::TargetRegisterInfo::getAllocatableClass(), getAllocatableSetForRC(), and llvm::MachineRegisterInfo::setRegClass().

◆ isBaseClass()

bool llvm::MCRegisterClass::isBaseClass ( ) const

inline

Return true if this register class has a defined BaseClassOrder.

Definition at line 146 of file MCRegisterInfo.h.

References BaseClass.

◆ superclasses()

ArrayRef< unsigned > llvm::MCRegisterClass::superclasses ( ) const

inline

Returns a list of super-classes.

The classes are ordered by ID which is also a topological ordering from large to small classes. The list does NOT include the current class.

Definition at line 224 of file MCRegisterInfo.h.

References llvm::ArrayRef(), SuperClassesOff, and SuperClassesSize.

Referenced by llvm::HexagonRegisterInfo::getHexagonSubRegIndex(), llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass(), llvm::PPCRegisterInfo::getLargestLegalSuperClass(), and llvm::X86RegisterInfo::getLargestLegalSuperClass().

Member Data Documentation

◆ Allocatable

const bool llvm::MCRegisterClass::Allocatable

Definition at line 53 of file MCRegisterInfo.h.

Referenced by isAllocatable().

◆ AllocationPriority

const uint8_t llvm::MCRegisterClass::AllocationPriority

Classes with a higher priority value are assigned first by register allocators using a greedy heuristic.

The value is in the range [0,31].

Definition at line 64 of file MCRegisterInfo.h.

◆ BaseClass

const bool llvm::MCRegisterClass::BaseClass

Definition at line 54 of file MCRegisterInfo.h.

Referenced by isBaseClass().

◆ CopyCost

const uint8_t llvm::MCRegisterClass::CopyCost

Definition at line 52 of file MCRegisterInfo.h.

Referenced by expensiveOrImpossibleToCopy(), and getCopyCost().

◆ CoveredBySubRegs

const bool llvm::MCRegisterClass::CoveredBySubRegs

Whether a combination of subregisters can cover every register in the class.

See also the CoveredBySubRegs description in Target.td.

Definition at line 76 of file MCRegisterInfo.h.

Referenced by llvm::DeadLaneDetector::transferUsedLanes().

◆ GlobalPriority

const bool llvm::MCRegisterClass::GlobalPriority

Definition at line 67 of file MCRegisterInfo.h.

◆ HasDisjunctSubRegs

const bool llvm::MCRegisterClass::HasDisjunctSubRegs

Whether the class supports two (or more) disjunct subregister indices.

Definition at line 73 of file MCRegisterInfo.h.

Referenced by llvm::ScheduleDAGInstrs::getLaneMaskForMO(), and llvm::MachineRegisterInfo::shouldTrackSubRegLiveness().

◆ ID

const uint16_t llvm::MCRegisterClass::ID

Definition at line 51 of file MCRegisterInfo.h.

Referenced by getID(), and hasSubClassEq().

◆ LaneMask

const LaneBitmask llvm::MCRegisterClass::LaneMask

Definition at line 61 of file MCRegisterInfo.h.

Referenced by getLaneMask(), llvm::rdf::PhysicalRegisterInfo::mapTo(), llvm::rdf::AggressiveCopyPropagation::run(), llvm::rdf::CopyPropagation::run(), and llvm::DeadLaneDetector::transferUsedLanes().

◆ NameIdx

const uint32_t llvm::MCRegisterClass::NameIdx

Definition at line 45 of file MCRegisterInfo.h.

◆ RegSetBegin

const MCPhysReg llvm::MCRegisterClass::RegSetBegin

Register denoted by first bit in RegSet.

Definition at line 49 of file MCRegisterInfo.h.

Referenced by contains().

◆ RegSetOff

const uint32_t llvm::MCRegisterClass::RegSetOff

Relative offset to uint8_t array.

Definition at line 44 of file MCRegisterInfo.h.

Referenced by contains().

◆ RegSetSize

const uint16_t llvm::MCRegisterClass::RegSetSize

Definition at line 50 of file MCRegisterInfo.h.

Referenced by contains().

◆ RegSizeInBits

const uint32_t llvm::MCRegisterClass::RegSizeInBits

Definition at line 46 of file MCRegisterInfo.h.

Referenced by getSizeInBits().

◆ RegsOff

const uint32_t llvm::MCRegisterClass::RegsOff

Relative offset to MCPhysReg array.

Definition at line 43 of file MCRegisterInfo.h.

Referenced by begin().

◆ RegsSize

const uint16_t llvm::MCRegisterClass::RegsSize

Definition at line 47 of file MCRegisterInfo.h.

Referenced by end(), getNumRegs(), and getRegisters().

◆ SpillStackID

const uint8_t llvm::MCRegisterClass::SpillStackID

Definition at line 71 of file MCRegisterInfo.h.

Referenced by llvm::TargetRegisterInfo::getSpillStackID().

◆ SubClassMaskOff

const uint32_t llvm::MCRegisterClass::SubClassMaskOff

Relative offset to uint32_t array.

Definition at line 56 of file MCRegisterInfo.h.

Referenced by getSubClassMask().

◆ SuperClassesOff

const uint32_t llvm::MCRegisterClass::SuperClassesOff

Relative offset to unsigned array.

Definition at line 77 of file MCRegisterInfo.h.

Referenced by superclasses().

◆ SuperClassesSize

const uint16_t llvm::MCRegisterClass::SuperClassesSize

Definition at line 78 of file MCRegisterInfo.h.

Referenced by superclasses().

◆ SuperRegIndicesOff

const uint32_t llvm::MCRegisterClass::SuperRegIndicesOff

Relative offset to MCPhysReg array.

Definition at line 60 of file MCRegisterInfo.h.

Referenced by getSuperRegIndices().

◆ SuperRegMaskOffsetsOff

const uint32_t llvm::MCRegisterClass::SuperRegMaskOffsetsOff

Relative offset to a uint32_t array holding, for each entry of getSuperRegIndices(), the relative offset of that entry's bit mask.

Definition at line 59 of file MCRegisterInfo.h.

Referenced by getSuperRegClassMaskOffsets().

◆ TSFlags

const uint8_t llvm::MCRegisterClass::TSFlags

Configurable target specific flags.

Definition at line 70 of file MCRegisterInfo.h.

Referenced by llvm::RISCVInstrInfo::copyPhysRegVector(), llvm::RISCVRegisterInfo::findVRegWithEncoding(), llvm::SIRegisterInfo::getRegClassAlignmentNumBits(), llvm::SIRegisterInfo::getSubRegAlignmentNumBits(), llvm::SIRegisterInfo::hasAGPRs(), llvm::SIRegisterInfo::hasSGPRs(), llvm::SIRegisterInfo::hasVGPRs(), llvm::RISCVRegisterInfo::isRVVRegClass(), isTupleInsertInstr(), llvm::RISCVInstrInfo::isVRegCopy(), llvm::RISCVRegisterInfo::isVRNRegClass(), and llvm::RISCVRegisterInfo::isVRRegClass().

The documentation for this class was generated from the following file:

include/llvm/MC/MCRegisterInfo.h

Public Types

Public Member Functions

Public Attributes

Detailed Description

Member Typedef Documentation

◆ const_iterator

◆ iterator

Member Function Documentation

◆ begin()

◆ contains() [1/2]

◆ contains() [2/2]

◆ end()

◆ expensiveOrImpossibleToCopy()

◆ getCopyCost()

◆ getID()

◆ getLaneMask()

◆ getNumRegs()

◆ getRegister()

◆ getRegisters()

◆ getSizeInBits()

◆ getSubClassMask()

◆ getSuperRegClassMaskAt()

◆ getSuperRegClassMaskOffsets()

◆ getSuperRegIndices()

◆ hasSubClass()

◆ hasSubClassEq()

◆ hasSuperClass()

◆ hasSuperClassEq()

◆ isAllocatable()

◆ isBaseClass()

◆ superclasses()

Member Data Documentation

◆ Allocatable

◆ AllocationPriority

◆ BaseClass

◆ CopyCost

◆ CoveredBySubRegs

◆ GlobalPriority

◆ HasDisjunctSubRegs

◆ ID

◆ LaneMask

◆ NameIdx

◆ RegSetBegin

◆ RegSetOff

◆ RegSetSize

◆ RegSizeInBits

◆ RegsOff

◆ RegsSize

◆ SpillStackID

◆ SubClassMaskOff

◆ SuperClassesOff

◆ SuperClassesSize

◆ SuperRegIndicesOff

◆ SuperRegMaskOffsetsOff

◆ TSFlags