LLVM  15.0.0git
MachineOperand.cpp
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1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/FoldingSet.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
23 #include "llvm/Config/llvm-config.h"
24 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/Instructions.h"
28 #include "llvm/MC/MCDwarf.h"
31 
32 using namespace llvm;
33 
34 static cl::opt<int>
35  PrintRegMaskNumRegs("print-regmask-num-regs",
36  cl::desc("Number of registers to limit to when "
37  "printing regmask operands in IR dumps. "
38  "unlimited = -1"),
39  cl::init(32), cl::Hidden);
40 
42  if (const MachineInstr *MI = MO.getParent())
43  if (const MachineBasicBlock *MBB = MI->getParent())
44  if (const MachineFunction *MF = MBB->getParent())
45  return MF;
46  return nullptr;
47 }
49  return const_cast<MachineFunction *>(
50  getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
51 }
52 
54  if (getReg() == Reg)
55  return; // No change.
56 
57  // Clear the IsRenamable bit to keep it conservatively correct.
58  IsRenamable = false;
59 
60  // Otherwise, we have to change the register. If this operand is embedded
61  // into a machine function, we need to update the old and new register's
62  // use/def lists.
63  if (MachineFunction *MF = getMFIfAvailable(*this)) {
64  MachineRegisterInfo &MRI = MF->getRegInfo();
66  SmallContents.RegNo = Reg;
68  return;
69  }
70 
71  // Otherwise, just change the register, no problem. :)
72  SmallContents.RegNo = Reg;
73 }
74 
76  const TargetRegisterInfo &TRI) {
77  assert(Reg.isVirtual());
78  if (SubIdx && getSubReg())
79  SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
80  setReg(Reg);
81  if (SubIdx)
82  setSubReg(SubIdx);
83 }
84 
87  if (getSubReg()) {
89  // Note that getSubReg() may return 0 if the sub-register doesn't exist.
90  // That won't happen in legal code.
91  setSubReg(0);
92  if (isDef())
93  setIsUndef(false);
94  }
95  setReg(Reg);
96 }
97 
98 /// Change a def to a use, or a use to a def.
99 void MachineOperand::setIsDef(bool Val) {
100  assert(isReg() && "Wrong MachineOperand accessor");
101  assert((!Val || !isDebug()) && "Marking a debug operation as def");
102  if (IsDef == Val)
103  return;
104  assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
105  // MRI may keep uses and defs in different list positions.
106  if (MachineFunction *MF = getMFIfAvailable(*this)) {
107  MachineRegisterInfo &MRI = MF->getRegInfo();
109  IsDef = Val;
111  return;
112  }
113  IsDef = Val;
114 }
115 
117  assert(isReg() && "Wrong MachineOperand accessor");
119  "isRenamable should only be checked on physical registers");
120  if (!IsRenamable)
121  return false;
122 
123  const MachineInstr *MI = getParent();
124  if (!MI)
125  return true;
126 
127  if (isDef())
128  return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
129 
130  assert(isUse() && "Reg is not def or use");
131  return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
132 }
133 
135  assert(isReg() && "Wrong MachineOperand accessor");
137  "setIsRenamable should only be called on physical registers");
138  IsRenamable = Val;
139 }
140 
141 // If this operand is currently a register operand, and if this is in a
142 // function, deregister the operand from the register's use/def list.
143 void MachineOperand::removeRegFromUses() {
144  if (!isReg() || !isOnRegUseList())
145  return;
146 
147  if (MachineFunction *MF = getMFIfAvailable(*this))
148  MF->getRegInfo().removeRegOperandFromUseList(this);
149 }
150 
151 /// ChangeToImmediate - Replace this operand with a new immediate operand of
152 /// the specified value. If an operand is known to be an immediate already,
153 /// the setImm method should be used.
154 void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
155  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
156 
157  removeRegFromUses();
158 
159  OpKind = MO_Immediate;
160  Contents.ImmVal = ImmVal;
161  setTargetFlags(TargetFlags);
162 }
163 
165  unsigned TargetFlags) {
166  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
167 
168  removeRegFromUses();
169 
170  OpKind = MO_FPImmediate;
171  Contents.CFP = FPImm;
172  setTargetFlags(TargetFlags);
173 }
174 
175 void MachineOperand::ChangeToES(const char *SymName,
176  unsigned TargetFlags) {
177  assert((!isReg() || !isTied()) &&
178  "Cannot change a tied operand into an external symbol");
179 
180  removeRegFromUses();
181 
182  OpKind = MO_ExternalSymbol;
183  Contents.OffsetedInfo.Val.SymbolName = SymName;
184  setOffset(0); // Offset is always 0.
185  setTargetFlags(TargetFlags);
186 }
187 
188 void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
189  unsigned TargetFlags) {
190  assert((!isReg() || !isTied()) &&
191  "Cannot change a tied operand into a global address");
192 
193  removeRegFromUses();
194 
195  OpKind = MO_GlobalAddress;
196  Contents.OffsetedInfo.Val.GV = GV;
197  setOffset(Offset);
198  setTargetFlags(TargetFlags);
199 }
200 
201 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
202  assert((!isReg() || !isTied()) &&
203  "Cannot change a tied operand into an MCSymbol");
204 
205  removeRegFromUses();
206 
207  OpKind = MO_MCSymbol;
208  Contents.Sym = Sym;
209  setTargetFlags(TargetFlags);
210 }
211 
212 void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
213  assert((!isReg() || !isTied()) &&
214  "Cannot change a tied operand into a FrameIndex");
215 
216  removeRegFromUses();
217 
218  OpKind = MO_FrameIndex;
219  setIndex(Idx);
220  setTargetFlags(TargetFlags);
221 }
222 
223 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
224  unsigned TargetFlags) {
225  assert((!isReg() || !isTied()) &&
226  "Cannot change a tied operand into a FrameIndex");
227 
228  removeRegFromUses();
229 
230  OpKind = MO_TargetIndex;
231  setIndex(Idx);
232  setOffset(Offset);
233  setTargetFlags(TargetFlags);
234 }
235 
236 /// ChangeToRegister - Replace this operand with a new register operand of
237 /// the specified value. If an operand is known to be an register already,
238 /// the setReg method should be used.
239 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
240  bool isKill, bool isDead, bool isUndef,
241  bool isDebug) {
242  MachineRegisterInfo *RegInfo = nullptr;
243  if (MachineFunction *MF = getMFIfAvailable(*this))
244  RegInfo = &MF->getRegInfo();
245  // If this operand is already a register operand, remove it from the
246  // register's use/def lists.
247  bool WasReg = isReg();
248  if (RegInfo && WasReg)
249  RegInfo->removeRegOperandFromUseList(this);
250 
251  // Ensure debug instructions set debug flag on register uses.
252  const MachineInstr *MI = getParent();
253  if (!isDef && MI && MI->isDebugInstr())
254  isDebug = true;
255 
256  // Change this to a register and set the reg#.
257  assert(!(isDead && !isDef) && "Dead flag on non-def");
258  assert(!(isKill && isDef) && "Kill flag on def");
259  OpKind = MO_Register;
260  SmallContents.RegNo = Reg;
261  SubReg_TargetFlags = 0;
262  IsDef = isDef;
263  IsImp = isImp;
264  IsDeadOrKill = isKill | isDead;
265  IsRenamable = false;
266  IsUndef = isUndef;
267  IsInternalRead = false;
268  IsEarlyClobber = false;
269  IsDebug = isDebug;
270  // Ensure isOnRegUseList() returns false.
271  Contents.Reg.Prev = nullptr;
272  // Preserve the tie when the operand was already a register.
273  if (!WasReg)
274  TiedTo = 0;
275 
276  // If this operand is embedded in a function, add the operand to the
277  // register's use/def list.
278  if (RegInfo)
279  RegInfo->addRegOperandToUseList(this);
280 }
281 
282 /// isIdenticalTo - Return true if this operand is identical to the specified
283 /// operand. Note that this should stay in sync with the hash_value overload
284 /// below.
286  if (getType() != Other.getType() ||
287  getTargetFlags() != Other.getTargetFlags())
288  return false;
289 
290  switch (getType()) {
292  return getReg() == Other.getReg() && isDef() == Other.isDef() &&
293  getSubReg() == Other.getSubReg();
295  return getImm() == Other.getImm();
297  return getCImm() == Other.getCImm();
299  return getFPImm() == Other.getFPImm();
301  return getMBB() == Other.getMBB();
303  return getIndex() == Other.getIndex();
306  return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
308  return getIndex() == Other.getIndex();
310  return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
312  return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
313  getOffset() == Other.getOffset();
315  return getBlockAddress() == Other.getBlockAddress() &&
316  getOffset() == Other.getOffset();
319  // Shallow compare of the two RegMasks
320  const uint32_t *RegMask = getRegMask();
321  const uint32_t *OtherRegMask = Other.getRegMask();
322  if (RegMask == OtherRegMask)
323  return true;
324 
325  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
326  // Calculate the size of the RegMask
327  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
328  unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
329 
330  // Deep compare of the two RegMasks
331  return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
332  }
333  // We don't know the size of the RegMask, so we can't deep compare the two
334  // reg masks.
335  return false;
336  }
338  return getMCSymbol() == Other.getMCSymbol();
340  return getCFIIndex() == Other.getCFIIndex();
342  return getMetadata() == Other.getMetadata();
344  return getIntrinsicID() == Other.getIntrinsicID();
346  return getPredicate() == Other.getPredicate();
348  return getShuffleMask() == Other.getShuffleMask();
349  }
350  llvm_unreachable("Invalid machine operand type");
351 }
352 
353 // Note: this must stay exactly in sync with isIdenticalTo above.
355  switch (MO.getType()) {
357  // Register operands don't have target flags.
358  return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
360  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
362  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
364  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
366  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
368  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
371  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
372  MO.getOffset());
374  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
376  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
377  StringRef(MO.getSymbolName()));
379  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
380  MO.getOffset());
382  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
383  MO.getOffset());
386  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
388  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
390  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
392  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
394  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
396  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
398  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
399  }
400  llvm_unreachable("Invalid machine operand type");
401 }
402 
403 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
404 // it.
405 static void tryToGetTargetInfo(const MachineOperand &MO,
406  const TargetRegisterInfo *&TRI,
407  const TargetIntrinsicInfo *&IntrinsicInfo) {
408  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
409  TRI = MF->getSubtarget().getRegisterInfo();
410  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
411  }
412 }
413 
414 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
415  const auto *TII = MF.getSubtarget().getInstrInfo();
416  assert(TII && "expected instruction info");
417  auto Indices = TII->getSerializableTargetIndices();
418  auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
419  return I.first == Index;
420  });
421  if (Found != Indices.end())
422  return Found->second;
423  return nullptr;
424 }
425 
427  const MachineFunction *MF = getMFIfAvailable(*this);
428  return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
429 }
430 
431 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
433  for (const auto &I : Flags) {
434  if (I.first == TF) {
435  return I.second;
436  }
437  }
438  return nullptr;
439 }
440 
441 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
442  const TargetRegisterInfo *TRI) {
443  if (!TRI) {
444  OS << "%dwarfreg." << DwarfReg;
445  return;
446  }
447 
448  if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
449  OS << printReg(*Reg, TRI);
450  else
451  OS << "<badreg>";
452 }
453 
455  ModuleSlotTracker &MST) {
456  OS << "%ir-block.";
457  if (BB.hasName()) {
458  printLLVMNameWithoutPrefix(OS, BB.getName());
459  return;
460  }
461  Optional<int> Slot;
462  if (const Function *F = BB.getParent()) {
463  if (F == MST.getCurrentFunction()) {
464  Slot = MST.getLocalSlot(&BB);
465  } else if (const Module *M = F->getParent()) {
466  ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
467  CustomMST.incorporateFunction(*F);
468  Slot = CustomMST.getLocalSlot(&BB);
469  }
470  }
471  if (Slot)
473  else
474  OS << "<unknown>";
475 }
476 
478  SyncScope::ID SSID,
480  switch (SSID) {
481  case SyncScope::System:
482  break;
483  default:
484  if (SSNs.empty())
486 
487  OS << "syncscope(\"";
488  printEscapedString(SSNs[SSID], OS);
489  OS << "\") ";
490  break;
491  }
492 }
493 
494 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
495  unsigned TMMOFlag) {
496  auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
497  for (const auto &I : Flags) {
498  if (I.first == TMMOFlag) {
499  return I.second;
500  }
501  }
502  return nullptr;
503 }
504 
505 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
506  const MachineFrameInfo *MFI) {
507  StringRef Name;
508  if (MFI) {
509  IsFixed = MFI->isFixedObjectIndex(FrameIndex);
510  if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
511  if (Alloca->hasName())
512  Name = Alloca->getName();
513  if (IsFixed)
515  }
517 }
518 
520  const TargetRegisterInfo *TRI) {
521  OS << "%subreg.";
522  if (TRI)
523  OS << TRI->getSubRegIndexName(Index);
524  else
525  OS << Index;
526 }
527 
529  const MachineOperand &Op) {
530  if (!Op.getTargetFlags())
531  return;
532  const MachineFunction *MF = getMFIfAvailable(Op);
533  if (!MF)
534  return;
535 
536  const auto *TII = MF->getSubtarget().getInstrInfo();
537  assert(TII && "expected instruction info");
538  auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
539  OS << "target-flags(";
540  const bool HasDirectFlags = Flags.first;
541  const bool HasBitmaskFlags = Flags.second;
542  if (!HasDirectFlags && !HasBitmaskFlags) {
543  OS << "<unknown>) ";
544  return;
545  }
546  if (HasDirectFlags) {
547  if (const auto *Name = getTargetFlagName(TII, Flags.first))
548  OS << Name;
549  else
550  OS << "<unknown target flag>";
551  }
552  if (!HasBitmaskFlags) {
553  OS << ") ";
554  return;
555  }
556  bool IsCommaNeeded = HasDirectFlags;
557  unsigned BitMask = Flags.second;
559  for (const auto &Mask : BitMasks) {
560  // Check if the flag's bitmask has the bits of the current mask set.
561  if ((BitMask & Mask.first) == Mask.first) {
562  if (IsCommaNeeded)
563  OS << ", ";
564  IsCommaNeeded = true;
565  OS << Mask.second;
566  // Clear the bits which were serialized from the flag's bitmask.
567  BitMask &= ~(Mask.first);
568  }
569  }
570  if (BitMask) {
571  // When the resulting flag's bitmask isn't zero, we know that we didn't
572  // serialize all of the bit flags.
573  if (IsCommaNeeded)
574  OS << ", ";
575  OS << "<unknown bitmask target flag>";
576  }
577  OS << ") ";
578 }
579 
581  OS << "<mcsymbol " << Sym << ">";
582 }
583 
585  unsigned FrameIndex,
586  bool IsFixed, StringRef Name) {
587  if (IsFixed) {
588  OS << "%fixed-stack." << FrameIndex;
589  return;
590  }
591 
592  OS << "%stack." << FrameIndex;
593  if (!Name.empty())
594  OS << '.' << Name;
595 }
596 
598  if (Offset == 0)
599  return;
600  if (Offset < 0) {
601  OS << " - " << -Offset;
602  return;
603  }
604  OS << " + " << Offset;
605 }
606 
608  if (Slot == -1)
609  OS << "<badref>";
610  else
611  OS << Slot;
612 }
613 
614 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
615  const TargetRegisterInfo *TRI) {
616  switch (CFI.getOperation()) {
618  OS << "same_value ";
619  if (MCSymbol *Label = CFI.getLabel())
620  MachineOperand::printSymbol(OS, *Label);
621  printCFIRegister(CFI.getRegister(), OS, TRI);
622  break;
624  OS << "remember_state ";
625  if (MCSymbol *Label = CFI.getLabel())
626  MachineOperand::printSymbol(OS, *Label);
627  break;
629  OS << "restore_state ";
630  if (MCSymbol *Label = CFI.getLabel())
631  MachineOperand::printSymbol(OS, *Label);
632  break;
634  OS << "offset ";
635  if (MCSymbol *Label = CFI.getLabel())
636  MachineOperand::printSymbol(OS, *Label);
637  printCFIRegister(CFI.getRegister(), OS, TRI);
638  OS << ", " << CFI.getOffset();
639  break;
641  OS << "def_cfa_register ";
642  if (MCSymbol *Label = CFI.getLabel())
643  MachineOperand::printSymbol(OS, *Label);
644  printCFIRegister(CFI.getRegister(), OS, TRI);
645  break;
647  OS << "def_cfa_offset ";
648  if (MCSymbol *Label = CFI.getLabel())
649  MachineOperand::printSymbol(OS, *Label);
650  OS << CFI.getOffset();
651  break;
653  OS << "def_cfa ";
654  if (MCSymbol *Label = CFI.getLabel())
655  MachineOperand::printSymbol(OS, *Label);
656  printCFIRegister(CFI.getRegister(), OS, TRI);
657  OS << ", " << CFI.getOffset();
658  break;
660  OS << "llvm_def_aspace_cfa ";
661  if (MCSymbol *Label = CFI.getLabel())
662  MachineOperand::printSymbol(OS, *Label);
663  printCFIRegister(CFI.getRegister(), OS, TRI);
664  OS << ", " << CFI.getOffset();
665  OS << ", " << CFI.getAddressSpace();
666  break;
668  OS << "rel_offset ";
669  if (MCSymbol *Label = CFI.getLabel())
670  MachineOperand::printSymbol(OS, *Label);
671  printCFIRegister(CFI.getRegister(), OS, TRI);
672  OS << ", " << CFI.getOffset();
673  break;
675  OS << "adjust_cfa_offset ";
676  if (MCSymbol *Label = CFI.getLabel())
677  MachineOperand::printSymbol(OS, *Label);
678  OS << CFI.getOffset();
679  break;
681  OS << "restore ";
682  if (MCSymbol *Label = CFI.getLabel())
683  MachineOperand::printSymbol(OS, *Label);
684  printCFIRegister(CFI.getRegister(), OS, TRI);
685  break;
687  OS << "escape ";
688  if (MCSymbol *Label = CFI.getLabel())
689  MachineOperand::printSymbol(OS, *Label);
690  if (!CFI.getValues().empty()) {
691  size_t e = CFI.getValues().size() - 1;
692  for (size_t i = 0; i < e; ++i)
693  OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
694  OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
695  }
696  break;
697  }
699  OS << "undefined ";
700  if (MCSymbol *Label = CFI.getLabel())
701  MachineOperand::printSymbol(OS, *Label);
702  printCFIRegister(CFI.getRegister(), OS, TRI);
703  break;
705  OS << "register ";
706  if (MCSymbol *Label = CFI.getLabel())
707  MachineOperand::printSymbol(OS, *Label);
708  printCFIRegister(CFI.getRegister(), OS, TRI);
709  OS << ", ";
710  printCFIRegister(CFI.getRegister2(), OS, TRI);
711  break;
713  OS << "window_save ";
714  if (MCSymbol *Label = CFI.getLabel())
715  MachineOperand::printSymbol(OS, *Label);
716  break;
718  OS << "negate_ra_sign_state ";
719  if (MCSymbol *Label = CFI.getLabel())
720  MachineOperand::printSymbol(OS, *Label);
721  break;
722  default:
723  // TODO: Print the other CFI Operations.
724  OS << "<unserializable cfi directive>";
725  break;
726  }
727 }
728 
730  const TargetIntrinsicInfo *IntrinsicInfo) const {
731  print(OS, LLT{}, TRI, IntrinsicInfo);
732 }
733 
734 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
735  const TargetRegisterInfo *TRI,
736  const TargetIntrinsicInfo *IntrinsicInfo) const {
737  tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
738  ModuleSlotTracker DummyMST(nullptr);
739  print(OS, DummyMST, TypeToPrint, None, /*PrintDef=*/false,
740  /*IsStandalone=*/true,
741  /*ShouldPrintRegisterTies=*/true,
742  /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
743 }
744 
746  LLT TypeToPrint, Optional<unsigned> OpIdx, bool PrintDef,
747  bool IsStandalone, bool ShouldPrintRegisterTies,
748  unsigned TiedOperandIdx,
749  const TargetRegisterInfo *TRI,
750  const TargetIntrinsicInfo *IntrinsicInfo) const {
751  printTargetFlags(OS, *this);
752  switch (getType()) {
754  Register Reg = getReg();
755  if (isImplicit())
756  OS << (isDef() ? "implicit-def " : "implicit ");
757  else if (PrintDef && isDef())
758  // Print the 'def' flag only when the operand is defined after '='.
759  OS << "def ";
760  if (isInternalRead())
761  OS << "internal ";
762  if (isDead())
763  OS << "dead ";
764  if (isKill())
765  OS << "killed ";
766  if (isUndef())
767  OS << "undef ";
768  if (isEarlyClobber())
769  OS << "early-clobber ";
771  OS << "renamable ";
772  // isDebug() is exactly true for register operands of a DBG_VALUE. So we
773  // simply infer it when parsing and do not need to print it.
774 
775  const MachineRegisterInfo *MRI = nullptr;
777  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
778  MRI = &MF->getRegInfo();
779  }
780  }
781 
782  OS << printReg(Reg, TRI, 0, MRI);
783  // Print the sub register.
784  if (unsigned SubReg = getSubReg()) {
785  if (TRI)
786  OS << '.' << TRI->getSubRegIndexName(SubReg);
787  else
788  OS << ".subreg" << SubReg;
789  }
790  // Print the register class / bank.
792  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
793  const MachineRegisterInfo &MRI = MF->getRegInfo();
794  if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
795  OS << ':';
796  OS << printRegClassOrBank(Reg, MRI, TRI);
797  }
798  }
799  }
800  // Print ties.
801  if (ShouldPrintRegisterTies && isTied() && !isDef())
802  OS << "(tied-def " << TiedOperandIdx << ")";
803  // Print types.
804  if (TypeToPrint.isValid())
805  OS << '(' << TypeToPrint << ')';
806  break;
807  }
809  const MIRFormatter *Formatter = nullptr;
810  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
811  const auto *TII = MF->getSubtarget().getInstrInfo();
812  assert(TII && "expected instruction info");
813  Formatter = TII->getMIRFormatter();
814  }
815  if (Formatter)
816  Formatter->printImm(OS, *getParent(), OpIdx, getImm());
817  else
818  OS << getImm();
819  break;
820  }
822  getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
823  break;
825  getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
826  break;
828  OS << printMBBReference(*getMBB());
829  break;
831  int FrameIndex = getIndex();
832  bool IsFixed = false;
833  const MachineFrameInfo *MFI = nullptr;
834  if (const MachineFunction *MF = getMFIfAvailable(*this))
835  MFI = &MF->getFrameInfo();
836  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
837  break;
838  }
840  OS << "%const." << getIndex();
842  break;
844  OS << "target-index(";
845  const char *Name = "<unknown>";
846  if (const MachineFunction *MF = getMFIfAvailable(*this))
847  if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
848  Name = TargetIndexName;
849  OS << Name << ')';
851  break;
852  }
855  break;
857  getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
859  break;
862  OS << '&';
863  if (Name.empty()) {
864  OS << "\"\"";
865  } else {
867  }
869  break;
870  }
872  OS << "blockaddress(";
873  getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
874  MST);
875  OS << ", ";
876  printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
877  OS << ')';
879  break;
880  }
882  OS << "<regmask";
883  if (TRI) {
884  unsigned NumRegsInMask = 0;
885  unsigned NumRegsEmitted = 0;
886  for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
887  unsigned MaskWord = i / 32;
888  unsigned MaskBit = i % 32;
889  if (getRegMask()[MaskWord] & (1 << MaskBit)) {
890  if (PrintRegMaskNumRegs < 0 ||
891  NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
892  OS << " " << printReg(i, TRI);
893  NumRegsEmitted++;
894  }
895  NumRegsInMask++;
896  }
897  }
898  if (NumRegsEmitted != NumRegsInMask)
899  OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
900  } else {
901  OS << " ...";
902  }
903  OS << ">";
904  break;
905  }
907  const uint32_t *RegMask = getRegLiveOut();
908  OS << "liveout(";
909  if (!TRI) {
910  OS << "<unknown>";
911  } else {
912  bool IsCommaNeeded = false;
913  for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
914  if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
915  if (IsCommaNeeded)
916  OS << ", ";
917  OS << printReg(Reg, TRI);
918  IsCommaNeeded = true;
919  }
920  }
921  }
922  OS << ")";
923  break;
924  }
926  getMetadata()->printAsOperand(OS, MST);
927  break;
929  printSymbol(OS, *getMCSymbol());
930  break;
932  if (const MachineFunction *MF = getMFIfAvailable(*this))
933  printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
934  else
935  OS << "<cfi directive>";
936  break;
937  }
940  if (ID < Intrinsic::num_intrinsics)
941  OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';
942  else if (IntrinsicInfo)
943  OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
944  else
945  OS << "intrinsic(" << ID << ')';
946  break;
947  }
949  auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
950  OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
951  << CmpInst::getPredicateName(Pred) << ')';
952  break;
953  }
955  OS << "shufflemask(";
957  StringRef Separator;
958  for (int Elt : Mask) {
959  if (Elt == -1)
960  OS << Separator << "undef";
961  else
962  OS << Separator << Elt;
963  Separator = ", ";
964  }
965 
966  OS << ')';
967  break;
968  }
969 }
970 
971 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
972 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
973 #endif
974 
975 //===----------------------------------------------------------------------===//
976 // MachineMemOperand Implementation
977 //===----------------------------------------------------------------------===//
978 
979 /// getAddrSpace - Return the LLVM IR address space number that this pointer
980 /// points into.
981 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
982 
983 /// isDereferenceable - Return true if V is always dereferenceable for
984 /// Offset + Size byte.
986  const DataLayout &DL) const {
987  if (!V.is<const Value *>())
988  return false;
989 
990  const Value *BasePtr = V.get<const Value *>();
991  if (BasePtr == nullptr)
992  return false;
993 
995  BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
996 }
997 
998 /// getConstantPool - Return a MachinePointerInfo record that refers to the
999 /// constant pool.
1002 }
1003 
1004 /// getFixedStack - Return a MachinePointerInfo record that refers to the
1005 /// the specified FrameIndex.
1007  int FI, int64_t Offset) {
1009 }
1010 
1013 }
1014 
1016  return MachinePointerInfo(MF.getPSVManager().getGOT());
1017 }
1018 
1020  int64_t Offset, uint8_t ID) {
1022 }
1023 
1026 }
1027 
1029  LLT type, Align a, const AAMDNodes &AAInfo,
1030  const MDNode *Ranges, SyncScope::ID SSID,
1031  AtomicOrdering Ordering,
1032  AtomicOrdering FailureOrdering)
1033  : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),
1034  AAInfo(AAInfo), Ranges(Ranges) {
1035  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1036  isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1037  "invalid pointer value");
1038  assert((isLoad() || isStore()) && "Not a load/store!");
1039 
1040  AtomicInfo.SSID = static_cast<unsigned>(SSID);
1041  assert(getSyncScopeID() == SSID && "Value truncated");
1042  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1043  assert(getSuccessOrdering() == Ordering && "Value truncated");
1044  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1045  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1046 }
1047 
1049  uint64_t s, Align a,
1050  const AAMDNodes &AAInfo,
1051  const MDNode *Ranges, SyncScope::ID SSID,
1052  AtomicOrdering Ordering,
1053  AtomicOrdering FailureOrdering)
1054  : MachineMemOperand(ptrinfo, f,
1055  s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
1056  AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1057 
1058 /// Profile - Gather unique data for the object.
1059 ///
1061  ID.AddInteger(getOffset());
1062  ID.AddInteger(getMemoryType().getUniqueRAWLLTData());
1063  ID.AddPointer(getOpaqueValue());
1064  ID.AddInteger(getFlags());
1065  ID.AddInteger(getBaseAlign().value());
1066 }
1067 
1069  // The Value and Offset may differ due to CSE. But the flags and size
1070  // should be the same.
1071  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1072  assert((MMO->getSize() == ~UINT64_C(0) || getSize() == ~UINT64_C(0) ||
1073  MMO->getSize() == getSize()) &&
1074  "Size mismatch!");
1075 
1076  if (MMO->getBaseAlign() >= getBaseAlign()) {
1077  // Update the alignment value.
1078  BaseAlign = MMO->getBaseAlign();
1079  // Also update the base and offset, because the new alignment may
1080  // not be applicable with the old ones.
1081  PtrInfo = MMO->PtrInfo;
1082  }
1083 }
1084 
1085 /// getAlign - Return the minimum known alignment in bytes of the
1086 /// actual memory reference.
1088  return commonAlignment(getBaseAlign(), getOffset());
1089 }
1090 
1093  const LLVMContext &Context,
1094  const MachineFrameInfo *MFI,
1095  const TargetInstrInfo *TII) const {
1096  OS << '(';
1097  if (isVolatile())
1098  OS << "volatile ";
1099  if (isNonTemporal())
1100  OS << "non-temporal ";
1101  if (isDereferenceable())
1102  OS << "dereferenceable ";
1103  if (isInvariant())
1104  OS << "invariant ";
1107  << "\" ";
1110  << "\" ";
1113  << "\" ";
1114 
1115  assert((isLoad() || isStore()) &&
1116  "machine memory operand must be a load or store (or both)");
1117  if (isLoad())
1118  OS << "load ";
1119  if (isStore())
1120  OS << "store ";
1121 
1122  printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1123 
1125  OS << toIRString(getSuccessOrdering()) << ' ';
1127  OS << toIRString(getFailureOrdering()) << ' ';
1128 
1129  if (getMemoryType().isValid())
1130  OS << '(' << getMemoryType() << ')';
1131  else
1132  OS << "unknown-size";
1133 
1134  if (const Value *Val = getValue()) {
1135  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1136  MIRFormatter::printIRValue(OS, *Val, MST);
1137  } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1138  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1139  assert(PVal && "Expected a pseudo source value");
1140  switch (PVal->kind()) {
1142  OS << "stack";
1143  break;
1145  OS << "got";
1146  break;
1148  OS << "jump-table";
1149  break;
1151  OS << "constant-pool";
1152  break;
1154  int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1155  bool IsFixed = true;
1156  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1157  break;
1158  }
1160  OS << "call-entry ";
1161  cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1162  OS, /*PrintType=*/false, MST);
1163  break;
1165  OS << "call-entry &";
1167  OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1168  break;
1169  default: {
1170  const MIRFormatter *Formatter = TII->getMIRFormatter();
1171  // FIXME: This is not necessarily the correct MIR serialization format for
1172  // a custom pseudo source value, but at least it allows
1173  // MIR printing to work on a target with custom pseudo source
1174  // values.
1175  OS << "custom \"";
1176  Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1177  OS << '\"';
1178  break;
1179  }
1180  }
1181  } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1182  OS << ((isLoad() && isStore()) ? " on "
1183  : isLoad() ? " from "
1184  : " into ")
1185  << "unknown-address";
1186  }
1188  if (getSize() > 0 && getAlign() != getSize())
1189  OS << ", align " << getAlign().value();
1190  if (getAlign() != getBaseAlign())
1191  OS << ", basealign " << getBaseAlign().value();
1192  auto AAInfo = getAAInfo();
1193  if (AAInfo.TBAA) {
1194  OS << ", !tbaa ";
1195  AAInfo.TBAA->printAsOperand(OS, MST);
1196  }
1197  if (AAInfo.Scope) {
1198  OS << ", !alias.scope ";
1199  AAInfo.Scope->printAsOperand(OS, MST);
1200  }
1201  if (AAInfo.NoAlias) {
1202  OS << ", !noalias ";
1203  AAInfo.NoAlias->printAsOperand(OS, MST);
1204  }
1205  if (getRanges()) {
1206  OS << ", !range ";
1207  getRanges()->printAsOperand(OS, MST);
1208  }
1209  // FIXME: Implement addrspace printing/parsing in MIR.
1210  // For now, print this even though parsing it is not available in MIR.
1211  if (unsigned AS = getAddrSpace())
1212  OS << ", addrspace " << AS;
1213 
1214  OS << ')';
1215 }
llvm::Intrinsic::getBaseName
StringRef getBaseName(ID id)
Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....
Definition: Function.cpp:874
i
i
Definition: README.txt:29
llvm::MCCFIInstruction::OpWindowSave
@ OpWindowSave
Definition: MCDwarf.h:489
llvm::MIRFormatter::printIRValue
static void printIRValue(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)
Helper functions to print IR value as MIR serialization format which will be useful for target specif...
Definition: MIRPrinter.cpp:924
printCFI
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
Definition: MachineOperand.cpp:614
llvm::MachineMemOperand::MachineMemOperand
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.
Definition: MachineOperand.cpp:1048
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:62
llvm::MachineMemOperand::isStore
bool isStore() const
Definition: MachineMemOperand.h:288
llvm::PseudoSourceValueManager::getGOT
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like).
Definition: PseudoSourceValue.cpp:112
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:52
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:494
llvm::PointerUnion::isNull
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:142
llvm::ModuleSlotTracker::getLocalSlot
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:866
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::PseudoSourceValue::GlobalValueCallEntry
@ GlobalValueCallEntry
Definition: PseudoSourceValue.h:43
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::MCCFIInstruction::OpRelOffset
@ OpRelOffset
Definition: MCDwarf.h:483
tryToGetTargetInfo
static void tryToGetTargetInfo(const MachineOperand &MO, const TargetRegisterInfo *&TRI, const TargetIntrinsicInfo *&IntrinsicInfo)
Definition: MachineOperand.cpp:405
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::MCCFIInstruction::OpDefCfaRegister
@ OpDefCfaRegister
Definition: MCDwarf.h:480
type
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1087
llvm::MachineOperand::MO_ShuffleMask
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
Definition: MachineOperand.h:70
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:572
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
Loads.h
llvm::MachineOperand::MO_RegisterLiveOut
@ MO_RegisterLiveOut
Mask of live-out registers.
Definition: MachineOperand.h:64
llvm::Function
Definition: Function.h:60
llvm::MachineMemOperand::print
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
Definition: MachineOperand.cpp:1091
llvm::MCCFIInstruction::OpOffset
@ OpOffset
Definition: MCDwarf.h:478
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
getMFIfAvailable
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
Definition: MachineOperand.cpp:41
llvm::MachinePointerInfo::getConstantPool
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
Definition: MachineOperand.cpp:1000
llvm::MachineOperand::printStackObjectReference
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Definition: MachineOperand.cpp:584
llvm::MachineOperand::printIRSlotNumber
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
Definition: MachineOperand.cpp:607
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:592
llvm::MachinePointerInfo::getUnknownStack
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
Definition: MachineOperand.cpp:1024
llvm::printLLVMNameWithoutPrefix
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:348
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:729
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:577
llvm::MachineMemOperand::isLoad
bool isLoad() const
Definition: MachineMemOperand.h:287
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:226
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:116
llvm::ModuleSlotTracker::getCurrentFunction
const Function * getCurrentFunction() const
Definition: ModuleSlotTracker.h:81
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:440
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::MachineMemOperand::MOTargetFlag2
@ MOTargetFlag2
Definition: MachineMemOperand.h:151
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:652
llvm::MachineMemOperand::getOpaqueValue
const void * getOpaqueValue() const
Definition: MachineMemOperand.h:216
llvm::HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
Definition: HexagonInstrInfo.cpp:2083
MachineJumpTableInfo.h
TargetInstrInfo.h
llvm::Metadata::printAsOperand
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4779
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineOperand::MO_CFIIndex
@ MO_CFIIndex
MCCFIInstruction index.
Definition: MachineOperand.h:67
llvm::MachineOperand::getTargetIndexName
const char * getTargetIndexName() const
getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...
Definition: MachineOperand.cpp:426
llvm::MachineFunction::getPSVManager
PseudoSourceValueManager & getPSVManager() const
Definition: MachineFunction.h:616
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
llvm::HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
Definition: HexagonInstrInfo.cpp:2064
llvm::Optional< unsigned >
llvm::LLVMContext::getSyncScopeNames
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
Definition: LLVMContext.cpp:309
llvm::MachineOperand::ChangeToTargetIndex
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
Definition: MachineOperand.cpp:223
llvm::ModuleSlotTracker::incorporateFunction
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:852
llvm::MachineMemOperand::isInvariant
bool isInvariant() const
Definition: MachineMemOperand.h:292
llvm::PseudoSourceValueManager::getStack
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function,...
Definition: PseudoSourceValue.cpp:108
llvm::MachineOperand::ChangeToFrameIndex
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
Definition: MachineOperand.cpp:212
llvm::CmpInst::getPredicateName
static StringRef getPredicateName(Predicate P)
Definition: Instructions.cpp:3937
llvm::AAMDNodes::Scope
MDNode * Scope
The tag for alias scope specification (used with noalias).
Definition: Metadata.h:675
llvm::minidump::MemoryType
MemoryType
Definition: Minidump.h:98
llvm::hash_value
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4828
llvm::MachineMemOperand::getAAInfo
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Definition: MachineMemOperand.h:257
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:609
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineOperand::dump
void dump() const
Definition: MachineOperand.cpp:972
llvm::PointerUnion::get
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:155
llvm::MachinePointerInfo::getJumpTable
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Definition: MachineOperand.cpp:1011
llvm::MachineOperand::getMCSymbol
MCSymbol * getMCSymbol() const
Definition: MachineOperand.h:582
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:51
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::PseudoSourceValue::JumpTable
@ JumpTable
Definition: PseudoSourceValue.h:40
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::PointerUnion::is
bool is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:150
llvm::lltok::equal
@ equal
Definition: LLToken.h:25
a
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
Definition: README.txt:489
llvm::MachineOperand::printSymbol
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
Definition: MachineOperand.cpp:580
isUndef
static bool isUndef(ArrayRef< int > Mask)
Definition: HexagonISelDAGToDAGHVX.cpp:909
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition: TargetIntrinsicInfo.h:29
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachinePointerInfo::Offset
int64_t Offset
Offset - This is an offset from the base Value*.
Definition: MachineMemOperand.h:44
llvm::MCCFIInstruction::OpDefCfa
@ OpDefCfa
Definition: MCDwarf.h:482
llvm::MachineOperand::printSubRegIdx
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Definition: MachineOperand.cpp:519
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:116
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition: MachineMemOperand.h:150
llvm::MCCFIInstruction::OpUndefined
@ OpUndefined
Definition: MCDwarf.h:487
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
TargetMachine.h
Constants.h
llvm::MachineMemOperand::getBaseAlign
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
Definition: MachineMemOperand.h:254
llvm::MachineOperand::ChangeToRegister
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Definition: MachineOperand.cpp:239
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:61
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:228
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
getTargetIndexName
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
Definition: MachineOperand.cpp:414
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:210
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineOperand::getRegMask
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Definition: MachineOperand.h:639
llvm::MachineOperand::setSubReg
void setSubReg(unsigned subReg)
Definition: MachineOperand.h:480
llvm::MachineOperand::MO_FrameIndex
@ MO_FrameIndex
Abstract Stack Frame Index.
Definition: MachineOperand.h:56
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MCCFIInstruction::getOffset
int getOffset() const
Definition: MCDwarf.h:657
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1015
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:154
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
IRPrintingPasses.h
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::PseudoSourceValue::FixedStack
@ FixedStack
Definition: PseudoSourceValue.h:42
llvm::MachineOperand::ChangeToMCSymbol
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
Definition: MachineOperand.cpp:201
llvm::MCCFIInstruction::getOperation
OpType getOperation() const
Definition: MCDwarf.h:635
llvm::printJumpTableEntryReference
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
Definition: MachineFunction.cpp:1373
llvm::MachineOperand::setTargetFlags
void setTargetFlags(unsigned F)
Definition: MachineOperand.h:223
llvm::SyncScope::System
@ System
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:58
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:680
printCFIRegister
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
Definition: MachineOperand.cpp:441
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:406
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(const Value *v, int64_t offset=0, uint8_t ID=0)
Definition: MachineMemOperand.h:50
llvm::MCCFIInstruction::getRegister
unsigned getRegister() const
Definition: MCDwarf.h:638
llvm::None
const NoneType None
Definition: None.h:24
isDebug
static bool isDebug()
Definition: HexagonGenInsert.cpp:83
llvm::MachineOperand::printOperandOffset
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
Definition: MachineOperand.cpp:597
llvm::MachineMemOperand::getSyncScopeID
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
Definition: MachineMemOperand.h:263
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MCCFIInstruction
Definition: MCDwarf.h:472
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:434
llvm::MCRegisterInfo::getLLVMRegNum
Optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
Definition: MCRegisterInfo.cpp:81
llvm::MachineMemOperand::Profile
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
Definition: MachineOperand.cpp:1060
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition: MachineOperand.h:655
llvm::PseudoSourceValue::ExternalSymbolCallEntry
@ ExternalSymbolCallEntry
Definition: PseudoSourceValue.h:44
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::cl::opt
Definition: CommandLine.h:1392
llvm::MachineOperand::MO_Metadata
@ MO_Metadata
Metadata reference (for debug info)
Definition: MachineOperand.h:65
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineOperand::ChangeToFPImmediate
void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
Definition: MachineOperand.cpp:164
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:394
llvm::MCCFIInstruction::OpDefCfaOffset
@ OpDefCfaOffset
Definition: MCDwarf.h:481
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:220
llvm::MachineOperand::substVirtReg
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Definition: MachineOperand.cpp:75
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::MachinePointerInfo::isDereferenceable
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
Definition: MachineOperand.cpp:985
llvm::MCCFIInstruction::OpRestore
@ OpRestore
Definition: MCDwarf.h:486
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:551
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineMemOperand::isDereferenceable
bool isDereferenceable() const
Definition: MachineMemOperand.h:291
uint64_t
s
multiplies can be turned into SHL s
Definition: README.txt:370
llvm::MCCFIInstruction::OpSameValue
@ OpSameValue
Definition: MCDwarf.h:475
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::SyncScope::ID
uint8_t ID
Definition: LLVMContext.h:47
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:384
llvm::MachineOperand::MO_Predicate
@ MO_Predicate
Generic predicate for ISel.
Definition: MachineOperand.h:69
I
#define I(x, y, z)
Definition: MD5.cpp:58
StringExtras.h
llvm::MachineOperand::MO_MCSymbol
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
Definition: MachineOperand.h:66
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:218
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition: MachineOperand.h:556
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:597
llvm::PseudoSourceValue::ConstantPool
@ ConstantPool
Definition: PseudoSourceValue.h:41
llvm::MCCFIInstruction::getRegister2
unsigned getRegister2() const
Definition: MCDwarf.h:647
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::MIRFormatter::printImm
virtual void printImm(raw_ostream &OS, const MachineInstr &MI, Optional< unsigned > OpIdx, int64_t Imm) const
Implement target specific printing for machine operand immediate value, so that we can have more mean...
Definition: MIRFormatter.h:39
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition: MachineOperand.h:435
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::MachineMemOperand::getSuccessOrdering
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
Definition: MachineMemOperand.h:270
MIRFormatter.h
llvm::MachineOperand::getShuffleMask
ArrayRef< int > getShuffleMask() const
Definition: MachineOperand.h:602
llvm::MachineOperand::MO_TargetIndex
@ MO_TargetIndex
Target-dependent index+offset operand.
Definition: MachineOperand.h:58
PrintRegMaskNumRegs
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
llvm::MachineMemOperand::getMemoryType
LLT getMemoryType() const
Return the memory type of the memory reference.
Definition: MachineMemOperand.h:232
llvm::MCCFIInstruction::OpAdjustCfaOffset
@ OpAdjustCfaOffset
Definition: MCDwarf.h:484
llvm::MachineOperand::MO_FPImmediate
@ MO_FPImmediate
Floating-point immediate operand.
Definition: MachineOperand.h:54
printFrameIndex
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
Definition: MachineOperand.cpp:505
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::MDNode
Metadata node.
Definition: Metadata.h:937
llvm::Value::printAsOperand
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:4673
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MCCFIInstruction::OpEscape
@ OpEscape
Definition: MCDwarf.h:485
llvm::CmpInst::isIntPredicate
bool isIntPredicate() const
Definition: InstrTypes.h:827
llvm::MachineOperand::MO_JumpTableIndex
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition: MachineOperand.h:59
llvm::MachineOperand::MO_CImmediate
@ MO_CImmediate
Immediate >64bit operand.
Definition: MachineOperand.h:53
llvm::printRegClassOrBank
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Definition: TargetRegisterInfo.cpp:175
llvm::MachineMemOperand::MOTargetFlag3
@ MOTargetFlag3
Definition: MachineMemOperand.h:152
llvm::MachineOperand::setIsDef
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Definition: MachineOperand.cpp:99
llvm::ArrayRef< int >
llvm::MCCFIInstruction::getAddressSpace
unsigned getAddressSpace() const
Definition: MCDwarf.h:652
llvm::MCCFIInstruction::OpRememberState
@ OpRememberState
Definition: MCDwarf.h:476
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
llvm::HexagonInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
Definition: HexagonInstrInfo.cpp:2058
llvm::MachinePointerInfo::V
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Definition: MachineMemOperand.h:41
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MCCFIInstruction::getValues
StringRef getValues() const
Definition: MCDwarf.h:665
llvm::MachineOperand::ChangeToES
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Definition: MachineOperand.cpp:175
llvm::TargetRegisterInfo::composeSubRegIndices
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Definition: TargetRegisterInfo.h:642
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:520
uint32_t
llvm::MachineOperand::setIsRenamable
void setIsRenamable(bool Val=true)
Definition: MachineOperand.cpp:134
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:55
llvm::MCCFIInstruction::OpLLVMDefAspaceCfa
@ OpLLVMDefAspaceCfa
Definition: MCDwarf.h:479
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachinePointerInfo::AddrSpace
unsigned AddrSpace
Definition: MachineMemOperand.h:46
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::FoldingSetNodeID
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:318
llvm::MachineOperand::MO_IntrinsicID
@ MO_IntrinsicID
Intrinsic ID for ISel.
Definition: MachineOperand.h:68
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:302
llvm::format
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
llvm::DataLayout::getAllocaAddrSpace
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:282
llvm::MachineOperand::setIndex
void setIndex(int Idx)
Definition: MachineOperand.h:687
llvm::TargetIntrinsicInfo::getName
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
llvm::MachinePointerInfo::getAddrSpace
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Definition: MachineOperand.cpp:981
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
FoldingSet.h
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1644
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::PseudoSourceValueManager::getJumpTable
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
Definition: PseudoSourceValue.cpp:118
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::PseudoSourceValue::GOT
@ GOT
Definition: PseudoSourceValue.h:39
llvm::StringRef::size
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
llvm::MachineMemOperand::isVolatile
bool isVolatile() const
Definition: MachineMemOperand.h:289
llvm::BlockAddress::getFunction
Function * getFunction() const
Definition: Constants.h:877
llvm::MachineOperand::printTargetFlags
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
Definition: MachineOperand.cpp:528
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:213
llvm::MachineOperand::ChangeToGA
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
Definition: MachineOperand.cpp:188
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:263
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::AAMDNodes::NoAlias
MDNode * NoAlias
The tag specifying the noalias scope.
Definition: Metadata.h:678
getTargetFlagName
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
Definition: MachineOperand.cpp:431
llvm::PseudoSourceValueManager::getFixedStack
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot.
Definition: PseudoSourceValue.cpp:123
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:345
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:235
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:60
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:566
llvm::MachineOperand::getCFIIndex
unsigned getCFIIndex() const
Definition: MachineOperand.h:587
llvm::PseudoSourceValue::Stack
@ Stack
Definition: PseudoSourceValue.h:38
llvm::MachineMemOperand::refineAlignment
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
Definition: MachineOperand.cpp:1068
llvm::MCCFIInstruction::OpRegister
@ OpRegister
Definition: MCDwarf.h:488
llvm::AAMDNodes::TBAA
MDNode * TBAA
The tag for type-based alias analysis.
Definition: Metadata.h:669
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:445
llvm::MachineInstr::IgnoreBundle
@ IgnoreBundle
Definition: MachineInstr.h:767
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:28
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:187
Instructions.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::hash_combine
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:605
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:617
TargetIntrinsicInfo.h
getTargetMMOFlagName
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
Definition: MachineOperand.cpp:494
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:53
llvm::toIRString
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
Definition: AtomicOrdering.h:81
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:285
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition: MachineOperand.h:430
llvm::MachineOperand::getRegLiveOut
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
Definition: MachineOperand.h:650
ModuleSlotTracker.h
llvm::SmallVectorImpl< StringRef >
llvm::MachineMemOperand::getFailureOrdering
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
Definition: MachineMemOperand.h:276
MachineOperand.h
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1113
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition: MachineOperand.cpp:85
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::AllocaInst
an instruction to allocate memory on the stack
Definition: Instructions.h:58
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:63
printIRBlockReference
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
Definition: MachineOperand.cpp:454
llvm::cl::desc
Definition: CommandLine.h:405
llvm::MachineMemOperand::isNonTemporal
bool isNonTemporal() const
Definition: MachineMemOperand.h:290
llvm::TargetRegisterInfo::getSubRegIndexName
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition: TargetRegisterInfo.h:368
llvm::MachineMemOperand::getRanges
const MDNode * getRanges() const
Return the range tag for the memory reference.
Definition: MachineMemOperand.h:260
llvm::MCCFIInstruction::OpNegateRAState
@ OpNegateRAState
Definition: MCDwarf.h:490
llvm::MIRFormatter::printCustomPseudoSourceValue
virtual void printCustomPseudoSourceValue(raw_ostream &OS, ModuleSlotTracker &MST, const PseudoSourceValue &PSV) const
Implement target specific printing of target custom pseudo source value.
Definition: MIRFormatter.h:56
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1019
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:219
TargetRegisterInfo.h
llvm::MCCFIInstruction::OpRestoreState
@ OpRestoreState
Definition: MCDwarf.h:477
llvm::PseudoSourceValueManager::getConstantPool
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
Definition: PseudoSourceValue.cpp:114
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::AtomicOrdering::NotAtomic
@ NotAtomic
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1236
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:285
llvm::MCCFIInstruction::getLabel
MCSymbol * getLabel() const
Definition: MCDwarf.h:636
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::isDereferenceableAndAlignedPointer
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
Definition: Loads.cpp:205
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:212
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::hash_code
An opaque object representing a hash code.
Definition: Hashing.h:73
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:57
llvm::MachineFrameInfo::getObjectAllocation
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
Definition: MachineFrameInfo.h:502
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::MachineOperand::setOffset
void setOffset(int64_t Offset)
Definition: MachineOperand.h:679
printSyncScope
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)
Definition: MachineOperand.cpp:477