LLVM 19.0.0git
MachineOperand.cpp
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1//===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file Methods common to all machine operands.
10//
11//===----------------------------------------------------------------------===//
12
16#include "llvm/Analysis/Loads.h"
24#include "llvm/Config/llvm-config.h"
25#include "llvm/IR/Constants.h"
29#include "llvm/MC/MCDwarf.h"
32#include <optional>
33
34using namespace llvm;
35
36static cl::opt<int>
37 PrintRegMaskNumRegs("print-regmask-num-regs",
38 cl::desc("Number of registers to limit to when "
39 "printing regmask operands in IR dumps. "
40 "unlimited = -1"),
41 cl::init(32), cl::Hidden);
42
44 if (const MachineInstr *MI = MO.getParent())
45 if (const MachineBasicBlock *MBB = MI->getParent())
46 if (const MachineFunction *MF = MBB->getParent())
47 return MF;
48 return nullptr;
49}
50
52 return const_cast<MachineFunction *>(
53 getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
54}
55
57 assert(getParent() && "Operand does not belong to any instruction!");
58 return getParent()->getOperandNo(this);
59}
60
62 if (getReg() == Reg)
63 return; // No change.
64
65 // Clear the IsRenamable bit to keep it conservatively correct.
66 IsRenamable = false;
67
68 // Otherwise, we have to change the register. If this operand is embedded
69 // into a machine function, we need to update the old and new register's
70 // use/def lists.
71 if (MachineFunction *MF = getMFIfAvailable(*this)) {
72 MachineRegisterInfo &MRI = MF->getRegInfo();
73 MRI.removeRegOperandFromUseList(this);
74 SmallContents.RegNo = Reg;
75 MRI.addRegOperandToUseList(this);
76 return;
77 }
78
79 // Otherwise, just change the register, no problem. :)
80 SmallContents.RegNo = Reg;
81}
82
83void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
84 const TargetRegisterInfo &TRI) {
85 assert(Reg.isVirtual());
86 if (SubIdx && getSubReg())
87 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
88 setReg(Reg);
89 if (SubIdx)
90 setSubReg(SubIdx);
91}
92
95 if (getSubReg()) {
96 Reg = TRI.getSubReg(Reg, getSubReg());
97 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
98 // That won't happen in legal code.
99 setSubReg(0);
100 if (isDef())
101 setIsUndef(false);
102 }
103 setReg(Reg);
104}
105
106/// Change a def to a use, or a use to a def.
108 assert(isReg() && "Wrong MachineOperand accessor");
109 assert((!Val || !isDebug()) && "Marking a debug operation as def");
110 if (IsDef == Val)
111 return;
112 assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
113 // MRI may keep uses and defs in different list positions.
114 if (MachineFunction *MF = getMFIfAvailable(*this)) {
115 MachineRegisterInfo &MRI = MF->getRegInfo();
116 MRI.removeRegOperandFromUseList(this);
117 IsDef = Val;
118 MRI.addRegOperandToUseList(this);
119 return;
120 }
121 IsDef = Val;
122}
123
125 assert(isReg() && "Wrong MachineOperand accessor");
126 assert(getReg().isPhysical() &&
127 "isRenamable should only be checked on physical registers");
128 if (!IsRenamable)
129 return false;
130
131 const MachineInstr *MI = getParent();
132 if (!MI)
133 return true;
134
135 if (isDef())
136 return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
137
138 assert(isUse() && "Reg is not def or use");
139 return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
140}
141
143 assert(isReg() && "Wrong MachineOperand accessor");
144 assert(getReg().isPhysical() &&
145 "setIsRenamable should only be called on physical registers");
146 IsRenamable = Val;
147}
148
149// If this operand is currently a register operand, and if this is in a
150// function, deregister the operand from the register's use/def list.
151void MachineOperand::removeRegFromUses() {
152 if (!isReg() || !isOnRegUseList())
153 return;
154
155 if (MachineFunction *MF = getMFIfAvailable(*this))
156 MF->getRegInfo().removeRegOperandFromUseList(this);
157}
158
159/// ChangeToImmediate - Replace this operand with a new immediate operand of
160/// the specified value. If an operand is known to be an immediate already,
161/// the setImm method should be used.
162void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
163 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
164
165 removeRegFromUses();
166
167 OpKind = MO_Immediate;
168 Contents.ImmVal = ImmVal;
169 setTargetFlags(TargetFlags);
170}
171
173 unsigned TargetFlags) {
174 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
175
176 removeRegFromUses();
177
178 OpKind = MO_FPImmediate;
179 Contents.CFP = FPImm;
180 setTargetFlags(TargetFlags);
181}
182
183void MachineOperand::ChangeToES(const char *SymName,
184 unsigned TargetFlags) {
185 assert((!isReg() || !isTied()) &&
186 "Cannot change a tied operand into an external symbol");
187
188 removeRegFromUses();
189
190 OpKind = MO_ExternalSymbol;
191 Contents.OffsetedInfo.Val.SymbolName = SymName;
192 setOffset(0); // Offset is always 0.
193 setTargetFlags(TargetFlags);
194}
195
197 unsigned TargetFlags) {
198 assert((!isReg() || !isTied()) &&
199 "Cannot change a tied operand into a global address");
200
201 removeRegFromUses();
202
203 OpKind = MO_GlobalAddress;
204 Contents.OffsetedInfo.Val.GV = GV;
206 setTargetFlags(TargetFlags);
207}
208
210 unsigned TargetFlags) {
211 assert((!isReg() || !isTied()) &&
212 "Cannot change a tied operand into a block address");
213
214 removeRegFromUses();
215
216 OpKind = MO_BlockAddress;
217 Contents.OffsetedInfo.Val.BA = BA;
219 setTargetFlags(TargetFlags);
220}
221
222void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
223 assert((!isReg() || !isTied()) &&
224 "Cannot change a tied operand into an MCSymbol");
225
226 removeRegFromUses();
227
228 OpKind = MO_MCSymbol;
229 Contents.Sym = Sym;
230 setTargetFlags(TargetFlags);
231}
232
233void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
234 assert((!isReg() || !isTied()) &&
235 "Cannot change a tied operand into a FrameIndex");
236
237 removeRegFromUses();
238
239 OpKind = MO_FrameIndex;
240 setIndex(Idx);
241 setTargetFlags(TargetFlags);
242}
243
245 unsigned TargetFlags) {
246 assert((!isReg() || !isTied()) &&
247 "Cannot change a tied operand into a FrameIndex");
248
249 removeRegFromUses();
250
251 OpKind = MO_TargetIndex;
252 setIndex(Idx);
254 setTargetFlags(TargetFlags);
255}
256
257void MachineOperand::ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx,
258 unsigned TargetFlags) {
259 assert((!isReg() || !isTied()) &&
260 "Cannot change a tied operand into a DbgInstrRef");
261
262 removeRegFromUses();
263
264 OpKind = MO_DbgInstrRef;
265 setInstrRefInstrIndex(InstrIdx);
266 setInstrRefOpIndex(OpIdx);
267 setTargetFlags(TargetFlags);
268}
269
270/// ChangeToRegister - Replace this operand with a new register operand of
271/// the specified value. If an operand is known to be an register already,
272/// the setReg method should be used.
273void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
274 bool isKill, bool isDead, bool isUndef,
275 bool isDebug) {
276 MachineRegisterInfo *RegInfo = nullptr;
277 if (MachineFunction *MF = getMFIfAvailable(*this))
278 RegInfo = &MF->getRegInfo();
279 // If this operand is already a register operand, remove it from the
280 // register's use/def lists.
281 bool WasReg = isReg();
282 if (RegInfo && WasReg)
283 RegInfo->removeRegOperandFromUseList(this);
284
285 // Ensure debug instructions set debug flag on register uses.
286 const MachineInstr *MI = getParent();
287 if (!isDef && MI && MI->isDebugInstr())
288 isDebug = true;
289
290 // Change this to a register and set the reg#.
291 assert(!(isDead && !isDef) && "Dead flag on non-def");
292 assert(!(isKill && isDef) && "Kill flag on def");
293 OpKind = MO_Register;
294 SmallContents.RegNo = Reg;
295 SubReg_TargetFlags = 0;
296 IsDef = isDef;
297 IsImp = isImp;
298 IsDeadOrKill = isKill | isDead;
299 IsRenamable = false;
300 IsUndef = isUndef;
301 IsInternalRead = false;
302 IsEarlyClobber = false;
303 IsDebug = isDebug;
304 // Ensure isOnRegUseList() returns false.
305 Contents.Reg.Prev = nullptr;
306 // Preserve the tie when the operand was already a register.
307 if (!WasReg)
308 TiedTo = 0;
309
310 // If this operand is embedded in a function, add the operand to the
311 // register's use/def list.
312 if (RegInfo)
313 RegInfo->addRegOperandToUseList(this);
314}
315
316/// isIdenticalTo - Return true if this operand is identical to the specified
317/// operand. Note that this should stay in sync with the hash_value overload
318/// below.
320 if (getType() != Other.getType() ||
321 getTargetFlags() != Other.getTargetFlags())
322 return false;
323
324 switch (getType()) {
326 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
327 getSubReg() == Other.getSubReg();
329 return getImm() == Other.getImm();
331 return getCImm() == Other.getCImm();
333 return getFPImm() == Other.getFPImm();
335 return getMBB() == Other.getMBB();
337 return getIndex() == Other.getIndex();
340 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
342 return getIndex() == Other.getIndex();
344 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
346 return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
347 getOffset() == Other.getOffset();
349 return getBlockAddress() == Other.getBlockAddress() &&
350 getOffset() == Other.getOffset();
353 // Shallow compare of the two RegMasks
354 const uint32_t *RegMask = getRegMask();
355 const uint32_t *OtherRegMask = Other.getRegMask();
356 if (RegMask == OtherRegMask)
357 return true;
358
359 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
360 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
361 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
362 // Deep compare of the two RegMasks
363 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
364 }
365 // We don't know the size of the RegMask, so we can't deep compare the two
366 // reg masks.
367 return false;
368 }
370 return getMCSymbol() == Other.getMCSymbol();
372 return getInstrRefInstrIndex() == Other.getInstrRefInstrIndex() &&
373 getInstrRefOpIndex() == Other.getInstrRefOpIndex();
375 return getCFIIndex() == Other.getCFIIndex();
377 return getMetadata() == Other.getMetadata();
379 return getIntrinsicID() == Other.getIntrinsicID();
381 return getPredicate() == Other.getPredicate();
383 return getShuffleMask() == Other.getShuffleMask();
384 }
385 llvm_unreachable("Invalid machine operand type");
386}
387
388// Note: this must stay exactly in sync with isIdenticalTo above.
390 switch (MO.getType()) {
392 // Register operands don't have target flags.
393 return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
395 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
397 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
399 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
401 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
403 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
406 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
407 MO.getOffset());
409 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
411 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
414 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
415 MO.getOffset());
417 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
418 MO.getOffset());
421 if (const MachineFunction *MF = getMFIfAvailable(MO)) {
422 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
423 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
424 const uint32_t *RegMask = MO.getRegMask();
425 std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize);
426 return hash_combine(MO.getType(), MO.getTargetFlags(),
427 stable_hash_combine_array(RegMaskHashes.data(),
428 RegMaskHashes.size()));
429 }
430
431 assert(0 && "MachineOperand not associated with any MachineFunction");
432 return hash_combine(MO.getType(), MO.getTargetFlags());
433 }
435 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
437 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
439 return hash_combine(MO.getType(), MO.getTargetFlags(),
442 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
444 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
446 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
448 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
449 }
450 llvm_unreachable("Invalid machine operand type");
451}
452
453// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
454// it.
455static void tryToGetTargetInfo(const MachineOperand &MO,
456 const TargetRegisterInfo *&TRI,
457 const TargetIntrinsicInfo *&IntrinsicInfo) {
458 if (const MachineFunction *MF = getMFIfAvailable(MO)) {
459 TRI = MF->getSubtarget().getRegisterInfo();
460 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
461 }
462}
463
464static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
465 const auto *TII = MF.getSubtarget().getInstrInfo();
466 assert(TII && "expected instruction info");
467 auto Indices = TII->getSerializableTargetIndices();
468 auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
469 return I.first == Index;
470 });
471 if (Found != Indices.end())
472 return Found->second;
473 return nullptr;
474}
475
477 const MachineFunction *MF = getMFIfAvailable(*this);
478 return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
479}
480
481static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
483 for (const auto &I : Flags) {
484 if (I.first == TF) {
485 return I.second;
486 }
487 }
488 return nullptr;
489}
490
491static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
492 const TargetRegisterInfo *TRI) {
493 if (!TRI) {
494 OS << "%dwarfreg." << DwarfReg;
495 return;
496 }
497
498 if (std::optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
499 OS << printReg(*Reg, TRI);
500 else
501 OS << "<badreg>";
502}
503
505 ModuleSlotTracker &MST) {
506 OS << "%ir-block.";
507 if (BB.hasName()) {
509 return;
510 }
511 std::optional<int> Slot;
512 if (const Function *F = BB.getParent()) {
513 if (F == MST.getCurrentFunction()) {
514 Slot = MST.getLocalSlot(&BB);
515 } else if (const Module *M = F->getParent()) {
516 ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
517 CustomMST.incorporateFunction(*F);
518 Slot = CustomMST.getLocalSlot(&BB);
519 }
520 }
521 if (Slot)
523 else
524 OS << "<unknown>";
525}
526
527static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
528 SyncScope::ID SSID,
530 switch (SSID) {
532 break;
533 default:
534 if (SSNs.empty())
536
537 OS << "syncscope(\"";
538 printEscapedString(SSNs[SSID], OS);
539 OS << "\") ";
540 break;
541 }
542}
543
544static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
545 unsigned TMMOFlag) {
546 auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
547 for (const auto &I : Flags) {
548 if (I.first == TMMOFlag) {
549 return I.second;
550 }
551 }
552 return nullptr;
553}
554
555static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
556 const MachineFrameInfo *MFI) {
558 if (MFI) {
559 IsFixed = MFI->isFixedObjectIndex(FrameIndex);
560 if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
561 if (Alloca->hasName())
562 Name = Alloca->getName();
563 if (IsFixed)
564 FrameIndex -= MFI->getObjectIndexBegin();
565 }
567}
568
570 const TargetRegisterInfo *TRI) {
571 OS << "%subreg.";
572 if (TRI && Index != 0 && Index < TRI->getNumSubRegIndices())
573 OS << TRI->getSubRegIndexName(Index);
574 else
575 OS << Index;
576}
577
579 const MachineOperand &Op) {
580 if (!Op.getTargetFlags())
581 return;
583 if (!MF)
584 return;
585
586 const auto *TII = MF->getSubtarget().getInstrInfo();
587 assert(TII && "expected instruction info");
588 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
589 OS << "target-flags(";
590 const bool HasDirectFlags = Flags.first;
591 const bool HasBitmaskFlags = Flags.second;
592 if (!HasDirectFlags && !HasBitmaskFlags) {
593 OS << "<unknown>) ";
594 return;
595 }
596 if (HasDirectFlags) {
597 if (const auto *Name = getTargetFlagName(TII, Flags.first))
598 OS << Name;
599 else
600 OS << "<unknown target flag>";
601 }
602 if (!HasBitmaskFlags) {
603 OS << ") ";
604 return;
605 }
606 bool IsCommaNeeded = HasDirectFlags;
607 unsigned BitMask = Flags.second;
609 for (const auto &Mask : BitMasks) {
610 // Check if the flag's bitmask has the bits of the current mask set.
611 if ((BitMask & Mask.first) == Mask.first) {
612 if (IsCommaNeeded)
613 OS << ", ";
614 IsCommaNeeded = true;
615 OS << Mask.second;
616 // Clear the bits which were serialized from the flag's bitmask.
617 BitMask &= ~(Mask.first);
618 }
619 }
620 if (BitMask) {
621 // When the resulting flag's bitmask isn't zero, we know that we didn't
622 // serialize all of the bit flags.
623 if (IsCommaNeeded)
624 OS << ", ";
625 OS << "<unknown bitmask target flag>";
626 }
627 OS << ") ";
628}
629
631 OS << "<mcsymbol " << Sym << ">";
632}
633
635 unsigned FrameIndex,
636 bool IsFixed, StringRef Name) {
637 if (IsFixed) {
638 OS << "%fixed-stack." << FrameIndex;
639 return;
640 }
641
642 OS << "%stack." << FrameIndex;
643 if (!Name.empty())
644 OS << '.' << Name;
645}
646
648 if (Offset == 0)
649 return;
650 if (Offset < 0) {
651 OS << " - " << -Offset;
652 return;
653 }
654 OS << " + " << Offset;
655}
656
658 if (Slot == -1)
659 OS << "<badref>";
660 else
661 OS << Slot;
662}
663
664static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
665 const TargetRegisterInfo *TRI) {
666 switch (CFI.getOperation()) {
668 OS << "same_value ";
669 if (MCSymbol *Label = CFI.getLabel())
672 break;
674 OS << "remember_state ";
675 if (MCSymbol *Label = CFI.getLabel())
677 break;
679 OS << "restore_state ";
680 if (MCSymbol *Label = CFI.getLabel())
682 break;
684 OS << "offset ";
685 if (MCSymbol *Label = CFI.getLabel())
688 OS << ", " << CFI.getOffset();
689 break;
691 OS << "def_cfa_register ";
692 if (MCSymbol *Label = CFI.getLabel())
695 break;
697 OS << "def_cfa_offset ";
698 if (MCSymbol *Label = CFI.getLabel())
700 OS << CFI.getOffset();
701 break;
703 OS << "def_cfa ";
704 if (MCSymbol *Label = CFI.getLabel())
707 OS << ", " << CFI.getOffset();
708 break;
710 OS << "llvm_def_aspace_cfa ";
711 if (MCSymbol *Label = CFI.getLabel())
714 OS << ", " << CFI.getOffset();
715 OS << ", " << CFI.getAddressSpace();
716 break;
718 OS << "rel_offset ";
719 if (MCSymbol *Label = CFI.getLabel())
722 OS << ", " << CFI.getOffset();
723 break;
725 OS << "adjust_cfa_offset ";
726 if (MCSymbol *Label = CFI.getLabel())
728 OS << CFI.getOffset();
729 break;
731 OS << "restore ";
732 if (MCSymbol *Label = CFI.getLabel())
735 break;
737 OS << "escape ";
738 if (MCSymbol *Label = CFI.getLabel())
740 if (!CFI.getValues().empty()) {
741 size_t e = CFI.getValues().size() - 1;
742 for (size_t i = 0; i < e; ++i)
743 OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
744 OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
745 }
746 break;
747 }
749 OS << "undefined ";
750 if (MCSymbol *Label = CFI.getLabel())
753 break;
755 OS << "register ";
756 if (MCSymbol *Label = CFI.getLabel())
759 OS << ", ";
761 break;
763 OS << "window_save ";
764 if (MCSymbol *Label = CFI.getLabel())
766 break;
768 OS << "negate_ra_sign_state ";
769 if (MCSymbol *Label = CFI.getLabel())
771 break;
772 default:
773 // TODO: Print the other CFI Operations.
774 OS << "<unserializable cfi directive>";
775 break;
776 }
777}
778
780 const TargetIntrinsicInfo *IntrinsicInfo) const {
781 print(OS, LLT{}, TRI, IntrinsicInfo);
782}
783
785 const TargetRegisterInfo *TRI,
786 const TargetIntrinsicInfo *IntrinsicInfo) const {
787 tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
788 ModuleSlotTracker DummyMST(nullptr);
789 print(OS, DummyMST, TypeToPrint, std::nullopt, /*PrintDef=*/false,
790 /*IsStandalone=*/true,
791 /*ShouldPrintRegisterTies=*/true,
792 /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
793}
794
796 LLT TypeToPrint, std::optional<unsigned> OpIdx,
797 bool PrintDef, bool IsStandalone,
798 bool ShouldPrintRegisterTies,
799 unsigned TiedOperandIdx,
800 const TargetRegisterInfo *TRI,
801 const TargetIntrinsicInfo *IntrinsicInfo) const {
802 printTargetFlags(OS, *this);
803 switch (getType()) {
805 Register Reg = getReg();
806 if (isImplicit())
807 OS << (isDef() ? "implicit-def " : "implicit ");
808 else if (PrintDef && isDef())
809 // Print the 'def' flag only when the operand is defined after '='.
810 OS << "def ";
811 if (isInternalRead())
812 OS << "internal ";
813 if (isDead())
814 OS << "dead ";
815 if (isKill())
816 OS << "killed ";
817 if (isUndef())
818 OS << "undef ";
819 if (isEarlyClobber())
820 OS << "early-clobber ";
821 if (getReg().isPhysical() && isRenamable())
822 OS << "renamable ";
823 // isDebug() is exactly true for register operands of a DBG_VALUE. So we
824 // simply infer it when parsing and do not need to print it.
825
826 const MachineRegisterInfo *MRI = nullptr;
827 if (Reg.isVirtual()) {
828 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
829 MRI = &MF->getRegInfo();
830 }
831 }
832
833 OS << printReg(Reg, TRI, 0, MRI);
834 // Print the sub register.
835 if (unsigned SubReg = getSubReg()) {
836 if (TRI)
837 OS << '.' << TRI->getSubRegIndexName(SubReg);
838 else
839 OS << ".subreg" << SubReg;
840 }
841 // Print the register class / bank.
842 if (Reg.isVirtual()) {
843 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
844 const MachineRegisterInfo &MRI = MF->getRegInfo();
845 if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
846 OS << ':';
847 OS << printRegClassOrBank(Reg, MRI, TRI);
848 }
849 }
850 }
851 // Print ties.
852 if (ShouldPrintRegisterTies && isTied() && !isDef())
853 OS << "(tied-def " << TiedOperandIdx << ")";
854 // Print types.
855 if (TypeToPrint.isValid())
856 OS << '(' << TypeToPrint << ')';
857 break;
858 }
860 const MIRFormatter *Formatter = nullptr;
861 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
862 const auto *TII = MF->getSubtarget().getInstrInfo();
863 assert(TII && "expected instruction info");
864 Formatter = TII->getMIRFormatter();
865 }
866 if (Formatter)
867 Formatter->printImm(OS, *getParent(), OpIdx, getImm());
868 else
869 OS << getImm();
870 break;
871 }
873 getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
874 break;
876 getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
877 break;
880 break;
882 int FrameIndex = getIndex();
883 bool IsFixed = false;
884 const MachineFrameInfo *MFI = nullptr;
885 if (const MachineFunction *MF = getMFIfAvailable(*this))
886 MFI = &MF->getFrameInfo();
887 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
888 break;
889 }
891 OS << "%const." << getIndex();
893 break;
895 OS << "target-index(";
896 const char *Name = "<unknown>";
897 if (const MachineFunction *MF = getMFIfAvailable(*this))
898 if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
899 Name = TargetIndexName;
900 OS << Name << ')';
902 break;
903 }
906 break;
908 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
910 break;
913 OS << '&';
914 if (Name.empty()) {
915 OS << "\"\"";
916 } else {
918 }
920 break;
921 }
923 OS << "blockaddress(";
924 getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
925 MST);
926 OS << ", ";
927 printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
928 OS << ')';
930 break;
931 }
933 OS << "<regmask";
934 if (TRI) {
935 unsigned NumRegsInMask = 0;
936 unsigned NumRegsEmitted = 0;
937 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
938 unsigned MaskWord = i / 32;
939 unsigned MaskBit = i % 32;
940 if (getRegMask()[MaskWord] & (1 << MaskBit)) {
941 if (PrintRegMaskNumRegs < 0 ||
942 NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
943 OS << " " << printReg(i, TRI);
944 NumRegsEmitted++;
945 }
946 NumRegsInMask++;
947 }
948 }
949 if (NumRegsEmitted != NumRegsInMask)
950 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
951 } else {
952 OS << " ...";
953 }
954 OS << ">";
955 break;
956 }
958 const uint32_t *RegMask = getRegLiveOut();
959 OS << "liveout(";
960 if (!TRI) {
961 OS << "<unknown>";
962 } else {
963 bool IsCommaNeeded = false;
964 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
965 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
966 if (IsCommaNeeded)
967 OS << ", ";
968 OS << printReg(Reg, TRI);
969 IsCommaNeeded = true;
970 }
971 }
972 }
973 OS << ")";
974 break;
975 }
978 break;
981 break;
983 OS << "dbg-instr-ref(" << getInstrRefInstrIndex() << ", "
984 << getInstrRefOpIndex() << ')';
985 break;
986 }
988 if (const MachineFunction *MF = getMFIfAvailable(*this))
989 printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
990 else
991 OS << "<cfi directive>";
992 break;
993 }
996 if (ID < Intrinsic::num_intrinsics)
997 OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';
998 else if (IntrinsicInfo)
999 OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
1000 else
1001 OS << "intrinsic(" << ID << ')';
1002 break;
1003 }
1005 auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
1006 OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
1007 << Pred << ')';
1008 break;
1009 }
1011 OS << "shufflemask(";
1013 StringRef Separator;
1014 for (int Elt : Mask) {
1015 if (Elt == -1)
1016 OS << Separator << "undef";
1017 else
1018 OS << Separator << Elt;
1019 Separator = ", ";
1020 }
1021
1022 OS << ')';
1023 break;
1024 }
1025}
1026
1027#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1028LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
1029#endif
1030
1031//===----------------------------------------------------------------------===//
1032// MachineMemOperand Implementation
1033//===----------------------------------------------------------------------===//
1034
1035/// getAddrSpace - Return the LLVM IR address space number that this pointer
1036/// points into.
1038
1039/// isDereferenceable - Return true if V is always dereferenceable for
1040/// Offset + Size byte.
1042 const DataLayout &DL) const {
1043 if (!isa<const Value *>(V))
1044 return false;
1045
1046 const Value *BasePtr = cast<const Value *>(V);
1047 if (BasePtr == nullptr)
1048 return false;
1049
1051 BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
1052}
1053
1054/// getConstantPool - Return a MachinePointerInfo record that refers to the
1055/// constant pool.
1058}
1059
1060/// getFixedStack - Return a MachinePointerInfo record that refers to the
1061/// the specified FrameIndex.
1063 int FI, int64_t Offset) {
1065}
1066
1069}
1070
1073}
1074
1076 int64_t Offset, uint8_t ID) {
1078}
1079
1082}
1083
1085 LLT type, Align a, const AAMDNodes &AAInfo,
1086 const MDNode *Ranges, SyncScope::ID SSID,
1087 AtomicOrdering Ordering,
1088 AtomicOrdering FailureOrdering)
1089 : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),
1090 AAInfo(AAInfo), Ranges(Ranges) {
1091 assert((PtrInfo.V.isNull() || isa<const PseudoSourceValue *>(PtrInfo.V) ||
1092 isa<PointerType>(cast<const Value *>(PtrInfo.V)->getType())) &&
1093 "invalid pointer value");
1094 assert((isLoad() || isStore()) && "Not a load/store!");
1095
1096 AtomicInfo.SSID = static_cast<unsigned>(SSID);
1097 assert(getSyncScopeID() == SSID && "Value truncated");
1098 AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1099 assert(getSuccessOrdering() == Ordering && "Value truncated");
1100 AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1101 assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1102}
1103
1105 uint64_t s, Align a,
1106 const AAMDNodes &AAInfo,
1107 const MDNode *Ranges, SyncScope::ID SSID,
1108 AtomicOrdering Ordering,
1109 AtomicOrdering FailureOrdering)
1110 : MachineMemOperand(ptrinfo, f,
1111 s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
1112 AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1113
1115 // The Value and Offset may differ due to CSE. But the flags and size
1116 // should be the same.
1117 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1118 assert((MMO->getSize() == ~UINT64_C(0) || getSize() == ~UINT64_C(0) ||
1119 MMO->getSize() == getSize()) &&
1120 "Size mismatch!");
1121
1122 if (MMO->getBaseAlign() >= getBaseAlign()) {
1123 // Update the alignment value.
1124 BaseAlign = MMO->getBaseAlign();
1125 // Also update the base and offset, because the new alignment may
1126 // not be applicable with the old ones.
1127 PtrInfo = MMO->PtrInfo;
1128 }
1129}
1130
1131/// getAlign - Return the minimum known alignment in bytes of the
1132/// actual memory reference.
1135}
1136
1139 const LLVMContext &Context,
1140 const MachineFrameInfo *MFI,
1141 const TargetInstrInfo *TII) const {
1142 OS << '(';
1143 if (isVolatile())
1144 OS << "volatile ";
1145 if (isNonTemporal())
1146 OS << "non-temporal ";
1147 if (isDereferenceable())
1148 OS << "dereferenceable ";
1149 if (isInvariant())
1150 OS << "invariant ";
1151 if (TII) {
1154 << "\" ";
1157 << "\" ";
1160 << "\" ";
1161 } else {
1163 OS << "\"MOTargetFlag1\" ";
1165 OS << "\"MOTargetFlag2\" ";
1167 OS << "\"MOTargetFlag3\" ";
1168 }
1169
1170 assert((isLoad() || isStore()) &&
1171 "machine memory operand must be a load or store (or both)");
1172 if (isLoad())
1173 OS << "load ";
1174 if (isStore())
1175 OS << "store ";
1176
1178
1180 OS << toIRString(getSuccessOrdering()) << ' ';
1182 OS << toIRString(getFailureOrdering()) << ' ';
1183
1184 if (getMemoryType().isValid())
1185 OS << '(' << getMemoryType() << ')';
1186 else
1187 OS << "unknown-size";
1188
1189 if (const Value *Val = getValue()) {
1190 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1191 MIRFormatter::printIRValue(OS, *Val, MST);
1192 } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1193 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1194 assert(PVal && "Expected a pseudo source value");
1195 switch (PVal->kind()) {
1197 OS << "stack";
1198 break;
1200 OS << "got";
1201 break;
1203 OS << "jump-table";
1204 break;
1206 OS << "constant-pool";
1207 break;
1209 int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1210 bool IsFixed = true;
1211 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1212 break;
1213 }
1215 OS << "call-entry ";
1216 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1217 OS, /*PrintType=*/false, MST);
1218 break;
1220 OS << "call-entry &";
1222 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1223 break;
1224 default: {
1225 const MIRFormatter *Formatter = TII->getMIRFormatter();
1226 // FIXME: This is not necessarily the correct MIR serialization format for
1227 // a custom pseudo source value, but at least it allows
1228 // MIR printing to work on a target with custom pseudo source
1229 // values.
1230 OS << "custom \"";
1231 Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1232 OS << '\"';
1233 break;
1234 }
1235 }
1236 } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1237 OS << ((isLoad() && isStore()) ? " on "
1238 : isLoad() ? " from "
1239 : " into ")
1240 << "unknown-address";
1241 }
1243 if (getSize() > 0 && getAlign() != getSize())
1244 OS << ", align " << getAlign().value();
1245 if (getAlign() != getBaseAlign())
1246 OS << ", basealign " << getBaseAlign().value();
1247 auto AAInfo = getAAInfo();
1248 if (AAInfo.TBAA) {
1249 OS << ", !tbaa ";
1250 AAInfo.TBAA->printAsOperand(OS, MST);
1251 }
1252 if (AAInfo.Scope) {
1253 OS << ", !alias.scope ";
1254 AAInfo.Scope->printAsOperand(OS, MST);
1255 }
1256 if (AAInfo.NoAlias) {
1257 OS << ", !noalias ";
1258 AAInfo.NoAlias->printAsOperand(OS, MST);
1259 }
1260 if (getRanges()) {
1261 OS << ", !range ";
1262 getRanges()->printAsOperand(OS, MST);
1263 }
1264 // FIXME: Implement addrspace printing/parsing in MIR.
1265 // For now, print this even though parsing it is not available in MIR.
1266 if (unsigned AS = getAddrSpace())
1267 OS << ", addrspace " << AS;
1268
1269 OS << ')';
1270}
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:529
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
std::string Name
uint64_t Size
Symbol * Sym
Definition: ELF_riscv.cpp:479
const HexagonInstrInfo * TII
static bool isDebug()
static bool isUndef(ArrayRef< int > Mask)
IRTranslator LLVM IR MI
This file contains an interface for creating legacy passes to print out IR in various granularities.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
unsigned const TargetRegisterInfo * TRI
LLVMContext & Context
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file contains some functions that are useful when dealing with strings.
Class for arbitrary precision integers.
Definition: APInt.h:76
an instruction to allocate memory on the stack
Definition: Instructions.h:59
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
LLVM Basic Block Representation.
Definition: BasicBlock.h:60
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:205
The address of a basic block.
Definition: Constants.h:888
Function * getFunction() const
Definition: Constants.h:916
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:965
bool isIntPredicate() const
Definition: InstrTypes.h:1084
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:267
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:276
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
constexpr bool isValid() const
Definition: LowLevelType.h:137
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
MCSymbol * getLabel() const
Definition: MCDwarf.h:659
unsigned getAddressSpace() const
Definition: MCDwarf.h:675
unsigned getRegister2() const
Definition: MCDwarf.h:670
unsigned getRegister() const
Definition: MCDwarf.h:661
int getOffset() const
Definition: MCDwarf.h:680
OpType getOperation() const
Definition: MCDwarf.h:658
StringRef getValues() const
Definition: MCDwarf.h:688
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
Metadata node.
Definition: Metadata.h:1067
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:32
virtual void printImm(raw_ostream &OS, const MachineInstr &MI, std::optional< unsigned > OpIdx, int64_t Imm) const
Implement target specific printing for machine operand immediate value, so that we can have more mean...
Definition: MIRFormatter.h:43
virtual void printCustomPseudoSourceValue(raw_ostream &OS, ModuleSlotTracker &MST, const PseudoSourceValue &PSV) const
Implement target specific printing of target custom pseudo source value.
Definition: MIRFormatter.h:60
static void printIRValue(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)
Helper functions to print IR value as MIR serialization format which will be useful for target specif...
Definition: MIRPrinter.cpp:962
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
int getObjectIndexBegin() const
Return the minimum frame object index.
PseudoSourceValueManager & getPSVManager() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:750
A description of a memory reference used in the backend.
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
const PseudoSourceValue * getPseudoValue() const
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.
LLT getMemoryType() const
Return the memory type of the memory reference.
unsigned getAddrSpace() const
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
const MDNode * getRanges() const
Return the range tag for the memory reference.
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
uint64_t getSize() const
Return the size in bytes of the memory reference.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
const void * getOpaqueValue() const
Flags
Flags values. These may be or'd together.
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
Flags getFlags() const
Return the raw flags of the source value,.
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
const Value * getValue() const
Return the base address of the memory access.
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
unsigned getInstrRefOpIndex() const
void setInstrRefInstrIndex(unsigned InstrIdx)
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
const GlobalValue * getGlobal() const
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
void setInstrRefOpIndex(unsigned OpIdx)
const ConstantInt * getCImm() const
const char * getTargetIndexName() const
getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
int64_t getImm() const
unsigned getInstrRefInstrIndex() const
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
bool isImplicit() const
void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
void setIsRenamable(bool Val=true)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const MDNode * getMetadata() const
MachineBasicBlock * getMBB() const
ArrayRef< int > getShuffleMask() const
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
void setReg(Register Reg)
Change the register this operand corresponds to.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
unsigned getCFIIndex() const
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
void ChangeToBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
ChangeToBA - Replace this operand with a new block address operand.
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
void ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx, unsigned TargetFlags=0)
Replace this operand with an Instruction Reference.
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
const BlockAddress * getBlockAddress() const
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
void setOffset(int64_t Offset)
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
unsigned getTargetFlags() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
void setIsUndef(bool Val=true)
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
Intrinsic::ID getIntrinsicID() const
bool isInternalRead() const
void setTargetFlags(unsigned F)
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void setIndex(int Idx)
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
const ConstantFP * getFPImm() const
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
unsigned getPredicate() const
MCSymbol * getMCSymbol() const
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_Predicate
Generic predicate for ISel.
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
@ MO_CImmediate
Immediate >64bit operand.
@ MO_BlockAddress
Address of a basic block.
@ MO_DbgInstrRef
Integer indices referring to an instruction+operand.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_IntrinsicID
Intrinsic ID for ISel.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
@ MO_TargetIndex
Target-dependent index+offset operand.
@ MO_Metadata
Metadata reference (for debug info)
@ MO_FPImmediate
Floating-point immediate operand.
@ MO_RegisterLiveOut
Mask of live-out registers.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:5158
Manage lifetime of a slot tracker for printing IR.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:910
const Function * getCurrentFunction() const
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:896
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:142
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot.
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like).
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function,...
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
bool empty() const
Definition: SmallVector.h:94
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
TargetInstrInfo - Interface to description of machine instruction set.
TargetIntrinsicInfo - Interface to description of machine instruction set.
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
Definition: Value.h:74
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:5052
bool hasName() const
Definition: Value.h:261
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:309
An opaque object representing a hash code.
Definition: Hashing.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
StringRef getBaseName(ID id)
Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....
Definition: Function.cpp:1008
@ System
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:57
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
hash_code hash_value(const FixedPointSemantics &Val)
Definition: APFixedPoint.h:128
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
Definition: Loads.cpp:199
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
stable_hash stable_hash_combine_array(const stable_hash *P, size_t C)
Definition: StableHashing.h:92
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:125
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ Other
Any other memory.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1758
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:212
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:613
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:377
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:760
MDNode * Scope
The tag for alias scope specification (used with noalias).
Definition: Metadata.h:783
MDNode * TBAA
The tag for type-based alias analysis.
Definition: Metadata.h:777
MDNode * NoAlias
The tag specifying the noalias scope.
Definition: Metadata.h:786
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
int64_t Offset
Offset - This is an offset from the base Value*.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.