LLVM  14.0.0git
MachineOperand.cpp
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1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/FoldingSet.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
25 #include "llvm/Config/llvm-config.h"
26 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/Instructions.h"
30 #include "llvm/MC/MCDwarf.h"
33 
34 using namespace llvm;
35 
36 static cl::opt<int>
37  PrintRegMaskNumRegs("print-regmask-num-regs",
38  cl::desc("Number of registers to limit to when "
39  "printing regmask operands in IR dumps. "
40  "unlimited = -1"),
41  cl::init(32), cl::Hidden);
42 
44  if (const MachineInstr *MI = MO.getParent())
45  if (const MachineBasicBlock *MBB = MI->getParent())
46  if (const MachineFunction *MF = MBB->getParent())
47  return MF;
48  return nullptr;
49 }
51  return const_cast<MachineFunction *>(
52  getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
53 }
54 
56  if (getReg() == Reg)
57  return; // No change.
58 
59  // Clear the IsRenamable bit to keep it conservatively correct.
60  IsRenamable = false;
61 
62  // Otherwise, we have to change the register. If this operand is embedded
63  // into a machine function, we need to update the old and new register's
64  // use/def lists.
65  if (MachineFunction *MF = getMFIfAvailable(*this)) {
66  MachineRegisterInfo &MRI = MF->getRegInfo();
68  SmallContents.RegNo = Reg;
70  return;
71  }
72 
73  // Otherwise, just change the register, no problem. :)
74  SmallContents.RegNo = Reg;
75 }
76 
78  const TargetRegisterInfo &TRI) {
79  assert(Reg.isVirtual());
80  if (SubIdx && getSubReg())
81  SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
82  setReg(Reg);
83  if (SubIdx)
84  setSubReg(SubIdx);
85 }
86 
89  if (getSubReg()) {
91  // Note that getSubReg() may return 0 if the sub-register doesn't exist.
92  // That won't happen in legal code.
93  setSubReg(0);
94  if (isDef())
95  setIsUndef(false);
96  }
97  setReg(Reg);
98 }
99 
100 /// Change a def to a use, or a use to a def.
101 void MachineOperand::setIsDef(bool Val) {
102  assert(isReg() && "Wrong MachineOperand accessor");
103  assert((!Val || !isDebug()) && "Marking a debug operation as def");
104  if (IsDef == Val)
105  return;
106  assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
107  // MRI may keep uses and defs in different list positions.
108  if (MachineFunction *MF = getMFIfAvailable(*this)) {
109  MachineRegisterInfo &MRI = MF->getRegInfo();
111  IsDef = Val;
113  return;
114  }
115  IsDef = Val;
116 }
117 
119  assert(isReg() && "Wrong MachineOperand accessor");
121  "isRenamable should only be checked on physical registers");
122  if (!IsRenamable)
123  return false;
124 
125  const MachineInstr *MI = getParent();
126  if (!MI)
127  return true;
128 
129  if (isDef())
130  return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
131 
132  assert(isUse() && "Reg is not def or use");
133  return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
134 }
135 
137  assert(isReg() && "Wrong MachineOperand accessor");
139  "setIsRenamable should only be called on physical registers");
140  IsRenamable = Val;
141 }
142 
143 // If this operand is currently a register operand, and if this is in a
144 // function, deregister the operand from the register's use/def list.
145 void MachineOperand::removeRegFromUses() {
146  if (!isReg() || !isOnRegUseList())
147  return;
148 
149  if (MachineFunction *MF = getMFIfAvailable(*this))
150  MF->getRegInfo().removeRegOperandFromUseList(this);
151 }
152 
153 /// ChangeToImmediate - Replace this operand with a new immediate operand of
154 /// the specified value. If an operand is known to be an immediate already,
155 /// the setImm method should be used.
156 void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
157  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
158 
159  removeRegFromUses();
160 
161  OpKind = MO_Immediate;
162  Contents.ImmVal = ImmVal;
163  setTargetFlags(TargetFlags);
164 }
165 
167  unsigned TargetFlags) {
168  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
169 
170  removeRegFromUses();
171 
172  OpKind = MO_FPImmediate;
173  Contents.CFP = FPImm;
174  setTargetFlags(TargetFlags);
175 }
176 
177 void MachineOperand::ChangeToES(const char *SymName,
178  unsigned TargetFlags) {
179  assert((!isReg() || !isTied()) &&
180  "Cannot change a tied operand into an external symbol");
181 
182  removeRegFromUses();
183 
184  OpKind = MO_ExternalSymbol;
185  Contents.OffsetedInfo.Val.SymbolName = SymName;
186  setOffset(0); // Offset is always 0.
187  setTargetFlags(TargetFlags);
188 }
189 
191  unsigned TargetFlags) {
192  assert((!isReg() || !isTied()) &&
193  "Cannot change a tied operand into a global address");
194 
195  removeRegFromUses();
196 
197  OpKind = MO_GlobalAddress;
198  Contents.OffsetedInfo.Val.GV = GV;
199  setOffset(Offset);
200  setTargetFlags(TargetFlags);
201 }
202 
203 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
204  assert((!isReg() || !isTied()) &&
205  "Cannot change a tied operand into an MCSymbol");
206 
207  removeRegFromUses();
208 
209  OpKind = MO_MCSymbol;
210  Contents.Sym = Sym;
211  setTargetFlags(TargetFlags);
212 }
213 
214 void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
215  assert((!isReg() || !isTied()) &&
216  "Cannot change a tied operand into a FrameIndex");
217 
218  removeRegFromUses();
219 
220  OpKind = MO_FrameIndex;
221  setIndex(Idx);
222  setTargetFlags(TargetFlags);
223 }
224 
225 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
226  unsigned TargetFlags) {
227  assert((!isReg() || !isTied()) &&
228  "Cannot change a tied operand into a FrameIndex");
229 
230  removeRegFromUses();
231 
232  OpKind = MO_TargetIndex;
233  setIndex(Idx);
234  setOffset(Offset);
235  setTargetFlags(TargetFlags);
236 }
237 
238 /// ChangeToRegister - Replace this operand with a new register operand of
239 /// the specified value. If an operand is known to be an register already,
240 /// the setReg method should be used.
241 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
242  bool isKill, bool isDead, bool isUndef,
243  bool isDebug) {
244  MachineRegisterInfo *RegInfo = nullptr;
245  if (MachineFunction *MF = getMFIfAvailable(*this))
246  RegInfo = &MF->getRegInfo();
247  // If this operand is already a register operand, remove it from the
248  // register's use/def lists.
249  bool WasReg = isReg();
250  if (RegInfo && WasReg)
251  RegInfo->removeRegOperandFromUseList(this);
252 
253  // Change this to a register and set the reg#.
254  assert(!(isDead && !isDef) && "Dead flag on non-def");
255  assert(!(isKill && isDef) && "Kill flag on def");
256  OpKind = MO_Register;
257  SmallContents.RegNo = Reg;
258  SubReg_TargetFlags = 0;
259  IsDef = isDef;
260  IsImp = isImp;
261  IsDeadOrKill = isKill | isDead;
262  IsRenamable = false;
263  IsUndef = isUndef;
264  IsInternalRead = false;
265  IsEarlyClobber = false;
266  IsDebug = isDebug;
267  // Ensure isOnRegUseList() returns false.
268  Contents.Reg.Prev = nullptr;
269  // Preserve the tie when the operand was already a register.
270  if (!WasReg)
271  TiedTo = 0;
272 
273  // If this operand is embedded in a function, add the operand to the
274  // register's use/def list.
275  if (RegInfo)
276  RegInfo->addRegOperandToUseList(this);
277 }
278 
279 /// isIdenticalTo - Return true if this operand is identical to the specified
280 /// operand. Note that this should stay in sync with the hash_value overload
281 /// below.
283  if (getType() != Other.getType() ||
284  getTargetFlags() != Other.getTargetFlags())
285  return false;
286 
287  switch (getType()) {
289  return getReg() == Other.getReg() && isDef() == Other.isDef() &&
290  getSubReg() == Other.getSubReg();
292  return getImm() == Other.getImm();
294  return getCImm() == Other.getCImm();
296  return getFPImm() == Other.getFPImm();
298  return getMBB() == Other.getMBB();
300  return getIndex() == Other.getIndex();
303  return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
305  return getIndex() == Other.getIndex();
307  return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
309  return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
310  getOffset() == Other.getOffset();
312  return getBlockAddress() == Other.getBlockAddress() &&
313  getOffset() == Other.getOffset();
316  // Shallow compare of the two RegMasks
317  const uint32_t *RegMask = getRegMask();
318  const uint32_t *OtherRegMask = Other.getRegMask();
319  if (RegMask == OtherRegMask)
320  return true;
321 
322  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
323  // Calculate the size of the RegMask
324  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
325  unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
326 
327  // Deep compare of the two RegMasks
328  return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
329  }
330  // We don't know the size of the RegMask, so we can't deep compare the two
331  // reg masks.
332  return false;
333  }
335  return getMCSymbol() == Other.getMCSymbol();
337  return getCFIIndex() == Other.getCFIIndex();
339  return getMetadata() == Other.getMetadata();
341  return getIntrinsicID() == Other.getIntrinsicID();
343  return getPredicate() == Other.getPredicate();
345  return getShuffleMask() == Other.getShuffleMask();
346  }
347  llvm_unreachable("Invalid machine operand type");
348 }
349 
350 // Note: this must stay exactly in sync with isIdenticalTo above.
352  switch (MO.getType()) {
354  // Register operands don't have target flags.
355  return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
357  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
359  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
361  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
363  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
365  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
368  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
369  MO.getOffset());
371  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
373  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
374  StringRef(MO.getSymbolName()));
376  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
377  MO.getOffset());
379  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
380  MO.getOffset());
383  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
385  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
387  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
389  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
391  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
393  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
395  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
396  }
397  llvm_unreachable("Invalid machine operand type");
398 }
399 
400 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
401 // it.
402 static void tryToGetTargetInfo(const MachineOperand &MO,
403  const TargetRegisterInfo *&TRI,
404  const TargetIntrinsicInfo *&IntrinsicInfo) {
405  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
406  TRI = MF->getSubtarget().getRegisterInfo();
407  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
408  }
409 }
410 
411 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
412  const auto *TII = MF.getSubtarget().getInstrInfo();
413  assert(TII && "expected instruction info");
414  auto Indices = TII->getSerializableTargetIndices();
415  auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
416  return I.first == Index;
417  });
418  if (Found != Indices.end())
419  return Found->second;
420  return nullptr;
421 }
422 
424  const MachineFunction *MF = getMFIfAvailable(*this);
425  return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
426 }
427 
428 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
430  for (const auto &I : Flags) {
431  if (I.first == TF) {
432  return I.second;
433  }
434  }
435  return nullptr;
436 }
437 
438 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
439  const TargetRegisterInfo *TRI) {
440  if (!TRI) {
441  OS << "%dwarfreg." << DwarfReg;
442  return;
443  }
444 
445  if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
446  OS << printReg(*Reg, TRI);
447  else
448  OS << "<badreg>";
449 }
450 
452  ModuleSlotTracker &MST) {
453  OS << "%ir-block.";
454  if (BB.hasName()) {
455  printLLVMNameWithoutPrefix(OS, BB.getName());
456  return;
457  }
458  Optional<int> Slot;
459  if (const Function *F = BB.getParent()) {
460  if (F == MST.getCurrentFunction()) {
461  Slot = MST.getLocalSlot(&BB);
462  } else if (const Module *M = F->getParent()) {
463  ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
464  CustomMST.incorporateFunction(*F);
465  Slot = CustomMST.getLocalSlot(&BB);
466  }
467  }
468  if (Slot)
470  else
471  OS << "<unknown>";
472 }
473 
475  SyncScope::ID SSID,
477  switch (SSID) {
478  case SyncScope::System:
479  break;
480  default:
481  if (SSNs.empty())
483 
484  OS << "syncscope(\"";
485  printEscapedString(SSNs[SSID], OS);
486  OS << "\") ";
487  break;
488  }
489 }
490 
491 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
492  unsigned TMMOFlag) {
493  auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
494  for (const auto &I : Flags) {
495  if (I.first == TMMOFlag) {
496  return I.second;
497  }
498  }
499  return nullptr;
500 }
501 
502 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
503  const MachineFrameInfo *MFI) {
504  StringRef Name;
505  if (MFI) {
506  IsFixed = MFI->isFixedObjectIndex(FrameIndex);
507  if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
508  if (Alloca->hasName())
509  Name = Alloca->getName();
510  if (IsFixed)
512  }
514 }
515 
517  const TargetRegisterInfo *TRI) {
518  OS << "%subreg.";
519  if (TRI)
520  OS << TRI->getSubRegIndexName(Index);
521  else
522  OS << Index;
523 }
524 
526  const MachineOperand &Op) {
527  if (!Op.getTargetFlags())
528  return;
529  const MachineFunction *MF = getMFIfAvailable(Op);
530  if (!MF)
531  return;
532 
533  const auto *TII = MF->getSubtarget().getInstrInfo();
534  assert(TII && "expected instruction info");
535  auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
536  OS << "target-flags(";
537  const bool HasDirectFlags = Flags.first;
538  const bool HasBitmaskFlags = Flags.second;
539  if (!HasDirectFlags && !HasBitmaskFlags) {
540  OS << "<unknown>) ";
541  return;
542  }
543  if (HasDirectFlags) {
544  if (const auto *Name = getTargetFlagName(TII, Flags.first))
545  OS << Name;
546  else
547  OS << "<unknown target flag>";
548  }
549  if (!HasBitmaskFlags) {
550  OS << ") ";
551  return;
552  }
553  bool IsCommaNeeded = HasDirectFlags;
554  unsigned BitMask = Flags.second;
556  for (const auto &Mask : BitMasks) {
557  // Check if the flag's bitmask has the bits of the current mask set.
558  if ((BitMask & Mask.first) == Mask.first) {
559  if (IsCommaNeeded)
560  OS << ", ";
561  IsCommaNeeded = true;
562  OS << Mask.second;
563  // Clear the bits which were serialized from the flag's bitmask.
564  BitMask &= ~(Mask.first);
565  }
566  }
567  if (BitMask) {
568  // When the resulting flag's bitmask isn't zero, we know that we didn't
569  // serialize all of the bit flags.
570  if (IsCommaNeeded)
571  OS << ", ";
572  OS << "<unknown bitmask target flag>";
573  }
574  OS << ") ";
575 }
576 
578  OS << "<mcsymbol " << Sym << ">";
579 }
580 
582  unsigned FrameIndex,
583  bool IsFixed, StringRef Name) {
584  if (IsFixed) {
585  OS << "%fixed-stack." << FrameIndex;
586  return;
587  }
588 
589  OS << "%stack." << FrameIndex;
590  if (!Name.empty())
591  OS << '.' << Name;
592 }
593 
595  if (Offset == 0)
596  return;
597  if (Offset < 0) {
598  OS << " - " << -Offset;
599  return;
600  }
601  OS << " + " << Offset;
602 }
603 
605  if (Slot == -1)
606  OS << "<badref>";
607  else
608  OS << Slot;
609 }
610 
611 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
612  const TargetRegisterInfo *TRI) {
613  switch (CFI.getOperation()) {
615  OS << "same_value ";
616  if (MCSymbol *Label = CFI.getLabel())
617  MachineOperand::printSymbol(OS, *Label);
618  printCFIRegister(CFI.getRegister(), OS, TRI);
619  break;
621  OS << "remember_state ";
622  if (MCSymbol *Label = CFI.getLabel())
623  MachineOperand::printSymbol(OS, *Label);
624  break;
626  OS << "restore_state ";
627  if (MCSymbol *Label = CFI.getLabel())
628  MachineOperand::printSymbol(OS, *Label);
629  break;
631  OS << "offset ";
632  if (MCSymbol *Label = CFI.getLabel())
633  MachineOperand::printSymbol(OS, *Label);
634  printCFIRegister(CFI.getRegister(), OS, TRI);
635  OS << ", " << CFI.getOffset();
636  break;
638  OS << "def_cfa_register ";
639  if (MCSymbol *Label = CFI.getLabel())
640  MachineOperand::printSymbol(OS, *Label);
641  printCFIRegister(CFI.getRegister(), OS, TRI);
642  break;
644  OS << "def_cfa_offset ";
645  if (MCSymbol *Label = CFI.getLabel())
646  MachineOperand::printSymbol(OS, *Label);
647  OS << CFI.getOffset();
648  break;
650  OS << "def_cfa ";
651  if (MCSymbol *Label = CFI.getLabel())
652  MachineOperand::printSymbol(OS, *Label);
653  printCFIRegister(CFI.getRegister(), OS, TRI);
654  OS << ", " << CFI.getOffset();
655  break;
657  OS << "llvm_def_aspace_cfa ";
658  if (MCSymbol *Label = CFI.getLabel())
659  MachineOperand::printSymbol(OS, *Label);
660  printCFIRegister(CFI.getRegister(), OS, TRI);
661  OS << ", " << CFI.getOffset();
662  OS << ", " << CFI.getAddressSpace();
663  break;
665  OS << "rel_offset ";
666  if (MCSymbol *Label = CFI.getLabel())
667  MachineOperand::printSymbol(OS, *Label);
668  printCFIRegister(CFI.getRegister(), OS, TRI);
669  OS << ", " << CFI.getOffset();
670  break;
672  OS << "adjust_cfa_offset ";
673  if (MCSymbol *Label = CFI.getLabel())
674  MachineOperand::printSymbol(OS, *Label);
675  OS << CFI.getOffset();
676  break;
678  OS << "restore ";
679  if (MCSymbol *Label = CFI.getLabel())
680  MachineOperand::printSymbol(OS, *Label);
681  printCFIRegister(CFI.getRegister(), OS, TRI);
682  break;
684  OS << "escape ";
685  if (MCSymbol *Label = CFI.getLabel())
686  MachineOperand::printSymbol(OS, *Label);
687  if (!CFI.getValues().empty()) {
688  size_t e = CFI.getValues().size() - 1;
689  for (size_t i = 0; i < e; ++i)
690  OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
691  OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
692  }
693  break;
694  }
696  OS << "undefined ";
697  if (MCSymbol *Label = CFI.getLabel())
698  MachineOperand::printSymbol(OS, *Label);
699  printCFIRegister(CFI.getRegister(), OS, TRI);
700  break;
702  OS << "register ";
703  if (MCSymbol *Label = CFI.getLabel())
704  MachineOperand::printSymbol(OS, *Label);
705  printCFIRegister(CFI.getRegister(), OS, TRI);
706  OS << ", ";
707  printCFIRegister(CFI.getRegister2(), OS, TRI);
708  break;
710  OS << "window_save ";
711  if (MCSymbol *Label = CFI.getLabel())
712  MachineOperand::printSymbol(OS, *Label);
713  break;
715  OS << "negate_ra_sign_state ";
716  if (MCSymbol *Label = CFI.getLabel())
717  MachineOperand::printSymbol(OS, *Label);
718  break;
719  default:
720  // TODO: Print the other CFI Operations.
721  OS << "<unserializable cfi directive>";
722  break;
723  }
724 }
725 
727  const TargetIntrinsicInfo *IntrinsicInfo) const {
728  print(OS, LLT{}, TRI, IntrinsicInfo);
729 }
730 
731 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
732  const TargetRegisterInfo *TRI,
733  const TargetIntrinsicInfo *IntrinsicInfo) const {
734  tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
735  ModuleSlotTracker DummyMST(nullptr);
736  print(OS, DummyMST, TypeToPrint, None, /*PrintDef=*/false,
737  /*IsStandalone=*/true,
738  /*ShouldPrintRegisterTies=*/true,
739  /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
740 }
741 
743  LLT TypeToPrint, Optional<unsigned> OpIdx, bool PrintDef,
744  bool IsStandalone, bool ShouldPrintRegisterTies,
745  unsigned TiedOperandIdx,
746  const TargetRegisterInfo *TRI,
747  const TargetIntrinsicInfo *IntrinsicInfo) const {
748  printTargetFlags(OS, *this);
749  switch (getType()) {
751  Register Reg = getReg();
752  if (isImplicit())
753  OS << (isDef() ? "implicit-def " : "implicit ");
754  else if (PrintDef && isDef())
755  // Print the 'def' flag only when the operand is defined after '='.
756  OS << "def ";
757  if (isInternalRead())
758  OS << "internal ";
759  if (isDead())
760  OS << "dead ";
761  if (isKill())
762  OS << "killed ";
763  if (isUndef())
764  OS << "undef ";
765  if (isEarlyClobber())
766  OS << "early-clobber ";
768  OS << "renamable ";
769  // isDebug() is exactly true for register operands of a DBG_VALUE. So we
770  // simply infer it when parsing and do not need to print it.
771 
772  const MachineRegisterInfo *MRI = nullptr;
774  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
775  MRI = &MF->getRegInfo();
776  }
777  }
778 
779  OS << printReg(Reg, TRI, 0, MRI);
780  // Print the sub register.
781  if (unsigned SubReg = getSubReg()) {
782  if (TRI)
783  OS << '.' << TRI->getSubRegIndexName(SubReg);
784  else
785  OS << ".subreg" << SubReg;
786  }
787  // Print the register class / bank.
789  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
790  const MachineRegisterInfo &MRI = MF->getRegInfo();
791  if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
792  OS << ':';
793  OS << printRegClassOrBank(Reg, MRI, TRI);
794  }
795  }
796  }
797  // Print ties.
798  if (ShouldPrintRegisterTies && isTied() && !isDef())
799  OS << "(tied-def " << TiedOperandIdx << ")";
800  // Print types.
801  if (TypeToPrint.isValid())
802  OS << '(' << TypeToPrint << ')';
803  break;
804  }
806  const MIRFormatter *Formatter = nullptr;
807  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
808  const auto *TII = MF->getSubtarget().getInstrInfo();
809  assert(TII && "expected instruction info");
810  Formatter = TII->getMIRFormatter();
811  }
812  if (Formatter)
813  Formatter->printImm(OS, *getParent(), OpIdx, getImm());
814  else
815  OS << getImm();
816  break;
817  }
819  getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
820  break;
822  getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
823  break;
825  OS << printMBBReference(*getMBB());
826  break;
828  int FrameIndex = getIndex();
829  bool IsFixed = false;
830  const MachineFrameInfo *MFI = nullptr;
831  if (const MachineFunction *MF = getMFIfAvailable(*this))
832  MFI = &MF->getFrameInfo();
833  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
834  break;
835  }
837  OS << "%const." << getIndex();
839  break;
841  OS << "target-index(";
842  const char *Name = "<unknown>";
843  if (const MachineFunction *MF = getMFIfAvailable(*this))
844  if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
845  Name = TargetIndexName;
846  OS << Name << ')';
848  break;
849  }
852  break;
854  getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
856  break;
859  OS << '&';
860  if (Name.empty()) {
861  OS << "\"\"";
862  } else {
864  }
866  break;
867  }
869  OS << "blockaddress(";
870  getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
871  MST);
872  OS << ", ";
873  printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
874  OS << ')';
876  break;
877  }
879  OS << "<regmask";
880  if (TRI) {
881  unsigned NumRegsInMask = 0;
882  unsigned NumRegsEmitted = 0;
883  for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
884  unsigned MaskWord = i / 32;
885  unsigned MaskBit = i % 32;
886  if (getRegMask()[MaskWord] & (1 << MaskBit)) {
887  if (PrintRegMaskNumRegs < 0 ||
888  NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
889  OS << " " << printReg(i, TRI);
890  NumRegsEmitted++;
891  }
892  NumRegsInMask++;
893  }
894  }
895  if (NumRegsEmitted != NumRegsInMask)
896  OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
897  } else {
898  OS << " ...";
899  }
900  OS << ">";
901  break;
902  }
904  const uint32_t *RegMask = getRegLiveOut();
905  OS << "liveout(";
906  if (!TRI) {
907  OS << "<unknown>";
908  } else {
909  bool IsCommaNeeded = false;
910  for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
911  if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
912  if (IsCommaNeeded)
913  OS << ", ";
914  OS << printReg(Reg, TRI);
915  IsCommaNeeded = true;
916  }
917  }
918  }
919  OS << ")";
920  break;
921  }
923  getMetadata()->printAsOperand(OS, MST);
924  break;
926  printSymbol(OS, *getMCSymbol());
927  break;
929  if (const MachineFunction *MF = getMFIfAvailable(*this))
930  printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
931  else
932  OS << "<cfi directive>";
933  break;
934  }
937  if (ID < Intrinsic::num_intrinsics)
938  OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';
939  else if (IntrinsicInfo)
940  OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
941  else
942  OS << "intrinsic(" << ID << ')';
943  break;
944  }
946  auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
947  OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
948  << CmpInst::getPredicateName(Pred) << ')';
949  break;
950  }
952  OS << "shufflemask(";
954  StringRef Separator;
955  for (int Elt : Mask) {
956  if (Elt == -1)
957  OS << Separator << "undef";
958  else
959  OS << Separator << Elt;
960  Separator = ", ";
961  }
962 
963  OS << ')';
964  break;
965  }
966 }
967 
968 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
969 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
970 #endif
971 
972 //===----------------------------------------------------------------------===//
973 // MachineMemOperand Implementation
974 //===----------------------------------------------------------------------===//
975 
976 /// getAddrSpace - Return the LLVM IR address space number that this pointer
977 /// points into.
978 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
979 
980 /// isDereferenceable - Return true if V is always dereferenceable for
981 /// Offset + Size byte.
983  const DataLayout &DL) const {
984  if (!V.is<const Value *>())
985  return false;
986 
987  const Value *BasePtr = V.get<const Value *>();
988  if (BasePtr == nullptr)
989  return false;
990 
992  BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
993 }
994 
995 /// getConstantPool - Return a MachinePointerInfo record that refers to the
996 /// constant pool.
999 }
1000 
1001 /// getFixedStack - Return a MachinePointerInfo record that refers to the
1002 /// the specified FrameIndex.
1004  int FI, int64_t Offset) {
1006 }
1007 
1010 }
1011 
1013  return MachinePointerInfo(MF.getPSVManager().getGOT());
1014 }
1015 
1017  int64_t Offset, uint8_t ID) {
1019 }
1020 
1023 }
1024 
1026  LLT type, Align a, const AAMDNodes &AAInfo,
1027  const MDNode *Ranges, SyncScope::ID SSID,
1028  AtomicOrdering Ordering,
1029  AtomicOrdering FailureOrdering)
1030  : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),
1031  AAInfo(AAInfo), Ranges(Ranges) {
1032  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1033  isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1034  "invalid pointer value");
1035  assert((isLoad() || isStore()) && "Not a load/store!");
1036 
1037  AtomicInfo.SSID = static_cast<unsigned>(SSID);
1038  assert(getSyncScopeID() == SSID && "Value truncated");
1039  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1040  assert(getSuccessOrdering() == Ordering && "Value truncated");
1041  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1042  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1043 }
1044 
1046  uint64_t s, Align a,
1047  const AAMDNodes &AAInfo,
1048  const MDNode *Ranges, SyncScope::ID SSID,
1049  AtomicOrdering Ordering,
1050  AtomicOrdering FailureOrdering)
1051  : MachineMemOperand(ptrinfo, f,
1052  s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
1053  AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1054 
1055 /// Profile - Gather unique data for the object.
1056 ///
1058  ID.AddInteger(getOffset());
1059  ID.AddInteger(getMemoryType().getUniqueRAWLLTData());
1060  ID.AddPointer(getOpaqueValue());
1061  ID.AddInteger(getFlags());
1062  ID.AddInteger(getBaseAlign().value());
1063 }
1064 
1066  // The Value and Offset may differ due to CSE. But the flags and size
1067  // should be the same.
1068  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1069  assert(MMO->getSize() == getSize() && "Size mismatch!");
1070 
1071  if (MMO->getBaseAlign() >= getBaseAlign()) {
1072  // Update the alignment value.
1073  BaseAlign = MMO->getBaseAlign();
1074  // Also update the base and offset, because the new alignment may
1075  // not be applicable with the old ones.
1076  PtrInfo = MMO->PtrInfo;
1077  }
1078 }
1079 
1080 /// getAlign - Return the minimum known alignment in bytes of the
1081 /// actual memory reference.
1083  return commonAlignment(getBaseAlign(), getOffset());
1084 }
1085 
1088  const LLVMContext &Context,
1089  const MachineFrameInfo *MFI,
1090  const TargetInstrInfo *TII) const {
1091  OS << '(';
1092  if (isVolatile())
1093  OS << "volatile ";
1094  if (isNonTemporal())
1095  OS << "non-temporal ";
1096  if (isDereferenceable())
1097  OS << "dereferenceable ";
1098  if (isInvariant())
1099  OS << "invariant ";
1102  << "\" ";
1105  << "\" ";
1108  << "\" ";
1109 
1110  assert((isLoad() || isStore()) &&
1111  "machine memory operand must be a load or store (or both)");
1112  if (isLoad())
1113  OS << "load ";
1114  if (isStore())
1115  OS << "store ";
1116 
1117  printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1118 
1120  OS << toIRString(getSuccessOrdering()) << ' ';
1122  OS << toIRString(getFailureOrdering()) << ' ';
1123 
1124  if (getMemoryType().isValid())
1125  OS << '(' << getMemoryType() << ')';
1126  else
1127  OS << "unknown-size";
1128 
1129  if (const Value *Val = getValue()) {
1130  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1131  MIRFormatter::printIRValue(OS, *Val, MST);
1132  } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1133  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1134  assert(PVal && "Expected a pseudo source value");
1135  switch (PVal->kind()) {
1137  OS << "stack";
1138  break;
1140  OS << "got";
1141  break;
1143  OS << "jump-table";
1144  break;
1146  OS << "constant-pool";
1147  break;
1149  int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1150  bool IsFixed = true;
1151  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1152  break;
1153  }
1155  OS << "call-entry ";
1156  cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1157  OS, /*PrintType=*/false, MST);
1158  break;
1160  OS << "call-entry &";
1162  OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1163  break;
1164  default: {
1165  const MIRFormatter *Formatter = TII->getMIRFormatter();
1166  // FIXME: This is not necessarily the correct MIR serialization format for
1167  // a custom pseudo source value, but at least it allows
1168  // MIR printing to work on a target with custom pseudo source
1169  // values.
1170  OS << "custom \"";
1171  Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1172  OS << '\"';
1173  break;
1174  }
1175  }
1176  } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1177  OS << ((isLoad() && isStore()) ? " on "
1178  : isLoad() ? " from "
1179  : " into ")
1180  << "unknown-address";
1181  }
1183  if (getSize() > 0 && getAlign() != getSize())
1184  OS << ", align " << getAlign().value();
1185  if (getAlign() != getBaseAlign())
1186  OS << ", basealign " << getBaseAlign().value();
1187  auto AAInfo = getAAInfo();
1188  if (AAInfo.TBAA) {
1189  OS << ", !tbaa ";
1190  AAInfo.TBAA->printAsOperand(OS, MST);
1191  }
1192  if (AAInfo.Scope) {
1193  OS << ", !alias.scope ";
1194  AAInfo.Scope->printAsOperand(OS, MST);
1195  }
1196  if (AAInfo.NoAlias) {
1197  OS << ", !noalias ";
1198  AAInfo.NoAlias->printAsOperand(OS, MST);
1199  }
1200  if (getRanges()) {
1201  OS << ", !range ";
1202  getRanges()->printAsOperand(OS, MST);
1203  }
1204  // FIXME: Implement addrspace printing/parsing in MIR.
1205  // For now, print this even though parsing it is not available in MIR.
1206  if (unsigned AS = getAddrSpace())
1207  OS << ", addrspace " << AS;
1208 
1209  OS << ')';
1210 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::Intrinsic::getBaseName
StringRef getBaseName(ID id)
Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....
Definition: Function.cpp:831
i
i
Definition: README.txt:29
llvm::MCCFIInstruction::OpWindowSave
@ OpWindowSave
Definition: MCDwarf.h:451
llvm::MIRFormatter::printIRValue
static void printIRValue(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)
Helper functions to print IR value as MIR serialization format which will be useful for target specif...
Definition: MIRPrinter.cpp:922
printCFI
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
Definition: MachineOperand.cpp:611
llvm::MachineMemOperand::MachineMemOperand
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.
Definition: MachineOperand.cpp:1045
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:63
llvm::MachineMemOperand::isStore
bool isStore() const
Definition: MachineMemOperand.h:299
llvm::PseudoSourceValueManager::getGOT
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like).
Definition: PseudoSourceValue.cpp:118
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:53
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:491
llvm::PointerUnion::isNull
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:142
llvm::ModuleSlotTracker::getLocalSlot
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:869
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::PseudoSourceValue::GlobalValueCallEntry
@ GlobalValueCallEntry
Definition: PseudoSourceValue.h:43
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::MCCFIInstruction::OpRelOffset
@ OpRelOffset
Definition: MCDwarf.h:445
tryToGetTargetInfo
static void tryToGetTargetInfo(const MachineOperand &MO, const TargetRegisterInfo *&TRI, const TargetIntrinsicInfo *&IntrinsicInfo)
Definition: MachineOperand.cpp:402
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::MCCFIInstruction::OpDefCfaRegister
@ OpDefCfaRegister
Definition: MCDwarf.h:442
type
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1082
llvm::MachineOperand::MO_ShuffleMask
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
Definition: MachineOperand.h:71
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:563
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
Loads.h
llvm::MachineOperand::MO_RegisterLiveOut
@ MO_RegisterLiveOut
Mask of live-out registers.
Definition: MachineOperand.h:65
llvm::Function
Definition: Function.h:61
llvm::MachineMemOperand::print
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
Definition: MachineOperand.cpp:1086
llvm::MCCFIInstruction::OpOffset
@ OpOffset
Definition: MCDwarf.h:440
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
getMFIfAvailable
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
Definition: MachineOperand.cpp:43
llvm::MachinePointerInfo::getConstantPool
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
Definition: MachineOperand.cpp:997
llvm::MachineOperand::printStackObjectReference
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Definition: MachineOperand.cpp:581
llvm::MachineOperand::printIRSlotNumber
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
Definition: MachineOperand.cpp:604
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:583
llvm::MachinePointerInfo::getUnknownStack
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
Definition: MachineOperand.cpp:1021
llvm::printLLVMNameWithoutPrefix
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:349
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:726
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:568
llvm::MachineMemOperand::isLoad
bool isLoad() const
Definition: MachineMemOperand.h:298
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:227
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:119
llvm::isDereferenceableAndAlignedPointer
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, MaybeAlign Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
Definition: Loads.cpp:210
llvm::ModuleSlotTracker::getCurrentFunction
const Function * getCurrentFunction() const
Definition: ModuleSlotTracker.h:81
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:441
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::SyncScope::System
@ System
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:58
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MachineMemOperand::MOTargetFlag2
@ MOTargetFlag2
Definition: MachineMemOperand.h:152
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::MachineMemOperand::getOpaqueValue
const void * getOpaqueValue() const
Definition: MachineMemOperand.h:217
llvm::HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
Definition: HexagonInstrInfo.cpp:2004
MachineJumpTableInfo.h
TargetInstrInfo.h
llvm::Metadata::printAsOperand
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4712
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::MachineOperand::MO_CFIIndex
@ MO_CFIIndex
MCCFIInstruction index.
Definition: MachineOperand.h:68
llvm::MachineOperand::getTargetIndexName
const char * getTargetIndexName() const
getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...
Definition: MachineOperand.cpp:423
llvm::MachineFunction::getPSVManager
PseudoSourceValueManager & getPSVManager() const
Definition: MachineFunction.h:582
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:117
llvm::HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
Definition: HexagonInstrInfo.cpp:1985
llvm::Optional< unsigned >
llvm::LLVMContext::getSyncScopeNames
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
Definition: LLVMContext.cpp:294
llvm::MachineOperand::ChangeToTargetIndex
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
Definition: MachineOperand.cpp:225
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::ModuleSlotTracker::incorporateFunction
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:855
llvm::MachineMemOperand::isInvariant
bool isInvariant() const
Definition: MachineMemOperand.h:303
llvm::PseudoSourceValueManager::getStack
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function,...
Definition: PseudoSourceValue.cpp:114
llvm::MachineOperand::ChangeToFrameIndex
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
Definition: MachineOperand.cpp:214
llvm::CmpInst::getPredicateName
static StringRef getPredicateName(Predicate P)
Definition: Instructions.cpp:3795
llvm::AAMDNodes::Scope
MDNode * Scope
The tag for alias scope specification (used with noalias).
Definition: Metadata.h:674
llvm::minidump::MemoryType
MemoryType
Definition: Minidump.h:98
llvm::hash_value
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4810
llvm::MachineMemOperand::getAAInfo
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Definition: MachineMemOperand.h:258
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:600
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineOperand::dump
void dump() const
Definition: MachineOperand.cpp:969
llvm::PointerUnion::get
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:157
llvm::MachinePointerInfo::getJumpTable
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Definition: MachineOperand.cpp:1008
llvm::MachineOperand::getMCSymbol
MCSymbol * getMCSymbol() const
Definition: MachineOperand.h:573
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:52
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::PseudoSourceValue::JumpTable
@ JumpTable
Definition: PseudoSourceValue.h:40
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::PointerUnion::is
bool is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:147
llvm::lltok::equal
@ equal
Definition: LLToken.h:25
a
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
Definition: README.txt:489
llvm::MachineOperand::printSymbol
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
Definition: MachineOperand.cpp:577
isUndef
static bool isUndef(ArrayRef< int > Mask)
Definition: HexagonISelDAGToDAGHVX.cpp:912
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition: TargetIntrinsicInfo.h:29
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachinePointerInfo::Offset
int64_t Offset
Offset - This is an offset from the base Value*.
Definition: MachineMemOperand.h:45
llvm::MCCFIInstruction::OpDefCfa
@ OpDefCfa
Definition: MCDwarf.h:444
llvm::MachineOperand::printSubRegIdx
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Definition: MachineOperand.cpp:516
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:390
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:118
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition: MachineMemOperand.h:151
llvm::MCCFIInstruction::OpUndefined
@ OpUndefined
Definition: MCDwarf.h:449
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:380
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
TargetMachine.h
Constants.h
llvm::MachineMemOperand::getBaseAlign
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
Definition: MachineMemOperand.h:255
llvm::MachineOperand::ChangeToRegister
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Definition: MachineOperand.cpp:241
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:62
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:229
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
getTargetIndexName
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
Definition: MachineOperand.cpp:411
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:211
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:370
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineOperand::getRegMask
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Definition: MachineOperand.h:630
llvm::MachineOperand::setSubReg
void setSubReg(unsigned subReg)
Definition: MachineOperand.h:471
llvm::MachineOperand::MO_FrameIndex
@ MO_FrameIndex
Abstract Stack Frame Index.
Definition: MachineOperand.h:57
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MCCFIInstruction::getOffset
int getOffset() const
Definition: MCDwarf.h:619
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1012
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:156
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
IRPrintingPasses.h
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::PseudoSourceValue::FixedStack
@ FixedStack
Definition: PseudoSourceValue.h:42
llvm::MachineOperand::ChangeToMCSymbol
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
Definition: MachineOperand.cpp:203
llvm::MCCFIInstruction::getOperation
OpType getOperation() const
Definition: MCDwarf.h:597
llvm::printJumpTableEntryReference
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
Definition: MachineFunction.cpp:1335
llvm::MachineOperand::setTargetFlags
void setTargetFlags(unsigned F)
Definition: MachineOperand.h:224
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:654
printCFIRegister
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
Definition: MachineOperand.cpp:438
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:388
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(const Value *v, int64_t offset=0, uint8_t ID=0)
Definition: MachineMemOperand.h:51
llvm::MCCFIInstruction::getRegister
unsigned getRegister() const
Definition: MCDwarf.h:600
llvm::None
const NoneType None
Definition: None.h:23
isDebug
static bool isDebug()
Definition: HexagonGenInsert.cpp:81
llvm::MachineOperand::printOperandOffset
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
Definition: MachineOperand.cpp:594
llvm::MachineMemOperand::getSyncScopeID
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
Definition: MachineMemOperand.h:264
llvm::MCCFIInstruction
Definition: MCDwarf.h:434
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:426
llvm::MCRegisterInfo::getLLVMRegNum
Optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
Definition: MCRegisterInfo.cpp:81
llvm::MachineMemOperand::Profile
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
Definition: MachineOperand.cpp:1057
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition: MachineOperand.h:646
llvm::PseudoSourceValue::ExternalSymbolCallEntry
@ ExternalSymbolCallEntry
Definition: PseudoSourceValue.h:44
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:622
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::cl::opt
Definition: CommandLine.h:1422
llvm::MachineOperand::MO_Metadata
@ MO_Metadata
Metadata reference (for debug info)
Definition: MachineOperand.h:66
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineOperand::ChangeToFPImmediate
void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
Definition: MachineOperand.cpp:166
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:395
llvm::MCCFIInstruction::OpDefCfaOffset
@ OpDefCfaOffset
Definition: MCDwarf.h:443
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:221
llvm::MachineOperand::substVirtReg
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Definition: MachineOperand.cpp:77
llvm::MachinePointerInfo::isDereferenceable
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
Definition: MachineOperand.cpp:982
llvm::MCCFIInstruction::OpRestore
@ OpRestore
Definition: MCDwarf.h:448
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:542
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineMemOperand::isDereferenceable
bool isDereferenceable() const
Definition: MachineMemOperand.h:302
uint64_t
s
multiplies can be turned into SHL s
Definition: README.txt:370
llvm::MCCFIInstruction::OpSameValue
@ OpSameValue
Definition: MCDwarf.h:437
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
MemoryLocation.h
llvm::SyncScope::ID
uint8_t ID
Definition: LLVMContext.h:47
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:385
llvm::MachineOperand::MO_Predicate
@ MO_Predicate
Generic predicate for ISel.
Definition: MachineOperand.h:70
MIRPrinter.h
I
#define I(x, y, z)
Definition: MD5.cpp:59
StringExtras.h
llvm::MachineOperand::MO_MCSymbol
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
Definition: MachineOperand.h:67
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:219
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition: MachineOperand.h:547
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:588
llvm::PseudoSourceValue::ConstantPool
@ ConstantPool
Definition: PseudoSourceValue.h:41
llvm::MCCFIInstruction::getRegister2
unsigned getRegister2() const
Definition: MCDwarf.h:609
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::MIRFormatter::printImm
virtual void printImm(raw_ostream &OS, const MachineInstr &MI, Optional< unsigned > OpIdx, int64_t Imm) const
Implement target specific printing for machine operand immediate value, so that we can have more mean...
Definition: MIRFormatter.h:41
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition: MachineOperand.h:436
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineMemOperand::getSuccessOrdering
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
Definition: MachineMemOperand.h:271
MIRFormatter.h
llvm::MachineOperand::getShuffleMask
ArrayRef< int > getShuffleMask() const
Definition: MachineOperand.h:593
llvm::MachineOperand::MO_TargetIndex
@ MO_TargetIndex
Target-dependent index+offset operand.
Definition: MachineOperand.h:59
PrintRegMaskNumRegs
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
llvm::MachineMemOperand::getMemoryType
LLT getMemoryType() const
Return the memory type of the memory reference.
Definition: MachineMemOperand.h:233
llvm::MCCFIInstruction::OpAdjustCfaOffset
@ OpAdjustCfaOffset
Definition: MCDwarf.h:446
llvm::MachineOperand::MO_FPImmediate
@ MO_FPImmediate
Floating-point immediate operand.
Definition: MachineOperand.h:55
printFrameIndex
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
Definition: MachineOperand.cpp:502
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::MDNode
Metadata node.
Definition: Metadata.h:897
llvm::Value::printAsOperand
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:4670
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MCCFIInstruction::OpEscape
@ OpEscape
Definition: MCDwarf.h:447
llvm::CmpInst::isIntPredicate
bool isIntPredicate() const
Definition: InstrTypes.h:814
llvm::MachineOperand::MO_JumpTableIndex
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition: MachineOperand.h:60
llvm::MachineOperand::MO_CImmediate
@ MO_CImmediate
Immediate >64bit operand.
Definition: MachineOperand.h:54
llvm::printRegClassOrBank
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Definition: TargetRegisterInfo.cpp:174
llvm::MachineMemOperand::MOTargetFlag3
@ MOTargetFlag3
Definition: MachineMemOperand.h:153
llvm::MachineOperand::setIsDef
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Definition: MachineOperand.cpp:101
llvm::ArrayRef< int >
llvm::MCCFIInstruction::getAddressSpace
unsigned getAddressSpace() const
Definition: MCDwarf.h:614
llvm::MCCFIInstruction::OpRememberState
@ OpRememberState
Definition: MCDwarf.h:438
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
llvm::HexagonInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
Definition: HexagonInstrInfo.cpp:1979
llvm::MachinePointerInfo::V
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Definition: MachineMemOperand.h:42
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MCCFIInstruction::getValues
StringRef getValues() const
Definition: MCDwarf.h:627
llvm::MachineOperand::ChangeToES
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Definition: MachineOperand.cpp:177
llvm::TargetRegisterInfo::composeSubRegIndices
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Definition: TargetRegisterInfo.h:629
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:511
uint32_t
llvm::MachineOperand::setIsRenamable
void setIsRenamable(bool Val=true)
Definition: MachineOperand.cpp:136
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:56
llvm::MCCFIInstruction::OpLLVMDefAspaceCfa
@ OpLLVMDefAspaceCfa
Definition: MCDwarf.h:441
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachinePointerInfo::AddrSpace
unsigned AddrSpace
Definition: MachineMemOperand.h:47
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::FoldingSetNodeID
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:313
llvm::MachineOperand::MO_IntrinsicID
@ MO_IntrinsicID
Intrinsic ID for ISel.
Definition: MachineOperand.h:69
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:304
llvm::format
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
llvm::DataLayout::getAllocaAddrSpace
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:279
llvm::MachineOperand::setIndex
void setIndex(int Idx)
Definition: MachineOperand.h:678
llvm::TargetIntrinsicInfo::getName
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
llvm::MachinePointerInfo::getAddrSpace
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Definition: MachineOperand.cpp:978
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
FoldingSet.h
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1574
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::PseudoSourceValueManager::getJumpTable
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
Definition: PseudoSourceValue.cpp:124
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::PseudoSourceValue::GOT
@ GOT
Definition: PseudoSourceValue.h:39
llvm::MachineMemOperand::isVolatile
bool isVolatile() const
Definition: MachineMemOperand.h:300
llvm::BlockAddress::getFunction
Function * getFunction() const
Definition: Constants.h:876
llvm::MachineOperand::printTargetFlags
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
Definition: MachineOperand.cpp:525
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:211
llvm::MachineOperand::ChangeToGA
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
Definition: MachineOperand.cpp:190
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:265
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::AAMDNodes::NoAlias
MDNode * NoAlias
The tag specifying the noalias scope.
Definition: Metadata.h:677
getTargetFlagName
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
Definition: MachineOperand.cpp:428
llvm::PseudoSourceValueManager::getFixedStack
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot.
Definition: PseudoSourceValue.cpp:129
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:236
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:61
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:557
llvm::MachineOperand::getCFIIndex
unsigned getCFIIndex() const
Definition: MachineOperand.h:578
llvm::PseudoSourceValue::Stack
@ Stack
Definition: PseudoSourceValue.h:38
llvm::MachineMemOperand::refineAlignment
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
Definition: MachineOperand.cpp:1065
llvm::MCCFIInstruction::OpRegister
@ OpRegister
Definition: MCDwarf.h:450
llvm::AAMDNodes::TBAA
MDNode * TBAA
The tag for type-based alias analysis.
Definition: Metadata.h:668
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:446
llvm::MachineInstr::IgnoreBundle
@ IgnoreBundle
Definition: MachineInstr.h:766
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:30
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:216
Instructions.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1003
llvm::hash_combine
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:604
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:608
TargetIntrinsicInfo.h
getTargetMMOFlagName
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
Definition: MachineOperand.cpp:491
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::toIRString
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
Definition: AtomicOrdering.h:81
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition: MachineOperand.h:431
llvm::MachineOperand::getRegLiveOut
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
Definition: MachineOperand.h:641
ModuleSlotTracker.h
llvm::SmallVectorImpl< StringRef >
llvm::MachineMemOperand::getFailureOrdering
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
Definition: MachineMemOperand.h:277
MachineOperand.h
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1096
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition: MachineOperand.cpp:87
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::AllocaInst
an instruction to allocate memory on the stack
Definition: Instructions.h:62
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:64
printIRBlockReference
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
Definition: MachineOperand.cpp:451
llvm::cl::desc
Definition: CommandLine.h:414
llvm::MachineMemOperand::isNonTemporal
bool isNonTemporal() const
Definition: MachineMemOperand.h:301
llvm::TargetRegisterInfo::getSubRegIndexName
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition: TargetRegisterInfo.h:365
llvm::MachineMemOperand::getRanges
const MDNode * getRanges() const
Return the range tag for the memory reference.
Definition: MachineMemOperand.h:261
llvm::MCCFIInstruction::OpNegateRAState
@ OpNegateRAState
Definition: MCDwarf.h:452
llvm::MIRFormatter::printCustomPseudoSourceValue
virtual void printCustomPseudoSourceValue(raw_ostream &OS, ModuleSlotTracker &MST, const PseudoSourceValue &PSV) const
Implement target specific printing of target custom pseudo source value.
Definition: MIRFormatter.h:58
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1016
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:220
TargetRegisterInfo.h
llvm::MCCFIInstruction::OpRestoreState
@ OpRestoreState
Definition: MCDwarf.h:439
llvm::PseudoSourceValueManager::getConstantPool
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
Definition: PseudoSourceValue.cpp:120
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::AtomicOrdering::NotAtomic
@ NotAtomic
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1172
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:282
llvm::MCCFIInstruction::getLabel
MCSymbol * getLabel() const
Definition: MCDwarf.h:598
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:213
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::hash_code
An opaque object representing a hash code.
Definition: Hashing.h:72
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:58
llvm::MachineFrameInfo::getObjectAllocation
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
Definition: MachineFrameInfo.h:484
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::MachineOperand::setOffset
void setOffset(int64_t Offset)
Definition: MachineOperand.h:670
printSyncScope
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)
Definition: MachineOperand.cpp:474