LLVM  16.0.0git
MachineOperand.cpp
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1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/FoldingSet.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
24 #include "llvm/Config/llvm-config.h"
25 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/Instructions.h"
29 #include "llvm/MC/MCDwarf.h"
32 
33 using namespace llvm;
34 
35 static cl::opt<int>
36  PrintRegMaskNumRegs("print-regmask-num-regs",
37  cl::desc("Number of registers to limit to when "
38  "printing regmask operands in IR dumps. "
39  "unlimited = -1"),
40  cl::init(32), cl::Hidden);
41 
43  if (const MachineInstr *MI = MO.getParent())
44  if (const MachineBasicBlock *MBB = MI->getParent())
45  if (const MachineFunction *MF = MBB->getParent())
46  return MF;
47  return nullptr;
48 }
49 
51  return const_cast<MachineFunction *>(
52  getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
53 }
54 
56  if (getReg() == Reg)
57  return; // No change.
58 
59  // Clear the IsRenamable bit to keep it conservatively correct.
60  IsRenamable = false;
61 
62  // Otherwise, we have to change the register. If this operand is embedded
63  // into a machine function, we need to update the old and new register's
64  // use/def lists.
65  if (MachineFunction *MF = getMFIfAvailable(*this)) {
66  MachineRegisterInfo &MRI = MF->getRegInfo();
68  SmallContents.RegNo = Reg;
70  return;
71  }
72 
73  // Otherwise, just change the register, no problem. :)
74  SmallContents.RegNo = Reg;
75 }
76 
78  const TargetRegisterInfo &TRI) {
79  assert(Reg.isVirtual());
80  if (SubIdx && getSubReg())
81  SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
82  setReg(Reg);
83  if (SubIdx)
84  setSubReg(SubIdx);
85 }
86 
89  if (getSubReg()) {
91  // Note that getSubReg() may return 0 if the sub-register doesn't exist.
92  // That won't happen in legal code.
93  setSubReg(0);
94  if (isDef())
95  setIsUndef(false);
96  }
97  setReg(Reg);
98 }
99 
100 /// Change a def to a use, or a use to a def.
101 void MachineOperand::setIsDef(bool Val) {
102  assert(isReg() && "Wrong MachineOperand accessor");
103  assert((!Val || !isDebug()) && "Marking a debug operation as def");
104  if (IsDef == Val)
105  return;
106  assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
107  // MRI may keep uses and defs in different list positions.
108  if (MachineFunction *MF = getMFIfAvailable(*this)) {
109  MachineRegisterInfo &MRI = MF->getRegInfo();
111  IsDef = Val;
113  return;
114  }
115  IsDef = Val;
116 }
117 
119  assert(isReg() && "Wrong MachineOperand accessor");
121  "isRenamable should only be checked on physical registers");
122  if (!IsRenamable)
123  return false;
124 
125  const MachineInstr *MI = getParent();
126  if (!MI)
127  return true;
128 
129  if (isDef())
130  return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
131 
132  assert(isUse() && "Reg is not def or use");
133  return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
134 }
135 
137  assert(isReg() && "Wrong MachineOperand accessor");
139  "setIsRenamable should only be called on physical registers");
140  IsRenamable = Val;
141 }
142 
143 // If this operand is currently a register operand, and if this is in a
144 // function, deregister the operand from the register's use/def list.
145 void MachineOperand::removeRegFromUses() {
146  if (!isReg() || !isOnRegUseList())
147  return;
148 
149  if (MachineFunction *MF = getMFIfAvailable(*this))
150  MF->getRegInfo().removeRegOperandFromUseList(this);
151 }
152 
153 /// ChangeToImmediate - Replace this operand with a new immediate operand of
154 /// the specified value. If an operand is known to be an immediate already,
155 /// the setImm method should be used.
156 void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
157  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
158 
159  removeRegFromUses();
160 
161  OpKind = MO_Immediate;
162  Contents.ImmVal = ImmVal;
163  setTargetFlags(TargetFlags);
164 }
165 
167  unsigned TargetFlags) {
168  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
169 
170  removeRegFromUses();
171 
172  OpKind = MO_FPImmediate;
173  Contents.CFP = FPImm;
174  setTargetFlags(TargetFlags);
175 }
176 
177 void MachineOperand::ChangeToES(const char *SymName,
178  unsigned TargetFlags) {
179  assert((!isReg() || !isTied()) &&
180  "Cannot change a tied operand into an external symbol");
181 
182  removeRegFromUses();
183 
184  OpKind = MO_ExternalSymbol;
185  Contents.OffsetedInfo.Val.SymbolName = SymName;
186  setOffset(0); // Offset is always 0.
187  setTargetFlags(TargetFlags);
188 }
189 
190 void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
191  unsigned TargetFlags) {
192  assert((!isReg() || !isTied()) &&
193  "Cannot change a tied operand into a global address");
194 
195  removeRegFromUses();
196 
197  OpKind = MO_GlobalAddress;
198  Contents.OffsetedInfo.Val.GV = GV;
199  setOffset(Offset);
200  setTargetFlags(TargetFlags);
201 }
202 
203 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
204  assert((!isReg() || !isTied()) &&
205  "Cannot change a tied operand into an MCSymbol");
206 
207  removeRegFromUses();
208 
209  OpKind = MO_MCSymbol;
210  Contents.Sym = Sym;
211  setTargetFlags(TargetFlags);
212 }
213 
214 void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
215  assert((!isReg() || !isTied()) &&
216  "Cannot change a tied operand into a FrameIndex");
217 
218  removeRegFromUses();
219 
220  OpKind = MO_FrameIndex;
221  setIndex(Idx);
222  setTargetFlags(TargetFlags);
223 }
224 
225 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
226  unsigned TargetFlags) {
227  assert((!isReg() || !isTied()) &&
228  "Cannot change a tied operand into a FrameIndex");
229 
230  removeRegFromUses();
231 
232  OpKind = MO_TargetIndex;
233  setIndex(Idx);
234  setOffset(Offset);
235  setTargetFlags(TargetFlags);
236 }
237 
238 /// ChangeToRegister - Replace this operand with a new register operand of
239 /// the specified value. If an operand is known to be an register already,
240 /// the setReg method should be used.
241 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
242  bool isKill, bool isDead, bool isUndef,
243  bool isDebug) {
244  MachineRegisterInfo *RegInfo = nullptr;
245  if (MachineFunction *MF = getMFIfAvailable(*this))
246  RegInfo = &MF->getRegInfo();
247  // If this operand is already a register operand, remove it from the
248  // register's use/def lists.
249  bool WasReg = isReg();
250  if (RegInfo && WasReg)
251  RegInfo->removeRegOperandFromUseList(this);
252 
253  // Ensure debug instructions set debug flag on register uses.
254  const MachineInstr *MI = getParent();
255  if (!isDef && MI && MI->isDebugInstr())
256  isDebug = true;
257 
258  // Change this to a register and set the reg#.
259  assert(!(isDead && !isDef) && "Dead flag on non-def");
260  assert(!(isKill && isDef) && "Kill flag on def");
261  OpKind = MO_Register;
262  SmallContents.RegNo = Reg;
263  SubReg_TargetFlags = 0;
264  IsDef = isDef;
265  IsImp = isImp;
266  IsDeadOrKill = isKill | isDead;
267  IsRenamable = false;
268  IsUndef = isUndef;
269  IsInternalRead = false;
270  IsEarlyClobber = false;
271  IsDebug = isDebug;
272  // Ensure isOnRegUseList() returns false.
273  Contents.Reg.Prev = nullptr;
274  // Preserve the tie when the operand was already a register.
275  if (!WasReg)
276  TiedTo = 0;
277 
278  // If this operand is embedded in a function, add the operand to the
279  // register's use/def list.
280  if (RegInfo)
281  RegInfo->addRegOperandToUseList(this);
282 }
283 
284 /// isIdenticalTo - Return true if this operand is identical to the specified
285 /// operand. Note that this should stay in sync with the hash_value overload
286 /// below.
288  if (getType() != Other.getType() ||
289  getTargetFlags() != Other.getTargetFlags())
290  return false;
291 
292  switch (getType()) {
294  return getReg() == Other.getReg() && isDef() == Other.isDef() &&
295  getSubReg() == Other.getSubReg();
297  return getImm() == Other.getImm();
299  return getCImm() == Other.getCImm();
301  return getFPImm() == Other.getFPImm();
303  return getMBB() == Other.getMBB();
305  return getIndex() == Other.getIndex();
308  return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
310  return getIndex() == Other.getIndex();
312  return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
314  return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
315  getOffset() == Other.getOffset();
317  return getBlockAddress() == Other.getBlockAddress() &&
318  getOffset() == Other.getOffset();
321  // Shallow compare of the two RegMasks
322  const uint32_t *RegMask = getRegMask();
323  const uint32_t *OtherRegMask = Other.getRegMask();
324  if (RegMask == OtherRegMask)
325  return true;
326 
327  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
328  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
329  unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
330  // Deep compare of the two RegMasks
331  return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
332  }
333  // We don't know the size of the RegMask, so we can't deep compare the two
334  // reg masks.
335  return false;
336  }
338  return getMCSymbol() == Other.getMCSymbol();
340  return getCFIIndex() == Other.getCFIIndex();
342  return getMetadata() == Other.getMetadata();
344  return getIntrinsicID() == Other.getIntrinsicID();
346  return getPredicate() == Other.getPredicate();
348  return getShuffleMask() == Other.getShuffleMask();
349  }
350  llvm_unreachable("Invalid machine operand type");
351 }
352 
353 // Note: this must stay exactly in sync with isIdenticalTo above.
355  switch (MO.getType()) {
357  // Register operands don't have target flags.
358  return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
360  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
362  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
364  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
366  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
368  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
371  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
372  MO.getOffset());
374  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
376  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
377  StringRef(MO.getSymbolName()));
379  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
380  MO.getOffset());
382  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
383  MO.getOffset());
386  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
387  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
388  unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
389  const uint32_t *RegMask = MO.getRegMask();
390  std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize);
391  return hash_combine(MO.getType(), MO.getTargetFlags(),
392  stable_hash_combine_array(RegMaskHashes.data(),
393  RegMaskHashes.size()));
394  }
395 
396  assert(0 && "MachineOperand not associated with any MachineFunction");
397  return hash_combine(MO.getType(), MO.getTargetFlags());
398  }
400  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
402  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
404  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
406  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
408  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
410  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
411  }
412  llvm_unreachable("Invalid machine operand type");
413 }
414 
415 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
416 // it.
417 static void tryToGetTargetInfo(const MachineOperand &MO,
418  const TargetRegisterInfo *&TRI,
419  const TargetIntrinsicInfo *&IntrinsicInfo) {
420  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
421  TRI = MF->getSubtarget().getRegisterInfo();
422  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
423  }
424 }
425 
426 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
427  const auto *TII = MF.getSubtarget().getInstrInfo();
428  assert(TII && "expected instruction info");
429  auto Indices = TII->getSerializableTargetIndices();
430  auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
431  return I.first == Index;
432  });
433  if (Found != Indices.end())
434  return Found->second;
435  return nullptr;
436 }
437 
439  const MachineFunction *MF = getMFIfAvailable(*this);
440  return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
441 }
442 
443 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
445  for (const auto &I : Flags) {
446  if (I.first == TF) {
447  return I.second;
448  }
449  }
450  return nullptr;
451 }
452 
453 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
454  const TargetRegisterInfo *TRI) {
455  if (!TRI) {
456  OS << "%dwarfreg." << DwarfReg;
457  return;
458  }
459 
460  if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
461  OS << printReg(*Reg, TRI);
462  else
463  OS << "<badreg>";
464 }
465 
467  ModuleSlotTracker &MST) {
468  OS << "%ir-block.";
469  if (BB.hasName()) {
470  printLLVMNameWithoutPrefix(OS, BB.getName());
471  return;
472  }
473  Optional<int> Slot;
474  if (const Function *F = BB.getParent()) {
475  if (F == MST.getCurrentFunction()) {
476  Slot = MST.getLocalSlot(&BB);
477  } else if (const Module *M = F->getParent()) {
478  ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
479  CustomMST.incorporateFunction(*F);
480  Slot = CustomMST.getLocalSlot(&BB);
481  }
482  }
483  if (Slot)
485  else
486  OS << "<unknown>";
487 }
488 
490  SyncScope::ID SSID,
492  switch (SSID) {
493  case SyncScope::System:
494  break;
495  default:
496  if (SSNs.empty())
498 
499  OS << "syncscope(\"";
500  printEscapedString(SSNs[SSID], OS);
501  OS << "\") ";
502  break;
503  }
504 }
505 
506 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
507  unsigned TMMOFlag) {
508  auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
509  for (const auto &I : Flags) {
510  if (I.first == TMMOFlag) {
511  return I.second;
512  }
513  }
514  return nullptr;
515 }
516 
517 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
518  const MachineFrameInfo *MFI) {
519  StringRef Name;
520  if (MFI) {
521  IsFixed = MFI->isFixedObjectIndex(FrameIndex);
522  if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
523  if (Alloca->hasName())
524  Name = Alloca->getName();
525  if (IsFixed)
527  }
529 }
530 
532  const TargetRegisterInfo *TRI) {
533  OS << "%subreg.";
534  if (TRI && Index != 0 && Index < TRI->getNumSubRegIndices())
535  OS << TRI->getSubRegIndexName(Index);
536  else
537  OS << Index;
538 }
539 
541  const MachineOperand &Op) {
542  if (!Op.getTargetFlags())
543  return;
544  const MachineFunction *MF = getMFIfAvailable(Op);
545  if (!MF)
546  return;
547 
548  const auto *TII = MF->getSubtarget().getInstrInfo();
549  assert(TII && "expected instruction info");
550  auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
551  OS << "target-flags(";
552  const bool HasDirectFlags = Flags.first;
553  const bool HasBitmaskFlags = Flags.second;
554  if (!HasDirectFlags && !HasBitmaskFlags) {
555  OS << "<unknown>) ";
556  return;
557  }
558  if (HasDirectFlags) {
559  if (const auto *Name = getTargetFlagName(TII, Flags.first))
560  OS << Name;
561  else
562  OS << "<unknown target flag>";
563  }
564  if (!HasBitmaskFlags) {
565  OS << ") ";
566  return;
567  }
568  bool IsCommaNeeded = HasDirectFlags;
569  unsigned BitMask = Flags.second;
571  for (const auto &Mask : BitMasks) {
572  // Check if the flag's bitmask has the bits of the current mask set.
573  if ((BitMask & Mask.first) == Mask.first) {
574  if (IsCommaNeeded)
575  OS << ", ";
576  IsCommaNeeded = true;
577  OS << Mask.second;
578  // Clear the bits which were serialized from the flag's bitmask.
579  BitMask &= ~(Mask.first);
580  }
581  }
582  if (BitMask) {
583  // When the resulting flag's bitmask isn't zero, we know that we didn't
584  // serialize all of the bit flags.
585  if (IsCommaNeeded)
586  OS << ", ";
587  OS << "<unknown bitmask target flag>";
588  }
589  OS << ") ";
590 }
591 
593  OS << "<mcsymbol " << Sym << ">";
594 }
595 
597  unsigned FrameIndex,
598  bool IsFixed, StringRef Name) {
599  if (IsFixed) {
600  OS << "%fixed-stack." << FrameIndex;
601  return;
602  }
603 
604  OS << "%stack." << FrameIndex;
605  if (!Name.empty())
606  OS << '.' << Name;
607 }
608 
610  if (Offset == 0)
611  return;
612  if (Offset < 0) {
613  OS << " - " << -Offset;
614  return;
615  }
616  OS << " + " << Offset;
617 }
618 
620  if (Slot == -1)
621  OS << "<badref>";
622  else
623  OS << Slot;
624 }
625 
626 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
627  const TargetRegisterInfo *TRI) {
628  switch (CFI.getOperation()) {
630  OS << "same_value ";
631  if (MCSymbol *Label = CFI.getLabel())
632  MachineOperand::printSymbol(OS, *Label);
633  printCFIRegister(CFI.getRegister(), OS, TRI);
634  break;
636  OS << "remember_state ";
637  if (MCSymbol *Label = CFI.getLabel())
638  MachineOperand::printSymbol(OS, *Label);
639  break;
641  OS << "restore_state ";
642  if (MCSymbol *Label = CFI.getLabel())
643  MachineOperand::printSymbol(OS, *Label);
644  break;
646  OS << "offset ";
647  if (MCSymbol *Label = CFI.getLabel())
648  MachineOperand::printSymbol(OS, *Label);
649  printCFIRegister(CFI.getRegister(), OS, TRI);
650  OS << ", " << CFI.getOffset();
651  break;
653  OS << "def_cfa_register ";
654  if (MCSymbol *Label = CFI.getLabel())
655  MachineOperand::printSymbol(OS, *Label);
656  printCFIRegister(CFI.getRegister(), OS, TRI);
657  break;
659  OS << "def_cfa_offset ";
660  if (MCSymbol *Label = CFI.getLabel())
661  MachineOperand::printSymbol(OS, *Label);
662  OS << CFI.getOffset();
663  break;
665  OS << "def_cfa ";
666  if (MCSymbol *Label = CFI.getLabel())
667  MachineOperand::printSymbol(OS, *Label);
668  printCFIRegister(CFI.getRegister(), OS, TRI);
669  OS << ", " << CFI.getOffset();
670  break;
672  OS << "llvm_def_aspace_cfa ";
673  if (MCSymbol *Label = CFI.getLabel())
674  MachineOperand::printSymbol(OS, *Label);
675  printCFIRegister(CFI.getRegister(), OS, TRI);
676  OS << ", " << CFI.getOffset();
677  OS << ", " << CFI.getAddressSpace();
678  break;
680  OS << "rel_offset ";
681  if (MCSymbol *Label = CFI.getLabel())
682  MachineOperand::printSymbol(OS, *Label);
683  printCFIRegister(CFI.getRegister(), OS, TRI);
684  OS << ", " << CFI.getOffset();
685  break;
687  OS << "adjust_cfa_offset ";
688  if (MCSymbol *Label = CFI.getLabel())
689  MachineOperand::printSymbol(OS, *Label);
690  OS << CFI.getOffset();
691  break;
693  OS << "restore ";
694  if (MCSymbol *Label = CFI.getLabel())
695  MachineOperand::printSymbol(OS, *Label);
696  printCFIRegister(CFI.getRegister(), OS, TRI);
697  break;
699  OS << "escape ";
700  if (MCSymbol *Label = CFI.getLabel())
701  MachineOperand::printSymbol(OS, *Label);
702  if (!CFI.getValues().empty()) {
703  size_t e = CFI.getValues().size() - 1;
704  for (size_t i = 0; i < e; ++i)
705  OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
706  OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
707  }
708  break;
709  }
711  OS << "undefined ";
712  if (MCSymbol *Label = CFI.getLabel())
713  MachineOperand::printSymbol(OS, *Label);
714  printCFIRegister(CFI.getRegister(), OS, TRI);
715  break;
717  OS << "register ";
718  if (MCSymbol *Label = CFI.getLabel())
719  MachineOperand::printSymbol(OS, *Label);
720  printCFIRegister(CFI.getRegister(), OS, TRI);
721  OS << ", ";
722  printCFIRegister(CFI.getRegister2(), OS, TRI);
723  break;
725  OS << "window_save ";
726  if (MCSymbol *Label = CFI.getLabel())
727  MachineOperand::printSymbol(OS, *Label);
728  break;
730  OS << "negate_ra_sign_state ";
731  if (MCSymbol *Label = CFI.getLabel())
732  MachineOperand::printSymbol(OS, *Label);
733  break;
734  default:
735  // TODO: Print the other CFI Operations.
736  OS << "<unserializable cfi directive>";
737  break;
738  }
739 }
740 
742  const TargetIntrinsicInfo *IntrinsicInfo) const {
743  print(OS, LLT{}, TRI, IntrinsicInfo);
744 }
745 
746 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
747  const TargetRegisterInfo *TRI,
748  const TargetIntrinsicInfo *IntrinsicInfo) const {
749  tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
750  ModuleSlotTracker DummyMST(nullptr);
751  print(OS, DummyMST, TypeToPrint, None, /*PrintDef=*/false,
752  /*IsStandalone=*/true,
753  /*ShouldPrintRegisterTies=*/true,
754  /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
755 }
756 
758  LLT TypeToPrint, Optional<unsigned> OpIdx, bool PrintDef,
759  bool IsStandalone, bool ShouldPrintRegisterTies,
760  unsigned TiedOperandIdx,
761  const TargetRegisterInfo *TRI,
762  const TargetIntrinsicInfo *IntrinsicInfo) const {
763  printTargetFlags(OS, *this);
764  switch (getType()) {
766  Register Reg = getReg();
767  if (isImplicit())
768  OS << (isDef() ? "implicit-def " : "implicit ");
769  else if (PrintDef && isDef())
770  // Print the 'def' flag only when the operand is defined after '='.
771  OS << "def ";
772  if (isInternalRead())
773  OS << "internal ";
774  if (isDead())
775  OS << "dead ";
776  if (isKill())
777  OS << "killed ";
778  if (isUndef())
779  OS << "undef ";
780  if (isEarlyClobber())
781  OS << "early-clobber ";
783  OS << "renamable ";
784  // isDebug() is exactly true for register operands of a DBG_VALUE. So we
785  // simply infer it when parsing and do not need to print it.
786 
787  const MachineRegisterInfo *MRI = nullptr;
789  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
790  MRI = &MF->getRegInfo();
791  }
792  }
793 
794  OS << printReg(Reg, TRI, 0, MRI);
795  // Print the sub register.
796  if (unsigned SubReg = getSubReg()) {
797  if (TRI)
798  OS << '.' << TRI->getSubRegIndexName(SubReg);
799  else
800  OS << ".subreg" << SubReg;
801  }
802  // Print the register class / bank.
804  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
805  const MachineRegisterInfo &MRI = MF->getRegInfo();
806  if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
807  OS << ':';
808  OS << printRegClassOrBank(Reg, MRI, TRI);
809  }
810  }
811  }
812  // Print ties.
813  if (ShouldPrintRegisterTies && isTied() && !isDef())
814  OS << "(tied-def " << TiedOperandIdx << ")";
815  // Print types.
816  if (TypeToPrint.isValid())
817  OS << '(' << TypeToPrint << ')';
818  break;
819  }
821  const MIRFormatter *Formatter = nullptr;
822  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
823  const auto *TII = MF->getSubtarget().getInstrInfo();
824  assert(TII && "expected instruction info");
825  Formatter = TII->getMIRFormatter();
826  }
827  if (Formatter)
828  Formatter->printImm(OS, *getParent(), OpIdx, getImm());
829  else
830  OS << getImm();
831  break;
832  }
834  getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
835  break;
837  getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
838  break;
840  OS << printMBBReference(*getMBB());
841  break;
843  int FrameIndex = getIndex();
844  bool IsFixed = false;
845  const MachineFrameInfo *MFI = nullptr;
846  if (const MachineFunction *MF = getMFIfAvailable(*this))
847  MFI = &MF->getFrameInfo();
848  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
849  break;
850  }
852  OS << "%const." << getIndex();
854  break;
856  OS << "target-index(";
857  const char *Name = "<unknown>";
858  if (const MachineFunction *MF = getMFIfAvailable(*this))
859  if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
860  Name = TargetIndexName;
861  OS << Name << ')';
863  break;
864  }
867  break;
869  getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
871  break;
873  StringRef Name = getSymbolName();
874  OS << '&';
875  if (Name.empty()) {
876  OS << "\"\"";
877  } else {
878  printLLVMNameWithoutPrefix(OS, Name);
879  }
881  break;
882  }
884  OS << "blockaddress(";
885  getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
886  MST);
887  OS << ", ";
888  printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
889  OS << ')';
891  break;
892  }
894  OS << "<regmask";
895  if (TRI) {
896  unsigned NumRegsInMask = 0;
897  unsigned NumRegsEmitted = 0;
898  for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
899  unsigned MaskWord = i / 32;
900  unsigned MaskBit = i % 32;
901  if (getRegMask()[MaskWord] & (1 << MaskBit)) {
902  if (PrintRegMaskNumRegs < 0 ||
903  NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
904  OS << " " << printReg(i, TRI);
905  NumRegsEmitted++;
906  }
907  NumRegsInMask++;
908  }
909  }
910  if (NumRegsEmitted != NumRegsInMask)
911  OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
912  } else {
913  OS << " ...";
914  }
915  OS << ">";
916  break;
917  }
919  const uint32_t *RegMask = getRegLiveOut();
920  OS << "liveout(";
921  if (!TRI) {
922  OS << "<unknown>";
923  } else {
924  bool IsCommaNeeded = false;
925  for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
926  if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
927  if (IsCommaNeeded)
928  OS << ", ";
929  OS << printReg(Reg, TRI);
930  IsCommaNeeded = true;
931  }
932  }
933  }
934  OS << ")";
935  break;
936  }
938  getMetadata()->printAsOperand(OS, MST);
939  break;
941  printSymbol(OS, *getMCSymbol());
942  break;
944  if (const MachineFunction *MF = getMFIfAvailable(*this))
945  printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
946  else
947  OS << "<cfi directive>";
948  break;
949  }
952  if (ID < Intrinsic::num_intrinsics)
953  OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';
954  else if (IntrinsicInfo)
955  OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
956  else
957  OS << "intrinsic(" << ID << ')';
958  break;
959  }
961  auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
962  OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
963  << CmpInst::getPredicateName(Pred) << ')';
964  break;
965  }
967  OS << "shufflemask(";
969  StringRef Separator;
970  for (int Elt : Mask) {
971  if (Elt == -1)
972  OS << Separator << "undef";
973  else
974  OS << Separator << Elt;
975  Separator = ", ";
976  }
977 
978  OS << ')';
979  break;
980  }
981 }
982 
983 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
984 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
985 #endif
986 
987 //===----------------------------------------------------------------------===//
988 // MachineMemOperand Implementation
989 //===----------------------------------------------------------------------===//
990 
991 /// getAddrSpace - Return the LLVM IR address space number that this pointer
992 /// points into.
993 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
994 
995 /// isDereferenceable - Return true if V is always dereferenceable for
996 /// Offset + Size byte.
998  const DataLayout &DL) const {
999  if (!V.is<const Value *>())
1000  return false;
1001 
1002  const Value *BasePtr = V.get<const Value *>();
1003  if (BasePtr == nullptr)
1004  return false;
1005 
1007  BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
1008 }
1009 
1010 /// getConstantPool - Return a MachinePointerInfo record that refers to the
1011 /// constant pool.
1014 }
1015 
1016 /// getFixedStack - Return a MachinePointerInfo record that refers to the
1017 /// the specified FrameIndex.
1019  int FI, int64_t Offset) {
1021 }
1022 
1025 }
1026 
1028  return MachinePointerInfo(MF.getPSVManager().getGOT());
1029 }
1030 
1032  int64_t Offset, uint8_t ID) {
1034 }
1035 
1038 }
1039 
1041  LLT type, Align a, const AAMDNodes &AAInfo,
1042  const MDNode *Ranges, SyncScope::ID SSID,
1043  AtomicOrdering Ordering,
1044  AtomicOrdering FailureOrdering)
1045  : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),
1046  AAInfo(AAInfo), Ranges(Ranges) {
1047  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1048  isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1049  "invalid pointer value");
1050  assert((isLoad() || isStore()) && "Not a load/store!");
1051 
1052  AtomicInfo.SSID = static_cast<unsigned>(SSID);
1053  assert(getSyncScopeID() == SSID && "Value truncated");
1054  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1055  assert(getSuccessOrdering() == Ordering && "Value truncated");
1056  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1057  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1058 }
1059 
1061  uint64_t s, Align a,
1062  const AAMDNodes &AAInfo,
1063  const MDNode *Ranges, SyncScope::ID SSID,
1064  AtomicOrdering Ordering,
1065  AtomicOrdering FailureOrdering)
1066  : MachineMemOperand(ptrinfo, f,
1067  s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
1068  AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1069 
1070 /// Profile - Gather unique data for the object.
1071 ///
1073  ID.AddInteger(getOffset());
1074  ID.AddInteger(getMemoryType().getUniqueRAWLLTData());
1075  ID.AddPointer(getOpaqueValue());
1076  ID.AddInteger(getFlags());
1077  ID.AddInteger(getBaseAlign().value());
1078 }
1079 
1081  // The Value and Offset may differ due to CSE. But the flags and size
1082  // should be the same.
1083  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1084  assert((MMO->getSize() == ~UINT64_C(0) || getSize() == ~UINT64_C(0) ||
1085  MMO->getSize() == getSize()) &&
1086  "Size mismatch!");
1087 
1088  if (MMO->getBaseAlign() >= getBaseAlign()) {
1089  // Update the alignment value.
1090  BaseAlign = MMO->getBaseAlign();
1091  // Also update the base and offset, because the new alignment may
1092  // not be applicable with the old ones.
1093  PtrInfo = MMO->PtrInfo;
1094  }
1095 }
1096 
1097 /// getAlign - Return the minimum known alignment in bytes of the
1098 /// actual memory reference.
1100  return commonAlignment(getBaseAlign(), getOffset());
1101 }
1102 
1105  const LLVMContext &Context,
1106  const MachineFrameInfo *MFI,
1107  const TargetInstrInfo *TII) const {
1108  OS << '(';
1109  if (isVolatile())
1110  OS << "volatile ";
1111  if (isNonTemporal())
1112  OS << "non-temporal ";
1113  if (isDereferenceable())
1114  OS << "dereferenceable ";
1115  if (isInvariant())
1116  OS << "invariant ";
1117  if (TII) {
1120  << "\" ";
1123  << "\" ";
1126  << "\" ";
1127  } else {
1129  OS << "\"MOTargetFlag1\" ";
1131  OS << "\"MOTargetFlag2\" ";
1133  OS << "\"MOTargetFlag3\" ";
1134  }
1135 
1136  assert((isLoad() || isStore()) &&
1137  "machine memory operand must be a load or store (or both)");
1138  if (isLoad())
1139  OS << "load ";
1140  if (isStore())
1141  OS << "store ";
1142 
1143  printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1144 
1146  OS << toIRString(getSuccessOrdering()) << ' ';
1148  OS << toIRString(getFailureOrdering()) << ' ';
1149 
1150  if (getMemoryType().isValid())
1151  OS << '(' << getMemoryType() << ')';
1152  else
1153  OS << "unknown-size";
1154 
1155  if (const Value *Val = getValue()) {
1156  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1157  MIRFormatter::printIRValue(OS, *Val, MST);
1158  } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1159  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1160  assert(PVal && "Expected a pseudo source value");
1161  switch (PVal->kind()) {
1163  OS << "stack";
1164  break;
1166  OS << "got";
1167  break;
1169  OS << "jump-table";
1170  break;
1172  OS << "constant-pool";
1173  break;
1175  int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1176  bool IsFixed = true;
1177  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1178  break;
1179  }
1181  OS << "call-entry ";
1182  cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1183  OS, /*PrintType=*/false, MST);
1184  break;
1186  OS << "call-entry &";
1188  OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1189  break;
1190  default: {
1191  const MIRFormatter *Formatter = TII->getMIRFormatter();
1192  // FIXME: This is not necessarily the correct MIR serialization format for
1193  // a custom pseudo source value, but at least it allows
1194  // MIR printing to work on a target with custom pseudo source
1195  // values.
1196  OS << "custom \"";
1197  Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1198  OS << '\"';
1199  break;
1200  }
1201  }
1202  } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1203  OS << ((isLoad() && isStore()) ? " on "
1204  : isLoad() ? " from "
1205  : " into ")
1206  << "unknown-address";
1207  }
1209  if (getSize() > 0 && getAlign() != getSize())
1210  OS << ", align " << getAlign().value();
1211  if (getAlign() != getBaseAlign())
1212  OS << ", basealign " << getBaseAlign().value();
1213  auto AAInfo = getAAInfo();
1214  if (AAInfo.TBAA) {
1215  OS << ", !tbaa ";
1216  AAInfo.TBAA->printAsOperand(OS, MST);
1217  }
1218  if (AAInfo.Scope) {
1219  OS << ", !alias.scope ";
1220  AAInfo.Scope->printAsOperand(OS, MST);
1221  }
1222  if (AAInfo.NoAlias) {
1223  OS << ", !noalias ";
1224  AAInfo.NoAlias->printAsOperand(OS, MST);
1225  }
1226  if (getRanges()) {
1227  OS << ", !range ";
1228  getRanges()->printAsOperand(OS, MST);
1229  }
1230  // FIXME: Implement addrspace printing/parsing in MIR.
1231  // For now, print this even though parsing it is not available in MIR.
1232  if (unsigned AS = getAddrSpace())
1233  OS << ", addrspace " << AS;
1234 
1235  OS << ')';
1236 }
llvm::Intrinsic::getBaseName
StringRef getBaseName(ID id)
Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....
Definition: Function.cpp:937
i
i
Definition: README.txt:29
llvm::MCCFIInstruction::OpWindowSave
@ OpWindowSave
Definition: MCDwarf.h:495
llvm::MIRFormatter::printIRValue
static void printIRValue(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)
Helper functions to print IR value as MIR serialization format which will be useful for target specif...
Definition: MIRPrinter.cpp:937
printCFI
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
Definition: MachineOperand.cpp:626
llvm::MachineMemOperand::MachineMemOperand
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.
Definition: MachineOperand.cpp:1060
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:62
llvm::MachineMemOperand::isStore
bool isStore() const
Definition: MachineMemOperand.h:288
llvm::PseudoSourceValueManager::getGOT
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like).
Definition: PseudoSourceValue.cpp:112
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:52
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:492
llvm::PointerUnion::isNull
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:142
llvm::ModuleSlotTracker::getLocalSlot
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:875
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::PseudoSourceValue::GlobalValueCallEntry
@ GlobalValueCallEntry
Definition: PseudoSourceValue.h:43
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::MCCFIInstruction::OpRelOffset
@ OpRelOffset
Definition: MCDwarf.h:489
tryToGetTargetInfo
static void tryToGetTargetInfo(const MachineOperand &MO, const TargetRegisterInfo *&TRI, const TargetIntrinsicInfo *&IntrinsicInfo)
Definition: MachineOperand.cpp:417
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::MCCFIInstruction::OpDefCfaRegister
@ OpDefCfaRegister
Definition: MCDwarf.h:486
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1099
llvm::MachineOperand::MO_ShuffleMask
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
Definition: MachineOperand.h:70
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:572
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
Loads.h
llvm::MachineOperand::MO_RegisterLiveOut
@ MO_RegisterLiveOut
Mask of live-out registers.
Definition: MachineOperand.h:64
llvm::Function
Definition: Function.h:60
llvm::MachineMemOperand::print
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
Definition: MachineOperand.cpp:1103
llvm::MCCFIInstruction::OpOffset
@ OpOffset
Definition: MCDwarf.h:484
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:95
getMFIfAvailable
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
Definition: MachineOperand.cpp:42
llvm::MachinePointerInfo::getConstantPool
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
Definition: MachineOperand.cpp:1012
llvm::MachineOperand::printStackObjectReference
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Definition: MachineOperand.cpp:596
llvm::MachineOperand::printIRSlotNumber
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
Definition: MachineOperand.cpp:619
llvm::stable_hash_combine_array
stable_hash stable_hash_combine_array(const stable_hash *P, size_t C)
Definition: StableHashing.h:92
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:592
llvm::MachinePointerInfo::getUnknownStack
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
Definition: MachineOperand.cpp:1036
llvm::printLLVMNameWithoutPrefix
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:356
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:741
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:577
llvm::MachineMemOperand::isLoad
bool isLoad() const
Definition: MachineMemOperand.h:287
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:226
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:117
llvm::ModuleSlotTracker::getCurrentFunction
const Function * getCurrentFunction() const
Definition: ModuleSlotTracker.h:81
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:440
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::MachineMemOperand::MOTargetFlag2
@ MOTargetFlag2
Definition: MachineMemOperand.h:151
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:652
llvm::MachineMemOperand::getOpaqueValue
const void * getOpaqueValue() const
Definition: MachineMemOperand.h:216
llvm::HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
Definition: HexagonInstrInfo.cpp:2084
MachineJumpTableInfo.h
TargetInstrInfo.h
llvm::Metadata::printAsOperand
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4865
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineOperand::MO_CFIIndex
@ MO_CFIIndex
MCCFIInstruction index.
Definition: MachineOperand.h:67
llvm::MachineOperand::getTargetIndexName
const char * getTargetIndexName() const
getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...
Definition: MachineOperand.cpp:438
llvm::MachineFunction::getPSVManager
PseudoSourceValueManager & getPSVManager() const
Definition: MachineFunction.h:617
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
llvm::HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
Definition: HexagonInstrInfo.cpp:2065
llvm::Optional< unsigned >
llvm::LLVMContext::getSyncScopeNames
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
Definition: LLVMContext.cpp:314
llvm::MachineOperand::ChangeToTargetIndex
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
Definition: MachineOperand.cpp:225
llvm::ModuleSlotTracker::incorporateFunction
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:861
llvm::MachineMemOperand::isInvariant
bool isInvariant() const
Definition: MachineMemOperand.h:292
llvm::PseudoSourceValueManager::getStack
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function,...
Definition: PseudoSourceValue.cpp:108
llvm::MachineOperand::ChangeToFrameIndex
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
Definition: MachineOperand.cpp:214
llvm::CmpInst::getPredicateName
static StringRef getPredicateName(Predicate P)
Definition: Instructions.cpp:4095
llvm::AAMDNodes::Scope
MDNode * Scope
The tag for alias scope specification (used with noalias).
Definition: Metadata.h:675
llvm::minidump::MemoryType
MemoryType
Definition: Minidump.h:98
llvm::MachineMemOperand::getAAInfo
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Definition: MachineMemOperand.h:257
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:609
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineOperand::dump
void dump() const
Definition: MachineOperand.cpp:984
llvm::PointerUnion::get
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:155
llvm::MachinePointerInfo::getJumpTable
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Definition: MachineOperand.cpp:1023
llvm::commonAlignment
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:213
llvm::MachineOperand::getMCSymbol
MCSymbol * getMCSymbol() const
Definition: MachineOperand.h:582
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:51
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::PseudoSourceValue::JumpTable
@ JumpTable
Definition: PseudoSourceValue.h:40
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::PointerUnion::is
bool is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:150
llvm::lltok::equal
@ equal
Definition: LLToken.h:25
a
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
Definition: README.txt:489
llvm::MachineOperand::printSymbol
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
Definition: MachineOperand.cpp:592
isUndef
static bool isUndef(ArrayRef< int > Mask)
Definition: HexagonISelDAGToDAGHVX.cpp:910
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition: TargetIntrinsicInfo.h:29
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachinePointerInfo::Offset
int64_t Offset
Offset - This is an offset from the base Value*.
Definition: MachineMemOperand.h:44
llvm::MCCFIInstruction::OpDefCfa
@ OpDefCfa
Definition: MCDwarf.h:488
llvm::MachineOperand::printSubRegIdx
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Definition: MachineOperand.cpp:531
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:118
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition: MachineMemOperand.h:150
llvm::MCCFIInstruction::OpUndefined
@ OpUndefined
Definition: MCDwarf.h:493
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
TargetMachine.h
StableHashing.h
Constants.h
llvm::MachineMemOperand::getBaseAlign
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
Definition: MachineMemOperand.h:254
llvm::MachineOperand::ChangeToRegister
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Definition: MachineOperand.cpp:241
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:61
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:228
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
getTargetIndexName
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
Definition: MachineOperand.cpp:426
llvm::MachineOperand::getRegMaskSize
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
Definition: MachineOperand.h:645
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:210
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineOperand::getRegMask
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Definition: MachineOperand.h:639
llvm::MachineOperand::setSubReg
void setSubReg(unsigned subReg)
Definition: MachineOperand.h:480
llvm::MachineOperand::MO_FrameIndex
@ MO_FrameIndex
Abstract Stack Frame Index.
Definition: MachineOperand.h:56
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MCCFIInstruction::getOffset
int getOffset() const
Definition: MCDwarf.h:663
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1027
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:156
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
IRPrintingPasses.h
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::PseudoSourceValue::FixedStack
@ FixedStack
Definition: PseudoSourceValue.h:42
llvm::MachineOperand::ChangeToMCSymbol
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
Definition: MachineOperand.cpp:203
llvm::MCCFIInstruction::getOperation
OpType getOperation() const
Definition: MCDwarf.h:641
llvm::printJumpTableEntryReference
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
Definition: MachineFunction.cpp:1375
llvm::MachineOperand::setTargetFlags
void setTargetFlags(unsigned F)
Definition: MachineOperand.h:223
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:688
printCFIRegister
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
Definition: MachineOperand.cpp:453
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:407
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(const Value *v, int64_t offset=0, uint8_t ID=0)
Definition: MachineMemOperand.h:50
llvm::MCCFIInstruction::getRegister
unsigned getRegister() const
Definition: MCDwarf.h:644
isDebug
static bool isDebug()
Definition: HexagonGenInsert.cpp:83
llvm::MachineOperand::printOperandOffset
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
Definition: MachineOperand.cpp:609
llvm::MachineMemOperand::getSyncScopeID
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
Definition: MachineMemOperand.h:263
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MCCFIInstruction
Definition: MCDwarf.h:478
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:434
llvm::MCRegisterInfo::getLLVMRegNum
Optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
Definition: MCRegisterInfo.cpp:81
llvm::MachineMemOperand::Profile
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
Definition: MachineOperand.cpp:1072
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition: MachineOperand.h:655
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::PseudoSourceValue::ExternalSymbolCallEntry
@ ExternalSymbolCallEntry
Definition: PseudoSourceValue.h:44
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::cl::opt
Definition: CommandLine.h:1412
llvm::MachineOperand::MO_Metadata
@ MO_Metadata
Metadata reference (for debug info)
Definition: MachineOperand.h:65
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineOperand::ChangeToFPImmediate
void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
Definition: MachineOperand.cpp:166
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:394
type
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference and DH registers in an instruction requiring REX prefix divb and mulb both produce results in AH If isel emits a CopyFromReg which gets turned into a movb and that can be allocated a r8b r15b To get around isel emits a CopyFromReg from AX and then right shift it down by and truncate it It s not pretty but it works We need some register allocation magic to make the hack go which would often require a callee saved register Callees usually need to keep this value live for most of their body so it doesn t add a significant burden on them We currently implement this in however this is suboptimal because it means that it would be quite awkward to implement the optimization for callers A better implementation would be to relax the LLVM IR rules for sret arguments to allow a function with an sret argument to have a non void return type
Definition: README-X86-64.txt:70
llvm::MCCFIInstruction::OpDefCfaOffset
@ OpDefCfaOffset
Definition: MCDwarf.h:487
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:220
llvm::MachineOperand::substVirtReg
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Definition: MachineOperand.cpp:77
llvm::MachinePointerInfo::isDereferenceable
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
Definition: MachineOperand.cpp:997
llvm::SyncScope::System
@ System
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:57
llvm::MCCFIInstruction::OpRestore
@ OpRestore
Definition: MCDwarf.h:492
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:551
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineMemOperand::isDereferenceable
bool isDereferenceable() const
Definition: MachineMemOperand.h:291
uint64_t
s
multiplies can be turned into SHL s
Definition: README.txt:370
llvm::MCCFIInstruction::OpSameValue
@ OpSameValue
Definition: MCDwarf.h:481
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::SyncScope::ID
uint8_t ID
Definition: LLVMContext.h:46
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:384
llvm::MachineOperand::MO_Predicate
@ MO_Predicate
Generic predicate for ISel.
Definition: MachineOperand.h:69
I
#define I(x, y, z)
Definition: MD5.cpp:58
StringExtras.h
llvm::MachineOperand::MO_MCSymbol
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
Definition: MachineOperand.h:66
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:218
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition: MachineOperand.h:556
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:597
llvm::PseudoSourceValue::ConstantPool
@ ConstantPool
Definition: PseudoSourceValue.h:41
llvm::MCCFIInstruction::getRegister2
unsigned getRegister2() const
Definition: MCDwarf.h:653
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::MIRFormatter::printImm
virtual void printImm(raw_ostream &OS, const MachineInstr &MI, Optional< unsigned > OpIdx, int64_t Imm) const
Implement target specific printing for machine operand immediate value, so that we can have more mean...
Definition: MIRFormatter.h:39
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition: MachineOperand.h:435
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::MachineMemOperand::getSuccessOrdering
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
Definition: MachineMemOperand.h:270
MIRFormatter.h
llvm::MachineOperand::getShuffleMask
ArrayRef< int > getShuffleMask() const
Definition: MachineOperand.h:602
llvm::MachineOperand::MO_TargetIndex
@ MO_TargetIndex
Target-dependent index+offset operand.
Definition: MachineOperand.h:58
PrintRegMaskNumRegs
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
llvm::MachineMemOperand::getMemoryType
LLT getMemoryType() const
Return the memory type of the memory reference.
Definition: MachineMemOperand.h:232
llvm::MCCFIInstruction::OpAdjustCfaOffset
@ OpAdjustCfaOffset
Definition: MCDwarf.h:490
llvm::MachineOperand::MO_FPImmediate
@ MO_FPImmediate
Floating-point immediate operand.
Definition: MachineOperand.h:54
printFrameIndex
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
Definition: MachineOperand.cpp:517
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::MDNode
Metadata node.
Definition: Metadata.h:944
llvm::Value::printAsOperand
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:4759
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MCCFIInstruction::OpEscape
@ OpEscape
Definition: MCDwarf.h:491
llvm::CmpInst::isIntPredicate
bool isIntPredicate() const
Definition: InstrTypes.h:827
llvm::MachineOperand::MO_JumpTableIndex
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition: MachineOperand.h:59
llvm::MachineOperand::MO_CImmediate
@ MO_CImmediate
Immediate >64bit operand.
Definition: MachineOperand.h:53
llvm::printRegClassOrBank
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Definition: TargetRegisterInfo.cpp:175
llvm::MachineMemOperand::MOTargetFlag3
@ MOTargetFlag3
Definition: MachineMemOperand.h:152
llvm::MachineOperand::setIsDef
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Definition: MachineOperand.cpp:101
llvm::ArrayRef< int >
llvm::MCCFIInstruction::getAddressSpace
unsigned getAddressSpace() const
Definition: MCDwarf.h:658
llvm::MCCFIInstruction::OpRememberState
@ OpRememberState
Definition: MCDwarf.h:482
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
llvm::HexagonInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
Definition: HexagonInstrInfo.cpp:2059
llvm::MachinePointerInfo::V
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Definition: MachineMemOperand.h:41
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MCCFIInstruction::getValues
StringRef getValues() const
Definition: MCDwarf.h:671
llvm::MachineOperand::ChangeToES
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Definition: MachineOperand.cpp:177
llvm::TargetRegisterInfo::composeSubRegIndices
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Definition: TargetRegisterInfo.h:663
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:520
uint32_t
llvm::MachineOperand::setIsRenamable
void setIsRenamable(bool Val=true)
Definition: MachineOperand.cpp:136
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:55
llvm::MCCFIInstruction::OpLLVMDefAspaceCfa
@ OpLLVMDefAspaceCfa
Definition: MCDwarf.h:485
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachinePointerInfo::AddrSpace
unsigned AddrSpace
Definition: MachineMemOperand.h:46
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::FoldingSetNodeID
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:318
llvm::MachineOperand::MO_IntrinsicID
@ MO_IntrinsicID
Intrinsic ID for ISel.
Definition: MachineOperand.h:68
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:302
llvm::format
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
llvm::DataLayout::getAllocaAddrSpace
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:282
llvm::MachineOperand::setIndex
void setIndex(int Idx)
Definition: MachineOperand.h:687
llvm::TargetIntrinsicInfo::getName
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
llvm::MachinePointerInfo::getAddrSpace
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Definition: MachineOperand.cpp:993
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
FoldingSet.h
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1736
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::PseudoSourceValueManager::getJumpTable
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
Definition: PseudoSourceValue.cpp:118
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::PseudoSourceValue::GOT
@ GOT
Definition: PseudoSourceValue.h:39
llvm::MachineMemOperand::isVolatile
bool isVolatile() const
Definition: MachineMemOperand.h:289
llvm::BlockAddress::getFunction
Function * getFunction() const
Definition: Constants.h:877
llvm::MachineOperand::printTargetFlags
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
Definition: MachineOperand.cpp:540
llvm::MachineOperand::ChangeToGA
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
Definition: MachineOperand.cpp:190
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:263
llvm::None
constexpr std::nullopt_t None
Definition: None.h:27
llvm::AAMDNodes::NoAlias
MDNode * NoAlias
The tag specifying the noalias scope.
Definition: Metadata.h:678
getTargetFlagName
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
Definition: MachineOperand.cpp:443
llvm::PseudoSourceValueManager::getFixedStack
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot.
Definition: PseudoSourceValue.cpp:123
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:235
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:60
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:566
llvm::MachineOperand::getCFIIndex
unsigned getCFIIndex() const
Definition: MachineOperand.h:587
llvm::PseudoSourceValue::Stack
@ Stack
Definition: PseudoSourceValue.h:38
llvm::MachineMemOperand::refineAlignment
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
Definition: MachineOperand.cpp:1080
llvm::MCCFIInstruction::OpRegister
@ OpRegister
Definition: MCDwarf.h:494
llvm::AAMDNodes::TBAA
MDNode * TBAA
The tag for type-based alias analysis.
Definition: Metadata.h:669
llvm::hash_value
hash_code hash_value(const FixedPointSemantics &Val)
Definition: APFixedPoint.h:127
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:445
llvm::MachineInstr::IgnoreBundle
@ IgnoreBundle
Definition: MachineInstr.h:809
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:28
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:184
Instructions.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1018
llvm::hash_combine
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:605
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:617
TargetIntrinsicInfo.h
getTargetMMOFlagName
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
Definition: MachineOperand.cpp:506
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::toIRString
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
Definition: AtomicOrdering.h:81
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:285
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition: MachineOperand.h:430
llvm::MachineOperand::getRegLiveOut
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
Definition: MachineOperand.h:650
ModuleSlotTracker.h
llvm::SmallVectorImpl< StringRef >
llvm::MachineMemOperand::getFailureOrdering
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
Definition: MachineMemOperand.h:276
MachineOperand.h
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1142
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition: MachineOperand.cpp:87
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::AllocaInst
an instruction to allocate memory on the stack
Definition: Instructions.h:58
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:63
printIRBlockReference
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
Definition: MachineOperand.cpp:466
llvm::cl::desc
Definition: CommandLine.h:413
llvm::MachineMemOperand::isNonTemporal
bool isNonTemporal() const
Definition: MachineMemOperand.h:290
llvm::TargetRegisterInfo::getSubRegIndexName
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition: TargetRegisterInfo.h:371
llvm::MachineMemOperand::getRanges
const MDNode * getRanges() const
Return the range tag for the memory reference.
Definition: MachineMemOperand.h:260
llvm::MCCFIInstruction::OpNegateRAState
@ OpNegateRAState
Definition: MCDwarf.h:496
llvm::MIRFormatter::printCustomPseudoSourceValue
virtual void printCustomPseudoSourceValue(raw_ostream &OS, ModuleSlotTracker &MST, const PseudoSourceValue &PSV) const
Implement target specific printing of target custom pseudo source value.
Definition: MIRFormatter.h:56
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1031
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:219
TargetRegisterInfo.h
llvm::MCCFIInstruction::OpRestoreState
@ OpRestoreState
Definition: MCDwarf.h:483
llvm::PseudoSourceValueManager::getConstantPool
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
Definition: PseudoSourceValue.cpp:114
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::AtomicOrdering::NotAtomic
@ NotAtomic
llvm::isDereferenceableAndAlignedPointer
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
Definition: Loads.cpp:201
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1251
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:287
llvm::MCCFIInstruction::getLabel
MCSymbol * getLabel() const
Definition: MCDwarf.h:642
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:212
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::hash_code
An opaque object representing a hash code.
Definition: Hashing.h:73
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:57
llvm::MachineFrameInfo::getObjectAllocation
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
Definition: MachineFrameInfo.h:510
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::MachineOperand::setOffset
void setOffset(int64_t Offset)
Definition: MachineOperand.h:679
printSyncScope
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)
Definition: MachineOperand.cpp:489