LLVM  13.0.0git
MachineOperand.cpp
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1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/FoldingSet.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
25 #include "llvm/Config/llvm-config.h"
26 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/Instructions.h"
30 #include "llvm/MC/MCDwarf.h"
33 
34 using namespace llvm;
35 
36 static cl::opt<int>
37  PrintRegMaskNumRegs("print-regmask-num-regs",
38  cl::desc("Number of registers to limit to when "
39  "printing regmask operands in IR dumps. "
40  "unlimited = -1"),
41  cl::init(32), cl::Hidden);
42 
44  if (const MachineInstr *MI = MO.getParent())
45  if (const MachineBasicBlock *MBB = MI->getParent())
46  if (const MachineFunction *MF = MBB->getParent())
47  return MF;
48  return nullptr;
49 }
51  return const_cast<MachineFunction *>(
52  getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
53 }
54 
56  if (getReg() == Reg)
57  return; // No change.
58 
59  // Clear the IsRenamable bit to keep it conservatively correct.
60  IsRenamable = false;
61 
62  // Otherwise, we have to change the register. If this operand is embedded
63  // into a machine function, we need to update the old and new register's
64  // use/def lists.
65  if (MachineFunction *MF = getMFIfAvailable(*this)) {
66  MachineRegisterInfo &MRI = MF->getRegInfo();
68  SmallContents.RegNo = Reg;
70  return;
71  }
72 
73  // Otherwise, just change the register, no problem. :)
74  SmallContents.RegNo = Reg;
75 }
76 
78  const TargetRegisterInfo &TRI) {
79  assert(Reg.isVirtual());
80  if (SubIdx && getSubReg())
81  SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
82  setReg(Reg);
83  if (SubIdx)
84  setSubReg(SubIdx);
85 }
86 
89  if (getSubReg()) {
91  // Note that getSubReg() may return 0 if the sub-register doesn't exist.
92  // That won't happen in legal code.
93  setSubReg(0);
94  if (isDef())
95  setIsUndef(false);
96  }
97  setReg(Reg);
98 }
99 
100 /// Change a def to a use, or a use to a def.
101 void MachineOperand::setIsDef(bool Val) {
102  assert(isReg() && "Wrong MachineOperand accessor");
103  assert((!Val || !isDebug()) && "Marking a debug operation as def");
104  if (IsDef == Val)
105  return;
106  assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
107  // MRI may keep uses and defs in different list positions.
108  if (MachineFunction *MF = getMFIfAvailable(*this)) {
109  MachineRegisterInfo &MRI = MF->getRegInfo();
111  IsDef = Val;
113  return;
114  }
115  IsDef = Val;
116 }
117 
119  assert(isReg() && "Wrong MachineOperand accessor");
121  "isRenamable should only be checked on physical registers");
122  if (!IsRenamable)
123  return false;
124 
125  const MachineInstr *MI = getParent();
126  if (!MI)
127  return true;
128 
129  if (isDef())
130  return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
131 
132  assert(isUse() && "Reg is not def or use");
133  return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
134 }
135 
137  assert(isReg() && "Wrong MachineOperand accessor");
139  "setIsRenamable should only be called on physical registers");
140  IsRenamable = Val;
141 }
142 
143 // If this operand is currently a register operand, and if this is in a
144 // function, deregister the operand from the register's use/def list.
145 void MachineOperand::removeRegFromUses() {
146  if (!isReg() || !isOnRegUseList())
147  return;
148 
149  if (MachineFunction *MF = getMFIfAvailable(*this))
150  MF->getRegInfo().removeRegOperandFromUseList(this);
151 }
152 
153 /// ChangeToImmediate - Replace this operand with a new immediate operand of
154 /// the specified value. If an operand is known to be an immediate already,
155 /// the setImm method should be used.
156 void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
157  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
158 
159  removeRegFromUses();
160 
161  OpKind = MO_Immediate;
162  Contents.ImmVal = ImmVal;
163  setTargetFlags(TargetFlags);
164 }
165 
167  unsigned TargetFlags) {
168  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
169 
170  removeRegFromUses();
171 
172  OpKind = MO_FPImmediate;
173  Contents.CFP = FPImm;
174  setTargetFlags(TargetFlags);
175 }
176 
177 void MachineOperand::ChangeToES(const char *SymName,
178  unsigned TargetFlags) {
179  assert((!isReg() || !isTied()) &&
180  "Cannot change a tied operand into an external symbol");
181 
182  removeRegFromUses();
183 
184  OpKind = MO_ExternalSymbol;
185  Contents.OffsetedInfo.Val.SymbolName = SymName;
186  setOffset(0); // Offset is always 0.
187  setTargetFlags(TargetFlags);
188 }
189 
191  unsigned TargetFlags) {
192  assert((!isReg() || !isTied()) &&
193  "Cannot change a tied operand into a global address");
194 
195  removeRegFromUses();
196 
197  OpKind = MO_GlobalAddress;
198  Contents.OffsetedInfo.Val.GV = GV;
199  setOffset(Offset);
200  setTargetFlags(TargetFlags);
201 }
202 
203 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
204  assert((!isReg() || !isTied()) &&
205  "Cannot change a tied operand into an MCSymbol");
206 
207  removeRegFromUses();
208 
209  OpKind = MO_MCSymbol;
210  Contents.Sym = Sym;
211  setTargetFlags(TargetFlags);
212 }
213 
214 void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
215  assert((!isReg() || !isTied()) &&
216  "Cannot change a tied operand into a FrameIndex");
217 
218  removeRegFromUses();
219 
220  OpKind = MO_FrameIndex;
221  setIndex(Idx);
222  setTargetFlags(TargetFlags);
223 }
224 
225 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
226  unsigned TargetFlags) {
227  assert((!isReg() || !isTied()) &&
228  "Cannot change a tied operand into a FrameIndex");
229 
230  removeRegFromUses();
231 
232  OpKind = MO_TargetIndex;
233  setIndex(Idx);
234  setOffset(Offset);
235  setTargetFlags(TargetFlags);
236 }
237 
238 /// ChangeToRegister - Replace this operand with a new register operand of
239 /// the specified value. If an operand is known to be an register already,
240 /// the setReg method should be used.
241 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
242  bool isKill, bool isDead, bool isUndef,
243  bool isDebug) {
244  MachineRegisterInfo *RegInfo = nullptr;
245  if (MachineFunction *MF = getMFIfAvailable(*this))
246  RegInfo = &MF->getRegInfo();
247  // If this operand is already a register operand, remove it from the
248  // register's use/def lists.
249  bool WasReg = isReg();
250  if (RegInfo && WasReg)
251  RegInfo->removeRegOperandFromUseList(this);
252 
253  // Change this to a register and set the reg#.
254  assert(!(isDead && !isDef) && "Dead flag on non-def");
255  assert(!(isKill && isDef) && "Kill flag on def");
256  OpKind = MO_Register;
257  SmallContents.RegNo = Reg;
258  SubReg_TargetFlags = 0;
259  IsDef = isDef;
260  IsImp = isImp;
261  IsDeadOrKill = isKill | isDead;
262  IsRenamable = false;
263  IsUndef = isUndef;
264  IsInternalRead = false;
265  IsEarlyClobber = false;
266  IsDebug = isDebug;
267  // Ensure isOnRegUseList() returns false.
268  Contents.Reg.Prev = nullptr;
269  // Preserve the tie when the operand was already a register.
270  if (!WasReg)
271  TiedTo = 0;
272 
273  // If this operand is embedded in a function, add the operand to the
274  // register's use/def list.
275  if (RegInfo)
276  RegInfo->addRegOperandToUseList(this);
277 }
278 
279 /// isIdenticalTo - Return true if this operand is identical to the specified
280 /// operand. Note that this should stay in sync with the hash_value overload
281 /// below.
283  if (getType() != Other.getType() ||
284  getTargetFlags() != Other.getTargetFlags())
285  return false;
286 
287  switch (getType()) {
289  return getReg() == Other.getReg() && isDef() == Other.isDef() &&
290  getSubReg() == Other.getSubReg();
292  return getImm() == Other.getImm();
294  return getCImm() == Other.getCImm();
296  return getFPImm() == Other.getFPImm();
298  return getMBB() == Other.getMBB();
300  return getIndex() == Other.getIndex();
303  return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
305  return getIndex() == Other.getIndex();
307  return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
309  return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
310  getOffset() == Other.getOffset();
312  return getBlockAddress() == Other.getBlockAddress() &&
313  getOffset() == Other.getOffset();
316  // Shallow compare of the two RegMasks
317  const uint32_t *RegMask = getRegMask();
318  const uint32_t *OtherRegMask = Other.getRegMask();
319  if (RegMask == OtherRegMask)
320  return true;
321 
322  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
323  // Calculate the size of the RegMask
324  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
325  unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
326 
327  // Deep compare of the two RegMasks
328  return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
329  }
330  // We don't know the size of the RegMask, so we can't deep compare the two
331  // reg masks.
332  return false;
333  }
335  return getMCSymbol() == Other.getMCSymbol();
337  return getCFIIndex() == Other.getCFIIndex();
339  return getMetadata() == Other.getMetadata();
341  return getIntrinsicID() == Other.getIntrinsicID();
343  return getPredicate() == Other.getPredicate();
345  return getShuffleMask() == Other.getShuffleMask();
346  }
347  llvm_unreachable("Invalid machine operand type");
348 }
349 
350 // Note: this must stay exactly in sync with isIdenticalTo above.
352  switch (MO.getType()) {
354  // Register operands don't have target flags.
355  return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
357  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
359  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
361  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
363  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
365  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
368  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
369  MO.getOffset());
371  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
373  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
374  StringRef(MO.getSymbolName()));
376  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
377  MO.getOffset());
379  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
380  MO.getOffset());
383  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
385  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
387  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
389  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
391  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
393  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
395  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
396  }
397  llvm_unreachable("Invalid machine operand type");
398 }
399 
400 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
401 // it.
402 static void tryToGetTargetInfo(const MachineOperand &MO,
403  const TargetRegisterInfo *&TRI,
404  const TargetIntrinsicInfo *&IntrinsicInfo) {
405  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
406  TRI = MF->getSubtarget().getRegisterInfo();
407  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
408  }
409 }
410 
411 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
412  const auto *TII = MF.getSubtarget().getInstrInfo();
413  assert(TII && "expected instruction info");
414  auto Indices = TII->getSerializableTargetIndices();
415  auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
416  return I.first == Index;
417  });
418  if (Found != Indices.end())
419  return Found->second;
420  return nullptr;
421 }
422 
424  const MachineFunction *MF = getMFIfAvailable(*this);
425  return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
426 }
427 
428 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
430  for (const auto &I : Flags) {
431  if (I.first == TF) {
432  return I.second;
433  }
434  }
435  return nullptr;
436 }
437 
438 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
439  const TargetRegisterInfo *TRI) {
440  if (!TRI) {
441  OS << "%dwarfreg." << DwarfReg;
442  return;
443  }
444 
445  if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
446  OS << printReg(*Reg, TRI);
447  else
448  OS << "<badreg>";
449 }
450 
452  ModuleSlotTracker &MST) {
453  OS << "%ir-block.";
454  if (BB.hasName()) {
455  printLLVMNameWithoutPrefix(OS, BB.getName());
456  return;
457  }
458  Optional<int> Slot;
459  if (const Function *F = BB.getParent()) {
460  if (F == MST.getCurrentFunction()) {
461  Slot = MST.getLocalSlot(&BB);
462  } else if (const Module *M = F->getParent()) {
463  ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
464  CustomMST.incorporateFunction(*F);
465  Slot = CustomMST.getLocalSlot(&BB);
466  }
467  }
468  if (Slot)
470  else
471  OS << "<unknown>";
472 }
473 
475  SyncScope::ID SSID,
477  switch (SSID) {
478  case SyncScope::System:
479  break;
480  default:
481  if (SSNs.empty())
483 
484  OS << "syncscope(\"";
485  printEscapedString(SSNs[SSID], OS);
486  OS << "\") ";
487  break;
488  }
489 }
490 
491 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
492  unsigned TMMOFlag) {
493  auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
494  for (const auto &I : Flags) {
495  if (I.first == TMMOFlag) {
496  return I.second;
497  }
498  }
499  return nullptr;
500 }
501 
502 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
503  const MachineFrameInfo *MFI) {
504  StringRef Name;
505  if (MFI) {
506  IsFixed = MFI->isFixedObjectIndex(FrameIndex);
507  if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
508  if (Alloca->hasName())
509  Name = Alloca->getName();
510  if (IsFixed)
512  }
514 }
515 
517  const TargetRegisterInfo *TRI) {
518  OS << "%subreg.";
519  if (TRI)
520  OS << TRI->getSubRegIndexName(Index);
521  else
522  OS << Index;
523 }
524 
526  const MachineOperand &Op) {
527  if (!Op.getTargetFlags())
528  return;
529  const MachineFunction *MF = getMFIfAvailable(Op);
530  if (!MF)
531  return;
532 
533  const auto *TII = MF->getSubtarget().getInstrInfo();
534  assert(TII && "expected instruction info");
535  auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
536  OS << "target-flags(";
537  const bool HasDirectFlags = Flags.first;
538  const bool HasBitmaskFlags = Flags.second;
539  if (!HasDirectFlags && !HasBitmaskFlags) {
540  OS << "<unknown>) ";
541  return;
542  }
543  if (HasDirectFlags) {
544  if (const auto *Name = getTargetFlagName(TII, Flags.first))
545  OS << Name;
546  else
547  OS << "<unknown target flag>";
548  }
549  if (!HasBitmaskFlags) {
550  OS << ") ";
551  return;
552  }
553  bool IsCommaNeeded = HasDirectFlags;
554  unsigned BitMask = Flags.second;
556  for (const auto &Mask : BitMasks) {
557  // Check if the flag's bitmask has the bits of the current mask set.
558  if ((BitMask & Mask.first) == Mask.first) {
559  if (IsCommaNeeded)
560  OS << ", ";
561  IsCommaNeeded = true;
562  OS << Mask.second;
563  // Clear the bits which were serialized from the flag's bitmask.
564  BitMask &= ~(Mask.first);
565  }
566  }
567  if (BitMask) {
568  // When the resulting flag's bitmask isn't zero, we know that we didn't
569  // serialize all of the bit flags.
570  if (IsCommaNeeded)
571  OS << ", ";
572  OS << "<unknown bitmask target flag>";
573  }
574  OS << ") ";
575 }
576 
578  OS << "<mcsymbol " << Sym << ">";
579 }
580 
582  unsigned FrameIndex,
583  bool IsFixed, StringRef Name) {
584  if (IsFixed) {
585  OS << "%fixed-stack." << FrameIndex;
586  return;
587  }
588 
589  OS << "%stack." << FrameIndex;
590  if (!Name.empty())
591  OS << '.' << Name;
592 }
593 
595  if (Offset == 0)
596  return;
597  if (Offset < 0) {
598  OS << " - " << -Offset;
599  return;
600  }
601  OS << " + " << Offset;
602 }
603 
605  if (Slot == -1)
606  OS << "<badref>";
607  else
608  OS << Slot;
609 }
610 
611 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
612  const TargetRegisterInfo *TRI) {
613  switch (CFI.getOperation()) {
615  OS << "same_value ";
616  if (MCSymbol *Label = CFI.getLabel())
617  MachineOperand::printSymbol(OS, *Label);
618  printCFIRegister(CFI.getRegister(), OS, TRI);
619  break;
621  OS << "remember_state ";
622  if (MCSymbol *Label = CFI.getLabel())
623  MachineOperand::printSymbol(OS, *Label);
624  break;
626  OS << "restore_state ";
627  if (MCSymbol *Label = CFI.getLabel())
628  MachineOperand::printSymbol(OS, *Label);
629  break;
631  OS << "offset ";
632  if (MCSymbol *Label = CFI.getLabel())
633  MachineOperand::printSymbol(OS, *Label);
634  printCFIRegister(CFI.getRegister(), OS, TRI);
635  OS << ", " << CFI.getOffset();
636  break;
638  OS << "def_cfa_register ";
639  if (MCSymbol *Label = CFI.getLabel())
640  MachineOperand::printSymbol(OS, *Label);
641  printCFIRegister(CFI.getRegister(), OS, TRI);
642  break;
644  OS << "def_cfa_offset ";
645  if (MCSymbol *Label = CFI.getLabel())
646  MachineOperand::printSymbol(OS, *Label);
647  OS << CFI.getOffset();
648  break;
650  OS << "def_cfa ";
651  if (MCSymbol *Label = CFI.getLabel())
652  MachineOperand::printSymbol(OS, *Label);
653  printCFIRegister(CFI.getRegister(), OS, TRI);
654  OS << ", " << CFI.getOffset();
655  break;
657  OS << "rel_offset ";
658  if (MCSymbol *Label = CFI.getLabel())
659  MachineOperand::printSymbol(OS, *Label);
660  printCFIRegister(CFI.getRegister(), OS, TRI);
661  OS << ", " << CFI.getOffset();
662  break;
664  OS << "adjust_cfa_offset ";
665  if (MCSymbol *Label = CFI.getLabel())
666  MachineOperand::printSymbol(OS, *Label);
667  OS << CFI.getOffset();
668  break;
670  OS << "restore ";
671  if (MCSymbol *Label = CFI.getLabel())
672  MachineOperand::printSymbol(OS, *Label);
673  printCFIRegister(CFI.getRegister(), OS, TRI);
674  break;
676  OS << "escape ";
677  if (MCSymbol *Label = CFI.getLabel())
678  MachineOperand::printSymbol(OS, *Label);
679  if (!CFI.getValues().empty()) {
680  size_t e = CFI.getValues().size() - 1;
681  for (size_t i = 0; i < e; ++i)
682  OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
683  OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
684  }
685  break;
686  }
688  OS << "undefined ";
689  if (MCSymbol *Label = CFI.getLabel())
690  MachineOperand::printSymbol(OS, *Label);
691  printCFIRegister(CFI.getRegister(), OS, TRI);
692  break;
694  OS << "register ";
695  if (MCSymbol *Label = CFI.getLabel())
696  MachineOperand::printSymbol(OS, *Label);
697  printCFIRegister(CFI.getRegister(), OS, TRI);
698  OS << ", ";
699  printCFIRegister(CFI.getRegister2(), OS, TRI);
700  break;
702  OS << "window_save ";
703  if (MCSymbol *Label = CFI.getLabel())
704  MachineOperand::printSymbol(OS, *Label);
705  break;
707  OS << "negate_ra_sign_state ";
708  if (MCSymbol *Label = CFI.getLabel())
709  MachineOperand::printSymbol(OS, *Label);
710  break;
711  default:
712  // TODO: Print the other CFI Operations.
713  OS << "<unserializable cfi directive>";
714  break;
715  }
716 }
717 
719  const TargetIntrinsicInfo *IntrinsicInfo) const {
720  print(OS, LLT{}, TRI, IntrinsicInfo);
721 }
722 
723 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
724  const TargetRegisterInfo *TRI,
725  const TargetIntrinsicInfo *IntrinsicInfo) const {
726  tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
727  ModuleSlotTracker DummyMST(nullptr);
728  print(OS, DummyMST, TypeToPrint, None, /*PrintDef=*/false,
729  /*IsStandalone=*/true,
730  /*ShouldPrintRegisterTies=*/true,
731  /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
732 }
733 
735  LLT TypeToPrint, Optional<unsigned> OpIdx, bool PrintDef,
736  bool IsStandalone, bool ShouldPrintRegisterTies,
737  unsigned TiedOperandIdx,
738  const TargetRegisterInfo *TRI,
739  const TargetIntrinsicInfo *IntrinsicInfo) const {
740  printTargetFlags(OS, *this);
741  switch (getType()) {
743  Register Reg = getReg();
744  if (isImplicit())
745  OS << (isDef() ? "implicit-def " : "implicit ");
746  else if (PrintDef && isDef())
747  // Print the 'def' flag only when the operand is defined after '='.
748  OS << "def ";
749  if (isInternalRead())
750  OS << "internal ";
751  if (isDead())
752  OS << "dead ";
753  if (isKill())
754  OS << "killed ";
755  if (isUndef())
756  OS << "undef ";
757  if (isEarlyClobber())
758  OS << "early-clobber ";
760  OS << "renamable ";
761  // isDebug() is exactly true for register operands of a DBG_VALUE. So we
762  // simply infer it when parsing and do not need to print it.
763 
764  const MachineRegisterInfo *MRI = nullptr;
766  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
767  MRI = &MF->getRegInfo();
768  }
769  }
770 
771  OS << printReg(Reg, TRI, 0, MRI);
772  // Print the sub register.
773  if (unsigned SubReg = getSubReg()) {
774  if (TRI)
775  OS << '.' << TRI->getSubRegIndexName(SubReg);
776  else
777  OS << ".subreg" << SubReg;
778  }
779  // Print the register class / bank.
781  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
782  const MachineRegisterInfo &MRI = MF->getRegInfo();
783  if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
784  OS << ':';
785  OS << printRegClassOrBank(Reg, MRI, TRI);
786  }
787  }
788  }
789  // Print ties.
790  if (ShouldPrintRegisterTies && isTied() && !isDef())
791  OS << "(tied-def " << TiedOperandIdx << ")";
792  // Print types.
793  if (TypeToPrint.isValid())
794  OS << '(' << TypeToPrint << ')';
795  break;
796  }
798  const MIRFormatter *Formatter = nullptr;
799  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
800  const auto *TII = MF->getSubtarget().getInstrInfo();
801  assert(TII && "expected instruction info");
802  Formatter = TII->getMIRFormatter();
803  }
804  if (Formatter)
805  Formatter->printImm(OS, *getParent(), OpIdx, getImm());
806  else
807  OS << getImm();
808  break;
809  }
811  getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
812  break;
814  getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
815  break;
817  OS << printMBBReference(*getMBB());
818  break;
820  int FrameIndex = getIndex();
821  bool IsFixed = false;
822  const MachineFrameInfo *MFI = nullptr;
823  if (const MachineFunction *MF = getMFIfAvailable(*this))
824  MFI = &MF->getFrameInfo();
825  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
826  break;
827  }
829  OS << "%const." << getIndex();
831  break;
833  OS << "target-index(";
834  const char *Name = "<unknown>";
835  if (const MachineFunction *MF = getMFIfAvailable(*this))
836  if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
837  Name = TargetIndexName;
838  OS << Name << ')';
840  break;
841  }
844  break;
846  getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
848  break;
851  OS << '&';
852  if (Name.empty()) {
853  OS << "\"\"";
854  } else {
856  }
858  break;
859  }
861  OS << "blockaddress(";
862  getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
863  MST);
864  OS << ", ";
865  printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
866  OS << ')';
868  break;
869  }
871  OS << "<regmask";
872  if (TRI) {
873  unsigned NumRegsInMask = 0;
874  unsigned NumRegsEmitted = 0;
875  for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
876  unsigned MaskWord = i / 32;
877  unsigned MaskBit = i % 32;
878  if (getRegMask()[MaskWord] & (1 << MaskBit)) {
879  if (PrintRegMaskNumRegs < 0 ||
880  NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
881  OS << " " << printReg(i, TRI);
882  NumRegsEmitted++;
883  }
884  NumRegsInMask++;
885  }
886  }
887  if (NumRegsEmitted != NumRegsInMask)
888  OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
889  } else {
890  OS << " ...";
891  }
892  OS << ">";
893  break;
894  }
896  const uint32_t *RegMask = getRegLiveOut();
897  OS << "liveout(";
898  if (!TRI) {
899  OS << "<unknown>";
900  } else {
901  bool IsCommaNeeded = false;
902  for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
903  if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
904  if (IsCommaNeeded)
905  OS << ", ";
906  OS << printReg(Reg, TRI);
907  IsCommaNeeded = true;
908  }
909  }
910  }
911  OS << ")";
912  break;
913  }
915  getMetadata()->printAsOperand(OS, MST);
916  break;
918  printSymbol(OS, *getMCSymbol());
919  break;
921  if (const MachineFunction *MF = getMFIfAvailable(*this))
922  printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
923  else
924  OS << "<cfi directive>";
925  break;
926  }
929  if (ID < Intrinsic::num_intrinsics)
930  OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
931  else if (IntrinsicInfo)
932  OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
933  else
934  OS << "intrinsic(" << ID << ')';
935  break;
936  }
938  auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
939  OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
940  << CmpInst::getPredicateName(Pred) << ')';
941  break;
942  }
944  OS << "shufflemask(";
946  StringRef Separator;
947  for (int Elt : Mask) {
948  if (Elt == -1)
949  OS << Separator << "undef";
950  else
951  OS << Separator << Elt;
952  Separator = ", ";
953  }
954 
955  OS << ')';
956  break;
957  }
958 }
959 
960 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
961 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
962 #endif
963 
964 //===----------------------------------------------------------------------===//
965 // MachineMemOperand Implementation
966 //===----------------------------------------------------------------------===//
967 
968 /// getAddrSpace - Return the LLVM IR address space number that this pointer
969 /// points into.
970 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
971 
972 /// isDereferenceable - Return true if V is always dereferenceable for
973 /// Offset + Size byte.
975  const DataLayout &DL) const {
976  if (!V.is<const Value *>())
977  return false;
978 
979  const Value *BasePtr = V.get<const Value *>();
980  if (BasePtr == nullptr)
981  return false;
982 
984  BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
985 }
986 
987 /// getConstantPool - Return a MachinePointerInfo record that refers to the
988 /// constant pool.
991 }
992 
993 /// getFixedStack - Return a MachinePointerInfo record that refers to the
994 /// the specified FrameIndex.
996  int FI, int64_t Offset) {
998 }
999 
1002 }
1003 
1005  return MachinePointerInfo(MF.getPSVManager().getGOT());
1006 }
1007 
1009  int64_t Offset, uint8_t ID) {
1011 }
1012 
1015 }
1016 
1018  uint64_t s, Align a,
1019  const AAMDNodes &AAInfo,
1020  const MDNode *Ranges, SyncScope::ID SSID,
1021  AtomicOrdering Ordering,
1022  AtomicOrdering FailureOrdering)
1023  : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlign(a), AAInfo(AAInfo),
1024  Ranges(Ranges) {
1025  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1026  isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1027  "invalid pointer value");
1028  assert((isLoad() || isStore()) && "Not a load/store!");
1029 
1030  AtomicInfo.SSID = static_cast<unsigned>(SSID);
1031  assert(getSyncScopeID() == SSID && "Value truncated");
1032  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1033  assert(getOrdering() == Ordering && "Value truncated");
1034  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1035  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1036 }
1037 
1038 /// Profile - Gather unique data for the object.
1039 ///
1041  ID.AddInteger(getOffset());
1042  ID.AddInteger(Size);
1043  ID.AddPointer(getOpaqueValue());
1044  ID.AddInteger(getFlags());
1045  ID.AddInteger(getBaseAlign().value());
1046 }
1047 
1049  // The Value and Offset may differ due to CSE. But the flags and size
1050  // should be the same.
1051  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1052  assert(MMO->getSize() == getSize() && "Size mismatch!");
1053 
1054  if (MMO->getBaseAlign() >= getBaseAlign()) {
1055  // Update the alignment value.
1056  BaseAlign = MMO->getBaseAlign();
1057  // Also update the base and offset, because the new alignment may
1058  // not be applicable with the old ones.
1059  PtrInfo = MMO->PtrInfo;
1060  }
1061 }
1062 
1063 /// getAlignment - Return the minimum known alignment in bytes of the
1064 /// actual memory reference.
1065 uint64_t MachineMemOperand::getAlignment() const { return getAlign().value(); }
1066 
1067 /// getAlign - Return the minimum known alignment in bytes of the
1068 /// actual memory reference.
1070  return commonAlignment(getBaseAlign(), getOffset());
1071 }
1072 
1075  const LLVMContext &Context,
1076  const MachineFrameInfo *MFI,
1077  const TargetInstrInfo *TII) const {
1078  OS << '(';
1079  if (isVolatile())
1080  OS << "volatile ";
1081  if (isNonTemporal())
1082  OS << "non-temporal ";
1083  if (isDereferenceable())
1084  OS << "dereferenceable ";
1085  if (isInvariant())
1086  OS << "invariant ";
1089  << "\" ";
1092  << "\" ";
1095  << "\" ";
1096 
1097  assert((isLoad() || isStore()) &&
1098  "machine memory operand must be a load or store (or both)");
1099  if (isLoad())
1100  OS << "load ";
1101  if (isStore())
1102  OS << "store ";
1103 
1104  printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1105 
1107  OS << toIRString(getOrdering()) << ' ';
1109  OS << toIRString(getFailureOrdering()) << ' ';
1110 
1112  OS << "unknown-size";
1113  else
1114  OS << getSize();
1115 
1116  if (const Value *Val = getValue()) {
1117  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1118  MIRFormatter::printIRValue(OS, *Val, MST);
1119  } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1120  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1121  assert(PVal && "Expected a pseudo source value");
1122  switch (PVal->kind()) {
1124  OS << "stack";
1125  break;
1127  OS << "got";
1128  break;
1130  OS << "jump-table";
1131  break;
1133  OS << "constant-pool";
1134  break;
1136  int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1137  bool IsFixed = true;
1138  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1139  break;
1140  }
1142  OS << "call-entry ";
1143  cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1144  OS, /*PrintType=*/false, MST);
1145  break;
1147  OS << "call-entry &";
1149  OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1150  break;
1151  default: {
1152  const MIRFormatter *Formatter = TII->getMIRFormatter();
1153  // FIXME: This is not necessarily the correct MIR serialization format for
1154  // a custom pseudo source value, but at least it allows
1155  // MIR printing to work on a target with custom pseudo source
1156  // values.
1157  OS << "custom \"";
1158  Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1159  OS << '\"';
1160  break;
1161  }
1162  }
1163  } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1164  OS << ((isLoad() && isStore()) ? " on "
1165  : isLoad() ? " from "
1166  : " into ")
1167  << "unknown-address";
1168  }
1170  if (getAlign() != getSize())
1171  OS << ", align " << getAlign().value();
1172  if (getAlign() != getBaseAlign())
1173  OS << ", basealign " << getBaseAlign().value();
1174  auto AAInfo = getAAInfo();
1175  if (AAInfo.TBAA) {
1176  OS << ", !tbaa ";
1177  AAInfo.TBAA->printAsOperand(OS, MST);
1178  }
1179  if (AAInfo.Scope) {
1180  OS << ", !alias.scope ";
1181  AAInfo.Scope->printAsOperand(OS, MST);
1182  }
1183  if (AAInfo.NoAlias) {
1184  OS << ", !noalias ";
1185  AAInfo.NoAlias->printAsOperand(OS, MST);
1186  }
1187  if (getRanges()) {
1188  OS << ", !range ";
1189  getRanges()->printAsOperand(OS, MST);
1190  }
1191  // FIXME: Implement addrspace printing/parsing in MIR.
1192  // For now, print this even though parsing it is not available in MIR.
1193  if (unsigned AS = getAddrSpace())
1194  OS << ", addrspace " << AS;
1195 
1196  OS << ')';
1197 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::MCCFIInstruction::OpWindowSave
@ OpWindowSave
Definition: MCDwarf.h:457
llvm::MIRFormatter::printIRValue
static void printIRValue(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)
Helper functions to print IR value as MIR serialization format which will be useful for target specif...
Definition: MIRPrinter.cpp:897
getAlignment
static uint32_t getAlignment(const MCSectionCOFF &Sec)
Definition: WinCOFFObjectWriter.cpp:266
printCFI
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
Definition: MachineOperand.cpp:611
llvm::MachineMemOperand::MachineMemOperand
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.
Definition: MachineOperand.cpp:1017
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:63
llvm::MachineMemOperand::isStore
bool isStore() const
Definition: MachineMemOperand.h:267
llvm::PseudoSourceValueManager::getGOT
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like).
Definition: PseudoSourceValue.cpp:118
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:53
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:499
llvm::PointerUnion::isNull
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:172
llvm::ModuleSlotTracker::getLocalSlot
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:906
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::PseudoSourceValue::GlobalValueCallEntry
@ GlobalValueCallEntry
Definition: PseudoSourceValue.h:43
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::MCCFIInstruction::OpRelOffset
@ OpRelOffset
Definition: MCDwarf.h:451
tryToGetTargetInfo
static void tryToGetTargetInfo(const MachineOperand &MO, const TargetRegisterInfo *&TRI, const TargetIntrinsicInfo *&IntrinsicInfo)
Definition: MachineOperand.cpp:402
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:156
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::MCCFIInstruction::OpDefCfaRegister
@ OpDefCfaRegister
Definition: MCDwarf.h:448
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:722
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1069
llvm::MachineOperand::MO_ShuffleMask
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
Definition: MachineOperand.h:71
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:560
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
Loads.h
llvm::MachineOperand::MO_RegisterLiveOut
@ MO_RegisterLiveOut
Mask of live-out registers.
Definition: MachineOperand.h:65
llvm::Function
Definition: Function.h:61
llvm::MachineMemOperand::print
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
Definition: MachineOperand.cpp:1073
llvm::MCCFIInstruction::OpOffset
@ OpOffset
Definition: MCDwarf.h:447
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
getMFIfAvailable
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
Definition: MachineOperand.cpp:43
llvm::MachinePointerInfo::getConstantPool
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
Definition: MachineOperand.cpp:989
llvm::MachineOperand::printStackObjectReference
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Definition: MachineOperand.cpp:581
llvm::MachineOperand::printIRSlotNumber
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
Definition: MachineOperand.cpp:604
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:580
llvm::MachinePointerInfo::getUnknownStack
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
Definition: MachineOperand.cpp:1013
llvm::printLLVMNameWithoutPrefix
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:414
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:718
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:565
llvm::MachineMemOperand::isLoad
bool isLoad() const
Definition: MachineMemOperand.h:266
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:216
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:118
llvm::isDereferenceableAndAlignedPointer
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, MaybeAlign Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
Definition: Loads.cpp:210
llvm::ModuleSlotTracker::getCurrentFunction
const Function * getCurrentFunction() const
Definition: ModuleSlotTracker.h:61
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:438
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::Intrinsic::getName
StringRef getName(ID id)
Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".
Definition: Function.cpp:802
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::MachineMemOperand::MOTargetFlag2
@ MOTargetFlag2
Definition: MachineMemOperand.h:151
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::MachineMemOperand::getOpaqueValue
const void * getOpaqueValue() const
Definition: MachineMemOperand.h:206
llvm::HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
Definition: HexagonInstrInfo.cpp:2004
MachineJumpTableInfo.h
TargetInstrInfo.h
llvm::Metadata::printAsOperand
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4733
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineOperand::MO_CFIIndex
@ MO_CFIIndex
MCCFIInstruction index.
Definition: MachineOperand.h:68
llvm::MachineOperand::getTargetIndexName
const char * getTargetIndexName() const
getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...
Definition: MachineOperand.cpp:423
llvm::MachineFunction::getPSVManager
PseudoSourceValueManager & getPSVManager() const
Definition: MachineFunction.h:515
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:90
llvm::HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
Definition: HexagonInstrInfo.cpp:1985
llvm::Optional< unsigned >
llvm::LLVMContext::getSyncScopeNames
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
Definition: LLVMContext.cpp:294
llvm::MachineOperand::ChangeToTargetIndex
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
Definition: MachineOperand.cpp:225
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::ModuleSlotTracker::incorporateFunction
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:892
llvm::MachineMemOperand::isInvariant
bool isInvariant() const
Definition: MachineMemOperand.h:271
llvm::PseudoSourceValueManager::getStack
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function,...
Definition: PseudoSourceValue.cpp:114
llvm::MachineOperand::ChangeToFrameIndex
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
Definition: MachineOperand.cpp:214
llvm::CmpInst::getPredicateName
static StringRef getPredicateName(Predicate P)
Definition: Instructions.cpp:3700
llvm::AAMDNodes::Scope
MDNode * Scope
The tag for alias scope specification (used with noalias).
Definition: Metadata.h:674
llvm::hash_value
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4803
llvm::MachineMemOperand::getAAInfo
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Definition: MachineMemOperand.h:243
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:597
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:29
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineOperand::dump
void dump() const
Definition: MachineOperand.cpp:961
llvm::PointerUnion::get
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:187
llvm::MachinePointerInfo::getJumpTable
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Definition: MachineOperand.cpp:1000
llvm::MachineOperand::getMCSymbol
MCSymbol * getMCSymbol() const
Definition: MachineOperand.h:570
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:52
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::PseudoSourceValue::JumpTable
@ JumpTable
Definition: PseudoSourceValue.h:40
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::PointerUnion::is
bool is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:177
llvm::lltok::equal
@ equal
Definition: LLToken.h:25
a
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
Definition: README.txt:489
llvm::MachineOperand::printSymbol
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
Definition: MachineOperand.cpp:577
isUndef
static bool isUndef(ArrayRef< int > Mask)
Definition: HexagonISelDAGToDAGHVX.cpp:904
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition: TargetIntrinsicInfo.h:29
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::MachinePointerInfo::Offset
int64_t Offset
Offset - This is an offset from the base Value*.
Definition: MachineMemOperand.h:44
llvm::MCCFIInstruction::OpDefCfa
@ OpDefCfa
Definition: MCDwarf.h:450
llvm::MachineOperand::printSubRegIdx
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Definition: MachineOperand.cpp:516
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:387
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:118
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition: MachineMemOperand.h:150
llvm::MCCFIInstruction::OpUndefined
@ OpUndefined
Definition: MCDwarf.h:455
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:377
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
TargetMachine.h
Constants.h
llvm::MachineMemOperand::getBaseAlign
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
Definition: MachineMemOperand.h:240
llvm::MachineOperand::ChangeToRegister
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Definition: MachineOperand.cpp:241
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:62
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:218
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:534
getTargetIndexName
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
Definition: MachineOperand.cpp:411
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:200
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:367
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineOperand::getRegMask
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Definition: MachineOperand.h:627
llvm::MachineOperand::setSubReg
void setSubReg(unsigned subReg)
Definition: MachineOperand.h:468
llvm::MachineOperand::MO_FrameIndex
@ MO_FrameIndex
Abstract Stack Frame Index.
Definition: MachineOperand.h:57
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MCCFIInstruction::getOffset
int getOffset() const
Definition: MCDwarf.h:602
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1004
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:156
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
IRPrintingPasses.h
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:255
llvm::PseudoSourceValue::FixedStack
@ FixedStack
Definition: PseudoSourceValue.h:42
llvm::MachineOperand::ChangeToMCSymbol
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
Definition: MachineOperand.cpp:203
llvm::MCCFIInstruction::getOperation
OpType getOperation() const
Definition: MCDwarf.h:586
llvm::printJumpTableEntryReference
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
Definition: MachineFunction.cpp:1099
llvm::MachineOperand::setTargetFlags
void setTargetFlags(unsigned F)
Definition: MachineOperand.h:221
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:677
printCFIRegister
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
Definition: MachineOperand.cpp:438
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:388
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:235
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(const Value *v, int64_t offset=0, uint8_t ID=0)
Definition: MachineMemOperand.h:50
llvm::MCCFIInstruction::getRegister
unsigned getRegister() const
Definition: MCDwarf.h:589
llvm::None
const NoneType None
Definition: None.h:23
isDebug
static bool isDebug()
Definition: HexagonGenInsert.cpp:81
llvm::MachineOperand::printOperandOffset
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
Definition: MachineOperand.cpp:594
llvm::MachineMemOperand::getSyncScopeID
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
Definition: MachineMemOperand.h:249
llvm::MCCFIInstruction
Definition: MCDwarf.h:441
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:426
llvm::MCRegisterInfo::getLLVMRegNum
Optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
Definition: MCRegisterInfo.cpp:81
llvm::MachineMemOperand::Profile
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
Definition: MachineOperand.cpp:1040
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition: MachineOperand.h:643
llvm::PseudoSourceValue::ExternalSymbolCallEntry
@ ExternalSymbolCallEntry
Definition: PseudoSourceValue.h:44
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::cl::opt
Definition: CommandLine.h:1419
llvm::MachineOperand::MO_Metadata
@ MO_Metadata
Metadata reference (for debug info)
Definition: MachineOperand.h:66
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineOperand::ChangeToFPImmediate
void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
Definition: MachineOperand.cpp:166
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:392
llvm::MCCFIInstruction::OpDefCfaOffset
@ OpDefCfaOffset
Definition: MCDwarf.h:449
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:218
llvm::MachineOperand::substVirtReg
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Definition: MachineOperand.cpp:77
llvm::MachinePointerInfo::isDereferenceable
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
Definition: MachineOperand.cpp:974
llvm::MCCFIInstruction::OpRestore
@ OpRestore
Definition: MCDwarf.h:454
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:318
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:539
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineMemOperand::isDereferenceable
bool isDereferenceable() const
Definition: MachineMemOperand.h:270
s
multiplies can be turned into SHL s
Definition: README.txt:370
llvm::MCCFIInstruction::OpSameValue
@ OpSameValue
Definition: MCDwarf.h:444
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:37
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:58
MemoryLocation.h
llvm::SyncScope::ID
uint8_t ID
Definition: LLVMContext.h:47
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:382
llvm::MachineOperand::MO_Predicate
@ MO_Predicate
Generic predicate for ISel.
Definition: MachineOperand.h:70
MIRPrinter.h
I
#define I(x, y, z)
Definition: MD5.cpp:59
StringExtras.h
llvm::MachineOperand::MO_MCSymbol
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
Definition: MachineOperand.h:67
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:216
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition: MachineOperand.h:544
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:585
llvm::PseudoSourceValue::ConstantPool
@ ConstantPool
Definition: PseudoSourceValue.h:41
llvm::MCCFIInstruction::getRegister2
unsigned getRegister2() const
Definition: MCDwarf.h:597
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::MIRFormatter::printImm
virtual void printImm(raw_ostream &OS, const MachineInstr &MI, Optional< unsigned > OpIdx, int64_t Imm) const
Implement target specific printing for machine operand immediate value, so that we can have more mean...
Definition: MIRFormatter.h:41
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition: MachineOperand.h:433
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
MIRFormatter.h
llvm::MachineOperand::getShuffleMask
ArrayRef< int > getShuffleMask() const
Definition: MachineOperand.h:590
llvm::MachineOperand::MO_TargetIndex
@ MO_TargetIndex
Target-dependent index+offset operand.
Definition: MachineOperand.h:59
PrintRegMaskNumRegs
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
llvm::MCCFIInstruction::OpAdjustCfaOffset
@ OpAdjustCfaOffset
Definition: MCDwarf.h:452
llvm::MachineOperand::MO_FPImmediate
@ MO_FPImmediate
Floating-point immediate operand.
Definition: MachineOperand.h:55
printFrameIndex
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
Definition: MachineOperand.cpp:502
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::MDNode
Metadata node.
Definition: Metadata.h:897
llvm::Value::printAsOperand
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:4691
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::MCCFIInstruction::OpEscape
@ OpEscape
Definition: MCDwarf.h:453
llvm::CmpInst::isIntPredicate
bool isIntPredicate() const
Definition: InstrTypes.h:817
llvm::MachineOperand::MO_JumpTableIndex
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition: MachineOperand.h:60
llvm::MachineOperand::MO_CImmediate
@ MO_CImmediate
Immediate >64bit operand.
Definition: MachineOperand.h:54
llvm::printRegClassOrBank
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Definition: TargetRegisterInfo.cpp:174
llvm::MachineMemOperand::MOTargetFlag3
@ MOTargetFlag3
Definition: MachineMemOperand.h:152
llvm::MachineOperand::setIsDef
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Definition: MachineOperand.cpp:101
llvm::ArrayRef< int >
llvm::MCCFIInstruction::OpRememberState
@ OpRememberState
Definition: MCDwarf.h:445
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:549
llvm::HexagonInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
Definition: HexagonInstrInfo.cpp:1979
llvm::MachinePointerInfo::V
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Definition: MachineMemOperand.h:41
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MCCFIInstruction::getValues
StringRef getValues() const
Definition: MCDwarf.h:609
llvm::MachineOperand::ChangeToES
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Definition: MachineOperand.cpp:177
llvm::TargetRegisterInfo::composeSubRegIndices
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Definition: TargetRegisterInfo.h:615
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:508
uint32_t
llvm::MachineOperand::setIsRenamable
void setIsRenamable(bool Val=true)
Definition: MachineOperand.cpp:136
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:56
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachinePointerInfo::AddrSpace
unsigned AddrSpace
Definition: MachineMemOperand.h:46
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:372
llvm::FoldingSetNodeID
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:313
llvm::MachineOperand::MO_IntrinsicID
@ MO_IntrinsicID
Intrinsic ID for ISel.
Definition: MachineOperand.h:69
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:304
llvm::format
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
llvm::DataLayout::getAllocaAddrSpace
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:279
llvm::MachineOperand::setIndex
void setIndex(int Idx)
Definition: MachineOperand.h:675
llvm::TargetIntrinsicInfo::getName
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
llvm::MachinePointerInfo::getAddrSpace
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Definition: MachineOperand.cpp:970
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:362
FoldingSet.h
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1532
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
llvm::PseudoSourceValueManager::getJumpTable
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
Definition: PseudoSourceValue.cpp:124
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::PseudoSourceValue::GOT
@ GOT
Definition: PseudoSourceValue.h:39
llvm::MachineMemOperand::isVolatile
bool isVolatile() const
Definition: MachineMemOperand.h:268
llvm::BlockAddress::getFunction
Function * getFunction() const
Definition: Constants.h:873
llvm::MachineOperand::printTargetFlags
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
Definition: MachineOperand.cpp:525
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:221
llvm::MachineOperand::ChangeToGA
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
Definition: MachineOperand.cpp:190
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:265
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::AAMDNodes::NoAlias
MDNode * NoAlias
The tag specifying the noalias scope.
Definition: Metadata.h:677
getTargetFlagName
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
Definition: MachineOperand.cpp:428
llvm::PseudoSourceValueManager::getFixedStack
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot.
Definition: PseudoSourceValue.cpp:129
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:221
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:61
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:554
llvm::MachineOperand::getCFIIndex
unsigned getCFIIndex() const
Definition: MachineOperand.h:575
llvm::PseudoSourceValue::Stack
@ Stack
Definition: PseudoSourceValue.h:38
llvm::MemoryLocation::UnknownSize
@ UnknownSize
Definition: MemoryLocation.h:214
llvm::MachineMemOperand::refineAlignment
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
Definition: MachineOperand.cpp:1048
llvm::MCCFIInstruction::OpRegister
@ OpRegister
Definition: MCDwarf.h:456
llvm::AAMDNodes::TBAA
MDNode * TBAA
The tag for type-based alias analysis.
Definition: Metadata.h:668
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:443
llvm::MachineInstr::IgnoreBundle
@ IgnoreBundle
Definition: MachineInstr.h:755
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:30
Instructions.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:995
llvm::hash_combine
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:604
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:605
TargetIntrinsicInfo.h
getTargetMMOFlagName
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
Definition: MachineOperand.cpp:491
llvm::SyncScope::System
@ System
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:58
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::toIRString
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
Definition: AtomicOrdering.h:81
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition: MachineOperand.h:428
llvm::MachineOperand::getRegLiveOut
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
Definition: MachineOperand.h:638
ModuleSlotTracker.h
llvm::SmallVectorImpl< StringRef >
llvm::MachineMemOperand::getFailureOrdering
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
Definition: MachineMemOperand.h:262
MachineOperand.h
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1078
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition: MachineOperand.cpp:87
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MachineMemOperand::getOrdering
AtomicOrdering getOrdering() const
Return the atomic ordering requirements for this memory operation.
Definition: MachineMemOperand.h:256
llvm::AllocaInst
an instruction to allocate memory on the stack
Definition: Instructions.h:61
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:64
printIRBlockReference
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
Definition: MachineOperand.cpp:451
llvm::cl::desc
Definition: CommandLine.h:411
llvm::MachineMemOperand::isNonTemporal
bool isNonTemporal() const
Definition: MachineMemOperand.h:269
llvm::TargetRegisterInfo::getSubRegIndexName
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition: TargetRegisterInfo.h:351
llvm::MachineMemOperand::getRanges
const MDNode * getRanges() const
Return the range tag for the memory reference.
Definition: MachineMemOperand.h:246
llvm::MCCFIInstruction::OpNegateRAState
@ OpNegateRAState
Definition: MCDwarf.h:458
llvm::MIRFormatter::printCustomPseudoSourceValue
virtual void printCustomPseudoSourceValue(raw_ostream &OS, ModuleSlotTracker &MST, const PseudoSourceValue &PSV) const
Implement target specific printing of target custom pseudo source value.
Definition: MIRFormatter.h:58
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:160
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1008
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:209
TargetRegisterInfo.h
llvm::MCCFIInstruction::OpRestoreState
@ OpRestoreState
Definition: MCDwarf.h:446
llvm::PseudoSourceValueManager::getConstantPool
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
Definition: PseudoSourceValue.cpp:120
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::AtomicOrdering::NotAtomic
@ NotAtomic
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1161
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:282
llvm::MCCFIInstruction::getLabel
MCSymbol * getLabel() const
Definition: MCDwarf.h:587
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:202
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::hash_code
An opaque object representing a hash code.
Definition: Hashing.h:72
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:58
llvm::MachineFrameInfo::getObjectAllocation
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
Definition: MachineFrameInfo.h:496
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::MachineOperand::setOffset
void setOffset(int64_t Offset)
Definition: MachineOperand.h:667
printSyncScope
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)
Definition: MachineOperand.cpp:474