LLVM 17.0.0git
MachineOperand.cpp
Go to the documentation of this file.
1//===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file Methods common to all machine operands.
10//
11//===----------------------------------------------------------------------===//
12
14#include "llvm/ADT/FoldingSet.h"
16#include "llvm/Analysis/Loads.h"
24#include "llvm/Config/llvm-config.h"
25#include "llvm/IR/Constants.h"
29#include "llvm/MC/MCDwarf.h"
32#include <optional>
33
34using namespace llvm;
35
36static cl::opt<int>
37 PrintRegMaskNumRegs("print-regmask-num-regs",
38 cl::desc("Number of registers to limit to when "
39 "printing regmask operands in IR dumps. "
40 "unlimited = -1"),
41 cl::init(32), cl::Hidden);
42
44 if (const MachineInstr *MI = MO.getParent())
45 if (const MachineBasicBlock *MBB = MI->getParent())
46 if (const MachineFunction *MF = MBB->getParent())
47 return MF;
48 return nullptr;
49}
50
52 return const_cast<MachineFunction *>(
53 getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
54}
55
57 assert(getParent() && "Operand does not belong to any instruction!");
58 return getParent()->getOperandNo(this);
59}
60
62 if (getReg() == Reg)
63 return; // No change.
64
65 // Clear the IsRenamable bit to keep it conservatively correct.
66 IsRenamable = false;
67
68 // Otherwise, we have to change the register. If this operand is embedded
69 // into a machine function, we need to update the old and new register's
70 // use/def lists.
71 if (MachineFunction *MF = getMFIfAvailable(*this)) {
72 MachineRegisterInfo &MRI = MF->getRegInfo();
73 MRI.removeRegOperandFromUseList(this);
74 SmallContents.RegNo = Reg;
75 MRI.addRegOperandToUseList(this);
76 return;
77 }
78
79 // Otherwise, just change the register, no problem. :)
80 SmallContents.RegNo = Reg;
81}
82
83void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
84 const TargetRegisterInfo &TRI) {
85 assert(Reg.isVirtual());
86 if (SubIdx && getSubReg())
87 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
88 setReg(Reg);
89 if (SubIdx)
90 setSubReg(SubIdx);
91}
92
95 if (getSubReg()) {
96 Reg = TRI.getSubReg(Reg, getSubReg());
97 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
98 // That won't happen in legal code.
99 setSubReg(0);
100 if (isDef())
101 setIsUndef(false);
102 }
103 setReg(Reg);
104}
105
106/// Change a def to a use, or a use to a def.
108 assert(isReg() && "Wrong MachineOperand accessor");
109 assert((!Val || !isDebug()) && "Marking a debug operation as def");
110 if (IsDef == Val)
111 return;
112 assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
113 // MRI may keep uses and defs in different list positions.
114 if (MachineFunction *MF = getMFIfAvailable(*this)) {
115 MachineRegisterInfo &MRI = MF->getRegInfo();
116 MRI.removeRegOperandFromUseList(this);
117 IsDef = Val;
118 MRI.addRegOperandToUseList(this);
119 return;
120 }
121 IsDef = Val;
122}
123
125 assert(isReg() && "Wrong MachineOperand accessor");
126 assert(getReg().isPhysical() &&
127 "isRenamable should only be checked on physical registers");
128 if (!IsRenamable)
129 return false;
130
131 const MachineInstr *MI = getParent();
132 if (!MI)
133 return true;
134
135 if (isDef())
136 return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
137
138 assert(isUse() && "Reg is not def or use");
139 return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
140}
141
143 assert(isReg() && "Wrong MachineOperand accessor");
144 assert(getReg().isPhysical() &&
145 "setIsRenamable should only be called on physical registers");
146 IsRenamable = Val;
147}
148
149// If this operand is currently a register operand, and if this is in a
150// function, deregister the operand from the register's use/def list.
151void MachineOperand::removeRegFromUses() {
152 if (!isReg() || !isOnRegUseList())
153 return;
154
155 if (MachineFunction *MF = getMFIfAvailable(*this))
156 MF->getRegInfo().removeRegOperandFromUseList(this);
157}
158
159/// ChangeToImmediate - Replace this operand with a new immediate operand of
160/// the specified value. If an operand is known to be an immediate already,
161/// the setImm method should be used.
162void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
163 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
164
165 removeRegFromUses();
166
167 OpKind = MO_Immediate;
168 Contents.ImmVal = ImmVal;
169 setTargetFlags(TargetFlags);
170}
171
173 unsigned TargetFlags) {
174 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
175
176 removeRegFromUses();
177
178 OpKind = MO_FPImmediate;
179 Contents.CFP = FPImm;
180 setTargetFlags(TargetFlags);
181}
182
183void MachineOperand::ChangeToES(const char *SymName,
184 unsigned TargetFlags) {
185 assert((!isReg() || !isTied()) &&
186 "Cannot change a tied operand into an external symbol");
187
188 removeRegFromUses();
189
190 OpKind = MO_ExternalSymbol;
191 Contents.OffsetedInfo.Val.SymbolName = SymName;
192 setOffset(0); // Offset is always 0.
193 setTargetFlags(TargetFlags);
194}
195
197 unsigned TargetFlags) {
198 assert((!isReg() || !isTied()) &&
199 "Cannot change a tied operand into a global address");
200
201 removeRegFromUses();
202
203 OpKind = MO_GlobalAddress;
204 Contents.OffsetedInfo.Val.GV = GV;
206 setTargetFlags(TargetFlags);
207}
208
209void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
210 assert((!isReg() || !isTied()) &&
211 "Cannot change a tied operand into an MCSymbol");
212
213 removeRegFromUses();
214
215 OpKind = MO_MCSymbol;
216 Contents.Sym = Sym;
217 setTargetFlags(TargetFlags);
218}
219
220void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
221 assert((!isReg() || !isTied()) &&
222 "Cannot change a tied operand into a FrameIndex");
223
224 removeRegFromUses();
225
226 OpKind = MO_FrameIndex;
227 setIndex(Idx);
228 setTargetFlags(TargetFlags);
229}
230
232 unsigned TargetFlags) {
233 assert((!isReg() || !isTied()) &&
234 "Cannot change a tied operand into a FrameIndex");
235
236 removeRegFromUses();
237
238 OpKind = MO_TargetIndex;
239 setIndex(Idx);
241 setTargetFlags(TargetFlags);
242}
243
244void MachineOperand::ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx,
245 unsigned TargetFlags) {
246 assert((!isReg() || !isTied()) &&
247 "Cannot change a tied operand into a DbgInstrRef");
248
249 removeRegFromUses();
250
251 OpKind = MO_DbgInstrRef;
252 setInstrRefInstrIndex(InstrIdx);
253 setInstrRefOpIndex(OpIdx);
254 setTargetFlags(TargetFlags);
255}
256
257/// ChangeToRegister - Replace this operand with a new register operand of
258/// the specified value. If an operand is known to be an register already,
259/// the setReg method should be used.
260void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
261 bool isKill, bool isDead, bool isUndef,
262 bool isDebug) {
263 MachineRegisterInfo *RegInfo = nullptr;
264 if (MachineFunction *MF = getMFIfAvailable(*this))
265 RegInfo = &MF->getRegInfo();
266 // If this operand is already a register operand, remove it from the
267 // register's use/def lists.
268 bool WasReg = isReg();
269 if (RegInfo && WasReg)
270 RegInfo->removeRegOperandFromUseList(this);
271
272 // Ensure debug instructions set debug flag on register uses.
273 const MachineInstr *MI = getParent();
274 if (!isDef && MI && MI->isDebugInstr())
275 isDebug = true;
276
277 // Change this to a register and set the reg#.
278 assert(!(isDead && !isDef) && "Dead flag on non-def");
279 assert(!(isKill && isDef) && "Kill flag on def");
280 OpKind = MO_Register;
281 SmallContents.RegNo = Reg;
282 SubReg_TargetFlags = 0;
283 IsDef = isDef;
284 IsImp = isImp;
285 IsDeadOrKill = isKill | isDead;
286 IsRenamable = false;
287 IsUndef = isUndef;
288 IsInternalRead = false;
289 IsEarlyClobber = false;
290 IsDebug = isDebug;
291 // Ensure isOnRegUseList() returns false.
292 Contents.Reg.Prev = nullptr;
293 // Preserve the tie when the operand was already a register.
294 if (!WasReg)
295 TiedTo = 0;
296
297 // If this operand is embedded in a function, add the operand to the
298 // register's use/def list.
299 if (RegInfo)
300 RegInfo->addRegOperandToUseList(this);
301}
302
303/// isIdenticalTo - Return true if this operand is identical to the specified
304/// operand. Note that this should stay in sync with the hash_value overload
305/// below.
307 if (getType() != Other.getType() ||
308 getTargetFlags() != Other.getTargetFlags())
309 return false;
310
311 switch (getType()) {
313 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
314 getSubReg() == Other.getSubReg();
316 return getImm() == Other.getImm();
318 return getCImm() == Other.getCImm();
320 return getFPImm() == Other.getFPImm();
322 return getMBB() == Other.getMBB();
324 return getIndex() == Other.getIndex();
327 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
329 return getIndex() == Other.getIndex();
331 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
333 return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
334 getOffset() == Other.getOffset();
336 return getBlockAddress() == Other.getBlockAddress() &&
337 getOffset() == Other.getOffset();
340 // Shallow compare of the two RegMasks
341 const uint32_t *RegMask = getRegMask();
342 const uint32_t *OtherRegMask = Other.getRegMask();
343 if (RegMask == OtherRegMask)
344 return true;
345
346 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
347 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
348 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
349 // Deep compare of the two RegMasks
350 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
351 }
352 // We don't know the size of the RegMask, so we can't deep compare the two
353 // reg masks.
354 return false;
355 }
357 return getMCSymbol() == Other.getMCSymbol();
359 return getInstrRefInstrIndex() == Other.getInstrRefInstrIndex() &&
360 getInstrRefOpIndex() == Other.getInstrRefOpIndex();
362 return getCFIIndex() == Other.getCFIIndex();
364 return getMetadata() == Other.getMetadata();
366 return getIntrinsicID() == Other.getIntrinsicID();
368 return getPredicate() == Other.getPredicate();
370 return getShuffleMask() == Other.getShuffleMask();
371 }
372 llvm_unreachable("Invalid machine operand type");
373}
374
375// Note: this must stay exactly in sync with isIdenticalTo above.
377 switch (MO.getType()) {
379 // Register operands don't have target flags.
380 return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
382 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
384 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
386 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
388 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
390 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
393 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
394 MO.getOffset());
396 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
398 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
401 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
402 MO.getOffset());
404 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
405 MO.getOffset());
408 if (const MachineFunction *MF = getMFIfAvailable(MO)) {
409 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
410 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
411 const uint32_t *RegMask = MO.getRegMask();
412 std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize);
413 return hash_combine(MO.getType(), MO.getTargetFlags(),
414 stable_hash_combine_array(RegMaskHashes.data(),
415 RegMaskHashes.size()));
416 }
417
418 assert(0 && "MachineOperand not associated with any MachineFunction");
419 return hash_combine(MO.getType(), MO.getTargetFlags());
420 }
422 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
424 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
426 return hash_combine(MO.getType(), MO.getTargetFlags(),
429 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
431 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
433 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
435 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
436 }
437 llvm_unreachable("Invalid machine operand type");
438}
439
440// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
441// it.
442static void tryToGetTargetInfo(const MachineOperand &MO,
443 const TargetRegisterInfo *&TRI,
444 const TargetIntrinsicInfo *&IntrinsicInfo) {
445 if (const MachineFunction *MF = getMFIfAvailable(MO)) {
446 TRI = MF->getSubtarget().getRegisterInfo();
447 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
448 }
449}
450
451static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
452 const auto *TII = MF.getSubtarget().getInstrInfo();
453 assert(TII && "expected instruction info");
454 auto Indices = TII->getSerializableTargetIndices();
455 auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
456 return I.first == Index;
457 });
458 if (Found != Indices.end())
459 return Found->second;
460 return nullptr;
461}
462
464 const MachineFunction *MF = getMFIfAvailable(*this);
465 return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
466}
467
468static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
470 for (const auto &I : Flags) {
471 if (I.first == TF) {
472 return I.second;
473 }
474 }
475 return nullptr;
476}
477
478static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
479 const TargetRegisterInfo *TRI) {
480 if (!TRI) {
481 OS << "%dwarfreg." << DwarfReg;
482 return;
483 }
484
485 if (std::optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
486 OS << printReg(*Reg, TRI);
487 else
488 OS << "<badreg>";
489}
490
492 ModuleSlotTracker &MST) {
493 OS << "%ir-block.";
494 if (BB.hasName()) {
496 return;
497 }
498 std::optional<int> Slot;
499 if (const Function *F = BB.getParent()) {
500 if (F == MST.getCurrentFunction()) {
501 Slot = MST.getLocalSlot(&BB);
502 } else if (const Module *M = F->getParent()) {
503 ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
504 CustomMST.incorporateFunction(*F);
505 Slot = CustomMST.getLocalSlot(&BB);
506 }
507 }
508 if (Slot)
510 else
511 OS << "<unknown>";
512}
513
514static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
515 SyncScope::ID SSID,
517 switch (SSID) {
519 break;
520 default:
521 if (SSNs.empty())
523
524 OS << "syncscope(\"";
525 printEscapedString(SSNs[SSID], OS);
526 OS << "\") ";
527 break;
528 }
529}
530
531static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
532 unsigned TMMOFlag) {
533 auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
534 for (const auto &I : Flags) {
535 if (I.first == TMMOFlag) {
536 return I.second;
537 }
538 }
539 return nullptr;
540}
541
542static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
543 const MachineFrameInfo *MFI) {
545 if (MFI) {
546 IsFixed = MFI->isFixedObjectIndex(FrameIndex);
547 if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
548 if (Alloca->hasName())
549 Name = Alloca->getName();
550 if (IsFixed)
551 FrameIndex -= MFI->getObjectIndexBegin();
552 }
554}
555
557 const TargetRegisterInfo *TRI) {
558 OS << "%subreg.";
559 if (TRI && Index != 0 && Index < TRI->getNumSubRegIndices())
560 OS << TRI->getSubRegIndexName(Index);
561 else
562 OS << Index;
563}
564
566 const MachineOperand &Op) {
567 if (!Op.getTargetFlags())
568 return;
569 const MachineFunction *MF = getMFIfAvailable(Op);
570 if (!MF)
571 return;
572
573 const auto *TII = MF->getSubtarget().getInstrInfo();
574 assert(TII && "expected instruction info");
575 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
576 OS << "target-flags(";
577 const bool HasDirectFlags = Flags.first;
578 const bool HasBitmaskFlags = Flags.second;
579 if (!HasDirectFlags && !HasBitmaskFlags) {
580 OS << "<unknown>) ";
581 return;
582 }
583 if (HasDirectFlags) {
584 if (const auto *Name = getTargetFlagName(TII, Flags.first))
585 OS << Name;
586 else
587 OS << "<unknown target flag>";
588 }
589 if (!HasBitmaskFlags) {
590 OS << ") ";
591 return;
592 }
593 bool IsCommaNeeded = HasDirectFlags;
594 unsigned BitMask = Flags.second;
596 for (const auto &Mask : BitMasks) {
597 // Check if the flag's bitmask has the bits of the current mask set.
598 if ((BitMask & Mask.first) == Mask.first) {
599 if (IsCommaNeeded)
600 OS << ", ";
601 IsCommaNeeded = true;
602 OS << Mask.second;
603 // Clear the bits which were serialized from the flag's bitmask.
604 BitMask &= ~(Mask.first);
605 }
606 }
607 if (BitMask) {
608 // When the resulting flag's bitmask isn't zero, we know that we didn't
609 // serialize all of the bit flags.
610 if (IsCommaNeeded)
611 OS << ", ";
612 OS << "<unknown bitmask target flag>";
613 }
614 OS << ") ";
615}
616
618 OS << "<mcsymbol " << Sym << ">";
619}
620
622 unsigned FrameIndex,
623 bool IsFixed, StringRef Name) {
624 if (IsFixed) {
625 OS << "%fixed-stack." << FrameIndex;
626 return;
627 }
628
629 OS << "%stack." << FrameIndex;
630 if (!Name.empty())
631 OS << '.' << Name;
632}
633
635 if (Offset == 0)
636 return;
637 if (Offset < 0) {
638 OS << " - " << -Offset;
639 return;
640 }
641 OS << " + " << Offset;
642}
643
645 if (Slot == -1)
646 OS << "<badref>";
647 else
648 OS << Slot;
649}
650
651static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
652 const TargetRegisterInfo *TRI) {
653 switch (CFI.getOperation()) {
655 OS << "same_value ";
656 if (MCSymbol *Label = CFI.getLabel())
659 break;
661 OS << "remember_state ";
662 if (MCSymbol *Label = CFI.getLabel())
664 break;
666 OS << "restore_state ";
667 if (MCSymbol *Label = CFI.getLabel())
669 break;
671 OS << "offset ";
672 if (MCSymbol *Label = CFI.getLabel())
675 OS << ", " << CFI.getOffset();
676 break;
678 OS << "def_cfa_register ";
679 if (MCSymbol *Label = CFI.getLabel())
682 break;
684 OS << "def_cfa_offset ";
685 if (MCSymbol *Label = CFI.getLabel())
687 OS << CFI.getOffset();
688 break;
690 OS << "def_cfa ";
691 if (MCSymbol *Label = CFI.getLabel())
694 OS << ", " << CFI.getOffset();
695 break;
697 OS << "llvm_def_aspace_cfa ";
698 if (MCSymbol *Label = CFI.getLabel())
701 OS << ", " << CFI.getOffset();
702 OS << ", " << CFI.getAddressSpace();
703 break;
705 OS << "rel_offset ";
706 if (MCSymbol *Label = CFI.getLabel())
709 OS << ", " << CFI.getOffset();
710 break;
712 OS << "adjust_cfa_offset ";
713 if (MCSymbol *Label = CFI.getLabel())
715 OS << CFI.getOffset();
716 break;
718 OS << "restore ";
719 if (MCSymbol *Label = CFI.getLabel())
722 break;
724 OS << "escape ";
725 if (MCSymbol *Label = CFI.getLabel())
727 if (!CFI.getValues().empty()) {
728 size_t e = CFI.getValues().size() - 1;
729 for (size_t i = 0; i < e; ++i)
730 OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
731 OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
732 }
733 break;
734 }
736 OS << "undefined ";
737 if (MCSymbol *Label = CFI.getLabel())
740 break;
742 OS << "register ";
743 if (MCSymbol *Label = CFI.getLabel())
746 OS << ", ";
748 break;
750 OS << "window_save ";
751 if (MCSymbol *Label = CFI.getLabel())
753 break;
755 OS << "negate_ra_sign_state ";
756 if (MCSymbol *Label = CFI.getLabel())
758 break;
759 default:
760 // TODO: Print the other CFI Operations.
761 OS << "<unserializable cfi directive>";
762 break;
763 }
764}
765
767 const TargetIntrinsicInfo *IntrinsicInfo) const {
768 print(OS, LLT{}, TRI, IntrinsicInfo);
769}
770
772 const TargetRegisterInfo *TRI,
773 const TargetIntrinsicInfo *IntrinsicInfo) const {
774 tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
775 ModuleSlotTracker DummyMST(nullptr);
776 print(OS, DummyMST, TypeToPrint, std::nullopt, /*PrintDef=*/false,
777 /*IsStandalone=*/true,
778 /*ShouldPrintRegisterTies=*/true,
779 /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
780}
781
783 LLT TypeToPrint, std::optional<unsigned> OpIdx,
784 bool PrintDef, bool IsStandalone,
785 bool ShouldPrintRegisterTies,
786 unsigned TiedOperandIdx,
787 const TargetRegisterInfo *TRI,
788 const TargetIntrinsicInfo *IntrinsicInfo) const {
789 printTargetFlags(OS, *this);
790 switch (getType()) {
792 Register Reg = getReg();
793 if (isImplicit())
794 OS << (isDef() ? "implicit-def " : "implicit ");
795 else if (PrintDef && isDef())
796 // Print the 'def' flag only when the operand is defined after '='.
797 OS << "def ";
798 if (isInternalRead())
799 OS << "internal ";
800 if (isDead())
801 OS << "dead ";
802 if (isKill())
803 OS << "killed ";
804 if (isUndef())
805 OS << "undef ";
806 if (isEarlyClobber())
807 OS << "early-clobber ";
808 if (getReg().isPhysical() && isRenamable())
809 OS << "renamable ";
810 // isDebug() is exactly true for register operands of a DBG_VALUE. So we
811 // simply infer it when parsing and do not need to print it.
812
813 const MachineRegisterInfo *MRI = nullptr;
814 if (Reg.isVirtual()) {
815 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
816 MRI = &MF->getRegInfo();
817 }
818 }
819
820 OS << printReg(Reg, TRI, 0, MRI);
821 // Print the sub register.
822 if (unsigned SubReg = getSubReg()) {
823 if (TRI)
824 OS << '.' << TRI->getSubRegIndexName(SubReg);
825 else
826 OS << ".subreg" << SubReg;
827 }
828 // Print the register class / bank.
829 if (Reg.isVirtual()) {
830 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
831 const MachineRegisterInfo &MRI = MF->getRegInfo();
832 if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
833 OS << ':';
834 OS << printRegClassOrBank(Reg, MRI, TRI);
835 }
836 }
837 }
838 // Print ties.
839 if (ShouldPrintRegisterTies && isTied() && !isDef())
840 OS << "(tied-def " << TiedOperandIdx << ")";
841 // Print types.
842 if (TypeToPrint.isValid())
843 OS << '(' << TypeToPrint << ')';
844 break;
845 }
847 const MIRFormatter *Formatter = nullptr;
848 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
849 const auto *TII = MF->getSubtarget().getInstrInfo();
850 assert(TII && "expected instruction info");
851 Formatter = TII->getMIRFormatter();
852 }
853 if (Formatter)
854 Formatter->printImm(OS, *getParent(), OpIdx, getImm());
855 else
856 OS << getImm();
857 break;
858 }
860 getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
861 break;
863 getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
864 break;
867 break;
869 int FrameIndex = getIndex();
870 bool IsFixed = false;
871 const MachineFrameInfo *MFI = nullptr;
872 if (const MachineFunction *MF = getMFIfAvailable(*this))
873 MFI = &MF->getFrameInfo();
874 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
875 break;
876 }
878 OS << "%const." << getIndex();
880 break;
882 OS << "target-index(";
883 const char *Name = "<unknown>";
884 if (const MachineFunction *MF = getMFIfAvailable(*this))
885 if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
886 Name = TargetIndexName;
887 OS << Name << ')';
889 break;
890 }
893 break;
895 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
897 break;
900 OS << '&';
901 if (Name.empty()) {
902 OS << "\"\"";
903 } else {
905 }
907 break;
908 }
910 OS << "blockaddress(";
911 getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
912 MST);
913 OS << ", ";
914 printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
915 OS << ')';
917 break;
918 }
920 OS << "<regmask";
921 if (TRI) {
922 unsigned NumRegsInMask = 0;
923 unsigned NumRegsEmitted = 0;
924 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
925 unsigned MaskWord = i / 32;
926 unsigned MaskBit = i % 32;
927 if (getRegMask()[MaskWord] & (1 << MaskBit)) {
928 if (PrintRegMaskNumRegs < 0 ||
929 NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
930 OS << " " << printReg(i, TRI);
931 NumRegsEmitted++;
932 }
933 NumRegsInMask++;
934 }
935 }
936 if (NumRegsEmitted != NumRegsInMask)
937 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
938 } else {
939 OS << " ...";
940 }
941 OS << ">";
942 break;
943 }
945 const uint32_t *RegMask = getRegLiveOut();
946 OS << "liveout(";
947 if (!TRI) {
948 OS << "<unknown>";
949 } else {
950 bool IsCommaNeeded = false;
951 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
952 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
953 if (IsCommaNeeded)
954 OS << ", ";
955 OS << printReg(Reg, TRI);
956 IsCommaNeeded = true;
957 }
958 }
959 }
960 OS << ")";
961 break;
962 }
965 break;
968 break;
970 OS << "dbg-instr-ref(" << getInstrRefInstrIndex() << ", "
971 << getInstrRefOpIndex() << ')';
972 break;
973 }
975 if (const MachineFunction *MF = getMFIfAvailable(*this))
976 printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
977 else
978 OS << "<cfi directive>";
979 break;
980 }
983 if (ID < Intrinsic::num_intrinsics)
984 OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';
985 else if (IntrinsicInfo)
986 OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
987 else
988 OS << "intrinsic(" << ID << ')';
989 break;
990 }
992 auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
993 OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
994 << Pred << ')';
995 break;
996 }
998 OS << "shufflemask(";
1000 StringRef Separator;
1001 for (int Elt : Mask) {
1002 if (Elt == -1)
1003 OS << Separator << "undef";
1004 else
1005 OS << Separator << Elt;
1006 Separator = ", ";
1007 }
1008
1009 OS << ')';
1010 break;
1011 }
1012}
1013
1014#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1015LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
1016#endif
1017
1018//===----------------------------------------------------------------------===//
1019// MachineMemOperand Implementation
1020//===----------------------------------------------------------------------===//
1021
1022/// getAddrSpace - Return the LLVM IR address space number that this pointer
1023/// points into.
1025
1026/// isDereferenceable - Return true if V is always dereferenceable for
1027/// Offset + Size byte.
1029 const DataLayout &DL) const {
1030 if (!V.is<const Value *>())
1031 return false;
1032
1033 const Value *BasePtr = V.get<const Value *>();
1034 if (BasePtr == nullptr)
1035 return false;
1036
1038 BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
1039}
1040
1041/// getConstantPool - Return a MachinePointerInfo record that refers to the
1042/// constant pool.
1045}
1046
1047/// getFixedStack - Return a MachinePointerInfo record that refers to the
1048/// the specified FrameIndex.
1050 int FI, int64_t Offset) {
1052}
1053
1056}
1057
1060}
1061
1063 int64_t Offset, uint8_t ID) {
1065}
1066
1069}
1070
1072 LLT type, Align a, const AAMDNodes &AAInfo,
1073 const MDNode *Ranges, SyncScope::ID SSID,
1074 AtomicOrdering Ordering,
1075 AtomicOrdering FailureOrdering)
1076 : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),
1077 AAInfo(AAInfo), Ranges(Ranges) {
1078 assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1079 isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1080 "invalid pointer value");
1081 assert((isLoad() || isStore()) && "Not a load/store!");
1082
1083 AtomicInfo.SSID = static_cast<unsigned>(SSID);
1084 assert(getSyncScopeID() == SSID && "Value truncated");
1085 AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1086 assert(getSuccessOrdering() == Ordering && "Value truncated");
1087 AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1088 assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1089}
1090
1092 uint64_t s, Align a,
1093 const AAMDNodes &AAInfo,
1094 const MDNode *Ranges, SyncScope::ID SSID,
1095 AtomicOrdering Ordering,
1096 AtomicOrdering FailureOrdering)
1097 : MachineMemOperand(ptrinfo, f,
1098 s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
1099 AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1100
1101/// Profile - Gather unique data for the object.
1102///
1104 ID.AddInteger(getOffset());
1105 ID.AddInteger(getMemoryType().getUniqueRAWLLTData());
1106 ID.AddPointer(getOpaqueValue());
1107 ID.AddInteger(getFlags());
1108 ID.AddInteger(getBaseAlign().value());
1109}
1110
1112 // The Value and Offset may differ due to CSE. But the flags and size
1113 // should be the same.
1114 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1115 assert((MMO->getSize() == ~UINT64_C(0) || getSize() == ~UINT64_C(0) ||
1116 MMO->getSize() == getSize()) &&
1117 "Size mismatch!");
1118
1119 if (MMO->getBaseAlign() >= getBaseAlign()) {
1120 // Update the alignment value.
1121 BaseAlign = MMO->getBaseAlign();
1122 // Also update the base and offset, because the new alignment may
1123 // not be applicable with the old ones.
1124 PtrInfo = MMO->PtrInfo;
1125 }
1126}
1127
1128/// getAlign - Return the minimum known alignment in bytes of the
1129/// actual memory reference.
1132}
1133
1136 const LLVMContext &Context,
1137 const MachineFrameInfo *MFI,
1138 const TargetInstrInfo *TII) const {
1139 OS << '(';
1140 if (isVolatile())
1141 OS << "volatile ";
1142 if (isNonTemporal())
1143 OS << "non-temporal ";
1144 if (isDereferenceable())
1145 OS << "dereferenceable ";
1146 if (isInvariant())
1147 OS << "invariant ";
1148 if (TII) {
1151 << "\" ";
1154 << "\" ";
1157 << "\" ";
1158 } else {
1160 OS << "\"MOTargetFlag1\" ";
1162 OS << "\"MOTargetFlag2\" ";
1164 OS << "\"MOTargetFlag3\" ";
1165 }
1166
1167 assert((isLoad() || isStore()) &&
1168 "machine memory operand must be a load or store (or both)");
1169 if (isLoad())
1170 OS << "load ";
1171 if (isStore())
1172 OS << "store ";
1173
1175
1177 OS << toIRString(getSuccessOrdering()) << ' ';
1179 OS << toIRString(getFailureOrdering()) << ' ';
1180
1181 if (getMemoryType().isValid())
1182 OS << '(' << getMemoryType() << ')';
1183 else
1184 OS << "unknown-size";
1185
1186 if (const Value *Val = getValue()) {
1187 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1188 MIRFormatter::printIRValue(OS, *Val, MST);
1189 } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1190 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1191 assert(PVal && "Expected a pseudo source value");
1192 switch (PVal->kind()) {
1194 OS << "stack";
1195 break;
1197 OS << "got";
1198 break;
1200 OS << "jump-table";
1201 break;
1203 OS << "constant-pool";
1204 break;
1206 int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1207 bool IsFixed = true;
1208 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1209 break;
1210 }
1212 OS << "call-entry ";
1213 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1214 OS, /*PrintType=*/false, MST);
1215 break;
1217 OS << "call-entry &";
1219 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1220 break;
1221 default: {
1222 const MIRFormatter *Formatter = TII->getMIRFormatter();
1223 // FIXME: This is not necessarily the correct MIR serialization format for
1224 // a custom pseudo source value, but at least it allows
1225 // MIR printing to work on a target with custom pseudo source
1226 // values.
1227 OS << "custom \"";
1228 Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1229 OS << '\"';
1230 break;
1231 }
1232 }
1233 } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1234 OS << ((isLoad() && isStore()) ? " on "
1235 : isLoad() ? " from "
1236 : " into ")
1237 << "unknown-address";
1238 }
1240 if (getSize() > 0 && getAlign() != getSize())
1241 OS << ", align " << getAlign().value();
1242 if (getAlign() != getBaseAlign())
1243 OS << ", basealign " << getBaseAlign().value();
1244 auto AAInfo = getAAInfo();
1245 if (AAInfo.TBAA) {
1246 OS << ", !tbaa ";
1247 AAInfo.TBAA->printAsOperand(OS, MST);
1248 }
1249 if (AAInfo.Scope) {
1250 OS << ", !alias.scope ";
1251 AAInfo.Scope->printAsOperand(OS, MST);
1252 }
1253 if (AAInfo.NoAlias) {
1254 OS << ", !noalias ";
1255 AAInfo.NoAlias->printAsOperand(OS, MST);
1256 }
1257 if (getRanges()) {
1258 OS << ", !range ";
1259 getRanges()->printAsOperand(OS, MST);
1260 }
1261 // FIXME: Implement addrspace printing/parsing in MIR.
1262 // For now, print this even though parsing it is not available in MIR.
1263 if (unsigned AS = getAddrSpace())
1264 OS << ", addrspace " << AS;
1265
1266 OS << ')';
1267}
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:492
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Given that RA is a live value
std::string Name
uint64_t Size
This file defines a hash set that can be used to remove duplication of nodes in a graph.
const HexagonInstrInfo * TII
static bool isDebug()
static bool isUndef(ArrayRef< int > Mask)
IRTranslator LLVM IR MI
This file contains an interface for creating legacy passes to print out IR in various granularities.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
unsigned const TargetRegisterInfo * TRI
LLVMContext & Context
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file contains some functions that are useful when dealing with strings.
@ Flags
Definition: TextStubV5.cpp:93
Class for arbitrary precision integers.
Definition: APInt.h:75
an instruction to allocate memory on the stack
Definition: Instructions.h:58
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
LLVM Basic Block Representation.
Definition: BasicBlock.h:56
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:112
Function * getFunction() const
Definition: Constants.h:907
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:718
bool isIntPredicate() const
Definition: InstrTypes.h:826
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:260
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:276
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:318
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
constexpr bool isValid() const
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
MCSymbol * getLabel() const
Definition: MCDwarf.h:643
unsigned getAddressSpace() const
Definition: MCDwarf.h:659
unsigned getRegister2() const
Definition: MCDwarf.h:654
unsigned getRegister() const
Definition: MCDwarf.h:645
int getOffset() const
Definition: MCDwarf.h:664
OpType getOperation() const
Definition: MCDwarf.h:642
StringRef getValues() const
Definition: MCDwarf.h:672
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
Metadata node.
Definition: Metadata.h:943
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:28
virtual void printImm(raw_ostream &OS, const MachineInstr &MI, std::optional< unsigned > OpIdx, int64_t Imm) const
Implement target specific printing for machine operand immediate value, so that we can have more mean...
Definition: MIRFormatter.h:39
virtual void printCustomPseudoSourceValue(raw_ostream &OS, ModuleSlotTracker &MST, const PseudoSourceValue &PSV) const
Implement target specific printing of target custom pseudo source value.
Definition: MIRFormatter.h:56
static void printIRValue(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)
Helper functions to print IR value as MIR serialization format which will be useful for target specif...
Definition: MIRPrinter.cpp:939
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
int getObjectIndexBegin() const
Return the minimum frame object index.
PseudoSourceValueManager & getPSVManager() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:706
A description of a memory reference used in the backend.
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
const PseudoSourceValue * getPseudoValue() const
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.
LLT getMemoryType() const
Return the memory type of the memory reference.
unsigned getAddrSpace() const
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
const MDNode * getRanges() const
Return the range tag for the memory reference.
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
uint64_t getSize() const
Return the size in bytes of the memory reference.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
const void * getOpaqueValue() const
Flags
Flags values. These may be or'd together.
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
Flags getFlags() const
Return the raw flags of the source value,.
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
const Value * getValue() const
Return the base address of the memory access.
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
unsigned getInstrRefOpIndex() const
void setInstrRefInstrIndex(unsigned InstrIdx)
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
const GlobalValue * getGlobal() const
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
void setInstrRefOpIndex(unsigned OpIdx)
const ConstantInt * getCImm() const
const char * getTargetIndexName() const
getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
int64_t getImm() const
unsigned getInstrRefInstrIndex() const
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
bool isImplicit() const
void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
void setIsRenamable(bool Val=true)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const MDNode * getMetadata() const
MachineBasicBlock * getMBB() const
ArrayRef< int > getShuffleMask() const
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
void setReg(Register Reg)
Change the register this operand corresponds to.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
unsigned getCFIIndex() const
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
void ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx, unsigned TargetFlags=0)
Replace this operand with an Instruction Reference.
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
const BlockAddress * getBlockAddress() const
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
void setOffset(int64_t Offset)
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
unsigned getTargetFlags() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
void setIsUndef(bool Val=true)
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
Intrinsic::ID getIntrinsicID() const
bool isInternalRead() const
void setTargetFlags(unsigned F)
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void setIndex(int Idx)
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
const ConstantFP * getFPImm() const
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
unsigned getPredicate() const
MCSymbol * getMCSymbol() const
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_Predicate
Generic predicate for ISel.
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
@ MO_CImmediate
Immediate >64bit operand.
@ MO_BlockAddress
Address of a basic block.
@ MO_DbgInstrRef
Integer indices referring to an instruction+operand.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_IntrinsicID
Intrinsic ID for ISel.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
@ MO_TargetIndex
Target-dependent index+offset operand.
@ MO_Metadata
Metadata reference (for debug info)
@ MO_FPImmediate
Floating-point immediate operand.
@ MO_RegisterLiveOut
Mask of live-out registers.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4887
Manage lifetime of a slot tracker for printing IR.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:888
const Function * getCurrentFunction() const
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:874
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:142
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:155
bool is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:150
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot.
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like).
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function,...
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
bool empty() const
Definition: SmallVector.h:94
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
TargetInstrInfo - Interface to description of machine instruction set.
TargetIntrinsicInfo - Interface to description of machine instruction set.
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:4781
bool hasName() const
Definition: Value.h:261
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:308
An opaque object representing a hash code.
Definition: Hashing.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
StringRef getBaseName(ID id)
Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....
Definition: Function.cpp:974
@ System
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:57
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
hash_code hash_value(const FixedPointSemantics &Val)
Definition: APFixedPoint.h:128
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
Definition: Loads.cpp:201
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
stable_hash stable_hash_combine_array(const stable_hash *P, size_t C)
Definition: StableHashing.h:92
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
AtomicOrdering
Atomic ordering for LLVM's memory model.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1846
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:212
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:613
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:358
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
MDNode * Scope
The tag for alias scope specification (used with noalias).
Definition: Metadata.h:674
MDNode * TBAA
The tag for type-based alias analysis.
Definition: Metadata.h:668
MDNode * NoAlias
The tag specifying the noalias scope.
Definition: Metadata.h:677
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
int64_t Offset
Offset - This is an offset from the base Value*.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.