27#define DEBUG_TYPE "asm-printer"
33 cl::desc(
"Use full register names when printing assembly"));
38 cl::desc(
"Prints full register names with vs{31-63} as v{0-31}"));
44 cl::desc(
"Prints full register names with percent"));
46#define PRINT_ALIAS_INSTR
47#include "PPCGenAsmWriter.inc"
62 (
MI->getOpcode() == PPC::ADDIS8 ||
MI->getOpcode() == PPC::ADDIS) &&
63 MI->getOperand(2).isExpr()) {
64 assert((
MI->getOperand(0).isReg() &&
MI->getOperand(1).isReg()) &&
65 "The first and the second operand of an addis instruction"
66 " should be registers.");
68 assert(isa<MCSymbolRefExpr>(
MI->getOperand(2).getExpr()) &&
69 "The third operand of an addis instruction should be a symbol "
70 "reference expression if it is an expression at all.");
85 unsigned LastOp =
MI->getNumOperands() - 1;
86 if (
MI->getNumOperands() > 1) {
95 if (
MI->getOpcode() == PPC::PLDpc) {
98 Symbol.print(O, &
MAI);
103 Symbol.print(O, &
MAI);
104 O <<
"-8,R_PPC64_PCREL_OPT,.-(";
105 Symbol.print(O, &
MAI);
113 if (
MI->getOpcode() == PPC::RLWINM) {
114 unsigned char SH =
MI->getOperand(2).getImm();
115 unsigned char MB =
MI->getOperand(3).getImm();
116 unsigned char ME =
MI->getOperand(4).getImm();
117 bool useSubstituteMnemonic =
false;
118 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
119 O <<
"\tslwi "; useSubstituteMnemonic =
true;
121 if (SH <= 31 && MB == (32-SH) && ME == 31) {
122 O <<
"\tsrwi "; useSubstituteMnemonic =
true;
125 if (useSubstituteMnemonic) {
129 O <<
", " << (
unsigned int)SH;
136 if (
MI->getOpcode() == PPC::RLDICR ||
137 MI->getOpcode() == PPC::RLDICR_32) {
138 unsigned char SH =
MI->getOperand(2).getImm();
139 unsigned char ME =
MI->getOperand(3).getImm();
146 O <<
", " << (
unsigned int)SH;
162 if ((
MI->getOpcode() == PPC::DCBT ||
MI->getOpcode() == PPC::DCBTST) &&
164 unsigned char TH =
MI->getOperand(0).getImm();
166 if (
MI->getOpcode() == PPC::DCBTST)
172 bool IsBookE = STI.
hasFeature(PPC::FeatureBookE);
173 if (IsBookE && TH != 0 && TH != 16)
174 O << (
unsigned int) TH <<
", ";
180 if (!IsBookE && TH != 0 && TH != 16)
181 O <<
", " << (
unsigned int) TH;
187 if (
MI->getOpcode() == PPC::DCBF) {
188 unsigned char L =
MI->getOperand(0).getImm();
189 if (!L || L == 1 || L == 3 || L == 4 || L == 6) {
220 const char *Modifier) {
221 unsigned Code =
MI->getOperand(OpNo).getImm();
311 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
318 unsigned Code =
MI->getOperand(OpNo).getImm();
328 unsigned int Value =
MI->getOperand(OpNo).getImm();
330 O << (
unsigned int)
Value;
336 unsigned int Value =
MI->getOperand(OpNo).getImm();
338 O << (
unsigned int)
Value;
344 unsigned int Value =
MI->getOperand(OpNo).getImm();
346 O << (
unsigned int)
Value;
352 unsigned int Value =
MI->getOperand(OpNo).getImm();
354 O << (
unsigned int)
Value;
360 int Value =
MI->getOperand(OpNo).getImm();
368 unsigned int Value =
MI->getOperand(OpNo).getImm();
370 O << (
unsigned int)
Value;
376 unsigned int Value =
MI->getOperand(OpNo).getImm();
378 O << (
unsigned int)
Value;
384 unsigned int Value =
MI->getOperand(OpNo).getImm();
386 O << (
unsigned int)
Value;
392 unsigned int Value =
MI->getOperand(OpNo).getImm();
394 O << (
unsigned int)
Value;
403 unsigned char Value =
MI->getOperand(OpNo).getImm();
404 O << (
unsigned int)
Value;
410 unsigned short Value =
MI->getOperand(OpNo).getImm();
411 assert(
Value <= 1023 &&
"Invalid u10imm argument!");
412 O << (
unsigned short)
Value;
418 unsigned short Value =
MI->getOperand(OpNo).getImm();
419 assert(
Value <= 4095 &&
"Invalid u12imm argument!");
420 O << (
unsigned short)
Value;
426 if (
MI->getOperand(OpNo).isImm())
427 O << (short)
MI->getOperand(OpNo).getImm();
435 if (
MI->getOperand(OpNo).isImm()) {
436 long long Value =
MI->getOperand(OpNo).getImm();
437 assert(isInt<34>(
Value) &&
"Invalid s34imm argument!");
438 O << (
long long)
Value;
447 if (
MI->getOperand(OpNo).isImm())
448 O << (
unsigned short)
MI->getOperand(OpNo).getImm();
457 if (!
MI->getOperand(OpNo).isImm())
459 int32_t Imm = SignExtend32<32>((
unsigned)
MI->getOperand(OpNo).getImm() << 2);
483 if (!
MI->getOperand(OpNo).isImm())
486 O << SignExtend32<32>((
unsigned)
MI->getOperand(OpNo).getImm() << 2);
491 unsigned CCReg =
MI->getOperand(OpNo).getReg();
495 case PPC::CR0: RegNo = 0;
break;
496 case PPC::CR1: RegNo = 1;
break;
497 case PPC::CR2: RegNo = 2;
break;
498 case PPC::CR3: RegNo = 3;
break;
499 case PPC::CR4: RegNo = 4;
break;
500 case PPC::CR5: RegNo = 5;
break;
501 case PPC::CR6: RegNo = 6;
break;
502 case PPC::CR7: RegNo = 7;
break;
504 O << (0x80 >> RegNo);
512 if (
MI->getOperand(OpNo+1).getReg() == PPC::R0)
522 O <<
MI->getOperand(OpNo).getImm();
552 if (
MI->getOperand(OpNo).getReg() == PPC::R0)
566 const MCExpr *Rhs =
nullptr;
567 if (
const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(
Op.getExpr())) {
568 RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
569 Rhs = BinExpr->getRHS();
571 RefExp = cast<MCSymbolRefExpr>(
Op.getExpr());
598bool PPCInstPrinter::showRegistersWithPercentPrefix(
const char *
RegName)
const {
616const char *PPCInstPrinter::getVerboseConditionRegName(
unsigned RegNum,
617 unsigned RegEncoding)
621 if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
623 const char *CRBits[] = {
624 "lt",
"gt",
"eq",
"un",
625 "4*cr1+lt",
"4*cr1+gt",
"4*cr1+eq",
"4*cr1+un",
626 "4*cr2+lt",
"4*cr2+gt",
"4*cr2+eq",
"4*cr2+un",
627 "4*cr3+lt",
"4*cr3+gt",
"4*cr3+eq",
"4*cr3+un",
628 "4*cr4+lt",
"4*cr4+gt",
"4*cr4+eq",
"4*cr4+un",
629 "4*cr5+lt",
"4*cr5+gt",
"4*cr5+eq",
"4*cr5+un",
630 "4*cr6+lt",
"4*cr6+gt",
"4*cr6+eq",
"4*cr6+un",
631 "4*cr7+lt",
"4*cr7+gt",
"4*cr7+eq",
"4*cr7+un"
633 return CRBits[RegEncoding];
638bool PPCInstPrinter::showRegistersWithPrefix()
const {
646 unsigned Reg =
Op.getReg();
654 if (showRegistersWithPercentPrefix(
RegName))
656 if (!showRegistersWithPrefix())
668 assert(
Op.isExpr() &&
"unknown operand kind in printOperand");
static cl::opt< bool > ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false), cl::desc("Prints full register names with vs{31-63} as v{0-31}"))
static cl::opt< bool > FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden, cl::init(false), cl::desc("Prints full register names with percent"))
static cl::opt< bool > FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false), cl::desc("Use full register names when printing assembly"))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class represents an Operation in the Expression.
bool print(raw_ostream &OS, DIDumpOptions DumpOpts, const DWARFExpression *Expr, DWARFUnit *U) const
Binary assembler expressions.
Base class for the full range of assembler expressions which are needed for parsing.
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
format_object< int64_t > formatHex(int64_t Value) const
const MCRegisterInfo & MRI
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
Instances of this class represent a single low-level machine instruction.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
const MCExpr * getExpr() const
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
Represent a reference to a symbol from inside an expression.
const MCSymbol & getSymbol() const
static StringRef getVariantKindName(VariantKind Kind)
VariantKind getKind() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
StringRef getName() const
getName - Get the symbol name.
void printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printcrbitm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU6ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS)
void printMemRegReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU1ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU4ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printS34ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printS16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU12ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printU5ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemRegImm34(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
void printU7ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(MCRegister Reg)
void printU16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemRegImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printImmZeroOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printATBitsAsHint(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printPredicateOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier=nullptr)
void printU3ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU8ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printTLSCall(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printS5ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemRegImmHash(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU2ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU10ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
StringRef - Represent a constant reference to a string, i.e.
Target - Wrapper for Target specific information.
OSType getOS() const
Get the parsed operating system type of this triple.
bool isOSAIX() const
Tests whether the OS is AIX.
bool isPPC64() const
Tests whether the target is 64-bit PowerPC (little and big endian).
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an SmallVector or SmallString.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
const char * stripRegisterPrefix(const char *RegName)
stripRegisterPrefix - This method strips the character prefix from a register name so that only the n...
unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.