LLVM 18.0.0git
PPCInstPrinter.cpp
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1//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an PPC MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
16#include "llvm/MC/MCExpr.h"
17#include "llvm/MC/MCInst.h"
18#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCSymbol.h"
25using namespace llvm;
26
27#define DEBUG_TYPE "asm-printer"
28
29// FIXME: Once the integrated assembler supports full register names, tie this
30// to the verbose-asm setting.
31static cl::opt<bool>
32FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
33 cl::desc("Use full register names when printing assembly"));
34
35// Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
36static cl::opt<bool>
37ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
38 cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
39
40// Prints full register names with percent symbol.
41static cl::opt<bool>
42FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
43 cl::init(false),
44 cl::desc("Prints full register names with percent"));
45
46#define PRINT_ALIAS_INSTR
47#include "PPCGenAsmWriter.inc"
48
50 const char *RegName = getRegisterName(Reg);
51 OS << RegName;
52}
53
55 StringRef Annot, const MCSubtargetInfo &STI,
56 raw_ostream &O) {
57 // Customize printing of the addis instruction on AIX. When an operand is a
58 // symbol reference, the instruction syntax is changed to look like a load
59 // operation, i.e:
60 // Transform: addis $rD, $rA, $src --> addis $rD, $src($rA).
61 if (TT.isOSAIX() &&
62 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
63 MI->getOperand(2).isExpr()) {
64 assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&
65 "The first and the second operand of an addis instruction"
66 " should be registers.");
67
68 assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) &&
69 "The third operand of an addis instruction should be a symbol "
70 "reference expression if it is an expression at all.");
71
72 O << "\taddis ";
73 printOperand(MI, 0, STI, O);
74 O << ", ";
75 printOperand(MI, 2, STI, O);
76 O << "(";
77 printOperand(MI, 1, STI, O);
78 O << ")";
79 return;
80 }
81
82 // Check if the last operand is an expression with the variant kind
83 // VK_PPC_PCREL_OPT. If this is the case then this is a linker optimization
84 // relocation and the .reloc directive needs to be added.
85 unsigned LastOp = MI->getNumOperands() - 1;
86 if (MI->getNumOperands() > 1) {
87 const MCOperand &Operand = MI->getOperand(LastOp);
88 if (Operand.isExpr()) {
89 const MCExpr *Expr = Operand.getExpr();
90 const MCSymbolRefExpr *SymExpr =
91 static_cast<const MCSymbolRefExpr *>(Expr);
92
93 if (SymExpr && SymExpr->getKind() == MCSymbolRefExpr::VK_PPC_PCREL_OPT) {
94 const MCSymbol &Symbol = SymExpr->getSymbol();
95 if (MI->getOpcode() == PPC::PLDpc) {
96 printInstruction(MI, Address, STI, O);
97 O << "\n";
98 Symbol.print(O, &MAI);
99 O << ":";
100 return;
101 } else {
102 O << "\t.reloc ";
103 Symbol.print(O, &MAI);
104 O << "-8,R_PPC64_PCREL_OPT,.-(";
105 Symbol.print(O, &MAI);
106 O << "-8)\n";
107 }
108 }
109 }
110 }
111
112 // Check for slwi/srwi mnemonics.
113 if (MI->getOpcode() == PPC::RLWINM) {
114 unsigned char SH = MI->getOperand(2).getImm();
115 unsigned char MB = MI->getOperand(3).getImm();
116 unsigned char ME = MI->getOperand(4).getImm();
117 bool useSubstituteMnemonic = false;
118 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
119 O << "\tslwi "; useSubstituteMnemonic = true;
120 }
121 if (SH <= 31 && MB == (32-SH) && ME == 31) {
122 O << "\tsrwi "; useSubstituteMnemonic = true;
123 SH = 32-SH;
124 }
125 if (useSubstituteMnemonic) {
126 printOperand(MI, 0, STI, O);
127 O << ", ";
128 printOperand(MI, 1, STI, O);
129 O << ", " << (unsigned int)SH;
130
131 printAnnotation(O, Annot);
132 return;
133 }
134 }
135
136 if (MI->getOpcode() == PPC::RLDICR ||
137 MI->getOpcode() == PPC::RLDICR_32) {
138 unsigned char SH = MI->getOperand(2).getImm();
139 unsigned char ME = MI->getOperand(3).getImm();
140 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
141 if (63-SH == ME) {
142 O << "\tsldi ";
143 printOperand(MI, 0, STI, O);
144 O << ", ";
145 printOperand(MI, 1, STI, O);
146 O << ", " << (unsigned int)SH;
147 printAnnotation(O, Annot);
148 return;
149 }
150 }
151
152 // dcbt[st] is printed manually here because:
153 // 1. The assembly syntax is different between embedded and server targets
154 // 2. We must print the short mnemonics for TH == 0 because the
155 // embedded/server syntax default will not be stable across assemblers
156 // The syntax for dcbt is:
157 // dcbt ra, rb, th [server]
158 // dcbt th, ra, rb [embedded]
159 // where th can be omitted when it is 0. dcbtst is the same.
160 // On AIX, only emit the extended mnemonics for dcbt and dcbtst if
161 // the "modern assembler" is available.
162 if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
163 (!TT.isOSAIX() || STI.hasFeature(PPC::FeatureModernAIXAs))) {
164 unsigned char TH = MI->getOperand(0).getImm();
165 O << "\tdcbt";
166 if (MI->getOpcode() == PPC::DCBTST)
167 O << "st";
168 if (TH == 16)
169 O << "t";
170 O << " ";
171
172 bool IsBookE = STI.hasFeature(PPC::FeatureBookE);
173 if (IsBookE && TH != 0 && TH != 16)
174 O << (unsigned int) TH << ", ";
175
176 printOperand(MI, 1, STI, O);
177 O << ", ";
178 printOperand(MI, 2, STI, O);
179
180 if (!IsBookE && TH != 0 && TH != 16)
181 O << ", " << (unsigned int) TH;
182
183 printAnnotation(O, Annot);
184 return;
185 }
186
187 if (MI->getOpcode() == PPC::DCBF) {
188 unsigned char L = MI->getOperand(0).getImm();
189 if (!L || L == 1 || L == 3 || L == 4 || L == 6) {
190 O << "\tdcb";
191 if (L != 6)
192 O << "f";
193 if (L == 1)
194 O << "l";
195 if (L == 3)
196 O << "lp";
197 if (L == 4)
198 O << "ps";
199 if (L == 6)
200 O << "stps";
201 O << " ";
202
203 printOperand(MI, 1, STI, O);
204 O << ", ";
205 printOperand(MI, 2, STI, O);
206
207 printAnnotation(O, Annot);
208 return;
209 }
210 }
211
212 if (!printAliasInstr(MI, Address, STI, O))
213 printInstruction(MI, Address, STI, O);
214 printAnnotation(O, Annot);
215}
216
218 const MCSubtargetInfo &STI,
219 raw_ostream &O,
220 const char *Modifier) {
221 unsigned Code = MI->getOperand(OpNo).getImm();
222
223 if (StringRef(Modifier) == "cc") {
224 switch ((PPC::Predicate)Code) {
227 case PPC::PRED_LT:
228 O << "lt";
229 return;
232 case PPC::PRED_LE:
233 O << "le";
234 return;
237 case PPC::PRED_EQ:
238 O << "eq";
239 return;
242 case PPC::PRED_GE:
243 O << "ge";
244 return;
247 case PPC::PRED_GT:
248 O << "gt";
249 return;
252 case PPC::PRED_NE:
253 O << "ne";
254 return;
257 case PPC::PRED_UN:
258 O << "un";
259 return;
262 case PPC::PRED_NU:
263 O << "nu";
264 return;
267 llvm_unreachable("Invalid use of bit predicate code");
268 }
269 llvm_unreachable("Invalid predicate code");
270 }
271
272 if (StringRef(Modifier) == "pm") {
273 switch ((PPC::Predicate)Code) {
274 case PPC::PRED_LT:
275 case PPC::PRED_LE:
276 case PPC::PRED_EQ:
277 case PPC::PRED_GE:
278 case PPC::PRED_GT:
279 case PPC::PRED_NE:
280 case PPC::PRED_UN:
281 case PPC::PRED_NU:
282 return;
291 O << "-";
292 return;
301 O << "+";
302 return;
305 llvm_unreachable("Invalid use of bit predicate code");
306 }
307 llvm_unreachable("Invalid predicate code");
308 }
309
310 assert(StringRef(Modifier) == "reg" &&
311 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
312 printOperand(MI, OpNo + 1, STI, O);
313}
314
315void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
316 const MCSubtargetInfo &STI,
317 raw_ostream &O) {
318 unsigned Code = MI->getOperand(OpNo).getImm();
319 if (Code == 2)
320 O << "-";
321 else if (Code == 3)
322 O << "+";
323}
324
325void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
326 const MCSubtargetInfo &STI,
327 raw_ostream &O) {
328 unsigned int Value = MI->getOperand(OpNo).getImm();
329 assert(Value <= 1 && "Invalid u1imm argument!");
330 O << (unsigned int)Value;
331}
332
333void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
334 const MCSubtargetInfo &STI,
335 raw_ostream &O) {
336 unsigned int Value = MI->getOperand(OpNo).getImm();
337 assert(Value <= 3 && "Invalid u2imm argument!");
338 O << (unsigned int)Value;
339}
340
341void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
342 const MCSubtargetInfo &STI,
343 raw_ostream &O) {
344 unsigned int Value = MI->getOperand(OpNo).getImm();
345 assert(Value <= 8 && "Invalid u3imm argument!");
346 O << (unsigned int)Value;
347}
348
349void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
350 const MCSubtargetInfo &STI,
351 raw_ostream &O) {
352 unsigned int Value = MI->getOperand(OpNo).getImm();
353 assert(Value <= 15 && "Invalid u4imm argument!");
354 O << (unsigned int)Value;
355}
356
357void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
358 const MCSubtargetInfo &STI,
359 raw_ostream &O) {
360 int Value = MI->getOperand(OpNo).getImm();
361 Value = SignExtend32<5>(Value);
362 O << (int)Value;
363}
364
366 const MCSubtargetInfo &STI,
367 raw_ostream &O) {
368 unsigned int Value = MI->getOperand(OpNo).getImm();
369 assert(Value == 0 && "Operand must be zero");
370 O << (unsigned int)Value;
371}
372
373void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
374 const MCSubtargetInfo &STI,
375 raw_ostream &O) {
376 unsigned int Value = MI->getOperand(OpNo).getImm();
377 assert(Value <= 31 && "Invalid u5imm argument!");
378 O << (unsigned int)Value;
379}
380
381void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
382 const MCSubtargetInfo &STI,
383 raw_ostream &O) {
384 unsigned int Value = MI->getOperand(OpNo).getImm();
385 assert(Value <= 63 && "Invalid u6imm argument!");
386 O << (unsigned int)Value;
387}
388
389void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
390 const MCSubtargetInfo &STI,
391 raw_ostream &O) {
392 unsigned int Value = MI->getOperand(OpNo).getImm();
393 assert(Value <= 127 && "Invalid u7imm argument!");
394 O << (unsigned int)Value;
395}
396
397// Operands of BUILD_VECTOR are signed and we use this to print operands
398// of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
399// print as unsigned.
400void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
401 const MCSubtargetInfo &STI,
402 raw_ostream &O) {
403 unsigned char Value = MI->getOperand(OpNo).getImm();
404 O << (unsigned int)Value;
405}
406
408 const MCSubtargetInfo &STI,
409 raw_ostream &O) {
410 unsigned short Value = MI->getOperand(OpNo).getImm();
411 assert(Value <= 1023 && "Invalid u10imm argument!");
412 O << (unsigned short)Value;
413}
414
416 const MCSubtargetInfo &STI,
417 raw_ostream &O) {
418 unsigned short Value = MI->getOperand(OpNo).getImm();
419 assert(Value <= 4095 && "Invalid u12imm argument!");
420 O << (unsigned short)Value;
421}
422
424 const MCSubtargetInfo &STI,
425 raw_ostream &O) {
426 if (MI->getOperand(OpNo).isImm())
427 O << (short)MI->getOperand(OpNo).getImm();
428 else
429 printOperand(MI, OpNo, STI, O);
430}
431
433 const MCSubtargetInfo &STI,
434 raw_ostream &O) {
435 if (MI->getOperand(OpNo).isImm()) {
436 long long Value = MI->getOperand(OpNo).getImm();
437 assert(isInt<34>(Value) && "Invalid s34imm argument!");
438 O << (long long)Value;
439 }
440 else
441 printOperand(MI, OpNo, STI, O);
442}
443
445 const MCSubtargetInfo &STI,
446 raw_ostream &O) {
447 if (MI->getOperand(OpNo).isImm())
448 O << (unsigned short)MI->getOperand(OpNo).getImm();
449 else
450 printOperand(MI, OpNo, STI, O);
451}
452
454 unsigned OpNo,
455 const MCSubtargetInfo &STI,
456 raw_ostream &O) {
457 if (!MI->getOperand(OpNo).isImm())
458 return printOperand(MI, OpNo, STI, O);
459 int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
461 uint64_t Target = Address + Imm;
462 if (!TT.isPPC64())
463 Target &= 0xffffffff;
464 O << formatHex(Target);
465 } else {
466 // Branches can take an immediate operand. This is used by the branch
467 // selection pass to print, for example `.+8` (for ELF) or `$+8` (for AIX)
468 // to express an eight byte displacement from the program counter.
469 if (!TT.isOSAIX())
470 O << ".";
471 else
472 O << "$";
473
474 if (Imm >= 0)
475 O << "+";
476 O << Imm;
477 }
478}
479
481 const MCSubtargetInfo &STI,
482 raw_ostream &O) {
483 if (!MI->getOperand(OpNo).isImm())
484 return printOperand(MI, OpNo, STI, O);
485
486 O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
487}
488
489void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
490 const MCSubtargetInfo &STI, raw_ostream &O) {
491 unsigned CCReg = MI->getOperand(OpNo).getReg();
492 unsigned RegNo;
493 switch (CCReg) {
494 default: llvm_unreachable("Unknown CR register");
495 case PPC::CR0: RegNo = 0; break;
496 case PPC::CR1: RegNo = 1; break;
497 case PPC::CR2: RegNo = 2; break;
498 case PPC::CR3: RegNo = 3; break;
499 case PPC::CR4: RegNo = 4; break;
500 case PPC::CR5: RegNo = 5; break;
501 case PPC::CR6: RegNo = 6; break;
502 case PPC::CR7: RegNo = 7; break;
503 }
504 O << (0x80 >> RegNo);
505}
506
507void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
508 const MCSubtargetInfo &STI,
509 raw_ostream &O) {
510 printS16ImmOperand(MI, OpNo, STI, O);
511 O << '(';
512 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
513 O << "0";
514 else
515 printOperand(MI, OpNo + 1, STI, O);
516 O << ')';
517}
518
520 const MCSubtargetInfo &STI,
521 raw_ostream &O) {
522 O << MI->getOperand(OpNo).getImm();
523 O << '(';
524 printOperand(MI, OpNo + 1, STI, O);
525 O << ')';
526}
527
529 const MCSubtargetInfo &STI,
530 raw_ostream &O) {
531 printS34ImmOperand(MI, OpNo, STI, O);
532 O << '(';
533 printImmZeroOperand(MI, OpNo + 1, STI, O);
534 O << ')';
535}
536
537void PPCInstPrinter::printMemRegImm34(const MCInst *MI, unsigned OpNo,
538 const MCSubtargetInfo &STI,
539 raw_ostream &O) {
540 printS34ImmOperand(MI, OpNo, STI, O);
541 O << '(';
542 printOperand(MI, OpNo + 1, STI, O);
543 O << ')';
544}
545
546void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
547 const MCSubtargetInfo &STI,
548 raw_ostream &O) {
549 // When used as the base register, r0 reads constant zero rather than
550 // the value contained in the register. For this reason, the darwin
551 // assembler requires that we print r0 as 0 (no r) when used as the base.
552 if (MI->getOperand(OpNo).getReg() == PPC::R0)
553 O << "0";
554 else
555 printOperand(MI, OpNo, STI, O);
556 O << ", ";
557 printOperand(MI, OpNo + 1, STI, O);
558}
559
560void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
561 const MCSubtargetInfo &STI, raw_ostream &O) {
562 // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
563 // come at the _end_ of the expression.
564 const MCOperand &Op = MI->getOperand(OpNo);
565 const MCSymbolRefExpr *RefExp = nullptr;
566 const MCExpr *Rhs = nullptr;
567 if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
568 RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
569 Rhs = BinExpr->getRHS();
570 } else
571 RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
572
573 O << RefExp->getSymbol().getName();
574 // The variant kind VK_PPC_NOTOC needs to be handled as a special case
575 // because we do not want the assembly to print out the @notoc at the
576 // end like __tls_get_addr(x@tlsgd)@notoc. Instead we want it to look
577 // like __tls_get_addr@notoc(x@tlsgd).
578 if (RefExp->getKind() == MCSymbolRefExpr::VK_PPC_NOTOC)
579 O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
580 O << '(';
581 printOperand(MI, OpNo + 1, STI, O);
582 O << ')';
583 if (RefExp->getKind() != MCSymbolRefExpr::VK_None &&
585 O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
586 if (Rhs) {
587 SmallString<0> Buf;
588 raw_svector_ostream Tmp(Buf);
589 Rhs->print(Tmp, &MAI);
590 if (isdigit(Buf[0]))
591 O << '+';
592 O << Buf;
593 }
594}
595
596/// showRegistersWithPercentPrefix - Check if this register name should be
597/// printed with a percentage symbol as prefix.
598bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
600 return false;
601
602 switch (RegName[0]) {
603 default:
604 return false;
605 case 'r':
606 case 'f':
607 case 'q':
608 case 'v':
609 case 'c':
610 return true;
611 }
612}
613
614/// getVerboseConditionalRegName - This method expands the condition register
615/// when requested explicitly or targetting Darwin.
616const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
617 unsigned RegEncoding)
618 const {
619 if (!FullRegNames)
620 return nullptr;
621 if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
622 return nullptr;
623 const char *CRBits[] = {
624 "lt", "gt", "eq", "un",
625 "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
626 "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
627 "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
628 "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
629 "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
630 "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
631 "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
632 };
633 return CRBits[RegEncoding];
634}
635
636// showRegistersWithPrefix - This method determines whether registers
637// should be number-only or include the prefix.
638bool PPCInstPrinter::showRegistersWithPrefix() const {
640}
641
642void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
643 const MCSubtargetInfo &STI, raw_ostream &O) {
644 const MCOperand &Op = MI->getOperand(OpNo);
645 if (Op.isReg()) {
646 unsigned Reg = Op.getReg();
647 if (!ShowVSRNumsAsVR)
648 Reg = PPC::getRegNumForOperand(MII.get(MI->getOpcode()), Reg, OpNo);
649
650 const char *RegName;
651 RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
652 if (RegName == nullptr)
654 if (showRegistersWithPercentPrefix(RegName))
655 O << "%";
656 if (!showRegistersWithPrefix())
658
659 O << RegName;
660 return;
661 }
662
663 if (Op.isImm()) {
664 O << Op.getImm();
665 return;
666 }
667
668 assert(Op.isExpr() && "unknown operand kind in printOperand");
669 Op.getExpr()->print(O, &MAI);
670}
IRTranslator LLVM IR MI
#define RegName(no)
static cl::opt< bool > ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false), cl::desc("Prints full register names with vs{31-63} as v{0-31}"))
static cl::opt< bool > FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden, cl::init(false), cl::desc("Prints full register names with percent"))
static cl::opt< bool > FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false), cl::desc("Use full register names when printing assembly"))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This class represents an Operation in the Expression.
bool print(raw_ostream &OS, DIDumpOptions DumpOpts, const DWARFExpression *Expr, DWARFUnit *U) const
Binary assembler expressions.
Definition: MCExpr.h:484
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
format_object< int64_t > formatHex(int64_t Value) const
const MCInstrInfo & MII
Definition: MCInstPrinter.h:52
const MCRegisterInfo & MRI
Definition: MCInstPrinter.h:53
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:51
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
Definition: MCInstPrinter.h:74
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
const MCExpr * getExpr() const
Definition: MCInst.h:114
bool isExpr() const
Definition: MCInst.h:65
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
const MCSymbol & getSymbol() const
Definition: MCExpr.h:402
static StringRef getVariantKindName(VariantKind Kind)
Definition: MCExpr.cpp:221
VariantKind getKind() const
Definition: MCExpr.h:404
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:206
void printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printcrbitm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU6ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS)
void printMemRegReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU1ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU4ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printS34ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printS16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU12ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printU5ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemRegImm34(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
void printU7ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(MCRegister Reg)
void printU16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemRegImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printImmZeroOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printATBitsAsHint(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printPredicateOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier=nullptr)
void printU3ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU8ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printTLSCall(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printS5ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemRegImmHash(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU2ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printU10ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Target - Wrapper for Target specific information.
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:364
bool isOSAIX() const
Tests whether the OS is AIX.
Definition: Triple.h:670
bool isPPC64() const
Tests whether the target is 64-bit PowerPC (little and big endian).
Definition: Triple.h:918
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:672
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
const char * stripRegisterPrefix(const char *RegName)
stripRegisterPrefix - This method strips the character prefix from a register name so that only the n...
unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18