LLVM  13.0.0git
R600Subtarget.h
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1 //=====-- R600Subtarget.h - Define Subtarget for AMDGPU R600 ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //==-----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// AMDGPU R600 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
16 
17 #include "AMDGPUSubtarget.h"
18 #include "R600FrameLowering.h"
19 #include "R600ISelLowering.h"
20 #include "R600InstrInfo.h"
21 #include "Utils/AMDGPUBaseInfo.h"
23 
24 namespace llvm {
25 
26 class MCInst;
27 class MCInstrInfo;
28 
29 } // namespace llvm
30 
31 #define GET_SUBTARGETINFO_HEADER
32 #include "R600GenSubtargetInfo.inc"
33 
34 namespace llvm {
35 
36 class R600Subtarget final : public R600GenSubtargetInfo,
37  public AMDGPUSubtarget {
38 private:
39  R600InstrInfo InstrInfo;
40  R600FrameLowering FrameLowering;
41  bool FMA;
42  bool CaymanISA;
43  bool CFALUBug;
44  bool HasVertexCache;
45  bool R600ALUInst;
46  bool FP64;
47  short TexVTXClauseSize;
48  Generation Gen;
49  R600TargetLowering TLInfo;
50  InstrItineraryData InstrItins;
52 
53 public:
54  R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
55  const TargetMachine &TM);
56 
57  const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; }
58 
59  const R600FrameLowering *getFrameLowering() const override {
60  return &FrameLowering;
61  }
62 
63  const R600TargetLowering *getTargetLowering() const override {
64  return &TLInfo;
65  }
66 
67  const R600RegisterInfo *getRegisterInfo() const override {
68  return &InstrInfo.getRegisterInfo();
69  }
70 
71  const InstrItineraryData *getInstrItineraryData() const override {
72  return &InstrItins;
73  }
74 
75  // Nothing implemented, just prevent crashes on use.
76  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
77  return &TSInfo;
78  }
79 
81 
83  return Gen;
84  }
85 
86  Align getStackAlignment() const { return Align(4); }
87 
89  StringRef GPU, StringRef FS);
90 
91  bool hasBFE() const {
92  return (getGeneration() >= EVERGREEN);
93  }
94 
95  bool hasBFI() const {
96  return (getGeneration() >= EVERGREEN);
97  }
98 
99  bool hasBCNT(unsigned Size) const {
100  if (Size == 32)
101  return (getGeneration() >= EVERGREEN);
102 
103  return false;
104  }
105 
106  bool hasBORROW() const {
107  return (getGeneration() >= EVERGREEN);
108  }
109 
110  bool hasCARRY() const {
111  return (getGeneration() >= EVERGREEN);
112  }
113 
114  bool hasCaymanISA() const {
115  return CaymanISA;
116  }
117 
118  bool hasFFBL() const {
119  return (getGeneration() >= EVERGREEN);
120  }
121 
122  bool hasFFBH() const {
123  return (getGeneration() >= EVERGREEN);
124  }
125 
126  bool hasFMA() const { return FMA; }
127 
128  bool hasCFAluBug() const { return CFALUBug; }
129 
130  bool hasVertexCache() const { return HasVertexCache; }
131 
132  short getTexVTXClauseSize() const { return TexVTXClauseSize; }
133 
134  bool enableMachineScheduler() const override {
135  return true;
136  }
137 
138  bool enableSubRegLiveness() const override {
139  return true;
140  }
141 
142  /// \returns Maximum number of work groups per compute unit supported by the
143  /// subtarget and limited by given \p FlatWorkGroupSize.
144  unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {
145  return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize);
146  }
147 
148  /// \returns Minimum flat work group size supported by the subtarget.
149  unsigned getMinFlatWorkGroupSize() const override {
151  }
152 
153  /// \returns Maximum flat work group size supported by the subtarget.
154  unsigned getMaxFlatWorkGroupSize() const override {
156  }
157 
158  /// \returns Number of waves per execution unit required to support the given
159  /// \p FlatWorkGroupSize.
160  unsigned
161  getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override {
162  return AMDGPU::IsaInfo::getWavesPerEUForWorkGroup(this, FlatWorkGroupSize);
163  }
164 
165  /// \returns Minimum number of waves per execution unit supported by the
166  /// subtarget.
167  unsigned getMinWavesPerEU() const override {
169  }
170 };
171 
172 } // end namespace llvm
173 
174 #endif // LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm
Definition: AllocatorList.h:23
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::R600Subtarget::getSelectionDAGInfo
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
Definition: R600Subtarget.h:76
llvm::R600Subtarget::initializeSubtargetDependencies
R600Subtarget & initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS)
Definition: AMDGPUSubtarget.cpp:68
llvm::R600FrameLowering
Definition: R600FrameLowering.h:16
llvm::R600Subtarget::R600Subtarget
R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
Definition: AMDGPUSubtarget.cpp:618
llvm::R600Subtarget::getInstrInfo
const R600InstrInfo * getInstrInfo() const override
Definition: R600Subtarget.h:57
llvm::R600Subtarget::getStackAlignment
Align getStackAlignment() const
Definition: R600Subtarget.h:86
llvm::R600Subtarget::getMaxFlatWorkGroupSize
unsigned getMaxFlatWorkGroupSize() const override
Definition: R600Subtarget.h:154
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::R600Subtarget::hasBCNT
bool hasBCNT(unsigned Size) const
Definition: R600Subtarget.h:99
llvm::AMDGPU::IsaInfo::getMinWavesPerEU
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:530
llvm::R600Subtarget::hasCARRY
bool hasCARRY() const
Definition: R600Subtarget.h:110
llvm::R600Subtarget::getMaxWorkGroupsPerCU
unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override
Definition: R600Subtarget.h:144
llvm::R600Subtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: R600Subtarget.h:134
llvm::R600Subtarget::hasFFBL
bool hasFFBL() const
Definition: R600Subtarget.h:118
llvm::X86AS::FS
@ FS
Definition: X86.h:188
R600FrameLowering.h
R600ISelLowering.h
llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:518
llvm::R600RegisterInfo
Definition: R600RegisterInfo.h:22
llvm::R600Subtarget::hasCaymanISA
bool hasCaymanISA() const
Definition: R600Subtarget.h:114
llvm::R600Subtarget::hasBFE
bool hasBFE() const
Definition: R600Subtarget.h:91
llvm::R600Subtarget::hasFMA
bool hasFMA() const
Definition: R600Subtarget.h:126
AMDGPUSubtarget.h
llvm::R600Subtarget::getInstrItineraryData
const InstrItineraryData * getInstrItineraryData() const override
Definition: R600Subtarget.h:71
llvm::SelectionDAGTargetInfo
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
Definition: SelectionDAGTargetInfo.h:31
llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:549
R600InstrInfo.h
llvm::R600Subtarget::getTexVTXClauseSize
short getTexVTXClauseSize() const
Definition: R600Subtarget.h:132
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::R600Subtarget::getMinWavesPerEU
unsigned getMinWavesPerEU() const override
Definition: R600Subtarget.h:167
llvm::R600TargetLowering
Definition: R600ISelLowering.h:24
llvm::R600Subtarget
Definition: R600Subtarget.h:36
llvm::AMDGPUSubtarget
Definition: AMDGPUSubtarget.h:29
llvm::R600Subtarget::hasBORROW
bool hasBORROW() const
Definition: R600Subtarget.h:106
llvm::R600Subtarget::hasCFAluBug
bool hasCFAluBug() const
Definition: R600Subtarget.h:128
llvm::R600Subtarget::hasBFI
bool hasBFI() const
Definition: R600Subtarget.h:95
llvm::R600Subtarget::getGeneration
Generation getGeneration() const
Definition: R600Subtarget.h:82
llvm::R600Subtarget::hasFFBH
bool hasFFBH() const
Definition: R600Subtarget.h:122
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::R600InstrInfo::getRegisterInfo
const R600RegisterInfo & getRegisterInfo() const
Definition: R600InstrInfo.h:71
llvm::R600Subtarget::getFrameLowering
const R600FrameLowering * getFrameLowering() const override
Definition: R600Subtarget.h:59
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:553
llvm::R600Subtarget::getMinFlatWorkGroupSize
unsigned getMinFlatWorkGroupSize() const override
Definition: R600Subtarget.h:149
llvm::R600Subtarget::getTargetLowering
const R600TargetLowering * getTargetLowering() const override
Definition: R600Subtarget.h:63
llvm::R600Subtarget::getWavesPerEUForWorkGroup
unsigned getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override
Definition: R600Subtarget.h:161
llvm::R600Subtarget::getRegisterInfo
const R600RegisterInfo * getRegisterInfo() const override
Definition: R600Subtarget.h:67
llvm::R600InstrInfo
Definition: R600InstrInfo.h:39
R600GenSubtargetInfo
SelectionDAGTargetInfo.h
llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:543
llvm::R600Subtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Definition: R600Subtarget.h:138
llvm::AMDGPUSubtarget::Generation
Generation
Definition: AMDGPUSubtarget.h:31
llvm::R600Subtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::R600Subtarget::hasVertexCache
bool hasVertexCache() const
Definition: R600Subtarget.h:130
llvm::AMDGPUSubtarget::EVERGREEN
@ EVERGREEN
Definition: AMDGPUSubtarget.h:35
AMDGPUBaseInfo.h