LLVM 19.0.0git
R600Subtarget.h
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1//=====-- R600Subtarget.h - Define Subtarget for AMDGPU R600 ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//==-----------------------------------------------------------------------===//
8//
9/// \file
10/// AMDGPU R600 specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
15#define LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
16
17#include "AMDGPUSubtarget.h"
18#include "R600FrameLowering.h"
19#include "R600ISelLowering.h"
20#include "R600InstrInfo.h"
23
24#define GET_SUBTARGETINFO_HEADER
25#include "R600GenSubtargetInfo.inc"
26
27namespace llvm {
28
30 public AMDGPUSubtarget {
31private:
32 R600InstrInfo InstrInfo;
33 R600FrameLowering FrameLowering;
34 bool FMA = false;
35 bool CaymanISA = false;
36 bool CFALUBug = false;
37 bool HasVertexCache = false;
38 bool R600ALUInst = false;
39 bool FP64 = false;
40 short TexVTXClauseSize = 0;
41 Generation Gen = R600;
42 R600TargetLowering TLInfo;
43 InstrItineraryData InstrItins;
45
46public:
47 R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
48 const TargetMachine &TM);
49
50 const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; }
51
52 const R600FrameLowering *getFrameLowering() const override {
53 return &FrameLowering;
54 }
55
56 const R600TargetLowering *getTargetLowering() const override {
57 return &TLInfo;
58 }
59
60 const R600RegisterInfo *getRegisterInfo() const override {
61 return &InstrInfo.getRegisterInfo();
62 }
63
64 const InstrItineraryData *getInstrItineraryData() const override {
65 return &InstrItins;
66 }
67
68 // Nothing implemented, just prevent crashes on use.
70 return &TSInfo;
71 }
72
74
76 return Gen;
77 }
78
79 Align getStackAlignment() const { return Align(4); }
80
82 StringRef GPU, StringRef FS);
83
84 bool hasBFE() const {
85 return (getGeneration() >= EVERGREEN);
86 }
87
88 bool hasBFI() const {
89 return (getGeneration() >= EVERGREEN);
90 }
91
92 bool hasBCNT(unsigned Size) const {
93 if (Size == 32)
94 return (getGeneration() >= EVERGREEN);
95
96 return false;
97 }
98
99 bool hasBORROW() const {
100 return (getGeneration() >= EVERGREEN);
101 }
102
103 bool hasCARRY() const {
104 return (getGeneration() >= EVERGREEN);
105 }
106
107 bool hasCaymanISA() const {
108 return CaymanISA;
109 }
110
111 bool hasFFBL() const {
112 return (getGeneration() >= EVERGREEN);
113 }
114
115 bool hasFFBH() const {
116 return (getGeneration() >= EVERGREEN);
117 }
118
119 bool hasFMA() const { return FMA; }
120
121 bool hasCFAluBug() const { return CFALUBug; }
122
123 bool hasVertexCache() const { return HasVertexCache; }
124
125 short getTexVTXClauseSize() const { return TexVTXClauseSize; }
126
127 bool enableMachineScheduler() const override {
128 return true;
129 }
130
131 bool enableSubRegLiveness() const override {
132 return true;
133 }
134
135 /// \returns Maximum number of work groups per compute unit supported by the
136 /// subtarget and limited by given \p FlatWorkGroupSize.
137 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {
138 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize);
139 }
140
141 /// \returns Minimum flat work group size supported by the subtarget.
142 unsigned getMinFlatWorkGroupSize() const override {
144 }
145
146 /// \returns Maximum flat work group size supported by the subtarget.
147 unsigned getMaxFlatWorkGroupSize() const override {
149 }
150
151 /// \returns Number of waves per execution unit required to support the given
152 /// \p FlatWorkGroupSize.
153 unsigned
154 getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override {
155 return AMDGPU::IsaInfo::getWavesPerEUForWorkGroup(this, FlatWorkGroupSize);
156 }
157
158 /// \returns Minimum number of waves per execution unit supported by the
159 /// subtarget.
160 unsigned getMinWavesPerEU() const override {
162 }
163};
164
165} // end namespace llvm
166
167#endif // LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
Base class for AMDGPU specific classes of TargetSubtarget.
uint64_t Size
const char LLVMTargetMachineRef TM
R600 DAG Lowering interface definition.
Interface definition for R600InstrInfo.
Itinerary data supplied by a subtarget to be used by a target.
const R600RegisterInfo & getRegisterInfo() const
Definition: R600InstrInfo.h:70
bool hasVertexCache() const
bool hasFFBH() const
bool hasCFAluBug() const
unsigned getMinFlatWorkGroupSize() const override
unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override
bool hasFMA() const
short getTexVTXClauseSize() const
unsigned getMaxFlatWorkGroupSize() const override
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
Definition: R600Subtarget.h:69
bool hasBFI() const
Definition: R600Subtarget.h:88
unsigned getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override
const R600FrameLowering * getFrameLowering() const override
Definition: R600Subtarget.h:52
bool hasCaymanISA() const
unsigned getMinWavesPerEU() const override
bool hasCARRY() const
const R600TargetLowering * getTargetLowering() const override
Definition: R600Subtarget.h:56
const R600RegisterInfo * getRegisterInfo() const override
Definition: R600Subtarget.h:60
const R600InstrInfo * getInstrInfo() const override
Definition: R600Subtarget.h:50
bool enableSubRegLiveness() const override
R600Subtarget & initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS)
bool hasBCNT(unsigned Size) const
Definition: R600Subtarget.h:92
bool hasBORROW() const
Definition: R600Subtarget.h:99
bool hasFFBL() const
Align getStackAlignment() const
Definition: R600Subtarget.h:79
bool hasBFE() const
Definition: R600Subtarget.h:84
Generation getGeneration() const
Definition: R600Subtarget.h:75
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
const InstrItineraryData * getInstrItineraryData() const override
Definition: R600Subtarget.h:64
bool enableMachineScheduler() const override
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39