LLVM  14.0.0git
Public Types | Public Member Functions | List of all members
llvm::R600InstrInfo Class Referencefinal

#include "Target/AMDGPU/R600InstrInfo.h"

Inheritance diagram for llvm::R600InstrInfo:
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Public Types

enum  BankSwizzle {
  ALU_VEC_012_SCL_210 = 0, ALU_VEC_021_SCL_122, ALU_VEC_120_SCL_212, ALU_VEC_102_SCL_221,
  ALU_VEC_201, ALU_VEC_210
}
 

Public Member Functions

 R600InstrInfo (const R600Subtarget &)
 
const R600RegisterInfogetRegisterInfo () const
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
 
bool isLegalToSplitMBBAt (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
 
bool isReductionOp (unsigned opcode) const
 
bool isCubeOp (unsigned opcode) const
 
bool isALUInstr (unsigned Opcode) const
 
bool hasInstrModifiers (unsigned Opcode) const
 
bool isLDSInstr (unsigned Opcode) const
 
bool isLDSRetInstr (unsigned Opcode) const
 
bool canBeConsideredALU (const MachineInstr &MI) const
 
bool isTransOnly (unsigned Opcode) const
 
bool isTransOnly (const MachineInstr &MI) const
 
bool isVectorOnly (unsigned Opcode) const
 
bool isVectorOnly (const MachineInstr &MI) const
 
bool isExport (unsigned Opcode) const
 
bool usesVertexCache (unsigned Opcode) const
 
bool usesVertexCache (const MachineInstr &MI) const
 
bool usesTextureCache (unsigned Opcode) const
 
bool usesTextureCache (const MachineInstr &MI) const
 
bool mustBeLastInClause (unsigned Opcode) const
 
bool usesAddressRegister (MachineInstr &MI) const
 
bool definesAddressRegister (MachineInstr &MI) const
 
bool readsLDSSrcReg (const MachineInstr &MI) const
 
int getSelIdx (unsigned Opcode, unsigned SrcIdx) const
 
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs (MachineInstr &MI) const
 
unsigned isLegalUpTo (const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
 returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence. More...
 
bool FindSwizzleForVectorSlot (const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
 Enumerate all possible Swizzle sequence to find one that can meet all read port requirements. More...
 
bool fitsReadPortLimitations (const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
 Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first (in lexical order) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available. More...
 
bool fitsConstReadLimitations (const std::vector< MachineInstr * > &) const
 An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+. More...
 
bool fitsConstReadLimitations (const std::vector< unsigned > &) const
 Same but using const index set instead of MI set. More...
 
bool isVector (const MachineInstr &MI) const
 Vector instructions are instructions that must fill all instruction slots within an instruction group. More...
 
bool isMov (unsigned Opcode) const
 
DFAPacketizerCreateTargetScheduleState (const TargetSubtargetInfo &) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemvoed=nullptr) const override
 
bool isPredicated (const MachineInstr &MI) const override
 
bool isPredicable (const MachineInstr &MI) const override
 
bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const override
 
bool ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
 
bool isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
 
bool PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
 
unsigned int getPredicationCost (const MachineInstr &) const override
 
unsigned int getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
void reserveIndirectRegisters (BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const
 Reserve the registers that may be accessed using indirect addressing. More...
 
unsigned calculateIndirectAddress (unsigned RegIndex, unsigned Channel) const
 Calculate the "Indirect Address" for the given RegIndex and Channel. More...
 
const TargetRegisterClassgetIndirectAddrRegClass () const
 
int getIndirectIndexBegin (const MachineFunction &MF) const
 
int getIndirectIndexEnd (const MachineFunction &MF) const
 
MachineInstrBuilder buildIndirectWrite (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const
 Build instruction(s) for an indirect register write. More...
 
MachineInstrBuilder buildIndirectRead (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const
 Build instruction(s) for an indirect register read. More...
 
unsigned getMaxAlusPerClause () const
 
MachineInstrBuilder buildDefaultInstruction (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
 buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values. More...
 
MachineInstrbuildSlotOfVectorInstruction (MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
 
MachineInstrbuildMovImm (MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
 
MachineInstrbuildMovInstr (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const
 
int getOperandIdx (const MachineInstr &MI, unsigned Op) const
 Get the index of Op in the MachineInstr. More...
 
int getOperandIdx (unsigned Opcode, unsigned Op) const
 Get the index of Op for the given Opcode. More...
 
void setImmOperand (MachineInstr &MI, unsigned Op, int64_t Imm) const
 Helper function for setting instruction flag values. More...
 
void addFlag (MachineInstr &MI, unsigned Operand, unsigned Flag) const
 Add one of the MO_FLAG* flags to the specified Operand. More...
 
bool isFlagSet (const MachineInstr &MI, unsigned Operand, unsigned Flag) const
 Determine if the specified Flag is set on this Operand. More...
 
MachineOperandgetFlagOp (MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const
 
void clearFlag (MachineInstr &MI, unsigned Operand, unsigned Flag) const
 Clear the specified flag on the instruction. More...
 
bool isRegisterStore (const MachineInstr &MI) const
 
bool isRegisterLoad (const MachineInstr &MI) const
 
unsigned getAddressSpaceForPseudoSourceKind (unsigned Kind) const override
 

Detailed Description

Definition at line 39 of file R600InstrInfo.h.

Member Enumeration Documentation

◆ BankSwizzle

Enumerator
ALU_VEC_012_SCL_210 
ALU_VEC_021_SCL_122 
ALU_VEC_120_SCL_212 
ALU_VEC_102_SCL_221 
ALU_VEC_201 
ALU_VEC_210 

Definition at line 60 of file R600InstrInfo.h.

Constructor & Destructor Documentation

◆ R600InstrInfo()

R600InstrInfo::R600InstrInfo ( const R600Subtarget ST)
explicit

Definition at line 32 of file R600InstrInfo.cpp.

Member Function Documentation

◆ addFlag()

void R600InstrInfo::addFlag ( MachineInstr MI,
unsigned  Operand,
unsigned  Flag 
) const

Add one of the MO_FLAG* flags to the specified Operand.

Definition at line 1444 of file R600InstrInfo.cpp.

References clearFlag(), get, getFlagOp(), llvm::MachineOperand::getImm(), HAS_NATIVE_OPERANDS, MI, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NOT_LAST, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().

Referenced by insertBranch().

◆ analyzeBranch()

bool R600InstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override

◆ buildDefaultInstruction()

MachineInstrBuilder R600InstrInfo::buildDefaultInstruction ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  Opcode,
unsigned  DstReg,
unsigned  Src0Reg,
unsigned  Src1Reg = 0 
) const

buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values.

You can use this function to avoid manually specifying each instruction modifier operand when building a new instruction.

Returns
a MachineInstr with all the instruction modifiers initialized to their default values.

Definition at line 1216 of file R600InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineBasicBlock::findDebugLoc(), get, I, and MBB.

Referenced by buildMovImm(), buildMovInstr(), buildSlotOfVectorInstruction(), and copyPhysReg().

◆ buildIndirectRead()

MachineInstrBuilder R600InstrInfo::buildIndirectRead ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  ValueReg,
unsigned  Address,
unsigned  OffsetReg 
) const

Build instruction(s) for an indirect register read.

Returns
The instruction that performs the indirect register read

Definition at line 1124 of file R600InstrInfo.cpp.

References llvm::Address, I, and MBB.

◆ buildIndirectWrite()

MachineInstrBuilder R600InstrInfo::buildIndirectWrite ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  ValueReg,
unsigned  Address,
unsigned  OffsetReg 
) const

Build instruction(s) for an indirect register write.

Returns
The instruction that performs the indirect register write

Definition at line 1092 of file R600InstrInfo.cpp.

References llvm::Address, I, and MBB.

◆ buildMovImm()

MachineInstr * R600InstrInfo::buildMovImm ( MachineBasicBlock BB,
MachineBasicBlock::iterator  I,
unsigned  DstReg,
uint64_t  Imm 
) const

Definition at line 1343 of file R600InstrInfo.cpp.

References BB, buildDefaultInstruction(), I, and setImmOperand().

◆ buildMovInstr()

MachineInstr * R600InstrInfo::buildMovInstr ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  DstReg,
unsigned  SrcReg 
) const

Definition at line 1353 of file R600InstrInfo.cpp.

References buildDefaultInstruction(), I, and MBB.

Referenced by expandPostRAPseudo().

◆ buildSlotOfVectorInstruction()

MachineInstr * R600InstrInfo::buildSlotOfVectorInstruction ( MachineBasicBlock MBB,
MachineInstr MI,
unsigned  Slot,
unsigned  DstReg 
) const

◆ calculateIndirectAddress()

unsigned R600InstrInfo::calculateIndirectAddress ( unsigned  RegIndex,
unsigned  Channel 
) const

Calculate the "Indirect Address" for the given RegIndex and Channel.

We model indirect addressing using a virtual address space that can be accessed with loads and stores. The "Indirect Address" is the memory address in this virtual address space that maps to the given RegIndex and Channel.

Definition at line 996 of file R600InstrInfo.cpp.

References assert().

Referenced by expandPostRAPseudo().

◆ canBeConsideredALU()

bool R600InstrInfo::canBeConsideredALU ( const MachineInstr MI) const
Returns
true if this Opcode represents an ALU instruction or an instruction that will be lowered in ExpandSpecialInstrs Pass.

Definition at line 137 of file R600InstrInfo.cpp.

References isALUInstr(), isCubeOp(), isVector(), and MI.

◆ clearFlag()

void R600InstrInfo::clearFlag ( MachineInstr MI,
unsigned  Operand,
unsigned  Flag 
) const

Clear the specified flag on the instruction.

Definition at line 1465 of file R600InstrInfo.cpp.

References get, getFlagOp(), llvm::MachineOperand::getImm(), HAS_NATIVE_OPERANDS, MI, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().

Referenced by addFlag(), and removeBranch().

◆ ClobbersPredicate()

bool R600InstrInfo::ClobbersPredicate ( MachineInstr MI,
std::vector< MachineOperand > &  Pred,
bool  SkipDead 
) const
override

Definition at line 944 of file R600InstrInfo.cpp.

References isPredicateSetter(), and MI.

◆ copyPhysReg()

void R600InstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc 
) const
override

◆ CreateTargetScheduleState()

DFAPacketizer * R600InstrInfo::CreateTargetScheduleState ( const TargetSubtargetInfo STI) const
override

◆ definesAddressRegister()

bool R600InstrInfo::definesAddressRegister ( MachineInstr MI) const

Definition at line 212 of file R600InstrInfo.cpp.

References MI.

◆ expandPostRAPseudo()

bool R600InstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override

◆ FindSwizzleForVectorSlot()

bool R600InstrInfo::FindSwizzleForVectorSlot ( const std::vector< std::vector< std::pair< int, unsigned > > > &  IGSrcs,
std::vector< R600InstrInfo::BankSwizzle > &  SwzCandidate,
const std::vector< std::pair< int, unsigned > > &  TransSrcs,
R600InstrInfo::BankSwizzle  TransSwz 
) const

Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.

Definition at line 476 of file R600InstrInfo.cpp.

References isLegalUpTo(), and NextPossibleSolution().

Referenced by fitsReadPortLimitations().

◆ fitsConstReadLimitations() [1/2]

bool R600InstrInfo::fitsConstReadLimitations ( const std::vector< MachineInstr * > &  MIs) const

An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.

This function check if MI set in input meet this limitations

Definition at line 586 of file R600InstrInfo.cpp.

References contains(), llvm::R600RegisterInfo::getHWRegChan(), getSrcs(), i, Index, llvm::SmallSet< T, N, C >::insert(), isALUInstr(), MI, n, and llvm::SmallSet< T, N, C >::size().

◆ fitsConstReadLimitations() [2/2]

bool R600InstrInfo::fitsConstReadLimitations ( const std::vector< unsigned > &  Consts) const

Same but using const index set instead of MI set.

Definition at line 561 of file R600InstrInfo.cpp.

References assert(), i, and n.

◆ fitsReadPortLimitations()

bool R600InstrInfo::fitsReadPortLimitations ( const std::vector< MachineInstr * > &  MIs,
const DenseMap< unsigned, unsigned > &  PV,
std::vector< BankSwizzle > &  BS,
bool  isLastAluTrans 
) const

Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first (in lexical order) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available.

Otherwise returns false and undefined content in BS. isLastAluTrans should be set if the last Alu of MIs will be executed on Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to apply to the last instruction. PV holds GPR to PV registers in the Instruction Group MIs.

Definition at line 513 of file R600InstrInfo.cpp.

References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, ALU_VEC_102_SCL_221, ALU_VEC_120_SCL_212, llvm::numbers::e, FindSwizzleForVectorSlot(), getOpcode(), getOperandIdx(), i, isConstCompatible(), and move.

◆ getAddressSpaceForPseudoSourceKind()

unsigned R600InstrInfo::getAddressSpaceForPseudoSourceKind ( unsigned  Kind) const
override

◆ getFlagOp()

MachineOperand & R600InstrInfo::getFlagOp ( MachineInstr MI,
unsigned  SrcIdx = 0,
unsigned  Flag = 0 
) const
Parameters
SrcIdxThe register source to set the flag on (e.g src0, src1, src2)
FlagThe flag being set.
Returns
the operand containing the flags for this instruction.

Definition at line 1379 of file R600InstrInfo.cpp.

References assert(), get, GET_FLAG_OPERAND_IDX, getOperandIdx(), HAS_NATIVE_OPERANDS, llvm::MachineOperand::isImm(), MI, MO_FLAG_ABS, MO_FLAG_CLAMP, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NEG, MO_FLAG_NOT_LAST, R600_InstFlag::OP3, and write().

Referenced by addFlag(), and clearFlag().

◆ getIndirectAddrRegClass()

const TargetRegisterClass * R600InstrInfo::getIndirectAddrRegClass ( ) const
Returns
The register class to be used for loading and storing values from an "Indirect Address" .

Definition at line 1088 of file R600InstrInfo.cpp.

Referenced by expandPostRAPseudo(), and getIndirectIndexBegin().

◆ getIndirectIndexBegin()

int R600InstrInfo::getIndirectIndexBegin ( const MachineFunction MF) const

◆ getIndirectIndexEnd()

int R600InstrInfo::getIndirectIndexEnd ( const MachineFunction MF) const
Returns
the largest register index that will be accessed by an indirect read or write or -1 if indirect addressing is not used by this program.

Definition at line 1190 of file R600InstrInfo.cpp.

References llvm::MachineFunction::getFrameInfo(), getIndirectIndexBegin(), llvm::MachineFrameInfo::getNumObjects(), llvm::MachineFunction::getSubtarget(), llvm::MachineFrameInfo::hasVarSizedObjects(), and Offset.

◆ getInstrLatency()

unsigned int R600InstrInfo::getInstrLatency ( const InstrItineraryData ItinData,
const MachineInstr MI,
unsigned *  PredCost = nullptr 
) const
override

Definition at line 988 of file R600InstrInfo.cpp.

◆ getMaxAlusPerClause()

unsigned R600InstrInfo::getMaxAlusPerClause ( ) const

Definition at line 1212 of file R600InstrInfo.cpp.

◆ getOperandIdx() [1/2]

int R600InstrInfo::getOperandIdx ( const MachineInstr MI,
unsigned  Op 
) const

Get the index of Op in the MachineInstr.

Returns
-1 if the Instruction does not contain the specified Op.

Definition at line 1359 of file R600InstrInfo.cpp.

References MI.

Referenced by buildSlotOfVectorInstruction(), copyPhysReg(), fitsReadPortLimitations(), getFlagOp(), getSelIdx(), getSrcs(), isLDSRetInstr(), PredicateInstruction(), and setImmOperand().

◆ getOperandIdx() [2/2]

int R600InstrInfo::getOperandIdx ( unsigned  Opcode,
unsigned  Op 
) const

Get the index of Op for the given Opcode.

Returns
-1 if the Instruction does not contain the specified Op.

Definition at line 1363 of file R600InstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx().

◆ getPredicationCost()

unsigned int R600InstrInfo::getPredicationCost ( const MachineInstr ) const
override

Definition at line 984 of file R600InstrInfo.cpp.

◆ getRegisterInfo()

const R600RegisterInfo& llvm::R600InstrInfo::getRegisterInfo ( ) const
inline

Definition at line 71 of file R600InstrInfo.h.

Referenced by llvm::R600Subtarget::getRegisterInfo().

◆ getSelIdx()

int R600InstrInfo::getSelIdx ( unsigned  Opcode,
unsigned  SrcIdx 
) const
Returns
The operand Index for the Sel operand given an index to one of the instruction's src operands.

Definition at line 232 of file R600InstrInfo.cpp.

References getOperandIdx().

◆ getSrcs()

SmallVector< std::pair< MachineOperand *, int64_t >, 3 > R600InstrInfo::getSrcs ( MachineInstr MI) const
Returns
a pair for each src of an ALU instructions. The first member of a pair is the register id. If register is ALU_CONST, second member is SEL. If register is ALU_LITERAL, second member is IMM. Otherwise, second member value is undefined.

Definition at line 256 of file R600InstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), getOperandIdx(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), j(), MI, and Reg.

Referenced by fitsConstReadLimitations().

◆ hasInstrModifiers()

bool R600InstrInfo::hasInstrModifiers ( unsigned  Opcode) const

Definition at line 117 of file R600InstrInfo.cpp.

References get, R600_InstFlag::OP1, R600_InstFlag::OP2, and R600_InstFlag::OP3.

◆ insertBranch()

unsigned R600InstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int BytesAdded = nullptr 
) const
override

◆ isALUInstr()

bool R600InstrInfo::isALUInstr ( unsigned  Opcode) const
Returns
true if this Opcode represents an ALU instruction.

Definition at line 111 of file R600InstrInfo.cpp.

References R600_InstFlag::ALU_INST, and get.

Referenced by canBeConsideredALU(), fitsConstReadLimitations(), and readsLDSSrcReg().

◆ isCubeOp()

bool R600InstrInfo::isCubeOp ( unsigned  opcode) const

Definition at line 100 of file R600InstrInfo.cpp.

Referenced by canBeConsideredALU().

◆ isExport()

bool R600InstrInfo::isExport ( unsigned  Opcode) const

Definition at line 173 of file R600InstrInfo.cpp.

References get, and R600_InstFlag::IS_EXPORT.

◆ isFlagSet()

bool llvm::R600InstrInfo::isFlagSet ( const MachineInstr MI,
unsigned  Operand,
unsigned  Flag 
) const

Determine if the specified Flag is set on this Operand.

◆ isLDSInstr()

bool R600InstrInfo::isLDSInstr ( unsigned  Opcode) const

Definition at line 125 of file R600InstrInfo.cpp.

References get, R600_InstFlag::LDS_1A, R600_InstFlag::LDS_1A1D, and R600_InstFlag::LDS_1A2D.

Referenced by isLDSRetInstr().

◆ isLDSRetInstr()

bool R600InstrInfo::isLDSRetInstr ( unsigned  Opcode) const

Definition at line 133 of file R600InstrInfo.cpp.

References getOperandIdx(), and isLDSInstr().

◆ isLegalToSplitMBBAt()

bool R600InstrInfo::isLegalToSplitMBBAt ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI 
) const
override
Returns
true if MBBI can be moved into a new basic.

Definition at line 74 of file R600InstrInfo.cpp.

References E, I, llvm::R600RegisterInfo::isPhysRegLiveAcrossClauses(), and MBBI.

◆ isLegalUpTo()

unsigned R600InstrInfo::isLegalUpTo ( const std::vector< std::vector< std::pair< int, unsigned > > > &  IGSrcs,
const std::vector< R600InstrInfo::BankSwizzle > &  Swz,
const std::vector< std::pair< int, unsigned > > &  TransSrcs,
R600InstrInfo::BankSwizzle  TransSwz 
) const

returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence.

Definition at line 407 of file R600InstrInfo.cpp.

References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, llvm::numbers::e, GET_REG_INDEX, getTransSwizzle(), i, j(), Swizzle(), and Vector.

Referenced by FindSwizzleForVectorSlot().

◆ isMov()

bool R600InstrInfo::isMov ( unsigned  Opcode) const

Definition at line 85 of file R600InstrInfo.cpp.

◆ isPredicable()

bool R600InstrInfo::isPredicable ( const MachineInstr MI) const
override

Definition at line 855 of file R600InstrInfo.cpp.

References llvm::TargetInstrInfo::isPredicable(), isVector(), and MI.

◆ isPredicated()

bool R600InstrInfo::isPredicated ( const MachineInstr MI) const
override

Definition at line 840 of file R600InstrInfo.cpp.

References MI, and Reg.

◆ isProfitableToDupForIfCvt()

bool R600InstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
BranchProbability  Probability 
) const
override

Definition at line 897 of file R600InstrInfo.cpp.

◆ isProfitableToIfCvt() [1/2]

bool R600InstrInfo::isProfitableToIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
unsigned  ExtraPredCycles,
BranchProbability  Probability 
) const
override

Definition at line 878 of file R600InstrInfo.cpp.

◆ isProfitableToIfCvt() [2/2]

bool R600InstrInfo::isProfitableToIfCvt ( MachineBasicBlock TMBB,
unsigned  NumTCycles,
unsigned  ExtraTCycles,
MachineBasicBlock FMBB,
unsigned  NumFCycles,
unsigned  ExtraFCycles,
BranchProbability  Probability 
) const
override

Definition at line 886 of file R600InstrInfo.cpp.

◆ isProfitableToUnpredicate()

bool R600InstrInfo::isProfitableToUnpredicate ( MachineBasicBlock TMBB,
MachineBasicBlock FMBB 
) const
override

Definition at line 905 of file R600InstrInfo.cpp.

◆ isReductionOp()

bool R600InstrInfo::isReductionOp ( unsigned  opcode) const

Definition at line 96 of file R600InstrInfo.cpp.

◆ isRegisterLoad()

bool llvm::R600InstrInfo::isRegisterLoad ( const MachineInstr MI) const
inline

Definition at line 321 of file R600InstrInfo.h.

References get, MI, and llvm::R600InstrFlags::REGISTER_LOAD.

Referenced by expandPostRAPseudo().

◆ isRegisterStore()

bool llvm::R600InstrInfo::isRegisterStore ( const MachineInstr MI) const
inline

Definition at line 317 of file R600InstrInfo.h.

References get, MI, and llvm::R600InstrFlags::REGISTER_STORE.

Referenced by expandPostRAPseudo().

◆ isTransOnly() [1/2]

bool R600InstrInfo::isTransOnly ( const MachineInstr MI) const

Definition at line 161 of file R600InstrInfo.cpp.

References isTransOnly(), and MI.

◆ isTransOnly() [2/2]

bool R600InstrInfo::isTransOnly ( unsigned  Opcode) const

Definition at line 155 of file R600InstrInfo.cpp.

References get, and llvm::R600Subtarget::hasCaymanISA().

Referenced by isTransOnly().

◆ isVector()

bool R600InstrInfo::isVector ( const MachineInstr MI) const

Vector instructions are instructions that must fill all instruction slots within an instruction group.

Definition at line 35 of file R600InstrInfo.cpp.

References get, MI, and R600_InstFlag::VECTOR.

Referenced by canBeConsideredALU(), and isPredicable().

◆ isVectorOnly() [1/2]

bool R600InstrInfo::isVectorOnly ( const MachineInstr MI) const

Definition at line 169 of file R600InstrInfo.cpp.

References isVectorOnly(), and MI.

◆ isVectorOnly() [2/2]

bool R600InstrInfo::isVectorOnly ( unsigned  Opcode) const

Definition at line 165 of file R600InstrInfo.cpp.

References get.

Referenced by isVectorOnly().

◆ mustBeLastInClause()

bool R600InstrInfo::mustBeLastInClause ( unsigned  Opcode) const

Definition at line 198 of file R600InstrInfo.cpp.

◆ PredicateInstruction()

bool R600InstrInfo::PredicateInstruction ( MachineInstr MI,
ArrayRef< MachineOperand Pred 
) const
override

◆ readsLDSSrcReg()

bool R600InstrInfo::readsLDSSrcReg ( const MachineInstr MI) const

Definition at line 216 of file R600InstrInfo.cpp.

References contains(), E, I, isALUInstr(), and MI.

◆ removeBranch()

unsigned R600InstrInfo::removeBranch ( MachineBasicBlock MBB,
int BytesRemvoed = nullptr 
) const
override

◆ reserveIndirectRegisters()

void R600InstrInfo::reserveIndirectRegisters ( BitVector Reserved,
const MachineFunction MF,
const R600RegisterInfo TRI 
) const

Reserve the registers that may be accessed using indirect addressing.

Definition at line 1068 of file R600InstrInfo.cpp.

References llvm::MachineFunction::getSubtarget().

◆ reverseBranchCondition()

bool R600InstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

◆ setImmOperand()

void R600InstrInfo::setImmOperand ( MachineInstr MI,
unsigned  Op,
int64_t  Imm 
) const

Helper function for setting instruction flag values.

Definition at line 1367 of file R600InstrInfo.cpp.

References assert(), getOperandIdx(), and MI.

Referenced by buildMovImm(), and buildSlotOfVectorInstruction().

◆ usesAddressRegister()

bool R600InstrInfo::usesAddressRegister ( MachineInstr MI) const

Definition at line 208 of file R600InstrInfo.cpp.

References MI.

◆ usesTextureCache() [1/2]

bool R600InstrInfo::usesTextureCache ( const MachineInstr MI) const

◆ usesTextureCache() [2/2]

bool R600InstrInfo::usesTextureCache ( unsigned  Opcode) const

Definition at line 187 of file R600InstrInfo.cpp.

References get, llvm::R600Subtarget::hasVertexCache(), IS_TEX, and IS_VTX.

Referenced by usesTextureCache().

◆ usesVertexCache() [1/2]

bool R600InstrInfo::usesVertexCache ( const MachineInstr MI) const

◆ usesVertexCache() [2/2]

bool R600InstrInfo::usesVertexCache ( unsigned  Opcode) const

Definition at line 177 of file R600InstrInfo.cpp.

References get, llvm::R600Subtarget::hasVertexCache(), and IS_VTX.

Referenced by usesTextureCache(), and usesVertexCache().


The documentation for this class was generated from the following files: