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R600ISelLowering.h
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1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// R600 DAG Lowering interface definition
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
16 
17 #include "AMDGPUISelLowering.h"
19 
20 namespace llvm {
21 
22 class R600InstrInfo;
23 class R600Subtarget;
24 
26 
27  const R600Subtarget *Subtarget;
28 public:
30 
31  const R600Subtarget *getSubtarget() const;
32 
35  MachineBasicBlock *BB) const override;
36  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
37  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
40  SelectionDAG &DAG) const override;
41  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
43  bool isVarArg,
45  const SDLoc &DL, SelectionDAG &DAG,
46  SmallVectorImpl<SDValue> &InVals) const override;
48  EVT VT) const override;
49 
50  bool canMergeStoresTo(unsigned AS, EVT MemVT,
51  const MachineFunction &MF) const override;
52 
54  EVT VT, unsigned AS, Align Alignment,
56  bool *IsFast = nullptr) const override;
57 
58  virtual bool canCombineTruncStore(EVT ValVT, EVT MemVT,
59  bool LegalOperations) const override {
60  // R600 has "custom" lowering for truncating stores despite not supporting
61  // those instructions. If we allow that custom lowering in the DAG combiner
62  // then all truncates are merged into truncating stores, giving worse code
63  // generation. This hook prevents the DAG combiner performing that combine.
64  return isTruncStoreLegal(ValVT, MemVT);
65  }
66 
67 private:
68  unsigned Gen;
69  /// Each OpenCL kernel has nine implicit parameters that are stored in the
70  /// first nine dwords of a Vertex Buffer. These implicit parameters are
71  /// lowered to load instructions which retrieve the values from the Vertex
72  /// Buffer.
73  SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
74  unsigned DwordOffset) const;
75 
76  void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
77  MachineRegisterInfo & MRI, unsigned dword_offset) const;
78  SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
79  const SDLoc &DL) const;
80  SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
81 
82  SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
83  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
84  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
85  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
86  SelectionDAG &DAG) const override;
87  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
88 
89  SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
90  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
91  SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
92  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
93 
94  SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
95  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
96  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
97  SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
98  SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
99  SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
100  unsigned mainop, unsigned ovf) const;
101 
102  SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
103  SelectionDAG &DAG) const;
104  void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
105  unsigned &Channel, unsigned &PtrIncr) const;
106  bool isZero(SDValue Op) const;
107  bool isHWTrueValue(SDValue Op) const;
108  bool isHWFalseValue(SDValue Op) const;
109 
110  bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
111  SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
112  SelectionDAG &DAG) const;
113  SDValue constBufferLoad(LoadSDNode *LoadNode, int Block,
114  SelectionDAG &DAG) const;
115 
116  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
117 };
118 
119 } // End namespace llvm;
120 
121 #endif
llvm::TargetLoweringBase::isTruncStoreLegal
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
Definition: TargetLowering.h:1280
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1085
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::AMDGPUTargetLowering
Definition: AMDGPUISelLowering.h:27
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineSDNode
An SDNode that represents everything that will be needed to construct a MachineInstr.
Definition: SelectionDAGNodes.h:2762
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2297
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:847
llvm::R600TargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
XXX Only kernel functions are supported, so we can assume for now that every function is a kernel fun...
Definition: R600ISelLowering.cpp:1491
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3609
AMDGPUISelLowering.h
llvm::R600TargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Definition: R600ISelLowering.cpp:1466
llvm::R600TargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AS, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: R600ISelLowering.cpp:1568
llvm::R600TargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *IsFast=nullptr) const override
Determine if the target supports unaligned memory accesses.
Definition: R600ISelLowering.cpp:1577
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::R600TargetLowering
Definition: R600ISelLowering.h:25
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::R600Subtarget
Definition: R600Subtarget.h:35
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::StoreSDNode
This class is used to represent ISD::STORE nodes.
Definition: SelectionDAGNodes.h:2325
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::R600TargetLowering::getSubtarget
const R600Subtarget * getSubtarget() const
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::R600TargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: R600ISelLowering.cpp:449
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::R600TargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: R600ISelLowering.cpp:1755
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::R600TargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: R600ISelLowering.cpp:1561
N
#define N
llvm::R600TargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: R600ISelLowering.cpp:632
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::R600TargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: R600ISelLowering.cpp:265
MachineFunction.h
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:20
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:133
llvm::R600TargetLowering::R600TargetLowering
R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI)
Definition: R600ISelLowering.cpp:29
llvm::R600TargetLowering::canCombineTruncStore
virtual bool canCombineTruncStore(EVT ValVT, EVT MemVT, bool LegalOperations) const override
Definition: R600ISelLowering.h:58