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R600ISelLowering.h
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1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// R600 DAG Lowering interface definition
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
16 
17 #include "AMDGPUISelLowering.h"
18 
19 namespace llvm {
20 
21 class R600InstrInfo;
22 class R600Subtarget;
23 
25 
26  const R600Subtarget *Subtarget;
27 public:
29 
30  const R600Subtarget *getSubtarget() const;
31 
34  MachineBasicBlock *BB) const override;
35  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
36  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
39  SelectionDAG &DAG) const override;
40  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
42  bool isVarArg,
44  const SDLoc &DL, SelectionDAG &DAG,
45  SmallVectorImpl<SDValue> &InVals) const override;
47  EVT VT) const override;
48 
49  bool canMergeStoresTo(unsigned AS, EVT MemVT,
50  const SelectionDAG &DAG) const override;
51 
53  EVT VT, unsigned AS, Align Alignment,
55  bool *IsFast = nullptr) const override;
56 
57 private:
58  unsigned Gen;
59  /// Each OpenCL kernel has nine implicit parameters that are stored in the
60  /// first nine dwords of a Vertex Buffer. These implicit parameters are
61  /// lowered to load instructions which retrieve the values from the Vertex
62  /// Buffer.
63  SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
64  unsigned DwordOffset) const;
65 
66  void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
67  MachineRegisterInfo & MRI, unsigned dword_offset) const;
68  SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
69  const SDLoc &DL) const;
70  SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
71 
72  SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
73  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
74  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
75  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
76  SelectionDAG &DAG) const override;
77  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
78 
79  SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
80  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
81  SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
82  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
83 
84  SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
85  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
86  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
87  SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
88  SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
89  SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
90  unsigned mainop, unsigned ovf) const;
91 
92  SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
93  SelectionDAG &DAG) const;
94  void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
95  unsigned &Channel, unsigned &PtrIncr) const;
96  bool isZero(SDValue Op) const;
97  bool isHWTrueValue(SDValue Op) const;
98  bool isHWFalseValue(SDValue Op) const;
99 
100  bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
101  SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
102  SelectionDAG &DAG) const;
103  SDValue constBufferLoad(LoadSDNode *LoadNode, int Block,
104  SelectionDAG &DAG) const;
105 
106  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
107 };
108 
109 } // End namespace llvm;
110 
111 #endif
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
llvm
Definition: AllocatorList.h:23
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::AMDGPUTargetLowering
Definition: AMDGPUISelLowering.h:27
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineSDNode
An SDNode that represents everything that will be needed to construct a MachineInstr.
Definition: SelectionDAGNodes.h:2523
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2256
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:853
llvm::R600TargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
XXX Only kernel functions are supported, so we can assume for now that every function is a kernel fun...
Definition: R600ISelLowering.cpp:1489
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::R600TargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: R600ISelLowering.cpp:1566
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3506
AMDGPUISelLowering.h
llvm::R600TargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Definition: R600ISelLowering.cpp:1464
llvm::R600TargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *IsFast=nullptr) const override
Determine if the target supports unaligned memory accesses.
Definition: R600ISelLowering.cpp:1575
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::R600TargetLowering
Definition: R600ISelLowering.h:24
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::R600Subtarget
Definition: R600Subtarget.h:36
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::StoreSDNode
This class is used to represent ISD::STORE nodes.
Definition: SelectionDAGNodes.h:2284
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::R600TargetLowering::getSubtarget
const R600Subtarget * getSubtarget() const
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::R600TargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: R600ISelLowering.cpp:447
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::R600TargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: R600ISelLowering.cpp:1753
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::R600TargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: R600ISelLowering.cpp:1559
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
N
#define N
llvm::R600TargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: R600ISelLowering.cpp:630
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::R600TargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: R600ISelLowering.cpp:264
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:20
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:132
llvm::R600TargetLowering::R600TargetLowering
R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI)
Definition: R600ISelLowering.cpp:28