LLVM 19.0.0git
PPCCTRLoopsVerify.cpp
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1//===-- PPCCTRLoops.cpp - Verify CTR loops -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass verifies that all bdnz/bdz instructions are dominated by a loop
10// mtctr before any other instructions that might clobber the ctr register.
11//
12//===----------------------------------------------------------------------===//
13
14// CTR loops are produced by the HardwareLoops pass and this pass is simply a
15// verification that no invalid CTR loops are produced. As such, it isn't
16// something that needs to be run (or even defined) for Release builds so the
17// entire file is guarded by NDEBUG.
18#ifndef NDEBUG
20#include "PPC.h"
21#include "llvm/ADT/SmallSet.h"
23#include "llvm/ADT/StringRef.h"
34#include "llvm/Pass.h"
35#include "llvm/PassRegistry.h"
37#include "llvm/Support/Debug.h"
42
43using namespace llvm;
44
45#define DEBUG_TYPE "ppc-ctrloops-verify"
46
47namespace {
48
49 struct PPCCTRLoopsVerify : public MachineFunctionPass {
50 public:
51 static char ID;
52
53 PPCCTRLoopsVerify() : MachineFunctionPass(ID) {
55 }
56
57 void getAnalysisUsage(AnalysisUsage &AU) const override {
60 }
61
62 bool runOnMachineFunction(MachineFunction &MF) override;
63
64 private:
66 };
67
68 char PPCCTRLoopsVerify::ID = 0;
69} // end anonymous namespace
70
71INITIALIZE_PASS_BEGIN(PPCCTRLoopsVerify, "ppc-ctr-loops-verify",
72 "PowerPC CTR Loops Verify", false, false)
74INITIALIZE_PASS_END(PPCCTRLoopsVerify, "ppc-ctr-loops-verify",
75 "PowerPC CTR Loops Verify", false, false)
76
78 return new PPCCTRLoopsVerify();
79}
80
81static bool clobbersCTR(const MachineInstr &MI) {
82 for (const MachineOperand &MO : MI.operands()) {
83 if (MO.isReg()) {
84 if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8))
85 return true;
86 } else if (MO.isRegMask()) {
87 if (MO.clobbersPhysReg(PPC::CTR) || MO.clobbersPhysReg(PPC::CTR8))
88 return true;
89 }
90 }
91
92 return false;
93}
94
100 bool CheckPreds;
101
102 if (I == MBB->begin()) {
103 Visited.insert(MBB);
104 goto queue_preds;
105 } else
106 --I;
107
108check_block:
109 Visited.insert(MBB);
110 if (I == MBB->end())
111 goto queue_preds;
112
113 CheckPreds = true;
114 for (MachineBasicBlock::iterator IE = MBB->begin();; --I) {
115 unsigned Opc = I->getOpcode();
116 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) {
117 CheckPreds = false;
118 break;
119 }
120
121 if (I != BI && clobbersCTR(*I)) {
123 << ") instruction " << *I
124 << " clobbers CTR, invalidating "
125 << printMBBReference(*BI->getParent()) << " ("
126 << BI->getParent()->getFullName() << ") instruction "
127 << *BI << "\n");
128 return false;
129 }
130
131 if (I == IE)
132 break;
133 }
134
135 if (!CheckPreds && Preds.empty())
136 return true;
137
138 if (CheckPreds) {
139queue_preds:
141 LLVM_DEBUG(dbgs() << "Unable to find a MTCTR instruction for "
142 << printMBBReference(*BI->getParent()) << " ("
143 << BI->getParent()->getFullName() << ") instruction "
144 << *BI << "\n");
145 return false;
146 }
147
148 append_range(Preds, MBB->predecessors());
149 }
150
151 do {
152 MBB = Preds.pop_back_val();
153 if (!Visited.count(MBB)) {
155 goto check_block;
156 }
157 } while (!Preds.empty());
158
159 return true;
160}
161
162bool PPCCTRLoopsVerify::runOnMachineFunction(MachineFunction &MF) {
163 MDT = &getAnalysis<MachineDominatorTree>();
164
165 // Verify that all bdnz/bdz instructions are dominated by a loop mtctr before
166 // any other instructions that might clobber the ctr register.
167 for (MachineBasicBlock &MBB : MF) {
168 if (!MDT->isReachableFromEntry(&MBB))
169 continue;
170
172 MIIE = MBB.end(); MII != MIIE; ++MII) {
173 unsigned Opc = MII->getOpcode();
174 if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ ||
175 Opc == PPC::BDZ8 || Opc == PPC::BDZ)
176 if (!verifyCTRBranch(&MBB, MII))
177 llvm_unreachable("Invalid PPC CTR loop!");
178 }
179 }
180
181 return false;
182}
183#endif // NDEBUG
MachineBasicBlock & MBB
#define LLVM_DEBUG(X)
Definition: Debug.h:101
Generic dominator tree construction - this file provides routines to construct immediate dominator in...
Hexagon Hardware Loops
IRTranslator LLVM IR MI
loops
Definition: LoopInfo.cpp:1177
#define I(x, y, z)
Definition: MD5.cpp:58
static bool verifyCTRBranch(MachineBasicBlock *MBB, MachineBasicBlock::iterator I)
ppc ctr loops PowerPC CTR Loops Verify
ppc ctr loops verify
static bool clobbersCTR(const MachineInstr &MI)
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
This file defines the SmallSet class.
This file defines the SmallVector class.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
std::string getFullName() const
Return a formatted string to identify this block and its parent function.
iterator_range< pred_iterator > predecessors()
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:166
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:179
bool empty() const
Definition: SmallVector.h:94
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
Definition: STLExtras.h:2082
void initializePPCCTRLoopsVerifyPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
FunctionPass * createPPCCTRLoopsVerify()
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.