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16 #ifndef LLVM_CODEGEN_RESOURCEPRIORITYQUEUE_H
17 #define LLVM_CODEGEN_RESOURCEPRIORITYQUEUE_H
23 class InstrItineraryData;
24 class ResourcePriorityQueue;
25 class SelectionDAGISel;
26 class TargetInstrInfo;
27 class TargetRegisterInfo;
39 std::vector<SUnit> *SUnits;
45 std::vector<unsigned> NumNodesSolelyBlocking;
48 std::vector<SUnit*> Queue;
52 std::vector<unsigned> RegPressure;
56 std::vector<unsigned> RegLimit;
66 std::unique_ptr<DFAPacketizer> ResourcesModel;
70 std::vector<SUnit*> Packet;
73 unsigned ParallelLiveRanges;
74 int HorizontalVerticalBalance;
81 void initNodes(std::vector<SUnit> &sunits)
override;
84 NumNodesSolelyBlocking.resize(SUnits->size(), 0);
94 assert(NodeNum < (*SUnits).size());
95 return (*SUnits)[NodeNum].getHeight();
99 assert(NodeNum < NumNodesSolelyBlocking.size());
100 return NumNodesSolelyBlocking[NodeNum];
113 bool empty()
const override {
return Queue.empty(); }
127 void adjustPriorityOfUnscheduledPreds(
SUnit *SU);
129 unsigned numberRCValPredInSU (
SUnit *SU,
unsigned RCId);
130 unsigned numberRCValSuccInSU (
SUnit *SU,
unsigned RCId);
This is an optimization pass for GlobalISel generic memory operations.
void initNumRegDefsLeft(SUnit *SU)
InitNumRegDefsLeft - Determine the # of regs defined by this node.
unsigned getLatency(unsigned NodeNum) const
int SUSchedulingCost(SUnit *SU)
Single cost function reflecting benefit of scheduling SU in the current cycle.
ResourcePriorityQueue * PQ
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SUnit * pop() override
Main access point - returns next instructions to be placed in scheduling sequence.
resource_sort(ResourcePriorityQueue *pq)
bool operator()(const SUnit *LHS, const SUnit *RHS) const
This heuristic is used if DFA scheduling is not desired for some VLIW platform.
TargetInstrInfo - Interface to description of machine instruction set.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isBottomUp() const override
bool empty() const override
int rawRegPressureDelta(SUnit *SU, unsigned RCId)
int regPressureDelta(SUnit *SU, bool RawPressure=false)
Estimates change in reg pressure from this SU.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isResourceAvailable(SUnit *SU)
Check if scheduling of this SU is possible in the current packet.
void addNode(const SUnit *SU) override
ResourcePriorityQueue(SelectionDAGISel *IS)
void push(SUnit *U) override
unsigned getNumSolelyBlockNodes(unsigned NodeNum) const
Sorting functions for the Available queue.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
void scheduledNode(SUnit *SU) override
scheduledNode - Main resource tracking point.
void remove(SUnit *SU) override
Scheduling unit. This is a node in the scheduling DAG.
void initNodes(std::vector< SUnit > &sunits) override
Initialize nodes.
This interface is used to plug different priorities computation algorithms into the list scheduler.
void releaseState() override
Itinerary data supplied by a subtarget to be used by a target.
void updateNode(const SUnit *SU) override
void reserveResources(SUnit *SU)
Keep track of available resources.