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14 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
15 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
24 class AssumptionCache;
25 class TargetInstrInfo;
27 class SelectionDAGBuilder;
29 class MachineRegisterInfo;
30 class MachineFunction;
31 class OptimizationRemarkEmitter;
33 class TargetLibraryInfo;
34 class FunctionLoweringInfo;
35 class SwiftErrorValueTracking;
37 class ScheduleDAGSDNodes;
45 std::unique_ptr<FunctionLoweringInfo>
FuncInfo;
50 std::unique_ptr<SelectionDAGBuilder>
SDB;
62 std::unique_ptr<OptimizationRemarkEmitter>
ORE;
93 unsigned ConstraintID,
94 std::vector<SDValue> &OutOps) {
108 bool IgnoreChains =
false);
216 for (
unsigned i = 0;
i < Num; ++
i)
256 int64_t DesiredMaskS)
const;
258 int64_t DesiredMaskS)
const;
315 void Select_INLINEASM(
SDNode *
N);
316 void Select_READ_REGISTER(
SDNode *
Op);
317 void Select_WRITE_REGISTER(
SDNode *
Op);
319 void CannotYetSelect(
SDNode *
N);
322 void Select_ARITH_FENCE(
SDNode *
N);
323 void Select_MEMBARRIER(
SDNode *
N);
327 void Select_STACKMAP(
SDNode *
N);
328 void Select_PATCHPOINT(
SDNode *
N);
331 void DoInstructionSelection();
338 bool PrepareEHLandingPad();
341 void SelectAllBasicBlocks(
const Function &Fn);
349 void FinishBasicBlock();
351 void CodeGenAndEmitDAG();
357 void ComputeLiveOutVRegInfo();
367 std::vector<unsigned> OpcodeOffset;
const TargetLowering * getTargetLowering() const
const TargetLowering * TLI
This is an optimization pass for GlobalISel generic memory operations.
virtual StringRef getIncludePathForIndex(unsigned index)
getIncludePathForIndex - get the td source location of pattern instantiation
bool isOrEquivalentToAdd(const SDNode *N) const
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
@ OPC_EmitMergeInputChains1_2
static void EnforceNodeIdInvariant(SDNode *N)
virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result)
virtual void PostprocessISelDAG()
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
unsigned DAGSize
DAGSize - Size of DAG being instruction selected.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual void emitFunctionEntryCode()
void SelectInlineAsmMemoryOperands(std::vector< SDValue > &Ops, const SDLoc &DL)
SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
@ OPC_CheckFoldableChainNode
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Garbage collection metadata for a single function.
Represents one node in the SelectionDAG.
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
virtual bool CheckPatternPredicate(unsigned PredNo) const
CheckPatternPredicate - This function is generated by tblgen in the target.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
virtual void PreprocessISelDAG()
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
@ OPC_EmitMergeInputChains1_0
SmallPtrSet< const Instruction *, 4 > ElidedArgCopyInstrs
TargetInstrInfo - Interface to description of machine instruction set.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo)
std::unique_ptr< SelectionDAGBuilder > SDB
@ OPC_CheckPatternPredicate
void ReplaceUses(SDNode *F, SDNode *T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
MachineRegisterInfo * RegInfo
SelectionDAGISel(char &ID, TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default)
CodeGenOpt::Level OptLevel
virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const
CheckNodePredicate - This function is generated by tblgen in the target.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool ComplexPatternFuncMutatesDAG() const
Return true if complex patterns for this target can mutate the DAG.
Represent the analysis usage information of a pass.
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
std::unique_ptr< OptimizationRemarkEmitter > ORE
Current optimization remark emitter.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
mir Rename Register Operands
static void InvalidateNodeId(SDNode *N)
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const
IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during ...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const TargetInstrInfo * TII
std::unique_ptr< FunctionLoweringInfo > FuncInfo
static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false)
IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction sel...
bool mayRaiseFPException(SDNode *Node) const
Return whether the node may raise an FP exception.
bool shouldOptForSize() const
virtual StringRef getPatternForIndex(unsigned index)
getPatternForIndex - Patterns selected by tablegen during ISEL
bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckOrMask - The isel is trying to match something like (or X, 255).
Primary interface to the complete machine description for the target machine.
~SelectionDAGISel() override
@ OPC_EmitMergeInputChains
static int getUninvalidatedNodeId(SDNode *N)
@ OPC_CheckPredicateWithOperands
virtual bool CheckNodePredicateWithOperands(SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const
CheckNodePredicateWithOperands - This function is generated by tblgen in the target.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
StringRef - Represent a constant reference to a string, i.e.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps)
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
A cache of @llvm.assume calls within a function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SwiftErrorValueTracking * SwiftError
void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num)
ReplaceUses - replace all uses of the old nodes F with the use of the new nodes T.
bool shouldOptForSize(const MachineFunction *MF) const
@ OPC_EmitMergeInputChains1_1
static int getNumFixedFromVariadicInfo(unsigned Flags)
getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values ...
void ReplaceUses(SDValue F, SDValue T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
Provides information about what library functions are available for the current target.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
@ OPC_EmitConvertToTarget
const TargetLibraryInfo * LibInfo
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
@ OPC_CheckChild2CondCode
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize)
Level
Code generation optimization level.
virtual void Select(SDNode *N)=0
Main hook for targets to transform nodes into machine nodes.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckAndMask - The isel is trying to match something like (and X, 255).
InstListType::const_iterator const_iterator