SILowerI1Copies.cpp File Reference

#include "SILowerI1Copies.h"
#include "AMDGPU.h"
#include "llvm/CodeGen/MachineIDFSSAUpdater.h"
#include "llvm/InitializePasses.h"

Go to the source code of this file.

Classes
class	llvm::AMDGPU::PhiIncomingAnalysis
	Helper class that determines the relationship between incoming values of a phi in the control flow graph to determine where an incoming value can simply be taken as a scalar lane mask as-is, and where it needs to be merged with another, previously defined lane mask. More...
class	llvm::AMDGPU::LoopFinder
	Helper class that detects loops which require us to lower an i1 COPY into bitwise manipulation. More...
class	SILowerI1CopiesLegacy

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::AMDGPU

Macros
#define	DEBUG_TYPE   "si-i1-copies"

Functions
static Register	insertUndefLaneMask (MachineBasicBlock *MBB, MachineRegisterInfo *MRI, MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs)
static bool	isVRegCompatibleReg (const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI, Register Reg)
static void	instrDefsUsesSCC (const MachineInstr &MI, bool &Def, bool &Use)
static bool	runFixI1Copies (MachineFunction &MF, MachineDominatorTree &MDT, MachinePostDominatorTree &MPDT)
	Lower all instructions that def or use vreg_1 registers.
	INITIALIZE_PASS_BEGIN (SILowerI1CopiesLegacy, DEBUG_TYPE, "SI Lower i1 Copies", false, false) INITIALIZE_PASS_END(SILowerI1CopiesLegacy

Variables
	DEBUG_TYPE
SI Lower i1	Copies
SI Lower i1	false

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "si-i1-copies"

Definition at line 29 of file SILowerI1Copies.cpp.

Function Documentation

INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN	(	SILowerI1CopiesLegacy	,
		DEBUG_TYPE	,
		"SI Lower i1 Copies"	,
		false	,
		false	)

References DEBUG_TYPE, and INITIALIZE_PASS_DEPENDENCY.

insertUndefLaneMask()

Register insertUndefLaneMask ( MachineBasicBlock * MBB, MachineRegisterInfo * MRI, MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs )

static

Definition at line 385 of file SILowerI1Copies.cpp.

References llvm::BuildMI(), llvm::AMDGPU::createLaneMaskReg(), llvm::MachineFunction::getSubtarget(), MBB, and TII.

Referenced by llvm::AMDGPU::PhiLoweringHelper::mergeIncomingLaneMasks().

instrDefsUsesSCC()

void instrDefsUsesSCC ( const MachineInstr & MI, bool & Def, bool & Use )

static

Definition at line 697 of file SILowerI1Copies.cpp.

References MI.

Referenced by llvm::AMDGPU::PhiLoweringHelper::getSaluInsertionAtEnd().

isVRegCompatibleReg()

bool isVRegCompatibleReg ( const SIRegisterInfo & TRI, const MachineRegisterInfo & MRI, Register Reg )

static

Definition at line 397 of file SILowerI1Copies.cpp.

References Reg, Size, and TRI.

runFixI1Copies()

bool runFixI1Copies ( MachineFunction & MF, MachineDominatorTree & MDT, MachinePostDominatorTree & MPDT )

static

Lower all instructions that def or use vreg_1 registers.

In a first pass, we lower COPYs from vreg_1 to vector registers, as can occur around inline assembly. We do this first, before vreg_1 registers are changed to scalar mask registers.

Then we lower all defs of vreg_1 registers. Phi nodes are lowered before all others, because phi lowering looks through copies and can therefore often make copy lowering unnecessary.

Definition at line 858 of file SILowerI1Copies.cpp.

References Changed, and llvm::MachineFunction::getProperties().

Referenced by llvm::SILowerI1CopiesPass::run(), and SILowerI1CopiesLegacy::runOnMachineFunction().

Variable Documentation

Copies

SI Lower i1 Copies

Definition at line 916 of file SILowerI1Copies.cpp.

Referenced by llvm::AArch64RegisterInfo::getRegAllocationHints(), propagateLocalCopies(), and llvm::TailDuplicator::tailDuplicateAndUpdate().

DEBUG_TYPE

DEBUG_TYPE

Definition at line 916 of file SILowerI1Copies.cpp.

false

SI Lower i1 false

Definition at line 917 of file SILowerI1Copies.cpp.