LLVM 20.0.0git
SILowerI1Copies.h
Go to the documentation of this file.
1//===-- SILowerI1Copies.h --------------------------------------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition of the PhiLoweringHelper class that implements lane
11/// mask merging algorithm for divergent i1 phis.
12//
13//===----------------------------------------------------------------------===//
14
15#include "GCNSubtarget.h"
19
20namespace llvm {
21
22/// Incoming for lane maks phi as machine instruction, incoming register \p Reg
23/// and incoming block \p Block are taken from machine instruction.
24/// \p UpdatedReg (if valid) is \p Reg lane mask merged with another lane mask.
25struct Incoming {
29
32};
33
34Register createLaneMaskReg(MachineRegisterInfo *MRI,
35 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs);
36
38public:
41 virtual ~PhiLoweringHelper() = default;
42
43protected:
44 bool IsWave32 = false;
45 MachineFunction *MF = nullptr;
49 const GCNSubtarget *ST = nullptr;
50 const SIInstrInfo *TII = nullptr;
52
53#ifndef NDEBUG
55#endif
56
58 unsigned MovOp;
59 unsigned AndOp;
60 unsigned OrOp;
61 unsigned XorOp;
62 unsigned AndN2Op;
63 unsigned OrN2Op;
64
65public:
66 bool lowerPhis();
67 bool isConstantLaneMask(Register Reg, bool &Val) const;
70
73 }
74
76 return TII->getRegisterInfo().isSGPRReg(*MRI, Reg) &&
77 TII->getRegisterInfo().getRegSizeInBits(Reg, *MRI) ==
79 }
80
81 // Helpers from lowerPhis that are different between sdag and global-isel.
82
83 virtual void markAsLaneMask(Register DstReg) const = 0;
85 SmallVectorImpl<MachineInstr *> &Vreg1Phis) const = 0;
86 virtual void
88 SmallVectorImpl<Incoming> &Incomings) const = 0;
89 virtual void replaceDstReg(Register NewReg, Register OldReg,
93 const DebugLoc &DL, Register DstReg,
94 Register PrevReg, Register CurReg) = 0;
95 virtual void constrainAsLaneMask(Incoming &In) = 0;
96};
97
98} // end namespace llvm
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
AMD GCN specific subclass of TargetSubtarget.
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned Reg
unsigned getWavefrontSize() const
A debug info location.
Definition: DebugLoc.h:33
Implements a dense probed hash-table based set.
Definition: DenseSet.h:271
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachinePostDominatorTree - an analysis pass wrapper for DominatorTree used to compute the post-domina...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
VRegAttrs getVRegAttrs(Register Reg)
Returns register class or bank and low level type of Reg.
bool isLaneMaskReg(Register Reg) const
virtual ~PhiLoweringHelper()=default
MachineRegisterInfo * MRI
MachineDominatorTree * DT
DenseSet< Register > PhiRegisters
virtual void getCandidatesForLowering(SmallVectorImpl< MachineInstr * > &Vreg1Phis) const =0
MachineFunction * MF
virtual void constrainAsLaneMask(Incoming &In)=0
virtual void collectIncomingValuesFromPhi(const MachineInstr *MI, SmallVectorImpl< Incoming > &Incomings) const =0
virtual void markAsLaneMask(Register DstReg) const =0
MachinePostDominatorTree * PDT
const GCNSubtarget * ST
const SIInstrInfo * TII
MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs
MachineBasicBlock::iterator getSaluInsertionAtEnd(MachineBasicBlock &MBB) const
Return a point at the end of the given MBB to insert SALU instructions for lane mask calculation.
void initializeLaneMaskRegisterAttributes(Register LaneMask)
bool isConstantLaneMask(Register Reg, bool &Val) const
virtual void buildMergeLaneMasks(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, Register PrevReg, Register CurReg)=0
virtual void replaceDstReg(Register NewReg, Register OldReg, MachineBasicBlock *MBB)=0
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:222
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Register createLaneMaskReg(MachineRegisterInfo *MRI, MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs)
Incoming for lane maks phi as machine instruction, incoming register Reg and incoming block Block are...
MachineBasicBlock * Block
Incoming(Register Reg, MachineBasicBlock *Block, Register UpdatedReg)
Register UpdatedReg
All attributes(register class or bank and low-level type) a virtual register can have.