SILowerI1Copies.h

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//===-- SILowerI1Copies.h --------------------------------------*- C++ -*--===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
/// \file
/// Interface definition of the PhiLoweringHelper class that implements lane
/// mask merging algorithm for divergent i1 phis.
//
//===----------------------------------------------------------------------===//
 
#include "AMDGPULaneMaskUtils.h"
#include "GCNSubtarget.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineSSAUpdater.h"
 
namespace llvm {
namespace AMDGPU {
/// Incoming for lane mask phi as machine instruction, incoming register \p Reg
/// and incoming block \p Block are taken from machine instruction.
/// \p UpdatedReg (if valid) is \p Reg lane mask merged with another lane mask.
struct Incoming {
  Register Reg;
  MachineBasicBlock *Block;
  Register UpdatedReg;
 
  Incoming(Register Reg, MachineBasicBlock *Block, Register UpdatedReg)
      : Reg(Reg), Block(Block), UpdatedReg(UpdatedReg) {}
};
 
Register createLaneMaskReg(MachineRegisterInfo *MRI,
                           MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs);
 
class PhiLoweringHelper {
public:
  PhiLoweringHelper(MachineFunction *MF, MachineDominatorTree *DT,
                    MachinePostDominatorTree *PDT);
  virtual ~PhiLoweringHelper() = default;
 
protected:
  bool IsWave32 = false;
  MachineFunction *MF = nullptr;
  MachineDominatorTree *DT = nullptr;
  MachinePostDominatorTree *PDT = nullptr;
  MachineRegisterInfo *MRI = nullptr;
  const GCNSubtarget *ST = nullptr;
  const SIInstrInfo *TII = nullptr;
  MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs;
  const AMDGPU::LaneMaskConstants *LMC = nullptr;
 
#ifndef NDEBUG
  DenseSet<Register> PhiRegisters;
#endif
 
public:
  bool lowerPhis();
  bool isConstantLaneMask(Register Reg, bool &Val) const;
  MachineBasicBlock::iterator
  getSaluInsertionAtEnd(MachineBasicBlock &MBB) const;
 
  void initializeLaneMaskRegisterAttributes(Register LaneMask) {
    LaneMaskRegAttrs = MRI->getVRegAttrs(LaneMask);
  }
 
  void
  initializeLaneMaskRegisterAttributes(MachineRegisterInfo::VRegAttrs Attrs) {
    LaneMaskRegAttrs = Attrs;
  }
 
  bool isLaneMaskReg(Register Reg) const {
    return TII->getRegisterInfo().isSGPRReg(*MRI, Reg) &&
           TII->getRegisterInfo().getRegSizeInBits(Reg, *MRI) ==
               ST->getWavefrontSize();
  }
 
  // Helpers from lowerPhis that are different between sdag and global-isel.
 
  virtual void markAsLaneMask(Register DstReg) const = 0;
  virtual void getCandidatesForLowering(
      SmallVectorImpl<MachineInstr *> &Vreg1Phis) const = 0;
  virtual void
  collectIncomingValuesFromPhi(const MachineInstr *MI,
                               SmallVectorImpl<Incoming> &Incomings) const = 0;
  virtual void replaceDstReg(Register NewReg, Register OldReg,
                             MachineBasicBlock *MBB) = 0;
  virtual void buildMergeLaneMasks(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I,
                                   const DebugLoc &DL, Register DstReg,
                                   Register PrevReg, Register CurReg) = 0;
  virtual void constrainAsLaneMask(Incoming &In) = 0;
};
} // namespace AMDGPU
} // end namespace llvm