LLVM 17.0.0git
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#include "Target/AMDGPU/SIRegisterInfo.h"
Classes | |
struct | SpilledReg |
Static Public Member Functions | |
static unsigned | getSubRegFromChannel (unsigned Channel, unsigned NumRegs=1) |
static LLVM_READONLY const TargetRegisterClass * | getSGPRClassForBitWidth (unsigned BitWidth) |
static bool | isSGPRClass (const TargetRegisterClass *RC) |
static bool | isVGPRClass (const TargetRegisterClass *RC) |
static bool | isAGPRClass (const TargetRegisterClass *RC) |
static bool | hasVGPRs (const TargetRegisterClass *RC) |
static bool | hasAGPRs (const TargetRegisterClass *RC) |
static bool | hasSGPRs (const TargetRegisterClass *RC) |
static bool | hasVectorRegisters (const TargetRegisterClass *RC) |
static unsigned | getNumCoveredRegs (LaneBitmask LM) |
Definition at line 30 of file SIRegisterInfo.h.
SIRegisterInfo::SIRegisterInfo | ( | const GCNSubtarget & | ST | ) |
Definition at line 319 of file SIRegisterInfo.cpp.
References assert(), llvm::call_once(), E, llvm::MCRegister::from(), Idx, llvm::Offset, llvm::BitVector::resize(), llvm::BitVector::set(), llvm::size(), Size, and SubRegFromChannelTableWidthMap.
void SIRegisterInfo::buildSpillLoadStore | ( | MachineBasicBlock & | MBB, |
MachineBasicBlock::iterator | MI, | ||
const DebugLoc & | DL, | ||
unsigned | LoadStoreOp, | ||
int | Index, | ||
Register | ValueReg, | ||
bool | ValueIsKill, | ||
MCRegister | ScratchOffsetReg, | ||
int64_t | InstrOffset, | ||
MachineMemOperand * | MMO, | ||
RegScavenger * | RS, | ||
LivePhysRegs * | LiveRegs = nullptr |
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) | const |
Definition at line 1290 of file SIRegisterInfo.cpp.
References llvm::Add, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::LivePhysRegs::available(), llvm::BuildMI(), llvm::commonAlignment(), llvm::LivePhysRegs::contains(), DL, llvm::MachineBasicBlock::end(), llvm::SIInstrFlags::FlatScratch, llvm::GCNSubtarget::getConstantBusLimit(), llvm::getDefRegState(), llvm::MachineMemOperand::getFlags(), llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), getFlatScratchSpillOpcode(), llvm::MachineFunction::getFrameInfo(), llvm::TargetRegisterClass::getID(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectOffset(), getOffenMUBUFLoad(), getOffenMUBUFStore(), llvm::MachineBasicBlock::getParent(), llvm::MachineMemOperand::getPointerInfo(), llvm::AMDGPU::getRegBitWidth(), getRegClassForReg(), llvm::MachineFunction::getRegInfo(), getSubRegFromChannel(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::MachinePointerInfo::getWithOffset(), llvm::GCNSubtarget::hasFlatScratchSTMode(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, isAGPRClass(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::RegScavenger::isRegUsed(), llvm::MachineRegisterInfo::isReserved(), llvm::RegState::Kill, MBB, MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::MachineInstr::ReloadReuse, llvm::report_fatal_error(), llvm::RegScavenger::scavengeRegister(), llvm::RegScavenger::scavengeRegisterBackwards(), llvm::MachineInstr::setAsmPrinterFlag(), llvm::RegScavenger::setRegUsed(), Size, spillVGPRtoAGPR(), SubReg, and TII.
Referenced by buildVGPRSpillLoadStore(), and eliminateFrameIndex().
void SIRegisterInfo::buildVGPRSpillLoadStore | ( | SGPRSpillBuilder & | SB, |
int | Index, | ||
int | Offset, | ||
bool | IsLoad, | ||
bool | IsKill = true |
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) | const |
Definition at line 1684 of file SIRegisterInfo.cpp.
References llvm::SIMachineFunctionInfo::addToSpilledVGPRs(), assert(), buildSpillLoadStore(), llvm::SGPRSpillBuilder::DL, llvm::SGPRSpillBuilder::EltSize, llvm::GCNSubtarget::enableFlatScratch(), getBaseRegister(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getStackID(), hasBasePointer(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MF, llvm::SGPRSpillBuilder::MFI, llvm::SGPRSpillBuilder::MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::Offset, llvm::SGPRSpillBuilder::RS, llvm::TargetStackID::SGPRSpill, and llvm::SGPRSpillBuilder::TmpVGPR.
Referenced by llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), and llvm::SGPRSpillBuilder::restore().
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Definition at line 2025 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledVGPRs(), assert(), llvm::BuildMI(), buildMUBUFOffsetLoadStore(), buildSpillLoadStore(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), DL, llvm::GCNSubtarget::enableFlatScratch(), llvm::SIInstrFlags::FlatScratch, getBaseRegister(), llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSVS(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::MachineInstrBuilder::getInstr(), llvm::GCNSubtarget::getInstrInfo(), llvm::AMDGPU::getNamedOperandIdx(), getNumSubRegsForSpillOp(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstrBuilder::getReg(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::AMDGPUSubtarget::getWavefrontSizeLog2(), hasBasePointer(), llvm::GCNSubtarget::hasFlatScratchSTMode(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::AMDGPU::hasNamedOperand(), I, llvm::AMDGPUMachineFunction::isEntryFunction(), llvm::AMDGPU::isInlinableLiteral32(), llvm::MachineOperand::isKill(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::RegScavenger::isRegUsed(), isSGPRClass(), llvm::Register::isValid(), llvm::RegState::Kill, MBB, MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::report_fatal_error(), restoreSGPR(), llvm::RegScavenger::scavengeRegister(), llvm::MachineOperand::setImm(), llvm::MachineOperand::setIsDead(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), spillSGPR(), and TII.
bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex | ( | MachineBasicBlock::iterator | MI, |
int | FI, | ||
RegScavenger * | RS, | ||
SlotIndexes * | Indexes = nullptr , |
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LiveIntervals * | LIS = nullptr |
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) | const |
Special case of eliminateFrameIndex.
Returns true if the SGPR was spilled to a VGPR and the stack slot can be safely eliminated when all other users are handled.
Definition at line 1986 of file SIRegisterInfo.cpp.
References llvm_unreachable, MI, restoreSGPR(), and spillSGPR().
MachineInstr * SIRegisterInfo::findReachingDef | ( | Register | Reg, |
unsigned | SubReg, | ||
MachineInstr & | Use, | ||
MachineRegisterInfo & | MRI, | ||
LiveIntervals * | LIS | ||
) | const |
Definition at line 3078 of file SIRegisterInfo.cpp.
References assert(), llvm::Pass::getAnalysis(), llvm::LiveIntervals::getInstructionFromIndex(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::LiveIntervals::getRegUnit(), llvm::LiveRange::getVNInfoAt(), llvm::LiveIntervals::hasInterval(), llvm::LiveInterval::hasSubRanges(), llvm::SlotIndex::isValid(), llvm::MCRegisterInfo::DiffListIterator::isValid(), MRI, llvm::LiveInterval::subranges(), and SubReg.
MCRegister SIRegisterInfo::findUnusedRegister | ( | const MachineRegisterInfo & | MRI, |
const TargetRegisterClass * | RC, | ||
const MachineFunction & | MF, | ||
bool | ReserveHighestVGPR = false |
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) | const |
Returns a lowest register that is not used at any point in the function.
If all registers are used, then this function will return AMDGPU::NoRegister. If ReserveHighestVGPR
= true, then return highest unused register.
Definition at line 2879 of file SIRegisterInfo.cpp.
References MRI, and llvm::reverse().
Definition at line 3132 of file SIRegisterInfo.cpp.
References assert().
Referenced by llvm::SIInstrInfo::copyPhysReg(), and llvm::SIInstrInfo::FoldImmediate().
const TargetRegisterClass * SIRegisterInfo::getAGPRClassForBitWidth | ( | unsigned | BitWidth | ) | const |
Definition at line 2670 of file SIRegisterInfo.cpp.
References llvm::BitWidth, getAlignedAGPRClassForBitWidth(), getAnyAGPRClassForBitWidth(), and llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by getEquivalentAGPRClass(), getRegClassForSizeOnBank(), and isProperlyAlignedRC().
Definition at line 515 of file SIRegisterInfo.cpp.
Definition at line 523 of file SIRegisterInfo.cpp.
ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR128 | ( | const MachineFunction & | MF | ) | const |
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
Definition at line 3184 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::getMaxNumSGPRs().
ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR32 | ( | const MachineFunction & | MF | ) | const |
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
Definition at line 3194 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::getMaxNumSGPRs().
ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR64 | ( | const MachineFunction & | MF | ) | const |
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
Definition at line 3189 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::getMaxNumSGPRs().
Definition at line 519 of file SIRegisterInfo.cpp.
Definition at line 511 of file SIRegisterInfo.cpp.
Register SIRegisterInfo::getBaseRegister | ( | ) | const |
Definition at line 509 of file SIRegisterInfo.cpp.
Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and getReservedRegs().
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Definition at line 333 of file SIRegisterInfo.h.
Referenced by llvm::SIInstrInfo::convertNonUniformIfRegion(), llvm::SIInstrInfo::convertNonUniformLoopRegion(), llvm::SIInstrInfo::getAddNoCarry(), llvm::GCNSubtarget::getBoolRC(), getRegClass(), llvm::SIInstrInfo::insertEQ(), llvm::SIInstrInfo::insertNE(), and llvm::SIInstrInfo::insertVectorSelect().
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Definition at line 388 of file SIRegisterInfo.cpp.
References llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::C, CC, llvm::CallingConv::Cold, llvm::CallingConv::Fast, llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), and llvm::GCNSubtarget::hasGFX90AInsts().
const MCPhysReg * SIRegisterInfo::getCalleeSavedRegsViaCopy | ( | const MachineFunction * | MF | ) | const |
Definition at line 409 of file SIRegisterInfo.cpp.
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Definition at line 413 of file SIRegisterInfo.cpp.
References llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::C, CC, llvm::CallingConv::Cold, llvm::CallingConv::Fast, and llvm::GCNSubtarget::hasGFX90AInsts().
Definition at line 376 of file SIRegisterInfo.h.
References SubReg.
Referenced by expandSGPRCopy(), and llvm::SIInstrInfo::verifyInstruction().
const TargetRegisterClass * SIRegisterInfo::getCompatibleSubRegClass | ( | const TargetRegisterClass * | SuperRC, |
const TargetRegisterClass * | SubRC, | ||
unsigned | SubIdx | ||
) | const |
Returns a register class which is compatible with SuperRC
, such that a subregister exists with class SubRC
with subregister index SubIdx
.
If this is impossible (e.g., an unaligned subregister index within a register tuple), return null.
Definition at line 2827 of file SIRegisterInfo.cpp.
References llvm::TargetRegisterClass::hasSubClassEq().
Referenced by llvm::SIInstrInfo::verifyInstruction().
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Definition at line 3036 of file SIRegisterInfo.cpp.
References llvm::PointerUnion< PTs >::dyn_cast(), llvm::MachineOperand::getReg(), getRegClassForTypeOnBank(), and MRI.
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Returns a legal register class to copy a register in the specified class to or from.
If it is possible to copy the register directly without using a cross register class copy, return the specified RC. Returns NULL if it is not possible to copy between two registers of the specified class.
Definition at line 915 of file SIRegisterInfo.cpp.
References getEquivalentVGPRClass(), getWaveMaskRegClass(), llvm::GCNSubtarget::hasGFX90AInsts(), and isAGPRClass().
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Definition at line 89 of file SIRegisterInfo.h.
const TargetRegisterClass * SIRegisterInfo::getEquivalentAGPRClass | ( | const TargetRegisterClass * | SRC | ) | const |
SRC
Definition at line 2809 of file SIRegisterInfo.cpp.
References assert(), getAGPRClassForBitWidth(), and Size.
Referenced by llvm::SIInstrInfo::legalizeOperands().
const TargetRegisterClass * SIRegisterInfo::getEquivalentSGPRClass | ( | const TargetRegisterClass * | VRC | ) | const |
SRC
Definition at line 2817 of file SIRegisterInfo.cpp.
References assert(), getSGPRClassForBitWidth(), and Size.
Referenced by llvm::SIInstrInfo::readlaneVGPRToSGPR().
const TargetRegisterClass * SIRegisterInfo::getEquivalentVGPRClass | ( | const TargetRegisterClass * | SRC | ) | const |
SRC
Definition at line 2801 of file SIRegisterInfo.cpp.
References assert(), getVGPRClassForBitWidth(), and Size.
Referenced by getCrossCopyRegClass(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::moveToVALUImpl(), and llvm::SIInstrInfo::readlaneVGPRToSGPR().
MCRegister SIRegisterInfo::getExec | ( | ) | const |
Definition at line 3052 of file SIRegisterInfo.cpp.
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Definition at line 762 of file SIRegisterInfo.cpp.
References assert(), llvm::AMDGPU::getNamedOperandIdx(), getScratchInstrOffset(), Idx, llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isMUBUF(), and MI.
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Definition at line 488 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::getFrameLowering(), llvm::MachineFunction::getInfo(), and llvm::SIFrameLowering::hasFP().
Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and llvm::SIFrameLowering::getFrameIndexReference().
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Definition at line 168 of file SIRegisterInfo.h.
References Reg.
Referenced by llvm::SIInstrInfo::copyPhysReg(), indirectCopyToAGPR(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 434 of file SIRegisterInfo.cpp.
References llvm::TargetRegisterInfo::getLargestLegalSuperClass(), llvm::GCNSubtarget::hasMAIInsts(), isAGPRClass(), and isVGPRClass().
Referenced by llvm::SIInstrInfo::isLegalRegOperand().
Definition at line 429 of file SIRegisterInfo.cpp.
Definition at line 381 of file SIRegisterInfo.h.
References getNumCoveredRegs(), and SubReg.
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Definition at line 365 of file SIRegisterInfo.h.
References llvm::LaneBitmask::getAsInteger(), and llvm::popcount().
Referenced by getNumChannelsFromSubReg(), getUsedRegMask(), and llvm::GCNRegPressure::inc().
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Definition at line 906 of file SIRegisterInfo.cpp.
const TargetRegisterClass * SIRegisterInfo::getProperlyAlignedRC | ( | const TargetRegisterClass * | RC | ) | const |
Definition at line 3165 of file SIRegisterInfo.cpp.
References getAlignedAGPRClassForBitWidth(), getAlignedVectorSuperClassForBitWidth(), getAlignedVGPRClassForBitWidth(), isAGPRClass(), isVectorSuperClass(), isVGPRClass(), llvm::GCNSubtarget::needsAlignedVGPRs(), and Size.
Referenced by adjustAllocatableRegClass().
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Definition at line 2525 of file SIRegisterInfo.cpp.
References llvm::AMDGPUInstPrinter::getRegisterName().
const TargetRegisterClass * SIRegisterInfo::getRegClass | ( | unsigned | RCID | ) | const |
Definition at line 3063 of file SIRegisterInfo.cpp.
References getBoolRC().
Referenced by adjustAllocatableRegClass(), llvm::SIInstrInfo::FoldImmediate(), llvm::SIInstrInfo::getOpSize(), llvm::SIInstrInfo::insertVectorSelect(), llvm::SIInstrInfo::isBufferSMRD(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::SIInstrInfo::isOperandLegal(), isSGPRClassID(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::moveToVALUImpl(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 423 of file SIRegisterInfo.h.
References llvm::RegTupleAlignUnitsMask, and llvm::TargetRegisterClass::TSFlags.
Referenced by isRegClassAligned().
const TargetRegisterClass * SIRegisterInfo::getRegClassForOperandReg | ( | const MachineRegisterInfo & | MRI, |
const MachineOperand & | MO | ||
) | const |
Definition at line 2927 of file SIRegisterInfo.cpp.
References llvm::MachineOperand::getReg(), getRegClassForReg(), llvm::MachineOperand::getSubReg(), and MRI.
const TargetRegisterClass * SIRegisterInfo::getRegClassForReg | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 2921 of file SIRegisterInfo.cpp.
References MRI.
Referenced by buildSpillLoadStore(), getRegClassForOperandReg(), isAGPR(), isVGPR(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::moveToVALUImpl(), and llvm::SIInstrInfo::verifyInstruction().
const TargetRegisterClass * SIRegisterInfo::getRegClassForSizeOnBank | ( | unsigned | Size, |
const RegisterBank & | Bank | ||
) | const |
Definition at line 3017 of file SIRegisterInfo.cpp.
References assert(), getAGPRClassForBitWidth(), llvm::RegisterBank::getID(), getSGPRClassForBitWidth(), getVGPRClassForBitWidth(), llvm_unreachable, and Size.
Referenced by getRegClassForTypeOnBank().
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Definition at line 325 of file SIRegisterInfo.h.
References getRegClassForSizeOnBank(), and llvm::LLT::getSizeInBits().
Referenced by getConstrainedRegClassForOperand().
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Definition at line 2969 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFunction(), llvm::TargetRegisterClass::getID(), llvm::MachineFunction::getInfo(), llvm::AMDGPUMachineFunction::getLDSSize(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::GCNSubtarget::getMaxNumVGPRs(), and llvm::AMDGPUSubtarget::getOccupancyWithLocalMemSize().
Referenced by getRegPressureSetLimit(), and indirectCopyToAGPR().
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Definition at line 2988 of file SIRegisterInfo.cpp.
References getRegPressureLimit(), Idx, and llvm_unreachable.
ArrayRef< int16_t > SIRegisterInfo::getRegSplitParts | ( | const TargetRegisterClass * | RC, |
unsigned | EltSize | ||
) | const |
Definition at line 2905 of file SIRegisterInfo.cpp.
References assert(), llvm::AMDGPU::getRegBitWidth(), and llvm::TargetRegisterClass::MC.
Referenced by llvm::SIInstrInfo::copyPhysReg(), expandSGPRCopy(), llvm::SIInstrInfo::materializeImmediate(), and llvm::SGPRSpillBuilder::SGPRSpillBuilder().
Definition at line 3002 of file SIRegisterInfo.cpp.
References llvm::Empty.
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Definition at line 543 of file SIRegisterInfo.cpp.
References assert(), llvm::SIMachineFunctionInfo::getAGPRSpillVGPRs(), getBaseRegister(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::GCNSubtarget::getMaxNumVGPRs(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getSGPRSpillVGPRs(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::SIMachineFunctionInfo::getVGPRForAGPRCopy(), llvm::SIMachineFunctionInfo::getVGPRSpillAGPRs(), llvm::SIMachineFunctionInfo::getWWMReservedRegs(), hasBasePointer(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasMAIInsts(), llvm::Reserved, and llvm::SIMachineFunctionInfo::usesAGPRs().
MCRegister SIRegisterInfo::getReturnAddressReg | ( | const MachineFunction & | MF | ) | const |
Definition at line 3011 of file SIRegisterInfo.cpp.
int64_t SIRegisterInfo::getScratchInstrOffset | ( | const MachineInstr * | MI | ) | const |
Definition at line 754 of file SIRegisterInfo.cpp.
References assert(), llvm::AMDGPU::getNamedOperandIdx(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isMUBUF(), and MI.
Referenced by getFrameIndexInstrOffset(), isFrameOffsetLegal(), and needsFrameBaseReg().
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Definition at line 2755 of file SIRegisterInfo.cpp.
References llvm::BitWidth.
Referenced by getEquivalentSGPRClass(), getRegClassForSizeOnBank(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), isIllegalRegisterType(), moreElementsToNextExistingRegClass(), and AMDGPUDAGToDAGISel::Select().
unsigned SIRegisterInfo::getSubRegAlignmentNumBits | ( | const TargetRegisterClass * | RC, |
unsigned | SubReg | ||
) | const |
Definition at line 3199 of file SIRegisterInfo.cpp.
References llvm::HasAGPR, llvm::HasSGPR, llvm::HasVGPR, llvm::RegKindMask, SubReg, and llvm::TargetRegisterClass::TSFlags.
Channel
(e.g. getSubRegFromChannel(0) -> AMDGPU::sub0) Definition at line 527 of file SIRegisterInfo.cpp.
References assert(), llvm::size(), and SubRegFromChannelTableWidthMap.
Referenced by llvm::SITargetLowering::AddIMGInit(), buildSpillLoadStore(), computeIndirectRegAndOffset(), expandSGPRCopy(), llvm::SIInstrInfo::readlaneVGPRToSGPR(), and AMDGPUDAGToDAGISel::SelectBuildVector().
MCRegister SIRegisterInfo::getVCC | ( | ) | const |
Definition at line 3048 of file SIRegisterInfo.cpp.
Referenced by llvm::SIInstrInfo::getAddNoCarry(), and llvm::SIInstrInfo::moveToVALUImpl().
const TargetRegisterClass * SIRegisterInfo::getVectorSuperClassForBitWidth | ( | unsigned | BitWidth | ) | const |
Definition at line 2744 of file SIRegisterInfo.cpp.
References llvm::BitWidth, getAlignedVectorSuperClassForBitWidth(), getAnyVectorSuperClassForBitWidth(), and llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by isProperlyAlignedRC().
const TargetRegisterClass * SIRegisterInfo::getVGPR64Class | ( | ) | const |
Definition at line 3056 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by llvm::SIInstrInfo::copyPhysReg(), and llvm::SIInstrInfo::legalizeOpWithMove().
const TargetRegisterClass * SIRegisterInfo::getVGPRClassForBitWidth | ( | unsigned | BitWidth | ) | const |
Definition at line 2594 of file SIRegisterInfo.cpp.
References llvm::BitWidth, getAlignedVGPRClassForBitWidth(), getAnyVGPRClassForBitWidth(), and llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by getEquivalentVGPRClass(), getRegClassForSizeOnBank(), and isProperlyAlignedRC().
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Definition at line 338 of file SIRegisterInfo.h.
Referenced by llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), getCrossCopyRegClass(), and llvm::SIInstrInfo::moveToVALUImpl().
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Definition at line 223 of file SIRegisterInfo.h.
References llvm::HasAGPR, and llvm::TargetRegisterClass::TSFlags.
Referenced by hasVectorRegisters(), isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), isVSSuperClass(), llvm::SIInstrInfo::legalizeOperandsVOP3(), and llvm::SIInstrInfo::readlaneVGPRToSGPR().
bool SIRegisterInfo::hasBasePointer | ( | const MachineFunction & | MF | ) | const |
Definition at line 502 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), llvm::MachineFrameInfo::getNumFixedObjects(), and shouldRealignStack().
Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and getReservedRegs().
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Definition at line 228 of file SIRegisterInfo.h.
References llvm::HasSGPR, and llvm::TargetRegisterClass::TSFlags.
Referenced by isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), and isVSSuperClass().
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Definition at line 233 of file SIRegisterInfo.h.
References hasAGPRs(), and hasVGPRs().
Referenced by llvm::SIInstrInfo::legalizeOperands(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 218 of file SIRegisterInfo.h.
References llvm::HasVGPR, and llvm::TargetRegisterClass::TSFlags.
Referenced by llvm::SIInstrInfo::canInsertSelect(), llvm::SIInstrInfo::copyPhysReg(), llvm::SIInstrInfo::expandPostRAPseudo(), hasVectorRegisters(), isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), isVSSuperClass(), llvm::SIInstrInfo::legalizeOperands(), and llvm::SIInstrInfo::verifyInstruction().
bool SIRegisterInfo::isAGPR | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 2940 of file SIRegisterInfo.cpp.
References getRegClassForReg(), isAGPRClass(), and MRI.
Referenced by llvm::SIInstrInfo::enforceOperandRCAlignment(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::FoldImmediate(), llvm::SIInstrInfo::getVALUOp(), llvm::SIInstrInfo::isOperandLegal(), isVectorRegister(), llvm::SIInstrInfo::legalizeOperandsVOP2(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 203 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
Referenced by buildSpillLoadStore(), llvm::SIInstrInfo::copyPhysReg(), getCrossCopyRegClass(), getLargestLegalSuperClass(), llvm::SIInstrInfo::getMovOpcode(), getProperlyAlignedRC(), llvm::AMDGPURegisterBankInfo::getRegBankFromRegClass(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), isAGPR(), isProperlyAlignedRC(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::storeRegToStackSlot(), and llvm::SIMachineFunctionInfo::usesAGPRs().
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Definition at line 704 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getRegInfo(), and llvm::MachineRegisterInfo::isReserved().
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Definition at line 293 of file SIRegisterInfo.h.
References isSGPRClass().
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Definition at line 890 of file SIRegisterInfo.cpp.
References llvm::SIInstrFlags::FlatScratch, llvm::GCNSubtarget::getInstrInfo(), getScratchInstrOffset(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::SIInstrInfo::isMUBUF(), MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, and TII.
bool SIRegisterInfo::isProperlyAlignedRC | ( | const TargetRegisterClass & | RC | ) | const |
Definition at line 3149 of file SIRegisterInfo.cpp.
References getAGPRClassForBitWidth(), getVectorSuperClassForBitWidth(), getVGPRClassForBitWidth(), llvm::TargetRegisterClass::hasSuperClassEq(), isAGPRClass(), isVectorSuperClass(), isVGPRClass(), and llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by llvm::SIInstrInfo::copyPhysReg(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 428 of file SIRegisterInfo.h.
References assert(), and getRegClassAlignmentNumBits().
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Definition at line 186 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
Referenced by llvm::SIInstrInfo::canInsertSelect(), llvm::SIInstrInfo::copyPhysReg(), eliminateFrameIndex(), llvm::SIInstrInfo::FoldImmediate(), llvm::SIInstrInfo::getInstructionUniformity(), llvm::SIInstrInfo::getMovOpcode(), llvm::AMDGPURegisterBankInfo::getRegBankFromRegClass(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), isDivergentRegClass(), isSGPRClassID(), isSGPRReg(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsFLAT(), llvm::SIInstrInfo::legalizeOperandsSMRD(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::materializeImmediate(), llvm::SITargetLowering::requiresUniformRegister(), llvm::SIInstrInfo::storeRegToStackSlot(), and llvm::SIInstrInfo::usesConstantBus().
Definition at line 191 of file SIRegisterInfo.h.
References getRegClass(), and isSGPRClass().
bool SIRegisterInfo::isSGPRReg | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 2790 of file SIRegisterInfo.cpp.
References isSGPRClass(), and MRI.
Referenced by llvm::SIInstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::isOperandLegal(), llvm::SIInstrInfo::isVGPRCopy(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::mayReadEXEC(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 2895 of file SIRegisterInfo.cpp.
References llvm::RegisterBankInfo::getRegBank(), llvm::RegisterBankInfo::isDivergentRegBank(), and MRI.
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Definition at line 208 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
Referenced by getProperlyAlignedRC(), isProperlyAlignedRC(), llvm::SIInstrInfo::loadRegFromStackSlot(), and llvm::SIInstrInfo::storeRegToStackSlot().
bool SIRegisterInfo::isVGPR | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 2933 of file SIRegisterInfo.cpp.
References getRegClassForReg(), isVGPRClass(), and MRI.
Referenced by llvm::SIInstrInfo::canShrink(), llvm::SIInstrInfo::FoldImmediate(), isVectorRegister(), and llvm::SIInstrInfo::legalizeOperandsVOP2().
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Definition at line 198 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
Referenced by getLargestLegalSuperClass(), getProperlyAlignedRC(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), isProperlyAlignedRC(), and isVGPR().
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Definition at line 213 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
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Definition at line 790 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::GCNSubtarget::enableFlatScratch(), llvm::MachineBasicBlock::end(), llvm::GCNSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::RegState::Kill, MBB, MRI, llvm::Offset, and TII.
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Definition at line 776 of file SIRegisterInfo.cpp.
References llvm::SIInstrFlags::FlatScratch, llvm::GCNSubtarget::getInstrInfo(), getScratchInstrOffset(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::SIInstrInfo::isMUBUF(), MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, and TII.
Definition at line 2836 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::hasMFMAInlineLiteralBug(), llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST, llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST, llvm::AMDGPU::OPERAND_SRC_FIRST, and llvm::AMDGPU::OPERAND_SRC_LAST.
Referenced by llvm::SIInstrInfo::isImmOperandLegal().
Definition at line 2869 of file SIRegisterInfo.cpp.
References llvm::AMDGPU::OPERAND_REG_IMM_FIRST, and llvm::AMDGPU::OPERAND_REG_IMM_LAST.
Referenced by llvm::SIInstrInfo::isImmOperandLegal().
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Definition at line 742 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), and llvm::MachineFrameInfo::hasStackObjects().
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Definition at line 733 of file SIRegisterInfo.cpp.
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Definition at line 722 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFrameInfo::hasCalls(), llvm::MachineFrameInfo::hasStackObjects(), and Info.
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Definition at line 748 of file SIRegisterInfo.cpp.
MCRegister SIRegisterInfo::reservedPrivateSegmentBufferReg | ( | const MachineFunction & | MF | ) | const |
Return the end register initially reserved for the scratch buffer in case spilling is needed.
Definition at line 536 of file SIRegisterInfo.cpp.
References llvm::alignDown(), and llvm::GCNSubtarget::getMaxNumSGPRs().
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Definition at line 841 of file SIRegisterInfo.cpp.
References assert(), llvm::MachineOperand::ChangeToRegister(), llvm::SIInstrFlags::FlatScratch, llvm::MachineOperand::getImm(), llvm::GCNSubtarget::getInstrInfo(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm_unreachable, MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::MachineOperand::setImm(), and TII.
bool SIRegisterInfo::restoreSGPR | ( | MachineBasicBlock::iterator | MI, |
int | FI, | ||
RegScavenger * | RS, | ||
SlotIndexes * | Indexes = nullptr , |
||
LiveIntervals * | LIS = nullptr , |
||
bool | OnlyToVGPR = false |
||
) | const |
Definition at line 1837 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::ArrayRef< T >::empty(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), llvm::SIMachineFunctionInfo::getSGPRSpillToVGPRLanes(), llvm::RegState::ImplicitDefine, llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::SIRegisterInfo::SpilledReg::Lane, llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MFI, MI, llvm::SGPRSpillBuilder::NumSubRegs, llvm::Offset, llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), llvm::LiveIntervals::removeAllRegUnitsForPhysReg(), llvm::SlotIndexes::replaceMachineInstrInMaps(), llvm::SGPRSpillBuilder::restore(), llvm::SGPRSpillBuilder::SplitParts, SubReg, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, llvm::SGPRSpillBuilder::TmpVGPR, and llvm::SIRegisterInfo::SpilledReg::VGPR.
Referenced by eliminateFrameIndex(), and eliminateSGPRToVGPRSpillFrameIndex().
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Definition at line 2948 of file SIRegisterInfo.cpp.
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Definition at line 709 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getInfo(), Info, and llvm::TargetRegisterInfo::shouldRealignStack().
Referenced by hasBasePointer().
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Definition at line 2845 of file SIRegisterInfo.cpp.
bool SIRegisterInfo::spillEmergencySGPR | ( | MachineBasicBlock::iterator | MI, |
MachineBasicBlock & | RestoreMBB, | ||
Register | SGPR, | ||
RegScavenger * | RS | ||
) | const |
Definition at line 1914 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledSGPRs(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::MachineBasicBlock::end(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::SGPRSpillBuilder::IsKill, llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MFI, MI, llvm::SGPRSpillBuilder::NumSubRegs, llvm::Offset, llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::restore(), llvm::SGPRSpillBuilder::setMI(), llvm::SGPRSpillBuilder::SplitParts, SubReg, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, llvm::SGPRSpillBuilder::TmpVGPR, and llvm::RegState::Undef.
bool SIRegisterInfo::spillSGPR | ( | MachineBasicBlock::iterator | MI, |
int | FI, | ||
RegScavenger * | RS, | ||
SlotIndexes * | Indexes = nullptr , |
||
LiveIntervals * | LIS = nullptr , |
||
bool | OnlyToVGPR = false |
||
) | const |
If OnlyToVGPR
is true, this will only succeed if this.
Definition at line 1717 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledSGPRs(), assert(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::ArrayRef< T >::empty(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), llvm::SIMachineFunctionInfo::getSGPRSpillToVGPRLanes(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::SGPRSpillBuilder::IsKill, llvm::SIRegisterInfo::SpilledReg::Lane, llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MFI, MI, llvm::SGPRSpillBuilder::NumSubRegs, llvm::Offset, llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), llvm::LiveIntervals::removeAllRegUnitsForPhysReg(), llvm::SlotIndexes::replaceMachineInstrInMaps(), llvm::SGPRSpillBuilder::restore(), llvm::ArrayRef< T >::size(), llvm::SGPRSpillBuilder::SplitParts, SubReg, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, llvm::SGPRSpillBuilder::TmpVGPR, llvm::RegState::Undef, and llvm::SIRegisterInfo::SpilledReg::VGPR.
Referenced by eliminateFrameIndex(), and eliminateSGPRToVGPRSpillFrameIndex().
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Definition at line 69 of file SIRegisterInfo.h.
Referenced by llvm::SIInstrInfo::loadRegFromStackSlot(), and llvm::SIInstrInfo::storeRegToStackSlot().
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Definition at line 152 of file SIRegisterInfo.h.