LLVM  13.0.0git
Public Member Functions | Static Public Member Functions | List of all members
llvm::SIRegisterInfo Class Referencefinal

#include "Target/AMDGPU/SIRegisterInfo.h"

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Public Member Functions

 SIRegisterInfo (const GCNSubtarget &ST)
 
bool spillSGPRToVGPR () const
 
MCRegister reservedPrivateSegmentBufferReg (const MachineFunction &MF) const
 Return the end register initially reserved for the scratch buffer in case spilling is needed. More...
 
BitVector getReservedRegs (const MachineFunction &MF) const override
 
const MCPhysReggetCalleeSavedRegs (const MachineFunction *MF) const override
 
const MCPhysReggetCalleeSavedRegsViaCopy (const MachineFunction *MF) const
 
const uint32_tgetCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const override
 
const uint32_tgetNoPreservedMask () const override
 
unsigned getCSRFirstUseCost () const override
 
Register getFrameRegister (const MachineFunction &MF) const override
 
bool hasBasePointer (const MachineFunction &MF) const
 
Register getBaseRegister () const
 
bool shouldRealignStack (const MachineFunction &MF) const override
 
bool requiresRegisterScavenging (const MachineFunction &Fn) const override
 
bool requiresFrameIndexScavenging (const MachineFunction &MF) const override
 
bool requiresFrameIndexReplacementScavenging (const MachineFunction &MF) const override
 
bool requiresVirtualBaseRegisters (const MachineFunction &Fn) const override
 
int64_t getScratchInstrOffset (const MachineInstr *MI) const
 
int64_t getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const override
 
bool needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const override
 
Register materializeFrameBaseRegister (MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
 
void resolveFrameIndex (MachineInstr &MI, Register BaseReg, int64_t Offset) const override
 
bool isFrameOffsetLegal (const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
 
const TargetRegisterClassgetPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const override
 
void buildVGPRSpillLoadStore (SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
 
void buildSGPRSpillLoadStore (SGPRSpillBuilder &SB, int Offset, int64_t VGPRLanes) const
 
bool spillSGPR (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
 If OnlyToVGPR is true, this will only succeed if this. More...
 
bool restoreSGPR (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
 
void eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
 
bool eliminateSGPRToVGPRSpillFrameIndex (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const
 Special case of eliminateFrameIndex. More...
 
StringRef getRegAsmName (MCRegister Reg) const override
 
unsigned getHWRegIndex (MCRegister Reg) const
 
const LLVM_READONLY TargetRegisterClassgetVGPRClassForBitWidth (unsigned BitWidth) const
 
const LLVM_READONLY TargetRegisterClassgetAGPRClassForBitWidth (unsigned BitWidth) const
 
const TargetRegisterClassgetPhysRegClass (MCRegister Reg) const
 Return the 'base' register class for this register. More...
 
bool isSGPRClass (const TargetRegisterClass *RC) const
 
bool isSGPRClassID (unsigned RCID) const
 
bool isSGPRReg (const MachineRegisterInfo &MRI, Register Reg) const
 
bool isAGPRClass (const TargetRegisterClass *RC) const
 
bool hasVGPRs (const TargetRegisterClass *RC) const
 
bool hasAGPRs (const TargetRegisterClass *RC) const
 
bool hasVectorRegisters (const TargetRegisterClass *RC) const
 
const TargetRegisterClassgetEquivalentVGPRClass (const TargetRegisterClass *SRC) const
 
const TargetRegisterClassgetEquivalentAGPRClass (const TargetRegisterClass *SRC) const
 
const TargetRegisterClassgetEquivalentSGPRClass (const TargetRegisterClass *VRC) const
 
const TargetRegisterClassgetSubRegClass (const TargetRegisterClass *RC, unsigned SubIdx) const
 
const TargetRegisterClassgetCompatibleSubRegClass (const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
 Returns a register class which is compatible with SuperRC, such that a subregister exists with class SubRC with subregister index SubIdx. More...
 
bool shouldRewriteCopySrc (const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
 
bool opCanUseLiteralConstant (unsigned OpType) const
 
bool opCanUseInlineConstant (unsigned OpType) const
 
MCRegister findUnusedRegister (const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
 Returns a lowest register that is not used at any point in the function. More...
 
const TargetRegisterClassgetRegClassForReg (const MachineRegisterInfo &MRI, Register Reg) const
 
bool isVGPR (const MachineRegisterInfo &MRI, Register Reg) const
 
bool isAGPR (const MachineRegisterInfo &MRI, Register Reg) const
 
bool isVectorRegister (const MachineRegisterInfo &MRI, Register Reg) const
 
bool isConstantPhysReg (MCRegister PhysReg) const override
 
bool isDivergentRegClass (const TargetRegisterClass *RC) const override
 
ArrayRef< int16_t > getRegSplitParts (const TargetRegisterClass *RC, unsigned EltSize) const
 
bool shouldCoalesce (MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
 
unsigned getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const override
 
unsigned getRegPressureSetLimit (const MachineFunction &MF, unsigned Idx) const override
 
const intgetRegUnitPressureSets (unsigned RegUnit) const override
 
MCRegister getReturnAddressReg (const MachineFunction &MF) const
 
const TargetRegisterClassgetRegClassForSizeOnBank (unsigned Size, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
 
const TargetRegisterClassgetRegClassForTypeOnBank (LLT Ty, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
 
const TargetRegisterClassgetConstrainedRegClassForOperand (const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
 
const TargetRegisterClassgetBoolRC () const
 
const TargetRegisterClassgetWaveMaskRegClass () const
 
const TargetRegisterClassgetVGPR64Class () const
 
MCRegister getVCC () const
 
const TargetRegisterClassgetRegClass (unsigned RCID) const
 
MachineInstrfindReachingDef (Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
 
const uint32_tgetAllVGPRRegMask () const
 
const uint32_tgetAllAGPRRegMask () const
 
const uint32_tgetAllVectorRegMask () const
 
const uint32_tgetAllAllocatableSRegMask () const
 
unsigned getChannelFromSubReg (unsigned SubReg) const
 
unsigned getNumChannelsFromSubReg (unsigned SubReg) const
 
MCPhysReg get32BitRegister (MCPhysReg Reg) const
 
bool isProperlyAlignedRC (const TargetRegisterClass &RC) const
 
ArrayRef< MCPhysReggetAllSGPR128 (const MachineFunction &MF) const
 Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget. More...
 
ArrayRef< MCPhysReggetAllSGPR64 (const MachineFunction &MF) const
 Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget. More...
 
ArrayRef< MCPhysReggetAllSGPR32 (const MachineFunction &MF) const
 Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget. More...
 
void buildSpillLoadStore (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LivePhysRegs *LiveRegs=nullptr) const
 

Static Public Member Functions

static unsigned getSubRegFromChannel (unsigned Channel, unsigned NumRegs=1)
 
static const LLVM_READONLY TargetRegisterClassgetSGPRClassForBitWidth (unsigned BitWidth)
 
static unsigned getNumCoveredRegs (LaneBitmask LM)
 

Detailed Description

Definition at line 29 of file SIRegisterInfo.h.

Constructor & Destructor Documentation

◆ SIRegisterInfo()

SIRegisterInfo::SIRegisterInfo ( const GCNSubtarget ST)

Member Function Documentation

◆ buildSGPRSpillLoadStore()

void llvm::SIRegisterInfo::buildSGPRSpillLoadStore ( SGPRSpillBuilder SB,
int  Offset,
int64_t  VGPRLanes 
) const

◆ buildSpillLoadStore()

void SIRegisterInfo::buildSpillLoadStore ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  LoadStoreOp,
int  Index,
Register  ValueReg,
bool  ValueIsKill,
MCRegister  ScratchOffsetReg,
int64_t  InstrOffset,
MachineMemOperand MMO,
RegScavenger RS,
LivePhysRegs LiveRegs = nullptr 
) const

Definition at line 1021 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::LivePhysRegs::available(), llvm::BuildMI(), llvm::commonAlignment(), DL, llvm::numbers::e, llvm::MachineBasicBlock::end(), llvm::SIInstrFlags::FlatScratch, llvm::getDefRegState(), llvm::MachineMemOperand::getFlags(), llvm::AMDGPU::getFlatScratchInstSTfromSS(), getFlatScratchSpillOpcode(), llvm::MachineFunction::getFrameInfo(), llvm::TargetRegisterClass::getID(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineBasicBlock::getParent(), llvm::MachineMemOperand::getPointerInfo(), llvm::AMDGPU::getRegBitWidth(), getRegClassForReg(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getSubRegFromChannel(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::MachinePointerInfo::getWithOffset(), hasAGPRs(), llvm::GCNSubtarget::hasFlatScratchSTMode(), llvm::GCNSubtarget::hasGFX90AInsts(), i, llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, Index, llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::RegState::Kill, MBB, MI, llvm::min(), Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, Reg, llvm::MachineInstr::ReloadReuse, llvm::report_fatal_error(), llvm::RegScavenger::scavengeRegister(), llvm::MachineInstr::setAsmPrinterFlag(), llvm::RegScavenger::setRegUsed(), llvm::Check::Size, spillVGPRtoAGPR(), SubReg, and TII.

Referenced by buildVGPRSpillLoadStore(), and eliminateFrameIndex().

◆ buildVGPRSpillLoadStore()

void SIRegisterInfo::buildVGPRSpillLoadStore ( SGPRSpillBuilder SB,
int  Index,
int  Offset,
bool  IsLoad,
bool  IsKill = true 
) const

◆ eliminateFrameIndex()

void SIRegisterInfo::eliminateFrameIndex ( MachineBasicBlock::iterator  MI,
int  SPAdj,
unsigned  FIOperandNum,
RegScavenger RS 
) const
override

◆ eliminateSGPRToVGPRSpillFrameIndex()

bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex ( MachineBasicBlock::iterator  MI,
int  FI,
RegScavenger RS 
) const

Special case of eliminateFrameIndex.

Returns true if the SGPR was spilled to a VGPR and the stack slot can be safely eliminated when all other users are handled.

Definition at line 1468 of file SIRegisterInfo.cpp.

References llvm_unreachable, MI, restoreSGPR(), and spillSGPR().

◆ findReachingDef()

MachineInstr * SIRegisterInfo::findReachingDef ( Register  Reg,
unsigned  SubReg,
MachineInstr Use,
MachineRegisterInfo MRI,
LiveIntervals LIS 
) const

◆ findUnusedRegister()

MCRegister SIRegisterInfo::findUnusedRegister ( const MachineRegisterInfo MRI,
const TargetRegisterClass RC,
const MachineFunction MF,
bool  ReserveHighestVGPR = false 
) const

Returns a lowest register that is not used at any point in the function.

If all registers are used, then this function will return AMDGPU::NoRegister. If ReserveHighestVGPR = true, then return highest unused register.

Definition at line 2205 of file SIRegisterInfo.cpp.

References llvm::MachineRegisterInfo::isAllocatable(), llvm::MachineRegisterInfo::isPhysRegUsed(), MRI, Reg, and llvm::reverse().

◆ get32BitRegister()

MCPhysReg SIRegisterInfo::get32BitRegister ( MCPhysReg  Reg) const

◆ getAGPRClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getAGPRClassForBitWidth ( unsigned  BitWidth) const

◆ getAllAGPRRegMask()

const uint32_t * SIRegisterInfo::getAllAGPRRegMask ( ) const

Definition at line 415 of file SIRegisterInfo.cpp.

◆ getAllAllocatableSRegMask()

const uint32_t * SIRegisterInfo::getAllAllocatableSRegMask ( ) const

Definition at line 423 of file SIRegisterInfo.cpp.

◆ getAllSGPR128()

ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR128 ( const MachineFunction MF) const

Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.

Definition at line 2479 of file SIRegisterInfo.cpp.

References llvm::sys::path::begin(), llvm::GCNSubtarget::getMaxNumSGPRs(), and llvm::makeArrayRef().

◆ getAllSGPR32()

ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR32 ( const MachineFunction MF) const

Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.

Definition at line 2491 of file SIRegisterInfo.cpp.

References llvm::sys::path::begin(), llvm::GCNSubtarget::getMaxNumSGPRs(), and llvm::makeArrayRef().

◆ getAllSGPR64()

ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR64 ( const MachineFunction MF) const

Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.

Definition at line 2485 of file SIRegisterInfo.cpp.

References llvm::sys::path::begin(), llvm::GCNSubtarget::getMaxNumSGPRs(), and llvm::makeArrayRef().

◆ getAllVectorRegMask()

const uint32_t * SIRegisterInfo::getAllVectorRegMask ( ) const

Definition at line 419 of file SIRegisterInfo.cpp.

◆ getAllVGPRRegMask()

const uint32_t * SIRegisterInfo::getAllVGPRRegMask ( ) const

Definition at line 411 of file SIRegisterInfo.cpp.

◆ getBaseRegister()

Register SIRegisterInfo::getBaseRegister ( ) const

◆ getBoolRC()

const TargetRegisterClass* llvm::SIRegisterInfo::getBoolRC ( ) const
inline

◆ getCalleeSavedRegs()

const MCPhysReg * SIRegisterInfo::getCalleeSavedRegs ( const MachineFunction MF) const
override

◆ getCalleeSavedRegsViaCopy()

const MCPhysReg * SIRegisterInfo::getCalleeSavedRegsViaCopy ( const MachineFunction MF) const

Definition at line 364 of file SIRegisterInfo.cpp.

◆ getCallPreservedMask()

const uint32_t * SIRegisterInfo::getCallPreservedMask ( const MachineFunction MF,
CallingConv::ID  CC 
) const
override

◆ getChannelFromSubReg()

unsigned llvm::SIRegisterInfo::getChannelFromSubReg ( unsigned  SubReg) const
inline

Definition at line 319 of file SIRegisterInfo.h.

References SubReg.

Referenced by expandSGPRCopy().

◆ getCompatibleSubRegClass()

const TargetRegisterClass * SIRegisterInfo::getCompatibleSubRegClass ( const TargetRegisterClass SuperRC,
const TargetRegisterClass SubRC,
unsigned  SubIdx 
) const

Returns a register class which is compatible with SuperRC, such that a subregister exists with class SubRC with subregister index SubIdx.

If this is impossible (e.g., an unaligned subregister index within a register tuple), return null.

Definition at line 2153 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterClass::hasSubClassEq().

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ getConstrainedRegClassForOperand()

const TargetRegisterClass * SIRegisterInfo::getConstrainedRegClassForOperand ( const MachineOperand MO,
const MachineRegisterInfo MRI 
) const
override

◆ getCSRFirstUseCost()

unsigned llvm::SIRegisterInfo::getCSRFirstUseCost ( ) const
inlineoverride

Definition at line 75 of file SIRegisterInfo.h.

◆ getEquivalentAGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentAGPRClass ( const TargetRegisterClass SRC) const
Returns
An AGPR reg class with the same width as SRC

Definition at line 2114 of file SIRegisterInfo.cpp.

References assert(), getAGPRClassForBitWidth(), and llvm::Check::Size.

Referenced by llvm::SIInstrInfo::legalizeOperands().

◆ getEquivalentSGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentSGPRClass ( const TargetRegisterClass VRC) const
Returns
A SGPR reg class with the same width as SRC

Definition at line 2122 of file SIRegisterInfo.cpp.

References assert(), getSGPRClassForBitWidth(), and llvm::Check::Size.

Referenced by llvm::SIInstrInfo::readlaneVGPRToSGPR().

◆ getEquivalentVGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentVGPRClass ( const TargetRegisterClass SRC) const

◆ getFrameIndexInstrOffset()

int64_t SIRegisterInfo::getFrameIndexInstrOffset ( const MachineInstr MI,
int  Idx 
) const
override

◆ getFrameRegister()

Register SIRegisterInfo::getFrameRegister ( const MachineFunction MF) const
override

◆ getHWRegIndex()

unsigned llvm::SIRegisterInfo::getHWRegIndex ( MCRegister  Reg) const
inline

Definition at line 136 of file SIRegisterInfo.h.

References Reg.

Referenced by llvm::SIInstrInfo::copyPhysReg(), and indirectCopyToAGPR().

◆ getNoPreservedMask()

const uint32_t * SIRegisterInfo::getNoPreservedMask ( ) const
override

Definition at line 383 of file SIRegisterInfo.cpp.

◆ getNumChannelsFromSubReg()

unsigned llvm::SIRegisterInfo::getNumChannelsFromSubReg ( unsigned  SubReg) const
inline

Definition at line 324 of file SIRegisterInfo.h.

References getNumCoveredRegs(), and SubReg.

Referenced by getSubRegClass().

◆ getNumCoveredRegs()

static unsigned llvm::SIRegisterInfo::getNumCoveredRegs ( LaneBitmask  LM)
inlinestatic

◆ getPhysRegClass()

const TargetRegisterClass * SIRegisterInfo::getPhysRegClass ( MCRegister  Reg) const

Return the 'base' register class for this register.

e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.

Definition at line 2004 of file SIRegisterInfo.cpp.

References Reg.

Referenced by llvm::SIInstrInfo::copyPhysReg(), llvm::SIInstrInfo::FoldImmediate(), get32BitRegister(), llvm::SIInstrInfo::getOpRegClass(), getRegClassForReg(), isSGPRReg(), and llvm::SGPRSpillBuilder::SGPRSpillBuilder().

◆ getPointerRegClass()

const TargetRegisterClass * SIRegisterInfo::getPointerRegClass ( const MachineFunction MF,
unsigned  Kind = 0 
) const
override

Definition at line 785 of file SIRegisterInfo.cpp.

◆ getRegAsmName()

StringRef SIRegisterInfo::getRegAsmName ( MCRegister  Reg) const
override

Definition at line 1861 of file SIRegisterInfo.cpp.

References llvm::AMDGPUInstPrinter::getRegisterName(), and Reg.

◆ getRegClass()

const TargetRegisterClass * SIRegisterInfo::getRegClass ( unsigned  RCID) const

◆ getRegClassForReg()

const TargetRegisterClass * SIRegisterInfo::getRegClassForReg ( const MachineRegisterInfo MRI,
Register  Reg 
) const

◆ getRegClassForSizeOnBank()

const TargetRegisterClass * SIRegisterInfo::getRegClassForSizeOnBank ( unsigned  Size,
const RegisterBank Bank,
const MachineRegisterInfo MRI 
) const

◆ getRegClassForTypeOnBank()

const TargetRegisterClass* llvm::SIRegisterInfo::getRegClassForTypeOnBank ( LLT  Ty,
const RegisterBank Bank,
const MachineRegisterInfo MRI 
) const
inline

◆ getRegPressureLimit()

unsigned SIRegisterInfo::getRegPressureLimit ( const TargetRegisterClass RC,
MachineFunction MF 
) const
override

◆ getRegPressureSetLimit()

unsigned SIRegisterInfo::getRegPressureSetLimit ( const MachineFunction MF,
unsigned  Idx 
) const
override

◆ getRegSplitParts()

ArrayRef< int16_t > SIRegisterInfo::getRegSplitParts ( const TargetRegisterClass RC,
unsigned  EltSize 
) const

◆ getRegUnitPressureSets()

const int * SIRegisterInfo::getRegUnitPressureSets ( unsigned  RegUnit) const
override

Definition at line 2311 of file SIRegisterInfo.cpp.

◆ getReservedRegs()

BitVector SIRegisterInfo::getReservedRegs ( const MachineFunction MF) const
override

◆ getReturnAddressReg()

MCRegister SIRegisterInfo::getReturnAddressReg ( const MachineFunction MF) const

Definition at line 2320 of file SIRegisterInfo.cpp.

◆ getScratchInstrOffset()

int64_t SIRegisterInfo::getScratchInstrOffset ( const MachineInstr MI) const

◆ getSGPRClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getSGPRClassForBitWidth ( unsigned  BitWidth)
static

◆ getSubRegClass()

const TargetRegisterClass * SIRegisterInfo::getSubRegClass ( const TargetRegisterClass RC,
unsigned  SubIdx 
) const
Returns
The canonical register class that is used for a sub-register of RC for the given SubIdx. If SubIdx equals NoSubRegister, RC will be returned.

Definition at line 2131 of file SIRegisterInfo.cpp.

References assert(), getAGPRClassForBitWidth(), getNumChannelsFromSubReg(), getSGPRClassForBitWidth(), getVGPRClassForBitWidth(), hasAGPRs(), isSGPRClass(), and llvm::Check::Size.

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ getSubRegFromChannel()

unsigned SIRegisterInfo::getSubRegFromChannel ( unsigned  Channel,
unsigned  NumRegs = 1 
)
static
Returns
the sub reg enum value for the given Channel (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)

Definition at line 427 of file SIRegisterInfo.cpp.

References assert(), llvm::size(), and SubRegFromChannelTableWidthMap.

Referenced by llvm::SITargetLowering::AddIMGInit(), buildSpillLoadStore(), computeIndirectRegAndOffset(), expandSGPRCopy(), and llvm::SIInstrInfo::readlaneVGPRToSGPR().

◆ getVCC()

MCRegister SIRegisterInfo::getVCC ( ) const

Definition at line 2356 of file SIRegisterInfo.cpp.

Referenced by llvm::SIInstrInfo::getAddNoCarry().

◆ getVGPR64Class()

const TargetRegisterClass * SIRegisterInfo::getVGPR64Class ( ) const

◆ getVGPRClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getVGPRClassForBitWidth ( unsigned  BitWidth) const

◆ getWaveMaskRegClass()

const TargetRegisterClass* llvm::SIRegisterInfo::getWaveMaskRegClass ( ) const
inline

◆ hasAGPRs()

bool SIRegisterInfo::hasAGPRs ( const TargetRegisterClass RC) const

◆ hasBasePointer()

bool SIRegisterInfo::hasBasePointer ( const MachineFunction MF) const

◆ hasVectorRegisters()

bool llvm::SIRegisterInfo::hasVectorRegisters ( const TargetRegisterClass RC) const
inline
Returns
true if this class contains any vector registers.

Definition at line 177 of file SIRegisterInfo.h.

References hasAGPRs(), and hasVGPRs().

Referenced by llvm::SIInstrInfo::legalizeOperands().

◆ hasVGPRs()

bool SIRegisterInfo::hasVGPRs ( const TargetRegisterClass RC) const

◆ isAGPR()

bool SIRegisterInfo::isAGPR ( const MachineRegisterInfo MRI,
Register  Reg 
) const

◆ isAGPRClass()

bool llvm::SIRegisterInfo::isAGPRClass ( const TargetRegisterClass RC) const
inline
Returns
true if this class contains only AGPR registers

Definition at line 166 of file SIRegisterInfo.h.

References hasAGPRs(), and hasVGPRs().

Referenced by llvm::AMDGPURegisterBankInfo::getRegBankFromRegClass().

◆ isConstantPhysReg()

bool SIRegisterInfo::isConstantPhysReg ( MCRegister  PhysReg) const
override

Definition at line 2465 of file SIRegisterInfo.cpp.

◆ isDivergentRegClass()

bool llvm::SIRegisterInfo::isDivergentRegClass ( const TargetRegisterClass RC) const
inlineoverride

Definition at line 237 of file SIRegisterInfo.h.

References isSGPRClass().

◆ isFrameOffsetLegal()

bool SIRegisterInfo::isFrameOffsetLegal ( const MachineInstr MI,
Register  BaseReg,
int64_t  Offset 
) const
override

◆ isProperlyAlignedRC()

bool SIRegisterInfo::isProperlyAlignedRC ( const TargetRegisterClass RC) const

◆ isSGPRClass()

bool llvm::SIRegisterInfo::isSGPRClass ( const TargetRegisterClass RC) const
inline

◆ isSGPRClassID()

bool llvm::SIRegisterInfo::isSGPRClassID ( unsigned  RCID) const
inline
Returns
true if this class ID contains only SGPR registers

Definition at line 159 of file SIRegisterInfo.h.

References getRegClass(), and isSGPRClass().

◆ isSGPRReg()

bool SIRegisterInfo::isSGPRReg ( const MachineRegisterInfo MRI,
Register  Reg 
) const

◆ isVectorRegister()

bool llvm::SIRegisterInfo::isVectorRegister ( const MachineRegisterInfo MRI,
Register  Reg 
) const
inline

Definition at line 231 of file SIRegisterInfo.h.

References isAGPR(), isVGPR(), MRI, and Reg.

◆ isVGPR()

bool SIRegisterInfo::isVGPR ( const MachineRegisterInfo MRI,
Register  Reg 
) const

◆ materializeFrameBaseRegister()

Register SIRegisterInfo::materializeFrameBaseRegister ( MachineBasicBlock MBB,
int  FrameIdx,
int64_t  Offset 
) const
override

◆ needsFrameBaseReg()

bool SIRegisterInfo::needsFrameBaseReg ( MachineInstr MI,
int64_t  Offset 
) const
override

◆ opCanUseInlineConstant()

bool SIRegisterInfo::opCanUseInlineConstant ( unsigned  OpType) const
Returns
True if operands defined with this operand type can accept an inline constant. i.e. An integer value in the range (-16, 64) or -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.

Definition at line 2162 of file SIRegisterInfo.cpp.

References llvm::GCNSubtarget::hasMFMAInlineLiteralBug(), llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST, llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST, llvm::AMDGPU::OPERAND_SRC_FIRST, and llvm::AMDGPU::OPERAND_SRC_LAST.

Referenced by llvm::SIInstrInfo::isImmOperandLegal(), and tryAddToFoldList().

◆ opCanUseLiteralConstant()

bool SIRegisterInfo::opCanUseLiteralConstant ( unsigned  OpType) const
Returns
True if operands defined with this operand type can accept a literal constant (i.e. any 32-bit immediate).

Definition at line 2195 of file SIRegisterInfo.cpp.

References llvm::AMDGPU::OPERAND_REG_IMM_FIRST, and llvm::AMDGPU::OPERAND_REG_IMM_LAST.

Referenced by llvm::SIInstrInfo::isImmOperandLegal().

◆ requiresFrameIndexReplacementScavenging()

bool SIRegisterInfo::requiresFrameIndexReplacementScavenging ( const MachineFunction MF) const
override

◆ requiresFrameIndexScavenging()

bool SIRegisterInfo::requiresFrameIndexScavenging ( const MachineFunction MF) const
override

Definition at line 612 of file SIRegisterInfo.cpp.

◆ requiresRegisterScavenging()

bool SIRegisterInfo::requiresRegisterScavenging ( const MachineFunction Fn) const
override

◆ requiresVirtualBaseRegisters()

bool SIRegisterInfo::requiresVirtualBaseRegisters ( const MachineFunction Fn) const
override

Definition at line 627 of file SIRegisterInfo.cpp.

◆ reservedPrivateSegmentBufferReg()

MCRegister SIRegisterInfo::reservedPrivateSegmentBufferReg ( const MachineFunction MF) const

Return the end register initially reserved for the scratch buffer in case spilling is needed.

Definition at line 436 of file SIRegisterInfo.cpp.

References llvm::alignDown(), and llvm::GCNSubtarget::getMaxNumSGPRs().

◆ resolveFrameIndex()

void SIRegisterInfo::resolveFrameIndex ( MachineInstr MI,
Register  BaseReg,
int64_t  Offset 
) const
override

◆ restoreSGPR()

bool SIRegisterInfo::restoreSGPR ( MachineBasicBlock::iterator  MI,
int  FI,
RegScavenger RS,
bool  OnlyToVGPR = false 
) const

◆ shouldCoalesce()

bool SIRegisterInfo::shouldCoalesce ( MachineInstr MI,
const TargetRegisterClass SrcRC,
unsigned  SubReg,
const TargetRegisterClass DstRC,
unsigned  DstSubReg,
const TargetRegisterClass NewRC,
LiveIntervals LIS 
) const
override

Definition at line 2257 of file SIRegisterInfo.cpp.

◆ shouldRealignStack()

bool SIRegisterInfo::shouldRealignStack ( const MachineFunction MF) const
override

◆ shouldRewriteCopySrc()

bool SIRegisterInfo::shouldRewriteCopySrc ( const TargetRegisterClass DefRC,
unsigned  DefSubReg,
const TargetRegisterClass SrcRC,
unsigned  SrcSubReg 
) const
override

Definition at line 2171 of file SIRegisterInfo.cpp.

◆ spillSGPR()

bool SIRegisterInfo::spillSGPR ( MachineBasicBlock::iterator  MI,
int  FI,
RegScavenger RS,
bool  OnlyToVGPR = false 
) const

◆ spillSGPRToVGPR()

bool llvm::SIRegisterInfo::spillSGPRToVGPR ( ) const
inline

The documentation for this class was generated from the following files: