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16 #ifndef LLVM_LIB_TARGET_SPIRV_SPIRVTYPEMANAGER_H
17 #define LLVM_LIB_TARGET_SPIRV_SPIRVTYPEMANAGER_H
42 const unsigned PointerSize;
72 return DT.
find(
C, MF);
76 return DT.
find(GV, MF);
80 return DT.
find(
F, MF);
111 auto Res = SPIRVToLLVMType.
find(Ty);
127 assert(SpirvType &&
"Attempting to get type id for nullptr type.");
128 return SpirvType->
defs().begin()->getReg();
158 bool IsSigned =
false);
180 SPIRVType *SpvType =
nullptr,
bool EmitIR =
true);
197 unsigned NumElements,
211 #endif // LLLVM_LIB_TARGET_SPIRV_SPIRVTYPEMANAGER_H
This class represents an incoming formal argument to a Function.
Register find(const GlobalVariable *GV, MachineFunction *MF)
This is an optimization pass for GlobalISel generic memory operations.
bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const
bool isScalarOfType(Register VReg, unsigned TypeOpcode) const
SPIRVGlobalRegistry(unsigned PointerSize)
unsigned getScalarOrVectorBitWidth(const SPIRVType *Type) const
Reg
All possible values of the reg field in the ModR/M byte.
void buildDepsGraph(std::vector< SPIRV::DTSortableEntry * > &Graph, MachineModuleInfo *MMI)
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Register find(const Type *T, const MachineFunction *MF)
The instances of the Type class are immutable: once they are created, they are never changed.
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, MachineFunction &MF)
void setCurrentFunc(MachineFunction &MF)
SPIRVType * getSPIRVTypeForVReg(Register VReg) const
Register buildGlobalVariable(Register Reg, SPIRVType *BaseType, StringRef Name, const GlobalValue *GV, SPIRV::StorageClass Storage, const MachineInstr *Init, bool IsConst, bool HasLinkageTy, SPIRV::LinkageType LinkageType, MachineIRBuilder &MIRBuilder, bool IsInstSelector)
const Type * getTypeForSPIRVType(const SPIRVType *Ty) const
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
void add(const Argument *Arg, MachineFunction *MF, Register R)
Register buildConstantFP(APFloat Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType=nullptr)
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
void add(const GlobalVariable *GV, MachineFunction *MF, Register R)
(vector float) vec_cmpeq(*A, *B) C
const HexagonInstrInfo * TII
This class contains meta information specific to a module.
unsigned getPointerSize() const
This is an important base class in LLVM.
Helper class to build MachineInstr.
void add(const Constant *C, MachineFunction *MF, Register R)
Representation of each machine instruction.
void add(const Function *F, MachineFunction *MF, Register R)
iterator find(const_arg_type_t< KeyT > Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void buildDepsGraph(std::vector< SPIRV::DTSortableEntry * > &Graph, MachineModuleInfo *MMI=nullptr)
constexpr char IsConst[]
Key for Kernel::Arg::Metadata::mIsConst.
StringRef - Represent a constant reference to a string, i.e.
SPIRVType * getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder)
Wrapper class representing virtual and physical registers.
SPIRVType * getOrCreateSPIRVPointerType(SPIRVType *BaseType, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass SClass=SPIRV::StorageClass::Function)
SPIRVType * getOrCreateSPIRVIntegerType(unsigned BitWidth, MachineIRBuilder &MIRBuilder)
constexpr unsigned BitWidth
Register find(const Constant *C, MachineFunction *MF)
Register getSPIRVTypeID(const SPIRVType *SpirvType) const
SPIRV::StorageClass getPointerStorageClass(Register VReg) const
Register buildConstantInt(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType=nullptr, bool EmitIR=true)
SPIRVType * assignTypeToVReg(const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool hasSPIRVTypeForVReg(Register VReg) const
SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
void add(const Type *T, const MachineFunction *MF, Register R)
bool isScalarOrVectorSigned(const SPIRVType *Type) const
SPIRVType * getOrCreateSPIRVVectorType(SPIRVType *BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder)
Register find(const Function *F, MachineFunction *MF)