LLVM 17.0.0git
VEMCCodeEmitter.cpp
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1//===-- VEMCCodeEmitter.cpp - Convert VE code to machine code -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the VEMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
14#include "VE.h"
15#include "VEMCExpr.h"
17#include "llvm/ADT/Statistic.h"
19#include "llvm/MC/MCContext.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCFixup.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCSymbol.h"
30#include <cassert>
31#include <cstdint>
32
33using namespace llvm;
34
35#define DEBUG_TYPE "mccodeemitter"
36
37STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
38
39namespace {
40
41class VEMCCodeEmitter : public MCCodeEmitter {
42 MCContext &Ctx;
43
44public:
45 VEMCCodeEmitter(const MCInstrInfo &, MCContext &ctx)
46 : Ctx(ctx) {}
47 VEMCCodeEmitter(const VEMCCodeEmitter &) = delete;
48 VEMCCodeEmitter &operator=(const VEMCCodeEmitter &) = delete;
49 ~VEMCCodeEmitter() override = default;
50
53 const MCSubtargetInfo &STI) const override;
54
55 // getBinaryCodeForInstr - TableGen'erated function for getting the
56 // binary encoding for an instruction.
57 uint64_t getBinaryCodeForInstr(const MCInst &MI,
59 const MCSubtargetInfo &STI) const;
60
61 /// getMachineOpValue - Return binary encoding of operand. If the machine
62 /// operand requires relocation, record the relocation and return zero.
63 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
65 const MCSubtargetInfo &STI) const;
66
67 uint64_t getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
69 const MCSubtargetInfo &STI) const;
70 uint64_t getCCOpValue(const MCInst &MI, unsigned OpNo,
72 const MCSubtargetInfo &STI) const;
73 uint64_t getRDOpValue(const MCInst &MI, unsigned OpNo,
75 const MCSubtargetInfo &STI) const;
76};
77
78} // end anonymous namespace
79
80void VEMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
82 const MCSubtargetInfo &STI) const {
83 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
84 support::endian::write<uint64_t>(OS, Bits, support::little);
85
86 ++MCNumEmitted; // Keep track of the # of mi's emitted.
87}
88
89unsigned VEMCCodeEmitter::getMachineOpValue(const MCInst &MI,
90 const MCOperand &MO,
92 const MCSubtargetInfo &STI) const {
93 if (MO.isReg())
94 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
95 if (MO.isImm())
96 return static_cast<unsigned>(MO.getImm());
97
98 assert(MO.isExpr());
99
100 const MCExpr *Expr = MO.getExpr();
101 if (const VEMCExpr *SExpr = dyn_cast<VEMCExpr>(Expr)) {
102 MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
103 Fixups.push_back(MCFixup::create(0, Expr, Kind));
104 return 0;
105 }
106
107 int64_t Res;
108 if (Expr->evaluateAsAbsolute(Res))
109 return Res;
110
111 llvm_unreachable("Unhandled expression!");
112 return 0;
113}
114
116VEMCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
118 const MCSubtargetInfo &STI) const {
119 const MCOperand &MO = MI.getOperand(OpNo);
120 if (MO.isReg() || MO.isImm())
121 return getMachineOpValue(MI, MO, Fixups, STI);
122
123 Fixups.push_back(
125 return 0;
126}
127
128uint64_t VEMCCodeEmitter::getCCOpValue(const MCInst &MI, unsigned OpNo,
130 const MCSubtargetInfo &STI) const {
131 const MCOperand &MO = MI.getOperand(OpNo);
132 if (MO.isImm())
133 return VECondCodeToVal(
134 static_cast<VECC::CondCode>(getMachineOpValue(MI, MO, Fixups, STI)));
135 return 0;
136}
137
138uint64_t VEMCCodeEmitter::getRDOpValue(const MCInst &MI, unsigned OpNo,
140 const MCSubtargetInfo &STI) const {
141 const MCOperand &MO = MI.getOperand(OpNo);
142 if (MO.isImm())
143 return VERDToVal(static_cast<VERD::RoundingMode>(
144 getMachineOpValue(MI, MO, Fixups, STI)));
145 return 0;
146}
147
148#include "VEGenMCCodeEmitter.inc"
149
151 MCContext &Ctx) {
152 return new VEMCCodeEmitter(MCII, Ctx);
153}
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
IRTranslator LLVM IR MI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Definition: MCCodeEmitter.h:28
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
int64_t getImm() const
Definition: MCInst.h:80
bool isImm() const
Definition: MCInst.h:62
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
const MCExpr * getExpr() const
Definition: MCInst.h:114
bool isExpr() const
Definition: MCInst.h:65
Generic base class for all target subtargets.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CondCode
Definition: VE.h:44
RoundingMode
Definition: VE.h:76
@ fixup_ve_srel32
fixup_ve_srel32 - 32-bit fixup corresponding to foo for relative branch
Definition: VEFixupKinds.h:21
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static unsigned VECondCodeToVal(VECC::CondCode CC)
Definition: VE.h:156
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
static unsigned VERDToVal(VERD::RoundingMode R)
Definition: VE.h:370
MCCodeEmitter * createVEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)