LLVM  15.0.0git
VETargetTransformInfo.h
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1 //===- VETargetTransformInfo.h - VE specific TTI ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// VE target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
18 
19 #include "VE.h"
20 #include "VETargetMachine.h"
23 
25  return llvm::cast<llvm::FixedVectorType>(Ty)->getElementType();
26 }
27 
29  using namespace llvm;
30  if (!isa<VectorType>(Ty))
31  return Ty;
32  return getVectorElementType(Ty);
33 }
34 
35 static bool isVectorLaneType(llvm::Type &ElemTy) {
36  // check element sizes for vregs
37  if (ElemTy.isIntegerTy()) {
38  unsigned ScaBits = ElemTy.getScalarSizeInBits();
39  return ScaBits == 1 || ScaBits == 32 || ScaBits == 64;
40  }
41  if (ElemTy.isPointerTy()) {
42  return true;
43  }
44  if (ElemTy.isFloatTy() || ElemTy.isDoubleTy()) {
45  return true;
46  }
47  return false;
48 }
49 
50 namespace llvm {
51 
52 class VETTIImpl : public BasicTTIImplBase<VETTIImpl> {
54  friend BaseT;
55 
56  const VESubtarget *ST;
57  const VETargetLowering *TLI;
58 
59  const VESubtarget *getST() const { return ST; }
60  const VETargetLowering *getTLI() const { return TLI; }
61 
62  bool enableVPU() const { return getST()->enableVPU(); }
63 
64  static bool isSupportedReduction(Intrinsic::ID ReductionID) {
65 #define VEC_VP_CASE(SUFFIX) \
66  case Intrinsic::vp_reduce_##SUFFIX: \
67  case Intrinsic::vector_reduce_##SUFFIX:
68 
69  switch (ReductionID) {
75  return true;
76 
77  default:
78  return false;
79  }
80 #undef VEC_VP_CASE
81  }
82 
83 public:
84  explicit VETTIImpl(const VETargetMachine *TM, const Function &F)
85  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
86  TLI(ST->getTargetLowering()) {}
87 
88  unsigned getNumberOfRegisters(unsigned ClassID) const {
89  bool VectorRegs = (ClassID == 1);
90  if (VectorRegs) {
91  // TODO report vregs once vector isel is stable.
92  return 0;
93  }
94 
95  return 64;
96  }
97 
99  switch (K) {
101  return TypeSize::getFixed(64);
103  // TODO report vregs once vector isel is stable.
104  return TypeSize::getFixed(0);
106  return TypeSize::getScalable(0);
107  }
108 
109  llvm_unreachable("Unsupported register kind");
110  }
111 
112  /// \returns How the target needs this vector-predicated operation to be
113  /// transformed.
118  }
119 
120  unsigned getMinVectorRegisterBitWidth() const {
121  // TODO report vregs once vector isel is stable.
122  return 0;
123  }
124 
126  // NEC nld doesn't support relative lookup tables. It shows following
127  // errors. So, we disable it at the moment.
128  // /opt/nec/ve/bin/nld: src/CMakeFiles/cxxabi_shared.dir/cxa_demangle.cpp
129  // .o(.rodata+0x17b4): reloc against `.L.str.376': error 2
130  // /opt/nec/ve/bin/nld: final link failed: Nonrepresentable section on
131  // output
132  return false;
133  }
134 
135  // Load & Store {
136  bool isLegalMaskedLoad(Type *DataType, MaybeAlign Alignment) {
137  return isVectorLaneType(*getLaneType(DataType));
138  }
139  bool isLegalMaskedStore(Type *DataType, MaybeAlign Alignment) {
140  return isVectorLaneType(*getLaneType(DataType));
141  }
142  bool isLegalMaskedGather(Type *DataType, MaybeAlign Alignment) {
143  return isVectorLaneType(*getLaneType(DataType));
144  };
145  bool isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) {
146  return isVectorLaneType(*getLaneType(DataType));
147  }
148  // } Load & Store
149 
150  bool shouldExpandReduction(const IntrinsicInst *II) const {
151  if (!enableVPU())
152  return true;
153  return !isSupportedReduction(II->getIntrinsicID());
154  }
155 };
156 
157 } // namespace llvm
158 
159 #endif // LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
llvm::VETTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, MaybeAlign Alignment)
Definition: VETargetTransformInfo.h:136
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
getLaneType
static llvm::Type * getLaneType(llvm::Type *Ty)
Definition: VETargetTransformInfo.h:28
llvm::Type::isPointerTy
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:218
llvm::VETTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, MaybeAlign Alignment)
Definition: VETargetTransformInfo.h:142
llvm::Function
Definition: Function.h:60
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:53
llvm::VETTIImpl::getVPLegalizationStrategy
TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: VETargetTransformInfo.h:115
llvm::VESubtarget::enableVPU
bool enableVPU() const
Definition: VESubtarget.h:65
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:919
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1437
llvm::VETTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: VETargetTransformInfo.h:120
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::VETTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: VETargetTransformInfo.h:88
llvm::VETTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: VETargetTransformInfo.h:98
llvm::VETTIImpl
Definition: VETargetTransformInfo.h:52
and
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Definition: README.txt:1271
F
#define F(x, y, z)
Definition: MD5.cpp:55
isVectorLaneType
static bool isVectorLaneType(llvm::Type &ElemTy)
Definition: VETargetTransformInfo.h:35
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:46
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:189
llvm::TargetTransformInfo::RGK_FixedWidthVector
@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:919
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::Type::isIntegerTy
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:191
llvm::ARM_AM::add
@ add
Definition: ARMAddressingModes.h:39
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:77
llvm::VETTIImpl::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, MaybeAlign Alignment)
Definition: VETargetTransformInfo.h:139
llvm::VETTIImpl::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: VETargetTransformInfo.h:150
llvm::VETTIImpl::VETTIImpl
VETTIImpl(const VETargetMachine *TM, const Function &F)
Definition: VETargetTransformInfo.h:84
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:868
xor
We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 xor
Definition: README.txt:1271
llvm::VETargetMachine
Definition: VETargetMachine.h:22
llvm::Type::isFloatTy
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:148
or
compiles or
Definition: README.txt:606
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:391
VPLegalization
TargetTransformInfo::VPLegalization VPLegalization
Definition: ExpandVectorPredication.cpp:34
llvm::TypeSize
Definition: TypeSize.h:421
llvm::LinearPolySize< TypeSize >::getScalable
static TypeSize getScalable(ScalarTy MinVal)
Definition: TypeSize.h:286
llvm::Type::isDoubleTy
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
Definition: Type.h:151
llvm::TargetTransformInfo::RGK_ScalableVector
@ RGK_ScalableVector
Definition: TargetTransformInfo.h:919
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
VE.h
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:919
getVectorElementType
static llvm::Type * getVectorElementType(llvm::Type *Ty)
Definition: VETargetTransformInfo.h:24
llvm::VESubtarget
Definition: VESubtarget.h:31
llvm::TargetTransformInfo::VPLegalization::Legal
@ Legal
Definition: TargetTransformInfo.h:1440
TargetTransformInfo.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
VETargetMachine.h
llvm::VETargetLowering
Definition: VEISelLowering.h:65
BasicTTIImpl.h
llvm::VETTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment)
Definition: VETargetTransformInfo.h:145
VEC_VP_CASE
#define VEC_VP_CASE(SUFFIX)
llvm::APIntOps::smax
const APInt & smax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be signed.
Definition: APInt.h:2144
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::VETTIImpl::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Definition: VETargetTransformInfo.h:125