LLVM  14.0.0git
VETargetTransformInfo.h
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1 //===- VETargetTransformInfo.h - VE specific TTI ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// VE target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
18 
19 #include "VE.h"
20 #include "VETargetMachine.h"
23 
24 namespace llvm {
25 
26 class VETTIImpl : public BasicTTIImplBase<VETTIImpl> {
28  friend BaseT;
29 
30  const VESubtarget *ST;
31  const VETargetLowering *TLI;
32 
33  const VESubtarget *getST() const { return ST; }
34  const VETargetLowering *getTLI() const { return TLI; }
35 
36  bool enableVPU() const { return getST()->enableVPU(); }
37 
38 public:
39  explicit VETTIImpl(const VETargetMachine *TM, const Function &F)
40  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
41  TLI(ST->getTargetLowering()) {}
42 
43  unsigned getNumberOfRegisters(unsigned ClassID) const {
44  bool VectorRegs = (ClassID == 1);
45  if (VectorRegs) {
46  // TODO report vregs once vector isel is stable.
47  return 0;
48  }
49 
50  return 64;
51  }
52 
54  switch (K) {
56  return TypeSize::getFixed(64);
58  // TODO report vregs once vector isel is stable.
59  return TypeSize::getFixed(0);
61  return TypeSize::getScalable(0);
62  }
63 
64  llvm_unreachable("Unsupported register kind");
65  }
66 
67  /// \returns How the target needs this vector-predicated operation to be
68  /// transformed.
73  }
74 
75  unsigned getMinVectorRegisterBitWidth() const {
76  // TODO report vregs once vector isel is stable.
77  return 0;
78  }
79 
81  // NEC nld doesn't support relative lookup tables. It shows following
82  // errors. So, we disable it at the moment.
83  // /opt/nec/ve/bin/nld: src/CMakeFiles/cxxabi_shared.dir/cxa_demangle.cpp
84  // .o(.rodata+0x17b4): reloc against `.L.str.376': error 2
85  // /opt/nec/ve/bin/nld: final link failed: Nonrepresentable section on
86  // output
87  return false;
88  }
89 };
90 
91 } // namespace llvm
92 
93 #endif // LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::Function
Definition: Function.h:62
llvm::VETTIImpl::getVPLegalizationStrategy
TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: VETargetTransformInfo.h:70
llvm::VESubtarget::enableVPU
bool enableVPU() const
Definition: VESubtarget.h:65
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:911
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1398
llvm::VETTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: VETargetTransformInfo.h:75
llvm::VETTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: VETargetTransformInfo.h:43
llvm::VETTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: VETargetTransformInfo.h:53
llvm::VETTIImpl
Definition: VETargetTransformInfo.h:26
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:49
llvm::TargetTransformInfo::RGK_FixedWidthVector
@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:911
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:77
llvm::VETTIImpl::VETTIImpl
VETTIImpl(const VETargetMachine *TM, const Function &F)
Definition: VETargetTransformInfo.h:39
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:870
llvm::VETargetMachine
Definition: VETargetMachine.h:22
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:390
VPLegalization
TargetTransformInfo::VPLegalization VPLegalization
Definition: ExpandVectorPredication.cpp:36
llvm::TypeSize
Definition: TypeSize.h:416
llvm::LinearPolySize< TypeSize >::getScalable
static TypeSize getScalable(ScalarTy MinVal)
Definition: TypeSize.h:286
llvm::TargetTransformInfo::RGK_ScalableVector
@ RGK_ScalableVector
Definition: TargetTransformInfo.h:911
VE.h
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:911
llvm::VESubtarget
Definition: VESubtarget.h:31
llvm::TargetTransformInfo::VPLegalization::Legal
@ Legal
Definition: TargetTransformInfo.h:1401
TargetTransformInfo.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
VETargetMachine.h
llvm::VETargetLowering
Definition: VEISelLowering.h:50
BasicTTIImpl.h
llvm::VETTIImpl::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Definition: VETargetTransformInfo.h:80