LLVM 17.0.0git
VEISelLowering.h
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1//===-- VEISelLowering.h - VE DAG Lowering Interface ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that VE uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_VE_VEISELLOWERING_H
15#define LLVM_LIB_TARGET_VE_VEISELLOWERING_H
16
17#include "VE.h"
19
20namespace llvm {
21class VESubtarget;
22
23namespace VEISD {
24enum NodeType : unsigned {
26
27 CMPI, // Compare between two signed integer values.
28 CMPU, // Compare between two unsigned integer values.
29 CMPF, // Compare between two floating-point values.
30 CMPQ, // Compare between two quad floating-point values.
31 CMOV, // Select between two values using the result of comparison.
32
33 CALL, // A call instruction.
34 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
35 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
36 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
37 GETFUNPLT, // Load function address through %plt insturction.
38 GETTLSADDR, // Load address for TLS access.
39 GETSTACKTOP, // Retrieve address of stack top (first address of
40 // locals and temporaries).
41 GLOBAL_BASE_REG, // Global base reg for PIC.
42 Hi, // Hi/Lo operations, typically on a global address.
43 Lo, // Hi/Lo operations, typically on a global address.
44 RET_FLAG, // Return with a flag operand.
45 TS1AM, // A TS1AM instruction used for 1/2 bytes swap.
46 VEC_UNPACK_LO, // unpack the lo v256 slice of a packed v512 vector.
47 VEC_UNPACK_HI, // unpack the hi v256 slice of a packed v512 vector.
48 // 0: v512 vector, 1: AVL
49 VEC_PACK, // pack a lo and a hi vector into one v512 vector
50 // 0: v256 lo vector, 1: v256 hi vector, 2: AVL
51
52 VEC_BROADCAST, // A vector broadcast instruction.
53 // 0: scalar value, 1: VL
55 REPL_F32, // Replicate subregister to other half.
56
57 // Annotation as a wrapper. LEGALAVL(VL) means that VL refers to 64bit of
58 // data, whereas the raw EVL coming in from VP nodes always refers to number
59 // of elements, regardless of their size.
61
62// VVP_* nodes.
63#define ADD_VVP_OP(VVP_NAME, ...) VVP_NAME,
64#include "VVPNodes.def"
65};
66}
67
68class VECustomDAG;
69
71 const VESubtarget *Subtarget;
72
73 void initRegisterClasses();
74 void initSPUActions();
75 void initVPUActions();
76
77public:
78 VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);
79
80 const char *getTargetNodeName(unsigned Opcode) const override;
81 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
82 return MVT::i32;
83 }
84
85 Register getRegisterByName(const char *RegName, LLT VT,
86 const MachineFunction &MF) const override;
87
88 /// getSetCCResultType - Return the ISD::SETCC ValueType
90 EVT VT) const override;
91
93 bool isVarArg,
95 const SDLoc &dl, SelectionDAG &DAG,
96 SmallVectorImpl<SDValue> &InVals) const override;
97
99 SmallVectorImpl<SDValue> &InVals) const override;
100
102 bool isVarArg,
103 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
104 LLVMContext &Context) const override;
105 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
107 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
108 SelectionDAG &DAG) const override;
109
110 /// Helper functions for atomic operations.
111 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
112 // VE uses release consistency, so need fence for each atomics.
113 return true;
114 }
116 AtomicOrdering Ord) const override;
118 AtomicOrdering Ord) const override;
120 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
122 return ISD::ANY_EXTEND;
123 }
124
125 /// Custom Lower {
127 getCustomOperationAction(SDNode &) const override;
128
129 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
130 unsigned getJumpTableEncoding() const override;
132 const MachineBasicBlock *MBB,
133 unsigned Uid,
134 MCContext &Ctx) const override;
136 SelectionDAG &DAG) const override;
137 // VE doesn't need getPICJumpTableRelocBaseExpr since it is used for only
138 // EK_LabelDifference32.
139
152 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
153 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
156 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
157
161 /// } Custom Lower
162
163 /// Replace the results of node with an illegal result
164 /// type with new values built out of custom code.
165 ///
167 SelectionDAG &DAG) const override;
168
169 /// Custom Inserter {
172 MachineBasicBlock *MBB) const override;
174 MachineBasicBlock *MBB) const;
176 MachineBasicBlock *MBB) const;
178 MachineBasicBlock *BB) const;
179
181 MachineBasicBlock *DispatchBB, int FI,
182 int Offset) const;
183 // Setup basic block address.
185 MachineBasicBlock *TargetBB, const DebugLoc &DL) const;
186 // Prepare function/variable address.
188 StringRef Symbol, const DebugLoc &DL, bool IsLocal,
189 bool IsCall) const;
190 /// } Custom Inserter
191
192 /// VVP Lowering {
193 SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const;
196
199 SDValue splitVectorOp(SDValue Op, VECustomDAG &CDAG) const;
203 /// } VVPLowering
204
205 /// Custom DAGCombine {
206 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
207
208 SDValue combineSelect(SDNode *N, DAGCombinerInfo &DCI) const;
209 SDValue combineSelectCC(SDNode *N, DAGCombinerInfo &DCI) const;
210 SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
211 /// } Custom DAGCombine
212
213 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
214 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
215 SelectionDAG &DAG) const;
216 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
217
218 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
219 bool isFPImmLegal(const APFloat &Imm, EVT VT,
220 bool ForCodeSize) const override;
221 /// Returns true if the target allows unaligned memory accesses of the
222 /// specified type.
223 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A,
225 unsigned *Fast) const override;
226
227 /// Inline Assembly {
228
229 ConstraintType getConstraintType(StringRef Constraint) const override;
230 std::pair<unsigned, const TargetRegisterClass *>
232 StringRef Constraint, MVT VT) const override;
233
234 /// } Inline Assembly
235
236 /// Target Optimization {
237
238 // Return lower limit for number of blocks in a jump table.
239 unsigned getMinimumJumpTableEntries() const override;
240
241 // SX-Aurora VE's s/udiv is 5-9 times slower than multiply.
242 bool isIntDivCheap(EVT, AttributeList) const override { return false; }
243 // VE doesn't have rem.
244 bool hasStandaloneRem(EVT) const override { return false; }
245 // VE LDZ instruction returns 64 if the input is zero.
246 bool isCheapToSpeculateCtlz(Type *) const override { return true; }
247 // VE LDZ instruction is fast.
248 bool isCtlzFast() const override { return true; }
249 // VE has NND instruction.
250 bool hasAndNot(SDValue Y) const override;
251
252 /// } Target Optimization
253};
254} // namespace llvm
255
256#endif // LLVM_LIB_TARGET_VE_VEISELLOWERING_H
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
IRTranslator LLVM IR MI
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:114
A debug info location.
Definition: DebugLoc.h:33
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
SDValue splitMaskArithmetic(SDValue Op, SelectionDAG &DAG) const
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SDValue lowerVVP_GATHER_SCATTER(SDValue Op, VECustomDAG &) const
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const
} Custom Inserter
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
SDValue lowerVVP_LOAD_STORE(SDValue Op, VECustomDAG &) const
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Helper functions for atomic operations.
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const
SDValue combineSelect(SDNode *N, DAGCombinerInfo &DCI) const
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Custom Lower {.
SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
SDValue legalizePackedAVL(SDValue Op, VECustomDAG &CDAG) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
} VVPLowering
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
SDValue combineSelectCC(SDNode *N, DAGCombinerInfo &DCI) const
SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const
unsigned getMinimumJumpTableEntries() const override
} Inline Assembly
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
MachineBasicBlock * emitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Register prepareMBB(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TargetBB, const DebugLoc &DL) const
void setupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI, int Offset) const
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
Custom Inserter {.
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const
bool hasStandaloneRem(EVT) const override
Return true if the target can handle a standalone remainder operation.
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
TargetLoweringBase::LegalizeAction getCustomOperationAction(SDNode &) const override
Custom Lower {.
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
SDValue splitPackedLoadStore(SDValue Op, VECustomDAG &CDAG) const
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
SDValue legalizeInternalVectorOp(SDValue Op, SelectionDAG &DAG) const
Register prepareSymbol(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, StringRef Symbol, const DebugLoc &DL, bool IsLocal, bool IsCall) const
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
} Custom Lower
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
SDValue splitVectorOp(SDValue Op, VECustomDAG &CDAG) const
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
} Custom DAGCombine
SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
SDValue legalizeInternalLoadStoreOp(SDValue Op, VECustomDAG &CDAG) const
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned Uid, MCContext &Ctx) const override
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const
unsigned getJumpTableEncoding() const override
JumpTable for VE.
SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const
bool isIntDivCheap(EVT, AttributeList) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
ConstraintType getConstraintType(StringRef Constraint) const override
Inline Assembly {.
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1311
@ EH_SJLJ_SETUP_DISPATCH
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
AtomicOrdering
Atomic ordering for LLVM's memory model.
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
This structure contains all information that is necessary for lowering calls.