26#define DEBUG_TYPE "csky-mccode-emitter"
28STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
89 Fixups[Fixups.size() - 1].setOffset(2);
99 unsigned Size =
MI.getOpcode() == CSKY::NEG32 ? 4 : 2;
121 unsigned Size =
MI.getOpcode() == CSKY::RSUBI32 ? 4 : 2;
132 .
addImm(
MI.getOperand(2).getImm() + 1);
146 switch (
MI.getOpcode()) {
194 case CSKY::LRW32_Gen:
199 case CSKY::LRW16_Gen:
208 .
addImm(
MI.getOperand(2).getImm() + 1);
214 .
addImm(
MI.getOperand(2).getImm() + 1);
220 .
addImm(32 -
MI.getOperand(2).getImm());
223 auto V = 1 <<
MI.getOperand(1).getImm();
241 return static_cast<unsigned>(MO.
getImm());
251 assert(
MI.getOperand(
Idx).isReg() &&
"Unexpected MO type.");
252 assert(
MI.getOperand(
Idx + 1).isImm() &&
"Unexpected MO type.");
254 unsigned Ry =
MI.getOperand(
Idx).getReg();
255 unsigned Rz =
MI.getOperand(
Idx + 1).getImm();
272 unsigned Binary = ((Reg1 & 0x1f) << 5) | (Reg2 - Reg1);
280 if (
MI.getOperand(
Idx).getImm() == 16)
282 else if (
MI.getOperand(
Idx).getImm() == 24)
284 else if (
MI.getOperand(
Idx).getImm() == 32)
286 else if (
MI.getOperand(
Idx).getImm() == 40)
293 const CSKYMCExpr *CSKYExpr = cast<CSKYMCExpr>(Expr);
324#include "CSKYGenMCCodeEmitter.inc"
static void writeData(uint32_t Bin, unsigned Size, SmallVectorImpl< char > &CB)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
unsigned getRegisterSeqOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getOImmOpValue(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
uint64_t getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
void expandJBTF(const MCInst &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getImmOpValueMSBSize(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
MCFixupKind getTargetFixup(const MCExpr *Expr) const
void expandRSUBI(const MCInst &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
void expandNEG(const MCInst &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getRegSeqImmOpValue(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getImmOpValueIDLY(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override
Encode the given Inst to bytes and append to CB.
unsigned getImmJMPIX(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
VariantKind getKind() const
This class represents an Operation in the Expression.
MCCodeEmitter - Generic instruction encoding interface.
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
Base class for the full range of assembler expressions which are needed for parsing.
MCInstBuilder & addOperand(const MCOperand &Op)
Add an operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_csky_plt_imm18_scale4
@ fixup_csky_got_imm18_scale4
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
This is an optimization pass for GlobalISel generic memory operations.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
MCCodeEmitter * createCSKYMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Description of the encoding of one expression Op.