22#define DEBUG_TYPE "llvm-mca"
31 : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
32 CarryOver(0U), STI(Subtarget), RCU(R), PRF(
F) {
37void DispatchStage::notifyInstructionDispatched(
const InstRef &
IR,
39 unsigned UOps)
const {
45bool DispatchStage::checkPRF(
const InstRef &
IR)
const {
47 for (
const WriteState &RegDef :
IR.getInstruction()->getDefs())
50 const unsigned RegisterMask = PRF.
isAvailable(RegDefs);
61bool DispatchStage::checkRCU(
const InstRef &
IR)
const {
62 const unsigned NumMicroOps =
IR.getInstruction()->getNumMicroOps();
63 if (RCU.isAvailable(NumMicroOps))
70bool DispatchStage::canDispatch(
const InstRef &
IR)
const {
71 bool CanDispatch = checkRCU(
IR);
72 CanDispatch &= checkPRF(
IR);
78 assert(!CarryOver &&
"Cannot dispatch another instruction!");
80 const unsigned NumMicroOps = IS.getNumMicroOps();
81 if (NumMicroOps > DispatchWidth) {
82 assert(AvailableEntries == DispatchWidth);
84 CarryOver = NumMicroOps - DispatchWidth;
87 assert(AvailableEntries >= NumMicroOps);
88 AvailableEntries -= NumMicroOps;
96 if (IS.isOptimizableMove())
97 if (PRF.tryEliminateMoveOrSwap(IS.getDefs(), IS.getUses()))
109 if (!IS.isEliminated()) {
110 for (ReadState &RS : IS.getUses())
111 PRF.addRegisterRead(RS, STI);
117 SmallVector<unsigned, 4> RegisterFiles(PRF.getNumRegisterFiles());
118 for (WriteState &WS : IS.getDefs())
119 PRF.addRegisterWrite(WriteRef(
IR.getSourceIndex(), &WS), RegisterFiles);
122 unsigned RCUTokenID = RCU.dispatch(
IR);
124 IS.dispatch(RCUTokenID);
128 notifyInstructionDispatched(
IR, RegisterFiles,
129 std::min(DispatchWidth, NumMicroOps));
137 AvailableEntries = DispatchWidth;
141 AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
142 unsigned DispatchedOpcodes = DispatchWidth - AvailableEntries;
143 CarryOver -= DispatchedOpcodes;
144 assert(CarriedOver &&
"Invalid dispatched instruction");
147 notifyInstructionDispatched(CarriedOver, RegisterFiles, DispatchedOpcodes);
155 if (!AvailableEntries)
160 unsigned Required = std::min(NumMicroOps, DispatchWidth);
164 if (Inst.
getBeginGroup() && AvailableEntries != DispatchWidth)
170 return canDispatch(
IR);
174 assert(canDispatch(
IR) &&
"Cannot dispatch another instruction!");
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file models the dispatch component of an instruction pipeline.
This file defines the main interface for hardware event listeners.
Legalize the Machine IR a function s Machine IR
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Subclass of Error for the sole purpose of identifying the success path in the type system.
Lightweight error class with error context and mandatory checking.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
reference emplace_back(ArgTypes &&... Args)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Error cycleStart() override
Called once at the start of each cycle.
bool isAvailable(const InstRef &IR) const override
Returns true if it can execute IR during this cycle.
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI, unsigned MaxDispatchWidth, RetireControlUnit &R, RegisterFile &F)
An InstRef contains both a SourceMgr index and Instruction pair.
unsigned getNumMicroOps() const
bool getBeginGroup() const
An instruction propagated through the simulated instruction pipeline.
Manages hardware register files, and tracks register definitions for register renaming purposes.
unsigned isAvailable(ArrayRef< MCPhysReg > Regs) const
Error moveToTheNextStage(InstRef &IR)
Called when an instruction is ready to move the next pipeline stage.
void notifyEvent(const EventT &Event) const
Notify listeners of a particular hardware event.
bool checkNextStage(const InstRef &IR) const
friend class Instruction
Iterator for Instructions in a `BasicBlock.
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
This class tracks which instructions are in-flight (i.e., dispatched but not retired) in the OoO back...