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LoongArchInstrInfo.h
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1 //=- LoongArchInstrInfo.h - LoongArch Instruction Information ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the LoongArch implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
14 #define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
15 
16 #include "LoongArchRegisterInfo.h"
18 
19 #define GET_INSTRINFO_HEADER
20 #include "LoongArchGenInstrInfo.inc"
21 
22 namespace llvm {
23 
24 class LoongArchSubtarget;
25 
27 public:
29 
31  const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
32  bool KillSrc) const override;
33 
36  bool IsKill, int FrameIndex,
37  const TargetRegisterClass *RC,
38  const TargetRegisterInfo *TRI) const override;
41  int FrameIndex, const TargetRegisterClass *RC,
42  const TargetRegisterInfo *TRI) const override;
43 
44  // Materializes the given integer Val into DstReg.
46  const DebugLoc &DL, Register DstReg, uint64_t Val,
48 
49  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
50 
51  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
52 
54  MachineBasicBlock *&FBB,
56  bool AllowModify) const override;
57 
58  bool isBranchOffsetInRange(unsigned BranchOpc,
59  int64_t BrOffset) const override;
60 
62  int *BytesRemoved = nullptr) const override;
63 
66  const DebugLoc &dl,
67  int *BytesAdded = nullptr) const override;
68 
70  MachineBasicBlock &NewDestBB,
71  MachineBasicBlock &RestoreBB, const DebugLoc &DL,
72  int64_t BrOffset, RegScavenger *RS) const override;
73 
74  bool
76 
77  std::pair<unsigned, unsigned>
78  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
79 
82 
83 protected:
85 };
86 
87 } // end namespace llvm
88 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
llvm::LoongArchInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: LoongArchInstrInfo.cpp:290
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::LoongArchInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: LoongArchInstrInfo.cpp:461
llvm::LoongArchInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: LoongArchInstrInfo.cpp:466
LoongArchRegisterInfo.h
llvm::LoongArchInstrInfo::getBranchDestBlock
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Definition: LoongArchInstrInfo.cpp:188
llvm::LoongArchInstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Definition: LoongArchInstrInfo.cpp:267
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
TargetInstrInfo.h
llvm::LoongArchInstrInfo::insertIndirectBranch
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
Definition: LoongArchInstrInfo.cpp:361
llvm::LoongArchInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: LoongArchInstrInfo.cpp:107
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
LoongArchGenInstrInfo
llvm::LoongArchInstrInfo::STI
const LoongArchSubtarget & STI
Definition: LoongArchInstrInfo.h:84
llvm::LoongArchInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: LoongArchInstrInfo.cpp:453
llvm::LoongArchInstrInfo::movImm
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
Definition: LoongArchInstrInfo.cpp:141
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::LoongArchInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: LoongArchInstrInfo.cpp:207
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::LoongArchSubtarget
Definition: LoongArchSubtarget.h:32
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:83
llvm::LoongArchInstrInfo::LoongArchInstrInfo
LoongArchInstrInfo(LoongArchSubtarget &STI)
Definition: LoongArchInstrInfo.cpp:26
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:82
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:138
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LoongArchInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
Definition: LoongArchInstrInfo.cpp:31
llvm::LoongArchInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: LoongArchInstrInfo.cpp:178
llvm::LoongArchInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: LoongArchInstrInfo.cpp:72
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::LoongArchInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
Definition: LoongArchInstrInfo.cpp:323
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::LoongArchInstrInfo
Definition: LoongArchInstrInfo.h:26
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24