24#define GET_INSTRINFO_CTOR_DTOR
25#include "LoongArchGenInstrInfo.inc"
29 LoongArch::ADJCALLSTACKUP),
43 if (LoongArch::GPRRegClass.
contains(DstReg, SrcReg)) {
51 if (LoongArch::LSX128RegClass.
contains(DstReg, SrcReg)) {
59 if (LoongArch::LASX256RegClass.
contains(DstReg, SrcReg)) {
67 if (LoongArch::CFRRegClass.
contains(DstReg) &&
68 LoongArch::GPRRegClass.
contains(SrcReg)) {
74 if (LoongArch::GPRRegClass.
contains(DstReg) &&
75 LoongArch::CFRRegClass.
contains(SrcReg)) {
81 if (LoongArch::CFRRegClass.
contains(DstReg, SrcReg)) {
89 if (LoongArch::FPR32RegClass.
contains(DstReg, SrcReg)) {
90 Opc = LoongArch::FMOV_S;
91 }
else if (LoongArch::FPR64RegClass.
contains(DstReg, SrcReg)) {
92 Opc = LoongArch::FMOV_D;
93 }
else if (LoongArch::GPRRegClass.
contains(DstReg) &&
94 LoongArch::FPR32RegClass.
contains(SrcReg)) {
96 Opc = LoongArch::MOVFR2GR_S;
97 }
else if (LoongArch::GPRRegClass.
contains(DstReg) &&
98 LoongArch::FPR64RegClass.
contains(SrcReg)) {
100 Opc = LoongArch::MOVFR2GR_D;
118 if (LoongArch::GPRRegClass.hasSubClassEq(RC))
119 Opcode =
TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
122 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
123 Opcode = LoongArch::FST_S;
124 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
125 Opcode = LoongArch::FST_D;
126 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC))
127 Opcode = LoongArch::VST;
128 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC))
129 Opcode = LoongArch::XVST;
130 else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
131 Opcode = LoongArch::PseudoST_CFR;
156 if (LoongArch::GPRRegClass.hasSubClassEq(RC))
157 Opcode =
TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
160 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
161 Opcode = LoongArch::FLD_S;
162 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
163 Opcode = LoongArch::FLD_D;
164 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC))
165 Opcode = LoongArch::VLD;
166 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC))
167 Opcode = LoongArch::XVLD;
168 else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
169 Opcode = LoongArch::PseudoLD_CFR;
195 for (
auto &Inst : Seq) {
197 case LoongArch::LU12I_W:
202 case LoongArch::ADDI_W:
204 case LoongArch::LU32I_D:
205 case LoongArch::LU52I_D:
212 assert(
false &&
"Unknown insn emitted by LoongArchMatInt");
221 unsigned Opcode =
MI.getOpcode();
223 if (Opcode == TargetOpcode::INLINEASM ||
224 Opcode == TargetOpcode::INLINEASM_BR) {
227 return getInlineAsmLength(
MI.getOperand(0).getSymbolName(), *MAI);
229 return MI.getDesc().getSize();
234 assert(
MI.getDesc().isBranch() &&
"Unexpected opcode!");
236 return MI.getOperand(
MI.getNumExplicitOperands() - 1).getMBB();
243 "Unknown conditional branch");
248 for (
int i = 0; i < NumOp - 1; i++)
256 bool AllowModify)
const {
262 if (
I ==
MBB.
end() || !isUnpredicatedTerminator(*
I))
268 int NumTerminators = 0;
269 for (
auto J =
I.getReverse(); J !=
MBB.
rend() && isUnpredicatedTerminator(*J);
272 if (J->getDesc().isUnconditionalBranch() ||
273 J->getDesc().isIndirectBranch()) {
280 if (AllowModify && FirstUncondOrIndirectBr !=
MBB.
end()) {
281 while (std::next(FirstUncondOrIndirectBr) !=
MBB.
end()) {
282 std::next(FirstUncondOrIndirectBr)->eraseFromParent();
285 I = FirstUncondOrIndirectBr;
289 if (NumTerminators == 1 &&
I->getDesc().isUnconditionalBranch()) {
295 if (NumTerminators == 1 &&
I->getDesc().isConditionalBranch()) {
301 if (NumTerminators == 2 && std::prev(
I)->getDesc().isConditionalBranch() &&
302 I->getDesc().isUnconditionalBranch()) {
313 int64_t BrOffset)
const {
321 case LoongArch::BLTU:
322 case LoongArch::BGEU:
323 return isInt<18>(BrOffset);
324 case LoongArch::BEQZ:
325 case LoongArch::BNEZ:
326 case LoongArch::BCEQZ:
327 case LoongArch::BCNEZ:
328 return isInt<23>(BrOffset);
330 case LoongArch::PseudoBR:
331 return isInt<28>(BrOffset);
336 int *BytesRemoved)
const {
343 if (!
I->getDesc().isBranch())
349 I->eraseFromParent();
356 if (!
I->getDesc().isConditionalBranch())
362 I->eraseFromParent();
375 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
377 "LoongArch branch conditions have at most two components!");
389 for (
unsigned i = 1; i <
Cond.size(); ++i)
412 assert(RS &&
"RegScavenger required for long branching");
414 "new block should be inserted for expanding unconditional branch");
423 if (!isInt<32>(BrOffset))
425 "Branch offsets outside of the signed 32-bit range not supported");
427 Register ScratchReg =
MRI.createVirtualRegister(&LoongArch::GPRRegClass);
445 LoongArch::GPRRegClass, PCALAU12I.
getIterator(),
false,
447 if (Scav != LoongArch::NoRegister)
452 Scav = LoongArch::R20;
454 if (FrameIndex == -1)
464 TRI->eliminateFrameIndex(RestoreBB.
back(),
467 MRI.replaceRegWith(ScratchReg, Scav);
476 return LoongArch::BNE;
478 return LoongArch::BEQ;
479 case LoongArch::BEQZ:
480 return LoongArch::BNEZ;
481 case LoongArch::BNEZ:
482 return LoongArch::BEQZ;
483 case LoongArch::BCEQZ:
484 return LoongArch::BCNEZ;
485 case LoongArch::BCNEZ:
486 return LoongArch::BCEQZ;
488 return LoongArch::BGE;
490 return LoongArch::BLT;
491 case LoongArch::BLTU:
492 return LoongArch::BGEU;
493 case LoongArch::BGEU:
494 return LoongArch::BLTU;
500 assert((
Cond.size() &&
Cond.size() <= 3) &&
"Invalid branch condition!");
505std::pair<unsigned, unsigned>
507 return std::make_pair(TF, 0u);
512 using namespace LoongArchII;
514 static const std::pair<unsigned, const char *> TargetFlags[] = {
515 {MO_CALL,
"loongarch-call"},
516 {MO_CALL_PLT,
"loongarch-call-plt"},
517 {MO_PCREL_HI,
"loongarch-pcrel-hi"},
518 {MO_PCREL_LO,
"loongarch-pcrel-lo"},
519 {MO_PCREL64_LO,
"loongarch-pcrel64-lo"},
520 {MO_PCREL64_HI,
"loongarch-pcrel64-hi"},
521 {MO_GOT_PC_HI,
"loongarch-got-pc-hi"},
522 {MO_GOT_PC_LO,
"loongarch-got-pc-lo"},
523 {MO_GOT_PC64_LO,
"loongarch-got-pc64-lo"},
524 {MO_GOT_PC64_HI,
"loongarch-got-pc64-hi"},
525 {MO_LE_HI,
"loongarch-le-hi"},
526 {MO_LE_LO,
"loongarch-le-lo"},
527 {MO_LE64_LO,
"loongarch-le64-lo"},
528 {MO_LE64_HI,
"loongarch-le64-hi"},
529 {MO_IE_PC_HI,
"loongarch-ie-pc-hi"},
530 {MO_IE_PC_LO,
"loongarch-ie-pc-lo"},
531 {MO_IE_PC64_LO,
"loongarch-ie-pc64-lo"},
532 {MO_IE_PC64_HI,
"loongarch-ie-pc64-hi"},
533 {MO_LD_PC_HI,
"loongarch-ld-pc-hi"},
534 {MO_GD_PC_HI,
"loongarch-gd-pc-hi"}};
unsigned const MachineRegisterInfo * MRI
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static unsigned getOppositeBranchOpc(unsigned Opcode)
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
const LoongArchSubtarget & STI
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
LoongArchInstrInfo(LoongArchSubtarget &STI)
MCInst getNop() const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
LoongArchMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private Lo...
int getBranchRelaxationSpillFrameIndex()
This class is intended to be used as a base class for asm properties and features specific to the tar...
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Instances of this class represent a single low-level machine instruction.
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Wrapper class representing physical registers. Should be passed by value.
unsigned pred_size() const
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineBasicBlock * getMBB() const
void setMBB(MachineBasicBlock *MBB)
static MachineOperand CreateImm(int64_t Val)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Target - Wrapper for Target specific information.
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
InstSeq generateInstSeq(int64_t Val)
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
unsigned getKillRegState(bool B)
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.