LLVM 19.0.0git
LoongArchInstrInfo.cpp
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1//=- LoongArchInstrInfo.cpp - LoongArch Instruction Information -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the LoongArch implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "LoongArchInstrInfo.h"
14#include "LoongArch.h"
21
22using namespace llvm;
23
24#define GET_INSTRINFO_CTOR_DTOR
25#include "LoongArchGenInstrInfo.inc"
26
28 : LoongArchGenInstrInfo(LoongArch::ADJCALLSTACKDOWN,
29 LoongArch::ADJCALLSTACKUP),
30 STI(STI) {}
31
33 return MCInstBuilder(LoongArch::ANDI)
34 .addReg(LoongArch::R0)
35 .addReg(LoongArch::R0)
36 .addImm(0);
37}
38
41 const DebugLoc &DL, MCRegister DstReg,
42 MCRegister SrcReg, bool KillSrc) const {
43 if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
44 BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg)
45 .addReg(SrcReg, getKillRegState(KillSrc))
46 .addReg(LoongArch::R0);
47 return;
48 }
49
50 // VR->VR copies.
51 if (LoongArch::LSX128RegClass.contains(DstReg, SrcReg)) {
52 BuildMI(MBB, MBBI, DL, get(LoongArch::VORI_B), DstReg)
53 .addReg(SrcReg, getKillRegState(KillSrc))
54 .addImm(0);
55 return;
56 }
57
58 // XR->XR copies.
59 if (LoongArch::LASX256RegClass.contains(DstReg, SrcReg)) {
60 BuildMI(MBB, MBBI, DL, get(LoongArch::XVORI_B), DstReg)
61 .addReg(SrcReg, getKillRegState(KillSrc))
62 .addImm(0);
63 return;
64 }
65
66 // GPR->CFR copy.
67 if (LoongArch::CFRRegClass.contains(DstReg) &&
68 LoongArch::GPRRegClass.contains(SrcReg)) {
69 BuildMI(MBB, MBBI, DL, get(LoongArch::MOVGR2CF), DstReg)
70 .addReg(SrcReg, getKillRegState(KillSrc));
71 return;
72 }
73 // CFR->GPR copy.
74 if (LoongArch::GPRRegClass.contains(DstReg) &&
75 LoongArch::CFRRegClass.contains(SrcReg)) {
76 BuildMI(MBB, MBBI, DL, get(LoongArch::MOVCF2GR), DstReg)
77 .addReg(SrcReg, getKillRegState(KillSrc));
78 return;
79 }
80 // CFR->CFR copy.
81 if (LoongArch::CFRRegClass.contains(DstReg, SrcReg)) {
82 BuildMI(MBB, MBBI, DL, get(LoongArch::PseudoCopyCFR), DstReg)
83 .addReg(SrcReg, getKillRegState(KillSrc));
84 return;
85 }
86
87 // FPR->FPR copies.
88 unsigned Opc;
89 if (LoongArch::FPR32RegClass.contains(DstReg, SrcReg)) {
90 Opc = LoongArch::FMOV_S;
91 } else if (LoongArch::FPR64RegClass.contains(DstReg, SrcReg)) {
92 Opc = LoongArch::FMOV_D;
93 } else if (LoongArch::GPRRegClass.contains(DstReg) &&
94 LoongArch::FPR32RegClass.contains(SrcReg)) {
95 // FPR32 -> GPR copies
96 Opc = LoongArch::MOVFR2GR_S;
97 } else if (LoongArch::GPRRegClass.contains(DstReg) &&
98 LoongArch::FPR64RegClass.contains(SrcReg)) {
99 // FPR64 -> GPR copies
100 Opc = LoongArch::MOVFR2GR_D;
101 } else {
102 // TODO: support other copies.
103 llvm_unreachable("Impossible reg-to-reg copy");
104 }
105
106 BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
107 .addReg(SrcReg, getKillRegState(KillSrc));
108}
109
112 bool IsKill, int FI, const TargetRegisterClass *RC,
113 const TargetRegisterInfo *TRI, Register VReg) const {
115 MachineFrameInfo &MFI = MF->getFrameInfo();
116
117 unsigned Opcode;
118 if (LoongArch::GPRRegClass.hasSubClassEq(RC))
119 Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
120 ? LoongArch::ST_W
121 : LoongArch::ST_D;
122 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
123 Opcode = LoongArch::FST_S;
124 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
125 Opcode = LoongArch::FST_D;
126 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC))
127 Opcode = LoongArch::VST;
128 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC))
129 Opcode = LoongArch::XVST;
130 else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
131 Opcode = LoongArch::PseudoST_CFR;
132 else
133 llvm_unreachable("Can't store this register to stack slot");
134
137 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
138
139 BuildMI(MBB, I, DebugLoc(), get(Opcode))
140 .addReg(SrcReg, getKillRegState(IsKill))
141 .addFrameIndex(FI)
142 .addImm(0)
143 .addMemOperand(MMO);
144}
145
148 Register DstReg, int FI,
149 const TargetRegisterClass *RC,
150 const TargetRegisterInfo *TRI,
151 Register VReg) const {
153 MachineFrameInfo &MFI = MF->getFrameInfo();
154
155 unsigned Opcode;
156 if (LoongArch::GPRRegClass.hasSubClassEq(RC))
157 Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
158 ? LoongArch::LD_W
159 : LoongArch::LD_D;
160 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
161 Opcode = LoongArch::FLD_S;
162 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
163 Opcode = LoongArch::FLD_D;
164 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC))
165 Opcode = LoongArch::VLD;
166 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC))
167 Opcode = LoongArch::XVLD;
168 else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
169 Opcode = LoongArch::PseudoLD_CFR;
170 else
171 llvm_unreachable("Can't load this register from stack slot");
172
175 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
176
177 BuildMI(MBB, I, DebugLoc(), get(Opcode), DstReg)
178 .addFrameIndex(FI)
179 .addImm(0)
180 .addMemOperand(MMO);
181}
182
185 const DebugLoc &DL, Register DstReg,
186 uint64_t Val, MachineInstr::MIFlag Flag) const {
187 Register SrcReg = LoongArch::R0;
188
189 if (!STI.is64Bit() && !isInt<32>(Val))
190 report_fatal_error("Should only materialize 32-bit constants for LA32");
191
192 auto Seq = LoongArchMatInt::generateInstSeq(Val);
193 assert(!Seq.empty());
194
195 for (auto &Inst : Seq) {
196 switch (Inst.Opc) {
197 case LoongArch::LU12I_W:
198 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
199 .addImm(Inst.Imm)
200 .setMIFlag(Flag);
201 break;
202 case LoongArch::ADDI_W:
203 case LoongArch::ORI:
204 case LoongArch::LU32I_D: // "rj" is needed due to InstrInfo pattern
205 case LoongArch::LU52I_D:
206 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
207 .addReg(SrcReg, RegState::Kill)
208 .addImm(Inst.Imm)
209 .setMIFlag(Flag);
210 break;
211 default:
212 assert(false && "Unknown insn emitted by LoongArchMatInt");
213 }
214
215 // Only the first instruction has $zero as its source.
216 SrcReg = DstReg;
217 }
218}
219
221 unsigned Opcode = MI.getOpcode();
222
223 if (Opcode == TargetOpcode::INLINEASM ||
224 Opcode == TargetOpcode::INLINEASM_BR) {
225 const MachineFunction *MF = MI.getParent()->getParent();
226 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
227 return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
228 }
229 return MI.getDesc().getSize();
230}
231
234 assert(MI.getDesc().isBranch() && "Unexpected opcode!");
235 // The branch target is always the last operand.
236 return MI.getOperand(MI.getNumExplicitOperands() - 1).getMBB();
237}
238
241 // Block ends with fall-through condbranch.
242 assert(LastInst.getDesc().isConditionalBranch() &&
243 "Unknown conditional branch");
244 int NumOp = LastInst.getNumExplicitOperands();
245 Target = LastInst.getOperand(NumOp - 1).getMBB();
246
247 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
248 for (int i = 0; i < NumOp - 1; i++)
249 Cond.push_back(LastInst.getOperand(i));
250}
251
254 MachineBasicBlock *&FBB,
256 bool AllowModify) const {
257 TBB = FBB = nullptr;
258 Cond.clear();
259
260 // If the block has no terminators, it just falls into the block after it.
262 if (I == MBB.end() || !isUnpredicatedTerminator(*I))
263 return false;
264
265 // Count the number of terminators and find the first unconditional or
266 // indirect branch.
267 MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
268 int NumTerminators = 0;
269 for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
270 J++) {
271 NumTerminators++;
272 if (J->getDesc().isUnconditionalBranch() ||
273 J->getDesc().isIndirectBranch()) {
274 FirstUncondOrIndirectBr = J.getReverse();
275 }
276 }
277
278 // If AllowModify is true, we can erase any terminators after
279 // FirstUncondOrIndirectBR.
280 if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
281 while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
282 std::next(FirstUncondOrIndirectBr)->eraseFromParent();
283 NumTerminators--;
284 }
285 I = FirstUncondOrIndirectBr;
286 }
287
288 // Handle a single unconditional branch.
289 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
291 return false;
292 }
293
294 // Handle a single conditional branch.
295 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
297 return false;
298 }
299
300 // Handle a conditional branch followed by an unconditional branch.
301 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
302 I->getDesc().isUnconditionalBranch()) {
303 parseCondBranch(*std::prev(I), TBB, Cond);
304 FBB = getBranchDestBlock(*I);
305 return false;
306 }
307
308 // Otherwise, we can't handle this.
309 return true;
310}
311
313 int64_t BrOffset) const {
314 switch (BranchOp) {
315 default:
316 llvm_unreachable("Unknown branch instruction!");
317 case LoongArch::BEQ:
318 case LoongArch::BNE:
319 case LoongArch::BLT:
320 case LoongArch::BGE:
321 case LoongArch::BLTU:
322 case LoongArch::BGEU:
323 return isInt<18>(BrOffset);
324 case LoongArch::BEQZ:
325 case LoongArch::BNEZ:
326 case LoongArch::BCEQZ:
327 case LoongArch::BCNEZ:
328 return isInt<23>(BrOffset);
329 case LoongArch::B:
330 case LoongArch::PseudoBR:
331 return isInt<28>(BrOffset);
332 }
333}
334
336 int *BytesRemoved) const {
337 if (BytesRemoved)
338 *BytesRemoved = 0;
340 if (I == MBB.end())
341 return 0;
342
343 if (!I->getDesc().isBranch())
344 return 0;
345
346 // Remove the branch.
347 if (BytesRemoved)
348 *BytesRemoved += getInstSizeInBytes(*I);
349 I->eraseFromParent();
350
351 I = MBB.end();
352
353 if (I == MBB.begin())
354 return 1;
355 --I;
356 if (!I->getDesc().isConditionalBranch())
357 return 1;
358
359 // Remove the branch.
360 if (BytesRemoved)
361 *BytesRemoved += getInstSizeInBytes(*I);
362 I->eraseFromParent();
363 return 2;
364}
365
366// Inserts a branch into the end of the specific MachineBasicBlock, returning
367// the number of instructions inserted.
370 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
371 if (BytesAdded)
372 *BytesAdded = 0;
373
374 // Shouldn't be a fall through.
375 assert(TBB && "insertBranch must not be told to insert a fallthrough");
376 assert(Cond.size() <= 3 && Cond.size() != 1 &&
377 "LoongArch branch conditions have at most two components!");
378
379 // Unconditional branch.
380 if (Cond.empty()) {
381 MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(TBB);
382 if (BytesAdded)
383 *BytesAdded += getInstSizeInBytes(MI);
384 return 1;
385 }
386
387 // Either a one or two-way conditional branch.
388 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
389 for (unsigned i = 1; i < Cond.size(); ++i)
390 MIB.add(Cond[i]);
391 MIB.addMBB(TBB);
392 if (BytesAdded)
393 *BytesAdded += getInstSizeInBytes(*MIB);
394
395 // One-way conditional branch.
396 if (!FBB)
397 return 1;
398
399 // Two-way conditional branch.
400 MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(FBB);
401 if (BytesAdded)
402 *BytesAdded += getInstSizeInBytes(MI);
403 return 2;
404}
405
407 MachineBasicBlock &DestBB,
408 MachineBasicBlock &RestoreBB,
409 const DebugLoc &DL,
410 int64_t BrOffset,
411 RegScavenger *RS) const {
412 assert(RS && "RegScavenger required for long branching");
413 assert(MBB.empty() &&
414 "new block should be inserted for expanding unconditional branch");
415 assert(MBB.pred_size() == 1);
416
422
423 if (!isInt<32>(BrOffset))
425 "Branch offsets outside of the signed 32-bit range not supported");
426
427 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass);
428 auto II = MBB.end();
429
430 MachineInstr &PCALAU12I =
431 *BuildMI(MBB, II, DL, get(LoongArch::PCALAU12I), ScratchReg)
433 MachineInstr &ADDI =
434 *BuildMI(MBB, II, DL,
435 get(STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W),
436 ScratchReg)
437 .addReg(ScratchReg)
439 BuildMI(MBB, II, DL, get(LoongArch::PseudoBRIND))
440 .addReg(ScratchReg, RegState::Kill)
441 .addImm(0);
442
445 LoongArch::GPRRegClass, PCALAU12I.getIterator(), /*RestoreAfter=*/false,
446 /*SPAdj=*/0, /*AllowSpill=*/false);
447 if (Scav != LoongArch::NoRegister)
448 RS->setRegUsed(Scav);
449 else {
450 // When there is no scavenged register, it needs to specify a register.
451 // Specify t8 register because it won't be used too often.
452 Scav = LoongArch::R20;
453 int FrameIndex = LAFI->getBranchRelaxationSpillFrameIndex();
454 if (FrameIndex == -1)
455 report_fatal_error("The function size is incorrectly estimated.");
456 storeRegToStackSlot(MBB, PCALAU12I, Scav, /*IsKill=*/true, FrameIndex,
457 &LoongArch::GPRRegClass, TRI, Register());
458 TRI->eliminateFrameIndex(std::prev(PCALAU12I.getIterator()),
459 /*SpAdj=*/0, /*FIOperandNum=*/1);
460 PCALAU12I.getOperand(1).setMBB(&RestoreBB);
461 ADDI.getOperand(2).setMBB(&RestoreBB);
462 loadRegFromStackSlot(RestoreBB, RestoreBB.end(), Scav, FrameIndex,
463 &LoongArch::GPRRegClass, TRI, Register());
464 TRI->eliminateFrameIndex(RestoreBB.back(),
465 /*SpAdj=*/0, /*FIOperandNum=*/1);
466 }
467 MRI.replaceRegWith(ScratchReg, Scav);
468 MRI.clearVirtRegs();
469}
470
471static unsigned getOppositeBranchOpc(unsigned Opc) {
472 switch (Opc) {
473 default:
474 llvm_unreachable("Unrecognized conditional branch");
475 case LoongArch::BEQ:
476 return LoongArch::BNE;
477 case LoongArch::BNE:
478 return LoongArch::BEQ;
479 case LoongArch::BEQZ:
480 return LoongArch::BNEZ;
481 case LoongArch::BNEZ:
482 return LoongArch::BEQZ;
483 case LoongArch::BCEQZ:
484 return LoongArch::BCNEZ;
485 case LoongArch::BCNEZ:
486 return LoongArch::BCEQZ;
487 case LoongArch::BLT:
488 return LoongArch::BGE;
489 case LoongArch::BGE:
490 return LoongArch::BLT;
491 case LoongArch::BLTU:
492 return LoongArch::BGEU;
493 case LoongArch::BGEU:
494 return LoongArch::BLTU;
495 }
496}
497
500 assert((Cond.size() && Cond.size() <= 3) && "Invalid branch condition!");
501 Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
502 return false;
503}
504
505std::pair<unsigned, unsigned>
507 return std::make_pair(TF, 0u);
508}
509
512 using namespace LoongArchII;
513 // TODO: Add more target flags.
514 static const std::pair<unsigned, const char *> TargetFlags[] = {
515 {MO_CALL, "loongarch-call"},
516 {MO_CALL_PLT, "loongarch-call-plt"},
517 {MO_PCREL_HI, "loongarch-pcrel-hi"},
518 {MO_PCREL_LO, "loongarch-pcrel-lo"},
519 {MO_PCREL64_LO, "loongarch-pcrel64-lo"},
520 {MO_PCREL64_HI, "loongarch-pcrel64-hi"},
521 {MO_GOT_PC_HI, "loongarch-got-pc-hi"},
522 {MO_GOT_PC_LO, "loongarch-got-pc-lo"},
523 {MO_GOT_PC64_LO, "loongarch-got-pc64-lo"},
524 {MO_GOT_PC64_HI, "loongarch-got-pc64-hi"},
525 {MO_LE_HI, "loongarch-le-hi"},
526 {MO_LE_LO, "loongarch-le-lo"},
527 {MO_LE64_LO, "loongarch-le64-lo"},
528 {MO_LE64_HI, "loongarch-le64-hi"},
529 {MO_IE_PC_HI, "loongarch-ie-pc-hi"},
530 {MO_IE_PC_LO, "loongarch-ie-pc-lo"},
531 {MO_IE_PC64_LO, "loongarch-ie-pc64-lo"},
532 {MO_IE_PC64_HI, "loongarch-ie-pc64-hi"},
533 {MO_LD_PC_HI, "loongarch-ld-pc-hi"},
534 {MO_GD_PC_HI, "loongarch-gd-pc-hi"}};
535 return ArrayRef(TargetFlags);
536}
unsigned const MachineRegisterInfo * MRI
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static unsigned getOppositeBranchOpc(unsigned Opcode)
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
const LoongArchSubtarget & STI
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
LoongArchInstrInfo(LoongArchSubtarget &STI)
MCInst getNop() const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
LoongArchMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private Lo...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:317
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
unsigned pred_size() const
reverse_iterator rend()
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:543
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:540
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:553
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineBasicBlock * getMBB() const
void setMBB(MachineBasicBlock *MBB)
static MachineOperand CreateImm(int64_t Val)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Target - Wrapper for Target specific information.
self_iterator getIterator()
Definition: ilist_node.h:109
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
InstSeq generateInstSeq(int64_t Val)
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
unsigned getKillRegState(bool B)
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.