LLVM 17.0.0git
LoongArchInstrInfo.cpp
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1//=- LoongArchInstrInfo.cpp - LoongArch Instruction Information -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the LoongArch implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "LoongArchInstrInfo.h"
14#include "LoongArch.h"
21
22using namespace llvm;
23
24#define GET_INSTRINFO_CTOR_DTOR
25#include "LoongArchGenInstrInfo.inc"
26
28 : LoongArchGenInstrInfo(LoongArch::ADJCALLSTACKDOWN,
29 LoongArch::ADJCALLSTACKUP),
30 STI(STI) {}
31
33 return MCInstBuilder(LoongArch::ANDI)
34 .addReg(LoongArch::R0)
35 .addReg(LoongArch::R0)
36 .addImm(0);
37}
38
41 const DebugLoc &DL, MCRegister DstReg,
42 MCRegister SrcReg, bool KillSrc) const {
43 if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
44 BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg)
45 .addReg(SrcReg, getKillRegState(KillSrc))
46 .addReg(LoongArch::R0);
47 return;
48 }
49
50 // GPR->CFR copy.
51 if (LoongArch::CFRRegClass.contains(DstReg) &&
52 LoongArch::GPRRegClass.contains(SrcReg)) {
53 BuildMI(MBB, MBBI, DL, get(LoongArch::MOVGR2CF), DstReg)
54 .addReg(SrcReg, getKillRegState(KillSrc));
55 return;
56 }
57 // CFR->GPR copy.
58 if (LoongArch::GPRRegClass.contains(DstReg) &&
59 LoongArch::CFRRegClass.contains(SrcReg)) {
60 BuildMI(MBB, MBBI, DL, get(LoongArch::MOVCF2GR), DstReg)
61 .addReg(SrcReg, getKillRegState(KillSrc));
62 return;
63 }
64
65 // FPR->FPR copies.
66 unsigned Opc;
67 if (LoongArch::FPR32RegClass.contains(DstReg, SrcReg)) {
68 Opc = LoongArch::FMOV_S;
69 } else if (LoongArch::FPR64RegClass.contains(DstReg, SrcReg)) {
70 Opc = LoongArch::FMOV_D;
71 } else {
72 // TODO: support other copies.
73 llvm_unreachable("Impossible reg-to-reg copy");
74 }
75
76 BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
77 .addReg(SrcReg, getKillRegState(KillSrc));
78}
79
82 bool IsKill, int FI, const TargetRegisterClass *RC,
83 const TargetRegisterInfo *TRI, Register VReg) const {
85 if (I != MBB.end())
86 DL = I->getDebugLoc();
88 MachineFrameInfo &MFI = MF->getFrameInfo();
89
90 unsigned Opcode;
91 if (LoongArch::GPRRegClass.hasSubClassEq(RC))
92 Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
93 ? LoongArch::ST_W
94 : LoongArch::ST_D;
95 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
96 Opcode = LoongArch::FST_S;
97 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
98 Opcode = LoongArch::FST_D;
99 else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
100 Opcode = LoongArch::PseudoST_CFR;
101 else
102 llvm_unreachable("Can't store this register to stack slot");
103
106 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
107
108 BuildMI(MBB, I, DL, get(Opcode))
109 .addReg(SrcReg, getKillRegState(IsKill))
110 .addFrameIndex(FI)
111 .addImm(0)
112 .addMemOperand(MMO);
113}
114
117 Register DstReg, int FI,
118 const TargetRegisterClass *RC,
119 const TargetRegisterInfo *TRI,
120 Register VReg) const {
121 DebugLoc DL;
122 if (I != MBB.end())
123 DL = I->getDebugLoc();
125 MachineFrameInfo &MFI = MF->getFrameInfo();
126
127 unsigned Opcode;
128 if (LoongArch::GPRRegClass.hasSubClassEq(RC))
129 Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
130 ? LoongArch::LD_W
131 : LoongArch::LD_D;
132 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
133 Opcode = LoongArch::FLD_S;
134 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
135 Opcode = LoongArch::FLD_D;
136 else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
137 Opcode = LoongArch::PseudoLD_CFR;
138 else
139 llvm_unreachable("Can't load this register from stack slot");
140
143 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
144
145 BuildMI(MBB, I, DL, get(Opcode), DstReg)
146 .addFrameIndex(FI)
147 .addImm(0)
148 .addMemOperand(MMO);
149}
150
153 const DebugLoc &DL, Register DstReg,
154 uint64_t Val, MachineInstr::MIFlag Flag) const {
155 Register SrcReg = LoongArch::R0;
156
157 if (!STI.is64Bit() && !isInt<32>(Val))
158 report_fatal_error("Should only materialize 32-bit constants for LA32");
159
160 auto Seq = LoongArchMatInt::generateInstSeq(Val);
161 assert(!Seq.empty());
162
163 for (auto &Inst : Seq) {
164 switch (Inst.Opc) {
165 case LoongArch::LU12I_W:
166 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
167 .addImm(Inst.Imm)
168 .setMIFlag(Flag);
169 break;
170 case LoongArch::ADDI_W:
171 case LoongArch::ORI:
172 case LoongArch::LU32I_D: // "rj" is needed due to InstrInfo pattern
173 case LoongArch::LU52I_D:
174 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
175 .addReg(SrcReg, RegState::Kill)
176 .addImm(Inst.Imm)
177 .setMIFlag(Flag);
178 break;
179 default:
180 assert(false && "Unknown insn emitted by LoongArchMatInt");
181 }
182
183 // Only the first instruction has $zero as its source.
184 SrcReg = DstReg;
185 }
186}
187
189 unsigned Opcode = MI.getOpcode();
190
191 if (Opcode == TargetOpcode::INLINEASM ||
192 Opcode == TargetOpcode::INLINEASM_BR) {
193 const MachineFunction *MF = MI.getParent()->getParent();
194 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
195 return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
196 }
197 return MI.getDesc().getSize();
198}
199
202 assert(MI.getDesc().isBranch() && "Unexpected opcode!");
203 // The branch target is always the last operand.
204 return MI.getOperand(MI.getNumExplicitOperands() - 1).getMBB();
205}
206
209 // Block ends with fall-through condbranch.
210 assert(LastInst.getDesc().isConditionalBranch() &&
211 "Unknown conditional branch");
212 int NumOp = LastInst.getNumExplicitOperands();
213 Target = LastInst.getOperand(NumOp - 1).getMBB();
214
215 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
216 for (int i = 0; i < NumOp - 1; i++)
217 Cond.push_back(LastInst.getOperand(i));
218}
219
222 MachineBasicBlock *&FBB,
224 bool AllowModify) const {
225 TBB = FBB = nullptr;
226 Cond.clear();
227
228 // If the block has no terminators, it just falls into the block after it.
230 if (I == MBB.end() || !isUnpredicatedTerminator(*I))
231 return false;
232
233 // Count the number of terminators and find the first unconditional or
234 // indirect branch.
235 MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
236 int NumTerminators = 0;
237 for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
238 J++) {
239 NumTerminators++;
240 if (J->getDesc().isUnconditionalBranch() ||
241 J->getDesc().isIndirectBranch()) {
242 FirstUncondOrIndirectBr = J.getReverse();
243 }
244 }
245
246 // If AllowModify is true, we can erase any terminators after
247 // FirstUncondOrIndirectBR.
248 if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
249 while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
250 std::next(FirstUncondOrIndirectBr)->eraseFromParent();
251 NumTerminators--;
252 }
253 I = FirstUncondOrIndirectBr;
254 }
255
256 // Handle a single unconditional branch.
257 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
259 return false;
260 }
261
262 // Handle a single conditional branch.
263 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
265 return false;
266 }
267
268 // Handle a conditional branch followed by an unconditional branch.
269 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
270 I->getDesc().isUnconditionalBranch()) {
271 parseCondBranch(*std::prev(I), TBB, Cond);
272 FBB = getBranchDestBlock(*I);
273 return false;
274 }
275
276 // Otherwise, we can't handle this.
277 return true;
278}
279
281 int64_t BrOffset) const {
282 switch (BranchOp) {
283 default:
284 llvm_unreachable("Unknown branch instruction!");
285 case LoongArch::BEQ:
286 case LoongArch::BNE:
287 case LoongArch::BLT:
288 case LoongArch::BGE:
289 case LoongArch::BLTU:
290 case LoongArch::BGEU:
291 return isInt<18>(BrOffset);
292 case LoongArch::BEQZ:
293 case LoongArch::BNEZ:
294 case LoongArch::BCEQZ:
295 case LoongArch::BCNEZ:
296 return isInt<23>(BrOffset);
297 case LoongArch::B:
298 case LoongArch::PseudoBR:
299 return isInt<28>(BrOffset);
300 }
301}
302
304 int *BytesRemoved) const {
305 if (BytesRemoved)
306 *BytesRemoved = 0;
308 if (I == MBB.end())
309 return 0;
310
311 if (!I->getDesc().isBranch())
312 return 0;
313
314 // Remove the branch.
315 if (BytesRemoved)
316 *BytesRemoved += getInstSizeInBytes(*I);
317 I->eraseFromParent();
318
319 I = MBB.end();
320
321 if (I == MBB.begin())
322 return 1;
323 --I;
324 if (!I->getDesc().isConditionalBranch())
325 return 1;
326
327 // Remove the branch.
328 if (BytesRemoved)
329 *BytesRemoved += getInstSizeInBytes(*I);
330 I->eraseFromParent();
331 return 2;
332}
333
334// Inserts a branch into the end of the specific MachineBasicBlock, returning
335// the number of instructions inserted.
338 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
339 if (BytesAdded)
340 *BytesAdded = 0;
341
342 // Shouldn't be a fall through.
343 assert(TBB && "insertBranch must not be told to insert a fallthrough");
344 assert(Cond.size() <= 3 && Cond.size() != 1 &&
345 "LoongArch branch conditions have at most two components!");
346
347 // Unconditional branch.
348 if (Cond.empty()) {
349 MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(TBB);
350 if (BytesAdded)
351 *BytesAdded += getInstSizeInBytes(MI);
352 return 1;
353 }
354
355 // Either a one or two-way conditional branch.
356 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
357 for (unsigned i = 1; i < Cond.size(); ++i)
358 MIB.add(Cond[i]);
359 MIB.addMBB(TBB);
360 if (BytesAdded)
361 *BytesAdded += getInstSizeInBytes(*MIB);
362
363 // One-way conditional branch.
364 if (!FBB)
365 return 1;
366
367 // Two-way conditional branch.
368 MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(FBB);
369 if (BytesAdded)
370 *BytesAdded += getInstSizeInBytes(MI);
371 return 2;
372}
373
375 MachineBasicBlock &DestBB,
376 MachineBasicBlock &RestoreBB,
377 const DebugLoc &DL,
378 int64_t BrOffset,
379 RegScavenger *RS) const {
380 assert(RS && "RegScavenger required for long branching");
381 assert(MBB.empty() &&
382 "new block should be inserted for expanding unconditional branch");
383 assert(MBB.pred_size() == 1);
384
390
391 if (!isInt<32>(BrOffset))
393 "Branch offsets outside of the signed 32-bit range not supported");
394
395 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass);
396 auto II = MBB.end();
397
398 MachineInstr &PCALAU12I =
399 *BuildMI(MBB, II, DL, get(LoongArch::PCALAU12I), ScratchReg)
401 MachineInstr &ADDI =
402 *BuildMI(MBB, II, DL,
403 get(STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W),
404 ScratchReg)
405 .addReg(ScratchReg)
407 BuildMI(MBB, II, DL, get(LoongArch::PseudoBRIND))
408 .addReg(ScratchReg, RegState::Kill)
409 .addImm(0);
410
413 LoongArch::GPRRegClass, PCALAU12I.getIterator(), /*RestoreAfter=*/false,
414 /*SPAdj=*/0, /*AllowSpill=*/false);
415 if (Scav != LoongArch::NoRegister)
416 RS->setRegUsed(Scav);
417 else {
418 // When there is no scavenged register, it needs to specify a register.
419 // Specify t8 register because it won't be used too often.
420 Scav = LoongArch::R20;
421 int FrameIndex = LAFI->getBranchRelaxationSpillFrameIndex();
422 if (FrameIndex == -1)
423 report_fatal_error("The function size is incorrectly estimated.");
424 storeRegToStackSlot(MBB, PCALAU12I, Scav, /*IsKill=*/true, FrameIndex,
425 &LoongArch::GPRRegClass, TRI, Register());
426 TRI->eliminateFrameIndex(std::prev(PCALAU12I.getIterator()),
427 /*SpAdj=*/0, /*FIOperandNum=*/1);
428 PCALAU12I.getOperand(1).setMBB(&RestoreBB);
429 ADDI.getOperand(2).setMBB(&RestoreBB);
430 loadRegFromStackSlot(RestoreBB, RestoreBB.end(), Scav, FrameIndex,
431 &LoongArch::GPRRegClass, TRI, Register());
432 TRI->eliminateFrameIndex(RestoreBB.back(),
433 /*SpAdj=*/0, /*FIOperandNum=*/1);
434 }
435 MRI.replaceRegWith(ScratchReg, Scav);
436 MRI.clearVirtRegs();
437}
438
439static unsigned getOppositeBranchOpc(unsigned Opc) {
440 switch (Opc) {
441 default:
442 llvm_unreachable("Unrecognized conditional branch");
443 case LoongArch::BEQ:
444 return LoongArch::BNE;
445 case LoongArch::BNE:
446 return LoongArch::BEQ;
447 case LoongArch::BEQZ:
448 return LoongArch::BNEZ;
449 case LoongArch::BNEZ:
450 return LoongArch::BEQZ;
451 case LoongArch::BCEQZ:
452 return LoongArch::BCNEZ;
453 case LoongArch::BCNEZ:
454 return LoongArch::BCEQZ;
455 case LoongArch::BLT:
456 return LoongArch::BGE;
457 case LoongArch::BGE:
458 return LoongArch::BLT;
459 case LoongArch::BLTU:
460 return LoongArch::BGEU;
461 case LoongArch::BGEU:
462 return LoongArch::BLTU;
463 }
464}
465
468 assert((Cond.size() && Cond.size() <= 3) && "Invalid branch condition!");
469 Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
470 return false;
471}
472
473std::pair<unsigned, unsigned>
475 return std::make_pair(TF, 0u);
476}
477
480 using namespace LoongArchII;
481 // TODO: Add more target flags.
482 static const std::pair<unsigned, const char *> TargetFlags[] = {
483 {MO_CALL, "loongarch-call"},
484 {MO_CALL_PLT, "loongarch-call-plt"},
485 {MO_PCREL_HI, "loongarch-pcrel-hi"},
486 {MO_PCREL_LO, "loongarch-pcrel-lo"},
487 {MO_GOT_PC_HI, "loongarch-got-pc-hi"},
488 {MO_GOT_PC_LO, "loongarch-got-pc-lo"},
489 {MO_LE_HI, "loongarch-le-hi"},
490 {MO_LE_LO, "loongarch-le-lo"},
491 {MO_IE_PC_HI, "loongarch-ie-pc-hi"},
492 {MO_IE_PC_LO, "loongarch-ie-pc-lo"},
493 {MO_LD_PC_HI, "loongarch-ld-pc-hi"},
494 {MO_GD_PC_HI, "loongarch-gd-pc-hi"}};
495 return ArrayRef(TargetFlags);
496}
unsigned const MachineRegisterInfo * MRI
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
SmallVector< MachineOperand, 4 > Cond
static unsigned getOppositeBranchOpc(unsigned Opcode)
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:467
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
const LoongArchSubtarget & STI
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
LoongArchInstrInfo(LoongArchSubtarget &STI)
MCInst getNop() const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
LoongArchMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private Lo...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:317
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
unsigned pred_size() const
reverse_iterator rend()
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:513
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineBasicBlock * getMBB() const
void setMBB(MachineBasicBlock *MBB)
static MachineOperand CreateImm(int64_t Val)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Target - Wrapper for Target specific information.
self_iterator getIterator()
Definition: ilist_node.h:82
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
InstSeq generateInstSeq(int64_t Val)
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
unsigned getKillRegState(bool B)
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.