LLVM 18.0.0git
LoongArchInstrInfo.cpp
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1//=- LoongArchInstrInfo.cpp - LoongArch Instruction Information -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the LoongArch implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "LoongArchInstrInfo.h"
14#include "LoongArch.h"
21
22using namespace llvm;
23
24#define GET_INSTRINFO_CTOR_DTOR
25#include "LoongArchGenInstrInfo.inc"
26
28 : LoongArchGenInstrInfo(LoongArch::ADJCALLSTACKDOWN,
29 LoongArch::ADJCALLSTACKUP),
30 STI(STI) {}
31
33 return MCInstBuilder(LoongArch::ANDI)
34 .addReg(LoongArch::R0)
35 .addReg(LoongArch::R0)
36 .addImm(0);
37}
38
41 const DebugLoc &DL, MCRegister DstReg,
42 MCRegister SrcReg, bool KillSrc) const {
43 if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
44 BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg)
45 .addReg(SrcReg, getKillRegState(KillSrc))
46 .addReg(LoongArch::R0);
47 return;
48 }
49
50 // VR->VR copies.
51 if (LoongArch::LSX128RegClass.contains(DstReg, SrcReg)) {
52 BuildMI(MBB, MBBI, DL, get(LoongArch::VORI_B), DstReg)
53 .addReg(SrcReg, getKillRegState(KillSrc))
54 .addImm(0);
55 return;
56 }
57
58 // XR->XR copies.
59 if (LoongArch::LASX256RegClass.contains(DstReg, SrcReg)) {
60 BuildMI(MBB, MBBI, DL, get(LoongArch::XVORI_B), DstReg)
61 .addReg(SrcReg, getKillRegState(KillSrc))
62 .addImm(0);
63 return;
64 }
65
66 // GPR->CFR copy.
67 if (LoongArch::CFRRegClass.contains(DstReg) &&
68 LoongArch::GPRRegClass.contains(SrcReg)) {
69 BuildMI(MBB, MBBI, DL, get(LoongArch::MOVGR2CF), DstReg)
70 .addReg(SrcReg, getKillRegState(KillSrc));
71 return;
72 }
73 // CFR->GPR copy.
74 if (LoongArch::GPRRegClass.contains(DstReg) &&
75 LoongArch::CFRRegClass.contains(SrcReg)) {
76 BuildMI(MBB, MBBI, DL, get(LoongArch::MOVCF2GR), DstReg)
77 .addReg(SrcReg, getKillRegState(KillSrc));
78 return;
79 }
80
81 // FPR->FPR copies.
82 unsigned Opc;
83 if (LoongArch::FPR32RegClass.contains(DstReg, SrcReg)) {
84 Opc = LoongArch::FMOV_S;
85 } else if (LoongArch::FPR64RegClass.contains(DstReg, SrcReg)) {
86 Opc = LoongArch::FMOV_D;
87 } else {
88 // TODO: support other copies.
89 llvm_unreachable("Impossible reg-to-reg copy");
90 }
91
92 BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
93 .addReg(SrcReg, getKillRegState(KillSrc));
94}
95
98 bool IsKill, int FI, const TargetRegisterClass *RC,
99 const TargetRegisterInfo *TRI, Register VReg) const {
101 MachineFrameInfo &MFI = MF->getFrameInfo();
102
103 unsigned Opcode;
104 if (LoongArch::GPRRegClass.hasSubClassEq(RC))
105 Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
106 ? LoongArch::ST_W
107 : LoongArch::ST_D;
108 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
109 Opcode = LoongArch::FST_S;
110 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
111 Opcode = LoongArch::FST_D;
112 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC))
113 Opcode = LoongArch::VST;
114 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC))
115 Opcode = LoongArch::XVST;
116 else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
117 Opcode = LoongArch::PseudoST_CFR;
118 else
119 llvm_unreachable("Can't store this register to stack slot");
120
123 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
124
125 BuildMI(MBB, I, DebugLoc(), get(Opcode))
126 .addReg(SrcReg, getKillRegState(IsKill))
127 .addFrameIndex(FI)
128 .addImm(0)
129 .addMemOperand(MMO);
130}
131
134 Register DstReg, int FI,
135 const TargetRegisterClass *RC,
136 const TargetRegisterInfo *TRI,
137 Register VReg) const {
139 MachineFrameInfo &MFI = MF->getFrameInfo();
140
141 unsigned Opcode;
142 if (LoongArch::GPRRegClass.hasSubClassEq(RC))
143 Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
144 ? LoongArch::LD_W
145 : LoongArch::LD_D;
146 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
147 Opcode = LoongArch::FLD_S;
148 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
149 Opcode = LoongArch::FLD_D;
150 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC))
151 Opcode = LoongArch::VLD;
152 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC))
153 Opcode = LoongArch::XVLD;
154 else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
155 Opcode = LoongArch::PseudoLD_CFR;
156 else
157 llvm_unreachable("Can't load this register from stack slot");
158
161 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
162
163 BuildMI(MBB, I, DebugLoc(), get(Opcode), DstReg)
164 .addFrameIndex(FI)
165 .addImm(0)
166 .addMemOperand(MMO);
167}
168
171 const DebugLoc &DL, Register DstReg,
172 uint64_t Val, MachineInstr::MIFlag Flag) const {
173 Register SrcReg = LoongArch::R0;
174
175 if (!STI.is64Bit() && !isInt<32>(Val))
176 report_fatal_error("Should only materialize 32-bit constants for LA32");
177
178 auto Seq = LoongArchMatInt::generateInstSeq(Val);
179 assert(!Seq.empty());
180
181 for (auto &Inst : Seq) {
182 switch (Inst.Opc) {
183 case LoongArch::LU12I_W:
184 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
185 .addImm(Inst.Imm)
186 .setMIFlag(Flag);
187 break;
188 case LoongArch::ADDI_W:
189 case LoongArch::ORI:
190 case LoongArch::LU32I_D: // "rj" is needed due to InstrInfo pattern
191 case LoongArch::LU52I_D:
192 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
193 .addReg(SrcReg, RegState::Kill)
194 .addImm(Inst.Imm)
195 .setMIFlag(Flag);
196 break;
197 default:
198 assert(false && "Unknown insn emitted by LoongArchMatInt");
199 }
200
201 // Only the first instruction has $zero as its source.
202 SrcReg = DstReg;
203 }
204}
205
207 unsigned Opcode = MI.getOpcode();
208
209 if (Opcode == TargetOpcode::INLINEASM ||
210 Opcode == TargetOpcode::INLINEASM_BR) {
211 const MachineFunction *MF = MI.getParent()->getParent();
212 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
213 return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
214 }
215 return MI.getDesc().getSize();
216}
217
220 assert(MI.getDesc().isBranch() && "Unexpected opcode!");
221 // The branch target is always the last operand.
222 return MI.getOperand(MI.getNumExplicitOperands() - 1).getMBB();
223}
224
227 // Block ends with fall-through condbranch.
228 assert(LastInst.getDesc().isConditionalBranch() &&
229 "Unknown conditional branch");
230 int NumOp = LastInst.getNumExplicitOperands();
231 Target = LastInst.getOperand(NumOp - 1).getMBB();
232
233 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
234 for (int i = 0; i < NumOp - 1; i++)
235 Cond.push_back(LastInst.getOperand(i));
236}
237
240 MachineBasicBlock *&FBB,
242 bool AllowModify) const {
243 TBB = FBB = nullptr;
244 Cond.clear();
245
246 // If the block has no terminators, it just falls into the block after it.
248 if (I == MBB.end() || !isUnpredicatedTerminator(*I))
249 return false;
250
251 // Count the number of terminators and find the first unconditional or
252 // indirect branch.
253 MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
254 int NumTerminators = 0;
255 for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
256 J++) {
257 NumTerminators++;
258 if (J->getDesc().isUnconditionalBranch() ||
259 J->getDesc().isIndirectBranch()) {
260 FirstUncondOrIndirectBr = J.getReverse();
261 }
262 }
263
264 // If AllowModify is true, we can erase any terminators after
265 // FirstUncondOrIndirectBR.
266 if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
267 while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
268 std::next(FirstUncondOrIndirectBr)->eraseFromParent();
269 NumTerminators--;
270 }
271 I = FirstUncondOrIndirectBr;
272 }
273
274 // Handle a single unconditional branch.
275 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
277 return false;
278 }
279
280 // Handle a single conditional branch.
281 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
283 return false;
284 }
285
286 // Handle a conditional branch followed by an unconditional branch.
287 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
288 I->getDesc().isUnconditionalBranch()) {
289 parseCondBranch(*std::prev(I), TBB, Cond);
290 FBB = getBranchDestBlock(*I);
291 return false;
292 }
293
294 // Otherwise, we can't handle this.
295 return true;
296}
297
299 int64_t BrOffset) const {
300 switch (BranchOp) {
301 default:
302 llvm_unreachable("Unknown branch instruction!");
303 case LoongArch::BEQ:
304 case LoongArch::BNE:
305 case LoongArch::BLT:
306 case LoongArch::BGE:
307 case LoongArch::BLTU:
308 case LoongArch::BGEU:
309 return isInt<18>(BrOffset);
310 case LoongArch::BEQZ:
311 case LoongArch::BNEZ:
312 case LoongArch::BCEQZ:
313 case LoongArch::BCNEZ:
314 return isInt<23>(BrOffset);
315 case LoongArch::B:
316 case LoongArch::PseudoBR:
317 return isInt<28>(BrOffset);
318 }
319}
320
322 int *BytesRemoved) const {
323 if (BytesRemoved)
324 *BytesRemoved = 0;
326 if (I == MBB.end())
327 return 0;
328
329 if (!I->getDesc().isBranch())
330 return 0;
331
332 // Remove the branch.
333 if (BytesRemoved)
334 *BytesRemoved += getInstSizeInBytes(*I);
335 I->eraseFromParent();
336
337 I = MBB.end();
338
339 if (I == MBB.begin())
340 return 1;
341 --I;
342 if (!I->getDesc().isConditionalBranch())
343 return 1;
344
345 // Remove the branch.
346 if (BytesRemoved)
347 *BytesRemoved += getInstSizeInBytes(*I);
348 I->eraseFromParent();
349 return 2;
350}
351
352// Inserts a branch into the end of the specific MachineBasicBlock, returning
353// the number of instructions inserted.
356 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
357 if (BytesAdded)
358 *BytesAdded = 0;
359
360 // Shouldn't be a fall through.
361 assert(TBB && "insertBranch must not be told to insert a fallthrough");
362 assert(Cond.size() <= 3 && Cond.size() != 1 &&
363 "LoongArch branch conditions have at most two components!");
364
365 // Unconditional branch.
366 if (Cond.empty()) {
367 MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(TBB);
368 if (BytesAdded)
369 *BytesAdded += getInstSizeInBytes(MI);
370 return 1;
371 }
372
373 // Either a one or two-way conditional branch.
374 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
375 for (unsigned i = 1; i < Cond.size(); ++i)
376 MIB.add(Cond[i]);
377 MIB.addMBB(TBB);
378 if (BytesAdded)
379 *BytesAdded += getInstSizeInBytes(*MIB);
380
381 // One-way conditional branch.
382 if (!FBB)
383 return 1;
384
385 // Two-way conditional branch.
386 MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(FBB);
387 if (BytesAdded)
388 *BytesAdded += getInstSizeInBytes(MI);
389 return 2;
390}
391
393 MachineBasicBlock &DestBB,
394 MachineBasicBlock &RestoreBB,
395 const DebugLoc &DL,
396 int64_t BrOffset,
397 RegScavenger *RS) const {
398 assert(RS && "RegScavenger required for long branching");
399 assert(MBB.empty() &&
400 "new block should be inserted for expanding unconditional branch");
401 assert(MBB.pred_size() == 1);
402
408
409 if (!isInt<32>(BrOffset))
411 "Branch offsets outside of the signed 32-bit range not supported");
412
413 Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass);
414 auto II = MBB.end();
415
416 MachineInstr &PCALAU12I =
417 *BuildMI(MBB, II, DL, get(LoongArch::PCALAU12I), ScratchReg)
419 MachineInstr &ADDI =
420 *BuildMI(MBB, II, DL,
421 get(STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W),
422 ScratchReg)
423 .addReg(ScratchReg)
425 BuildMI(MBB, II, DL, get(LoongArch::PseudoBRIND))
426 .addReg(ScratchReg, RegState::Kill)
427 .addImm(0);
428
431 LoongArch::GPRRegClass, PCALAU12I.getIterator(), /*RestoreAfter=*/false,
432 /*SPAdj=*/0, /*AllowSpill=*/false);
433 if (Scav != LoongArch::NoRegister)
434 RS->setRegUsed(Scav);
435 else {
436 // When there is no scavenged register, it needs to specify a register.
437 // Specify t8 register because it won't be used too often.
438 Scav = LoongArch::R20;
439 int FrameIndex = LAFI->getBranchRelaxationSpillFrameIndex();
440 if (FrameIndex == -1)
441 report_fatal_error("The function size is incorrectly estimated.");
442 storeRegToStackSlot(MBB, PCALAU12I, Scav, /*IsKill=*/true, FrameIndex,
443 &LoongArch::GPRRegClass, TRI, Register());
444 TRI->eliminateFrameIndex(std::prev(PCALAU12I.getIterator()),
445 /*SpAdj=*/0, /*FIOperandNum=*/1);
446 PCALAU12I.getOperand(1).setMBB(&RestoreBB);
447 ADDI.getOperand(2).setMBB(&RestoreBB);
448 loadRegFromStackSlot(RestoreBB, RestoreBB.end(), Scav, FrameIndex,
449 &LoongArch::GPRRegClass, TRI, Register());
450 TRI->eliminateFrameIndex(RestoreBB.back(),
451 /*SpAdj=*/0, /*FIOperandNum=*/1);
452 }
453 MRI.replaceRegWith(ScratchReg, Scav);
454 MRI.clearVirtRegs();
455}
456
457static unsigned getOppositeBranchOpc(unsigned Opc) {
458 switch (Opc) {
459 default:
460 llvm_unreachable("Unrecognized conditional branch");
461 case LoongArch::BEQ:
462 return LoongArch::BNE;
463 case LoongArch::BNE:
464 return LoongArch::BEQ;
465 case LoongArch::BEQZ:
466 return LoongArch::BNEZ;
467 case LoongArch::BNEZ:
468 return LoongArch::BEQZ;
469 case LoongArch::BCEQZ:
470 return LoongArch::BCNEZ;
471 case LoongArch::BCNEZ:
472 return LoongArch::BCEQZ;
473 case LoongArch::BLT:
474 return LoongArch::BGE;
475 case LoongArch::BGE:
476 return LoongArch::BLT;
477 case LoongArch::BLTU:
478 return LoongArch::BGEU;
479 case LoongArch::BGEU:
480 return LoongArch::BLTU;
481 }
482}
483
486 assert((Cond.size() && Cond.size() <= 3) && "Invalid branch condition!");
487 Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
488 return false;
489}
490
491std::pair<unsigned, unsigned>
493 return std::make_pair(TF, 0u);
494}
495
498 using namespace LoongArchII;
499 // TODO: Add more target flags.
500 static const std::pair<unsigned, const char *> TargetFlags[] = {
501 {MO_CALL, "loongarch-call"},
502 {MO_CALL_PLT, "loongarch-call-plt"},
503 {MO_PCREL_HI, "loongarch-pcrel-hi"},
504 {MO_PCREL_LO, "loongarch-pcrel-lo"},
505 {MO_PCREL64_LO, "loongarch-pcrel64-lo"},
506 {MO_PCREL64_HI, "loongarch-pcrel64-hi"},
507 {MO_GOT_PC_HI, "loongarch-got-pc-hi"},
508 {MO_GOT_PC_LO, "loongarch-got-pc-lo"},
509 {MO_GOT_PC64_LO, "loongarch-got-pc64-lo"},
510 {MO_GOT_PC64_HI, "loongarch-got-pc64-hi"},
511 {MO_LE_HI, "loongarch-le-hi"},
512 {MO_LE_LO, "loongarch-le-lo"},
513 {MO_LE64_LO, "loongarch-le64-lo"},
514 {MO_LE64_HI, "loongarch-le64-hi"},
515 {MO_IE_PC_HI, "loongarch-ie-pc-hi"},
516 {MO_IE_PC_LO, "loongarch-ie-pc-lo"},
517 {MO_IE_PC64_LO, "loongarch-ie-pc64-lo"},
518 {MO_IE_PC64_HI, "loongarch-ie-pc64-hi"},
519 {MO_LD_PC_HI, "loongarch-ld-pc-hi"},
520 {MO_GD_PC_HI, "loongarch-gd-pc-hi"}};
521 return ArrayRef(TargetFlags);
522}
unsigned const MachineRegisterInfo * MRI
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static unsigned getOppositeBranchOpc(unsigned Opcode)
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:470
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
const LoongArchSubtarget & STI
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
LoongArchInstrInfo(LoongArchSubtarget &STI)
MCInst getNop() const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
LoongArchMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private Lo...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:317
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
unsigned pred_size() const
reverse_iterator rend()
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:543
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:540
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:553
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineBasicBlock * getMBB() const
void setMBB(MachineBasicBlock *MBB)
static MachineOperand CreateImm(int64_t Val)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Target - Wrapper for Target specific information.
self_iterator getIterator()
Definition: ilist_node.h:82
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
InstSeq generateInstSeq(int64_t Val)
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
unsigned getKillRegState(bool B)
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.