LLVM  14.0.0git
MCTargetAsmParser.h
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1 //===- llvm/MC/MCTargetAsmParser.h - Target Assembly Parser -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_MC_MCPARSER_MCTARGETASMPARSER_H
10 #define LLVM_MC_MCPARSER_MCTARGETASMPARSER_H
11 
12 #include "llvm/ADT/StringRef.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/Support/SMLoc.h"
21 #include <cstdint>
22 #include <memory>
23 
24 namespace llvm {
25 
26 class MCInst;
27 class MCStreamer;
28 class MCSubtargetInfo;
29 template <typename T> class SmallVectorImpl;
30 
32 
34  AOK_Align, // Rewrite align as .align.
35  AOK_EVEN, // Rewrite even as .even.
36  AOK_Emit, // Rewrite _emit as .byte.
37  AOK_CallInput, // Rewrite in terms of ${N:P}.
38  AOK_Input, // Rewrite in terms of $N.
39  AOK_Output, // Rewrite in terms of $N.
40  AOK_SizeDirective, // Add a sizing directive (e.g., dword ptr).
41  AOK_Label, // Rewrite local labels.
42  AOK_EndOfStatement, // Add EndOfStatement (e.g., "\n\t").
43  AOK_Skip, // Skip emission (e.g., offset/type operators).
44  AOK_IntelExpr // SizeDirective SymDisp [BaseReg + IndexReg * Scale + ImmDisp]
45 };
46 
47 const char AsmRewritePrecedence [] = {
48  2, // AOK_Align
49  2, // AOK_EVEN
50  2, // AOK_Emit
51  3, // AOK_Input
52  3, // AOK_CallInput
53  3, // AOK_Output
54  5, // AOK_SizeDirective
55  1, // AOK_Label
56  5, // AOK_EndOfStatement
57  2, // AOK_Skip
58  2 // AOK_IntelExpr
59 };
60 
61 // Represnt the various parts which makes up an intel expression,
62 // used for emitting compound intel expressions
63 struct IntelExpr {
64  bool NeedBracs;
65  int64_t Imm;
69  unsigned Scale;
70 
73  OffsetName(StringRef()), Scale(1) {}
74  // [BaseReg + IndexReg * ScaleExpression + OFFSET name + ImmediateExpression]
75  IntelExpr(StringRef baseReg, StringRef indexReg, unsigned scale,
76  StringRef offsetName, int64_t imm, bool needBracs)
77  : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg),
78  OffsetName(offsetName), Scale(1) {
79  if (scale)
80  Scale = scale;
81  }
82  bool hasBaseReg() const { return !BaseReg.empty(); }
83  bool hasIndexReg() const { return !IndexReg.empty(); }
84  bool hasRegs() const { return hasBaseReg() || hasIndexReg(); }
85  bool hasOffset() const { return !OffsetName.empty(); }
86  // Normally we won't emit immediates unconditionally,
87  // unless we've got no other components
88  bool emitImm() const { return !(hasRegs() || hasOffset()); }
89  bool isValid() const {
90  return (Scale == 1) ||
91  (hasIndexReg() && (Scale == 2 || Scale == 4 || Scale == 8));
92  }
93 };
94 
95 struct AsmRewrite {
98  unsigned Len;
99  bool Done;
100  int64_t Val;
103 
104 public:
105  AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len = 0, int64_t val = 0)
106  : Kind(kind), Loc(loc), Len(len), Done(false), Val(val) {}
107  AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len, StringRef label)
108  : AsmRewrite(kind, loc, len) { Label = label; }
109  AsmRewrite(SMLoc loc, unsigned len, IntelExpr exp)
110  : AsmRewrite(AOK_IntelExpr, loc, len) { IntelExp = exp; }
111 };
112 
115 
116  ParseInstructionInfo() = default;
118  : AsmRewrites(rewrites) {}
119 };
120 
122  MatchOperand_Success, // operand matched successfully
123  MatchOperand_NoMatch, // operand did not match
124  MatchOperand_ParseFail // operand matched but had errors
125 };
126 
128  Match,
129  NearMatch,
130  NoMatch,
131 };
132 
133 // When an operand is parsed, the assembler will try to iterate through a set of
134 // possible operand classes that the operand might match and call the
135 // corresponding PredicateMethod to determine that.
136 //
137 // If there are two AsmOperands that would give a specific diagnostic if there
138 // is no match, there is currently no mechanism to distinguish which operand is
139 // a closer match. The DiagnosticPredicate distinguishes between 'completely
140 // no match' and 'near match', so the assembler can decide whether to give a
141 // specific diagnostic, or use 'InvalidOperand' and continue to find a
142 // 'better matching' diagnostic.
143 //
144 // For example:
145 // opcode opnd0, onpd1, opnd2
146 //
147 // where:
148 // opnd2 could be an 'immediate of range [-8, 7]'
149 // opnd2 could be a 'register + shift/extend'.
150 //
151 // If opnd2 is a valid register, but with a wrong shift/extend suffix, it makes
152 // little sense to give a diagnostic that the operand should be an immediate
153 // in range [-8, 7].
154 //
155 // This is a light-weight alternative to the 'NearMissInfo' approach
156 // below which collects *all* possible diagnostics. This alternative
157 // is optional and fully backward compatible with existing
158 // PredicateMethods that return a 'bool' (match or no match).
161 
162  explicit DiagnosticPredicate(bool Match)
166  DiagnosticPredicate(const DiagnosticPredicate &) = default;
168 
169  operator bool() const { return Type == DiagnosticPredicateTy::Match; }
170  bool isMatch() const { return Type == DiagnosticPredicateTy::Match; }
172  bool isNoMatch() const { return Type == DiagnosticPredicateTy::NoMatch; }
173 };
174 
175 // When matching of an assembly instruction fails, there may be multiple
176 // encodings that are close to being a match. It's often ambiguous which one
177 // the programmer intended to use, so we want to report an error which mentions
178 // each of these "near-miss" encodings. This struct contains information about
179 // one such encoding, and why it did not match the parsed instruction.
181 public:
188  };
189 
190  // The encoding is valid for the parsed assembly string. This is only used
191  // internally to the table-generated assembly matcher.
192  static NearMissInfo getSuccess() { return NearMissInfo(); }
193 
194  // The instruction encoding is not valid because it requires some target
195  // features that are not currently enabled. MissingFeatures has a bit set for
196  // each feature that the encoding needs but which is not enabled.
197  static NearMissInfo getMissedFeature(const FeatureBitset &MissingFeatures) {
198  NearMissInfo Result;
199  Result.Kind = NearMissFeature;
200  Result.Features = MissingFeatures;
201  return Result;
202  }
203 
204  // The instruction encoding is not valid because the target-specific
205  // predicate function returned an error code. FailureCode is the
206  // target-specific error code returned by the predicate.
207  static NearMissInfo getMissedPredicate(unsigned FailureCode) {
208  NearMissInfo Result;
209  Result.Kind = NearMissPredicate;
210  Result.PredicateError = FailureCode;
211  return Result;
212  }
213 
214  // The instruction encoding is not valid because one (and only one) parsed
215  // operand is not of the correct type. OperandError is the error code
216  // relating to the operand class expected by the encoding. OperandClass is
217  // the type of the expected operand. Opcode is the opcode of the encoding.
218  // OperandIndex is the index into the parsed operand list.
219  static NearMissInfo getMissedOperand(unsigned OperandError,
220  unsigned OperandClass, unsigned Opcode,
221  unsigned OperandIndex) {
222  NearMissInfo Result;
223  Result.Kind = NearMissOperand;
224  Result.MissedOperand.Error = OperandError;
225  Result.MissedOperand.Class = OperandClass;
226  Result.MissedOperand.Opcode = Opcode;
227  Result.MissedOperand.Index = OperandIndex;
228  return Result;
229  }
230 
231  // The instruction encoding is not valid because it expects more operands
232  // than were parsed. OperandClass is the class of the expected operand that
233  // was not provided. Opcode is the instruction encoding.
234  static NearMissInfo getTooFewOperands(unsigned OperandClass,
235  unsigned Opcode) {
236  NearMissInfo Result;
237  Result.Kind = NearMissTooFewOperands;
238  Result.TooFewOperands.Class = OperandClass;
239  Result.TooFewOperands.Opcode = Opcode;
240  return Result;
241  }
242 
243  operator bool() const { return Kind != NoNearMiss; }
244 
245  NearMissKind getKind() const { return Kind; }
246 
247  // Feature flags required by the instruction, that the current target does
248  // not have.
249  const FeatureBitset& getFeatures() const {
250  assert(Kind == NearMissFeature);
251  return Features;
252  }
253  // Error code returned by the target predicate when validating this
254  // instruction encoding.
255  unsigned getPredicateError() const {
256  assert(Kind == NearMissPredicate);
257  return PredicateError;
258  }
259  // MatchClassKind of the operand that we expected to see.
260  unsigned getOperandClass() const {
261  assert(Kind == NearMissOperand || Kind == NearMissTooFewOperands);
262  return MissedOperand.Class;
263  }
264  // Opcode of the encoding we were trying to match.
265  unsigned getOpcode() const {
266  assert(Kind == NearMissOperand || Kind == NearMissTooFewOperands);
267  return MissedOperand.Opcode;
268  }
269  // Error code returned when validating the operand.
270  unsigned getOperandError() const {
271  assert(Kind == NearMissOperand);
272  return MissedOperand.Error;
273  }
274  // Index of the actual operand we were trying to match in the list of parsed
275  // operands.
276  unsigned getOperandIndex() const {
277  assert(Kind == NearMissOperand);
278  return MissedOperand.Index;
279  }
280 
281 private:
282  NearMissKind Kind;
283 
284  // These two structs share a common prefix, so we can safely rely on the fact
285  // that they overlap in the union.
286  struct MissedOpInfo {
287  unsigned Class;
288  unsigned Opcode;
289  unsigned Error;
290  unsigned Index;
291  };
292 
293  struct TooFewOperandsInfo {
294  unsigned Class;
295  unsigned Opcode;
296  };
297 
298  union {
300  unsigned PredicateError;
301  MissedOpInfo MissedOperand;
302  TooFewOperandsInfo TooFewOperands;
303  };
304 
305  NearMissInfo() : Kind(NoNearMiss) {}
306 };
307 
308 /// MCTargetAsmParser - Generic interface to target specific assembly parsers.
310 public:
319  };
320 
321 protected: // Can only create subclasses.
323  const MCInstrInfo &MII);
324 
325  /// Create a copy of STI and return a non-const reference to it.
327 
328  /// AvailableFeatures - The current set of available features.
330 
331  /// ParsingMSInlineAsm - Are we parsing ms-style inline assembly?
332  bool ParsingMSInlineAsm = false;
333 
334  /// SemaCallback - The Sema callback implementation. Must be set when parsing
335  /// ms-style inline assembly.
337 
338  /// Set of options which affects instrumentation of inline assembly.
340 
341  /// Current STI.
343 
344  const MCInstrInfo &MII;
345 
346 public:
347  MCTargetAsmParser(const MCTargetAsmParser &) = delete;
348  MCTargetAsmParser &operator=(const MCTargetAsmParser &) = delete;
349 
350  ~MCTargetAsmParser() override;
351 
352  const MCSubtargetInfo &getSTI() const;
353 
355  return AvailableFeatures;
356  }
359  }
360 
363 
365 
367  SemaCallback = Callback;
368  }
369 
370  // Target-specific parsing of expression.
371  virtual bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
372  return getParser().parsePrimaryExpr(Res, EndLoc, nullptr);
373  }
374 
375  virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
376  SMLoc &EndLoc) = 0;
377 
378  /// tryParseRegister - parse one register if possible
379  ///
380  /// Check whether a register specification can be parsed at the current
381  /// location, without failing the entire parse if it can't. Must not consume
382  /// tokens if the parse fails.
383  virtual OperandMatchResultTy
384  tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) = 0;
385 
386  /// ParseInstruction - Parse one assembly instruction.
387  ///
388  /// The parser is positioned following the instruction name. The target
389  /// specific instruction parser should parse the entire instruction and
390  /// construct the appropriate MCInst, or emit an error. On success, the entire
391  /// line should be parsed up to and including the end-of-statement token. On
392  /// failure, the parser is not required to read to the end of the line.
393  //
394  /// \param Name - The instruction name.
395  /// \param NameLoc - The source location of the name.
396  /// \param Operands [out] - The list of parsed operands, this returns
397  /// ownership of them to the caller.
398  /// \return True on failure.
400  SMLoc NameLoc, OperandVector &Operands) = 0;
402  AsmToken Token, OperandVector &Operands) {
403  return ParseInstruction(Info, Name, Token.getLoc(), Operands);
404  }
405 
406  /// ParseDirective - Parse a target specific assembler directive
407  ///
408  /// The parser is positioned following the directive name. The target
409  /// specific directive parser should parse the entire directive doing or
410  /// recording any target specific work, or return true and do nothing if the
411  /// directive is not target specific. If the directive is specific for
412  /// the target, the entire line is parsed up to and including the
413  /// end-of-statement token and false is returned.
414  ///
415  /// \param DirectiveID - the identifier token of the directive.
416  virtual bool ParseDirective(AsmToken DirectiveID) = 0;
417 
418  /// MatchAndEmitInstruction - Recognize a series of operands of a parsed
419  /// instruction as an actual MCInst and emit it to the specified MCStreamer.
420  /// This returns false on success and returns true on failure to match.
421  ///
422  /// On failure, the target parser is responsible for emitting a diagnostic
423  /// explaining the match failure.
424  virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
426  uint64_t &ErrorInfo,
427  bool MatchingInlineAsm) = 0;
428 
429  /// Allows targets to let registers opt out of clobber lists.
430  virtual bool OmitRegisterFromClobberLists(unsigned RegNo) { return false; }
431 
432  /// Allow a target to add special case operand matching for things that
433  /// tblgen doesn't/can't handle effectively. For example, literal
434  /// immediates on ARM. TableGen expects a token operand, but the parser
435  /// will recognize them as immediates.
437  unsigned Kind) {
438  return Match_InvalidOperand;
439  }
440 
441  /// Validate the instruction match against any complex target predicates
442  /// before rendering any operands to it.
443  virtual unsigned
445  return Match_Success;
446  }
447 
448  /// checkTargetMatchPredicate - Validate the instruction match against
449  /// any complex target predicates not expressible via match classes.
450  virtual unsigned checkTargetMatchPredicate(MCInst &Inst) {
451  return Match_Success;
452  }
453 
454  virtual void convertToMapAndConstraints(unsigned Kind,
455  const OperandVector &Operands) = 0;
456 
457  /// Returns whether two registers are equal and is used by the tied-operands
458  /// checks in the AsmMatcher. This method can be overridden allow e.g. a
459  /// sub- or super-register as the tied operand.
460  virtual bool regsEqual(const MCParsedAsmOperand &Op1,
461  const MCParsedAsmOperand &Op2) const {
462  assert(Op1.isReg() && Op2.isReg() && "Operands not all regs");
463  return Op1.getReg() == Op2.getReg();
464  }
465 
466  // Return whether this parser uses assignment statements with equals tokens
467  virtual bool equalIsAsmAssignment() { return true; };
468  // Return whether this start of statement identifier is a label
469  virtual bool isLabel(AsmToken &Token) { return true; };
470  // Return whether this parser accept star as start of statement
471  virtual bool starIsStartOfStatement() { return false; };
472 
473  virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
475  MCContext &Ctx) {
476  return nullptr;
477  }
478 
479  // For actions that have to be performed before a label is emitted
481 
482  virtual void onLabelParsed(MCSymbol *Symbol) {}
483 
484  /// Ensure that all previously parsed instructions have been emitted to the
485  /// output streamer, if the target does not emit them immediately.
486  virtual void flushPendingInstructions(MCStreamer &Out) {}
487 
488  virtual const MCExpr *createTargetUnaryExpr(const MCExpr *E,
489  AsmToken::TokenKind OperatorToken,
490  MCContext &Ctx) {
491  return nullptr;
492  }
493 
494  // For any initialization at the beginning of parsing.
495  virtual void onBeginOfFile() {}
496 
497  // For any checks or cleanups at the end of parsing.
498  virtual void onEndOfFile() {}
499 };
500 
501 } // end namespace llvm
502 
503 #endif // LLVM_MC_MCPARSER_MCTARGETASMPARSER_H
llvm::MCAsmParserSemaCallback
Generic Sema callback for assembly parser.
Definition: MCAsmParser.h:109
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::NearMissInfo::PredicateError
unsigned PredicateError
Definition: MCTargetAsmParser.h:300
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::IntelExpr::BaseReg
StringRef BaseReg
Definition: MCTargetAsmParser.h:66
llvm::AsmRewrite::AsmRewrite
AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len, StringRef label)
Definition: MCTargetAsmParser.h:107
MCTargetOptions.h
llvm::MCParsedAsmOperand
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Definition: MCParsedAsmOperand.h:24
llvm::IntelExpr::hasIndexReg
bool hasIndexReg() const
Definition: MCTargetAsmParser.h:83
llvm::AsmRewrite::Kind
AsmRewriteKind Kind
Definition: MCTargetAsmParser.h:96
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
StringRef.h
llvm::MCTargetAsmParser::tryParseRegister
virtual OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)=0
tryParseRegister - parse one register if possible
llvm::NearMissInfo::getKind
NearMissKind getKind() const
Definition: MCTargetAsmParser.h:245
llvm::NearMissInfo::getSuccess
static NearMissInfo getSuccess()
Definition: MCTargetAsmParser.h:192
llvm::DiagnosticPredicate::DiagnosticPredicate
DiagnosticPredicate(bool Match)
Definition: MCTargetAsmParser.h:162
MCParsedAsmOperand.h
llvm::AsmRewrite::Val
int64_t Val
Definition: MCTargetAsmParser.h:100
llvm::NearMissInfo::getMissedFeature
static NearMissInfo getMissedFeature(const FeatureBitset &MissingFeatures)
Definition: MCTargetAsmParser.h:197
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::MCTargetAsmParser::doBeforeLabelEmit
virtual void doBeforeLabelEmit(MCSymbol *Symbol)
Definition: MCTargetAsmParser.h:480
llvm::NearMissInfo::NearMissTooFewOperands
@ NearMissTooFewOperands
Definition: MCTargetAsmParser.h:187
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::DiagnosticPredicateTy::NearMatch
@ NearMatch
llvm::NearMissInfo
Definition: MCTargetAsmParser.h:180
llvm::MCParsedAsmOperand::isReg
virtual bool isReg() const =0
isReg - Is this a register operand?
llvm::MCTargetAsmParser::setAvailableFeatures
void setAvailableFeatures(const FeatureBitset &Value)
Definition: MCTargetAsmParser.h:357
llvm::DiagnosticPredicateTy::Match
@ Match
llvm::MCTargetAsmParser::checkTargetMatchPredicate
virtual unsigned checkTargetMatchPredicate(MCInst &Inst)
checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not ...
Definition: MCTargetAsmParser.h:450
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCTargetAsmParser::flushPendingInstructions
virtual void flushPendingInstructions(MCStreamer &Out)
Ensure that all previously parsed instructions have been emitted to the output streamer,...
Definition: MCTargetAsmParser.h:486
llvm::IntelExpr::hasOffset
bool hasOffset() const
Definition: MCTargetAsmParser.h:85
llvm::MCTargetAsmParser::parsePrimaryExpr
virtual bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc)
Definition: MCTargetAsmParser.h:371
llvm::IntelExpr::NeedBracs
bool NeedBracs
Definition: MCTargetAsmParser.h:64
llvm::MCTargetAsmParser::setParsingMSInlineAsm
void setParsingMSInlineAsm(bool Value)
Definition: MCTargetAsmParser.h:362
llvm::NearMissInfo::getOperandIndex
unsigned getOperandIndex() const
Definition: MCTargetAsmParser.h:276
llvm::NearMissInfo::NearMissKind
NearMissKind
Definition: MCTargetAsmParser.h:182
llvm::MCTargetAsmParser::setSemaCallback
void setSemaCallback(MCAsmParserSemaCallback *Callback)
Definition: MCTargetAsmParser.h:366
llvm::AsmToken
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
llvm::MCTargetAsmParser::starIsStartOfStatement
virtual bool starIsStartOfStatement()
Definition: MCTargetAsmParser.h:471
llvm::DiagnosticPredicateTy
DiagnosticPredicateTy
Definition: MCTargetAsmParser.h:127
llvm::MCTargetAsmParser::Match_InvalidOperand
@ Match_InvalidOperand
Definition: MCTargetAsmParser.h:312
llvm::NearMissInfo::Features
FeatureBitset Features
Definition: MCTargetAsmParser.h:299
llvm::AsmRewrite::AsmRewrite
AsmRewrite(SMLoc loc, unsigned len, IntelExpr exp)
Definition: MCTargetAsmParser.h:109
llvm::NearMissInfo::NearMissOperand
@ NearMissOperand
Definition: MCTargetAsmParser.h:184
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:197
llvm::NearMissInfo::getOperandClass
unsigned getOperandClass() const
Definition: MCTargetAsmParser.h:260
llvm::MCTargetAsmParser::SemaCallback
MCAsmParserSemaCallback * SemaCallback
SemaCallback - The Sema callback implementation.
Definition: MCTargetAsmParser.h:336
llvm::IntelExpr::IndexReg
StringRef IndexReg
Definition: MCTargetAsmParser.h:67
SubtargetFeature.h
llvm::MCTargetAsmParser::applyModifierToExpr
virtual const MCExpr * applyModifierToExpr(const MCExpr *E, MCSymbolRefExpr::VariantKind, MCContext &Ctx)
Definition: MCTargetAsmParser.h:473
llvm::MatchOperand_Success
@ MatchOperand_Success
Definition: MCTargetAsmParser.h:122
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::MCTargetAsmParser::ParseInstruction
virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands)=0
ParseInstruction - Parse one assembly instruction.
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MCTargetAsmParser::checkEarlyTargetMatchPredicate
virtual unsigned checkEarlyTargetMatchPredicate(MCInst &Inst, const OperandVector &Operands)
Validate the instruction match against any complex target predicates before rendering any operands to...
Definition: MCTargetAsmParser.h:444
llvm::MCTargetAsmParser::isParsingMSInlineAsm
bool isParsingMSInlineAsm()
Definition: MCTargetAsmParser.h:361
llvm::MCTargetAsmParser::validateTargetOperandClass
virtual unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind)
Allow a target to add special case operand matching for things that tblgen doesn't/can't handle effec...
Definition: MCTargetAsmParser.h:436
MCInstrInfo.h
llvm::MCTargetAsmParser::MII
const MCInstrInfo & MII
Definition: MCTargetAsmParser.h:344
llvm::NearMissInfo::getFeatures
const FeatureBitset & getFeatures() const
Definition: MCTargetAsmParser.h:249
false
Definition: StackSlotColoring.cpp:142
llvm::DiagnosticPredicate::isMatch
bool isMatch() const
Definition: MCTargetAsmParser.h:170
llvm::MCTargetAsmParser::MCTargetAsmParser
MCTargetAsmParser(MCTargetOptions const &, const MCSubtargetInfo &STI, const MCInstrInfo &MII)
Definition: MCTargetAsmParser.cpp:14
llvm::ParseInstructionInfo::AsmRewrites
SmallVectorImpl< AsmRewrite > * AsmRewrites
Definition: MCTargetAsmParser.h:114
SMLoc.h
llvm::AOK_Align
@ AOK_Align
Definition: MCTargetAsmParser.h:34
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::AsmRewrite::Loc
SMLoc Loc
Definition: MCTargetAsmParser.h:97
llvm::IntelExpr::emitImm
bool emitImm() const
Definition: MCTargetAsmParser.h:88
llvm::NearMissInfo::MissedOperand
MissedOpInfo MissedOperand
Definition: MCTargetAsmParser.h:301
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::NearMissInfo::getMissedPredicate
static NearMissInfo getMissedPredicate(unsigned FailureCode)
Definition: MCTargetAsmParser.h:207
llvm::MCAsmParser::parsePrimaryExpr
virtual bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc, AsmTypeInfo *TypeInfo)=0
Parse a primary expression.
llvm::DiagnosticPredicate::DiagnosticPredicate
DiagnosticPredicate(DiagnosticPredicateTy T)
Definition: MCTargetAsmParser.h:165
llvm::AOK_Output
@ AOK_Output
Definition: MCTargetAsmParser.h:39
llvm::NearMissInfo::NearMissPredicate
@ NearMissPredicate
Definition: MCTargetAsmParser.h:186
llvm::AsmRewritePrecedence
const char AsmRewritePrecedence[]
Definition: MCTargetAsmParser.h:47
llvm::MCTargetAsmParser::equalIsAsmAssignment
virtual bool equalIsAsmAssignment()
Definition: MCTargetAsmParser.h:467
llvm::DiagnosticPredicate::Type
DiagnosticPredicateTy Type
Definition: MCTargetAsmParser.h:160
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::MCTargetAsmParser::AvailableFeatures
FeatureBitset AvailableFeatures
AvailableFeatures - The current set of available features.
Definition: MCTargetAsmParser.h:329
llvm::DiagnosticPredicate::isNearMatch
bool isNearMatch() const
Definition: MCTargetAsmParser.h:171
llvm::MCTargetAsmParser::ParseInstruction
virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, AsmToken Token, OperandVector &Operands)
Definition: MCTargetAsmParser.h:401
llvm::MCTargetAsmParser::FIRST_TARGET_MATCH_RESULT_TY
@ FIRST_TARGET_MATCH_RESULT_TY
Definition: MCTargetAsmParser.h:318
val
The initial backend is deliberately restricted to z10 We should add support for later architectures at some point If an asm ties an i32 r result to an i64 the input will be treated as an leaving the upper bits uninitialised For i64 store i32 val
Definition: README.txt:15
llvm::MCTargetAsmParser::isLabel
virtual bool isLabel(AsmToken &Token)
Definition: MCTargetAsmParser.h:469
llvm::MCTargetAsmParser::MCOptions
MCTargetOptions MCOptions
Set of options which affects instrumentation of inline assembly.
Definition: MCTargetAsmParser.h:339
MCAsmLexer.h
llvm::MCTargetAsmParser::Match_MissingFeature
@ Match_MissingFeature
Definition: MCTargetAsmParser.h:314
llvm::MCTargetAsmParser::convertToMapAndConstraints
virtual void convertToMapAndConstraints(unsigned Kind, const OperandVector &Operands)=0
llvm::ParseInstructionInfo
Definition: MCTargetAsmParser.h:113
llvm::MCSymbolRefExpr::VariantKind
VariantKind
Definition: MCExpr.h:194
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::IntelExpr
Definition: MCTargetAsmParser.h:63
llvm::MCTargetAsmParser::ParseRegister
virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)=0
llvm::MCTargetAsmParser::createTargetUnaryExpr
virtual const MCExpr * createTargetUnaryExpr(const MCExpr *E, AsmToken::TokenKind OperatorToken, MCContext &Ctx)
Definition: MCTargetAsmParser.h:488
llvm::NearMissInfo::getOpcode
unsigned getOpcode() const
Definition: MCTargetAsmParser.h:265
llvm::MatchOperand_ParseFail
@ MatchOperand_ParseFail
Definition: MCTargetAsmParser.h:124
llvm::AOK_EVEN
@ AOK_EVEN
Definition: MCTargetAsmParser.h:35
llvm::MCTargetAsmParser::ParseDirective
virtual bool ParseDirective(AsmToken DirectiveID)=0
ParseDirective - Parse a target specific assembler directive.
llvm::AsmRewrite::AsmRewrite
AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len=0, int64_t val=0)
Definition: MCTargetAsmParser.h:105
llvm::NearMissInfo::NearMissFeature
@ NearMissFeature
Definition: MCTargetAsmParser.h:185
llvm::NearMissInfo::getTooFewOperands
static NearMissInfo getTooFewOperands(unsigned OperandClass, unsigned Opcode)
Definition: MCTargetAsmParser.h:234
llvm::DiagnosticPredicate::isNoMatch
bool isNoMatch() const
Definition: MCTargetAsmParser.h:172
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AsmRewrite
Definition: MCTargetAsmParser.h:95
llvm::MCTargetAsmParser::Match_MnemonicFail
@ Match_MnemonicFail
Definition: MCTargetAsmParser.h:315
llvm::MCTargetAsmParser::onLabelParsed
virtual void onLabelParsed(MCSymbol *Symbol)
Definition: MCTargetAsmParser.h:482
llvm::IntelExpr::hasBaseReg
bool hasBaseReg() const
Definition: MCTargetAsmParser.h:82
llvm::ErrorInfo
Base class for user error types.
Definition: Error.h:349
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::AOK_Skip
@ AOK_Skip
Definition: MCTargetAsmParser.h:43
llvm::MCTargetAsmParser::STI
const MCSubtargetInfo * STI
Current STI.
Definition: MCTargetAsmParser.h:342
llvm::MatchOperand_NoMatch
@ MatchOperand_NoMatch
Definition: MCTargetAsmParser.h:123
llvm::ParseInstructionInfo::ParseInstructionInfo
ParseInstructionInfo(SmallVectorImpl< AsmRewrite > *rewrites)
Definition: MCTargetAsmParser.h:117
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MCTargetAsmParser::onBeginOfFile
virtual void onBeginOfFile()
Definition: MCTargetAsmParser.h:495
llvm::MCParsedAsmOperand::getReg
virtual unsigned getReg() const =0
llvm::MCAsmParserExtension
Generic interface for extending the MCAsmParser, which is implemented by target and object file assem...
Definition: MCAsmParserExtension.h:25
llvm::MCTargetAsmParser::operator=
MCTargetAsmParser & operator=(const MCTargetAsmParser &)=delete
scale
static uint64_t scale(uint64_t Num, uint32_t N, uint32_t D)
Definition: BranchProbability.cpp:69
llvm::AOK_EndOfStatement
@ AOK_EndOfStatement
Definition: MCTargetAsmParser.h:42
llvm::MCTargetAsmParser::MatchAndEmitInstruction
virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm)=0
MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst ...
llvm::AOK_Emit
@ AOK_Emit
Definition: MCTargetAsmParser.h:36
llvm::IntelExpr::IntelExpr
IntelExpr()
Definition: MCTargetAsmParser.h:71
llvm::MCTargetAsmParser::ParsingMSInlineAsm
bool ParsingMSInlineAsm
ParsingMSInlineAsm - Are we parsing ms-style inline assembly?
Definition: MCTargetAsmParser.h:332
llvm::IntelExpr::isValid
bool isValid() const
Definition: MCTargetAsmParser.h:89
llvm::MCTargetAsmParser::Match_Success
@ Match_Success
Definition: MCTargetAsmParser.h:316
llvm::AsmRewrite::Len
unsigned Len
Definition: MCTargetAsmParser.h:98
llvm::OperandMatchResultTy
OperandMatchResultTy
Definition: MCTargetAsmParser.h:121
llvm::DiagnosticPredicate::operator=
DiagnosticPredicate & operator=(const DiagnosticPredicate &)=default
llvm::AsmRewrite::Done
bool Done
Definition: MCTargetAsmParser.h:99
llvm::DiagnosticPredicateTy::NoMatch
@ NoMatch
llvm::NearMissInfo::getOperandError
unsigned getOperandError() const
Definition: MCTargetAsmParser.h:270
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::MCTargetAsmParser::getSTI
const MCSubtargetInfo & getSTI() const
Definition: MCTargetAsmParser.cpp:27
llvm::AOK_Label
@ AOK_Label
Definition: MCTargetAsmParser.h:41
llvm::MCTargetAsmParser::onEndOfFile
virtual void onEndOfFile()
Definition: MCTargetAsmParser.h:498
MCAsmParserExtension.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::MCTargetAsmParser::regsEqual
virtual bool regsEqual(const MCParsedAsmOperand &Op1, const MCParsedAsmOperand &Op2) const
Returns whether two registers are equal and is used by the tied-operands checks in the AsmMatcher.
Definition: MCTargetAsmParser.h:460
llvm::IntelExpr::OffsetName
StringRef OffsetName
Definition: MCTargetAsmParser.h:68
llvm::NearMissInfo::TooFewOperands
TooFewOperandsInfo TooFewOperands
Definition: MCTargetAsmParser.h:302
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::MCTargetAsmParser::copySTI
MCSubtargetInfo & copySTI()
Create a copy of STI and return a non-const reference to it.
Definition: MCTargetAsmParser.cpp:21
llvm::AsmRewrite::Label
StringRef Label
Definition: MCTargetAsmParser.h:101
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::NearMissInfo::getPredicateError
unsigned getPredicateError() const
Definition: MCTargetAsmParser.h:255
llvm::MCTargetAsmParser::getAvailableFeatures
const FeatureBitset & getAvailableFeatures() const
Definition: MCTargetAsmParser.h:354
llvm::MCTargetAsmParser
MCTargetAsmParser - Generic interface to target specific assembly parsers.
Definition: MCTargetAsmParser.h:309
llvm::NearMissInfo::NoNearMiss
@ NoNearMiss
Definition: MCTargetAsmParser.h:183
llvm::MCTargetAsmParser::Match_InvalidTiedOperand
@ Match_InvalidTiedOperand
Definition: MCTargetAsmParser.h:313
llvm::AOK_IntelExpr
@ AOK_IntelExpr
Definition: MCTargetAsmParser.h:44
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
llvm::MCTargetAsmParser::~MCTargetAsmParser
~MCTargetAsmParser() override
llvm::AsmToken::TokenKind
TokenKind
Definition: MCAsmMacro.h:23
llvm::MCTargetAsmParser::MatchResultTy
MatchResultTy
Definition: MCTargetAsmParser.h:311
llvm::DiagnosticPredicate
Definition: MCTargetAsmParser.h:159
llvm::AsmRewriteKind
AsmRewriteKind
Definition: MCTargetAsmParser.h:33
llvm::MCTargetAsmParser::Match_NearMisses
@ Match_NearMisses
Definition: MCTargetAsmParser.h:317
llvm::AsmRewrite::IntelExp
IntelExpr IntelExp
Definition: MCTargetAsmParser.h:102
llvm::MCTargetAsmParser::OmitRegisterFromClobberLists
virtual bool OmitRegisterFromClobberLists(unsigned RegNo)
Allows targets to let registers opt out of clobber lists.
Definition: MCTargetAsmParser.h:430
llvm::NearMissInfo::getMissedOperand
static NearMissInfo getMissedOperand(unsigned OperandError, unsigned OperandClass, unsigned Opcode, unsigned OperandIndex)
Definition: MCTargetAsmParser.h:219
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::MCTargetAsmParser::getTargetOptions
MCTargetOptions getTargetOptions() const
Definition: MCTargetAsmParser.h:364
llvm::IntelExpr::Scale
unsigned Scale
Definition: MCTargetAsmParser.h:69
llvm::ParseInstructionInfo::ParseInstructionInfo
ParseInstructionInfo()=default
llvm::IntelExpr::Imm
int64_t Imm
Definition: MCTargetAsmParser.h:65
llvm::AOK_Input
@ AOK_Input
Definition: MCTargetAsmParser.h:38
llvm::AsmToken::getLoc
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:27
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::AOK_CallInput
@ AOK_CallInput
Definition: MCTargetAsmParser.h:37
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::MCAsmParserExtension::getParser
MCAsmParser & getParser()
Definition: MCAsmParserExtension.h:62
llvm::IntelExpr::IntelExpr
IntelExpr(StringRef baseReg, StringRef indexReg, unsigned scale, StringRef offsetName, int64_t imm, bool needBracs)
Definition: MCTargetAsmParser.h:75
llvm::AOK_SizeDirective
@ AOK_SizeDirective
Definition: MCTargetAsmParser.h:40
llvm::IntelExpr::hasRegs
bool hasRegs() const
Definition: MCTargetAsmParser.h:84