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9 #ifndef LLVM_MC_MCPARSER_MCTARGETASMPARSER_H
10 #define LLVM_MC_MCPARSER_MCTARGETASMPARSER_H
28 class MCSubtargetInfo;
30 template <
typename T>
class SmallVectorImpl;
77 StringRef offsetName, int64_t imm,
bool needBracs)
91 return (
Scale == 1) ||
108 bool Restricted =
false)
205 Result.Features = MissingFeatures;
215 Result.PredicateError = FailureCode;
225 unsigned OperandClass,
unsigned Opcode,
226 unsigned OperandIndex) {
229 Result.MissedOperand.Error = OperandError;
230 Result.MissedOperand.Class = OperandClass;
231 Result.MissedOperand.Opcode = Opcode;
232 Result.MissedOperand.Index = OperandIndex;
243 Result.TooFewOperands.Class = OperandClass;
244 Result.TooFewOperands.Opcode = Opcode;
291 struct MissedOpInfo {
298 struct TooFewOperandsInfo {
432 bool MatchingInlineAsm) = 0;
508 #endif // LLVM_MC_MCPARSER_MCTARGETASMPARSER_H
Generic Sema callback for assembly parser.
This is an optimization pass for GlobalISel generic memory operations.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len, StringRef label)
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Context object for machine code objects.
virtual OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)=0
tryParseRegister - parse one register if possible
NearMissKind getKind() const
static NearMissInfo getSuccess()
DiagnosticPredicate(bool Match)
AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len=0, int64_t val=0, bool Restricted=false)
static NearMissInfo getMissedFeature(const FeatureBitset &MissingFeatures)
The instances of the Type class are immutable: once they are created, they are never changed.
virtual void doBeforeLabelEmit(MCSymbol *Symbol)
Container class for subtarget features.
virtual bool isReg() const =0
isReg - Is this a register operand?
void setAvailableFeatures(const FeatureBitset &Value)
virtual unsigned checkTargetMatchPredicate(MCInst &Inst)
checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not ...
Instances of this class represent a single low-level machine instruction.
virtual void flushPendingInstructions(MCStreamer &Out)
Ensure that all previously parsed instructions have been emitted to the output streamer,...
virtual bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc)
void setParsingMSInlineAsm(bool Value)
unsigned getOperandIndex() const
void setSemaCallback(MCAsmParserSemaCallback *Callback)
Target independent representation for an assembler token.
virtual bool starIsStartOfStatement()
AsmRewrite(SMLoc loc, unsigned len, IntelExpr exp)
Streaming machine code generation interface.
unsigned getOperandClass() const
MCAsmParserSemaCallback * SemaCallback
SemaCallback - The Sema callback implementation.
virtual const MCExpr * applyModifierToExpr(const MCExpr *E, MCSymbolRefExpr::VariantKind, MCContext &Ctx)
Represents a location in source code.
virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands)=0
ParseInstruction - Parse one assembly instruction.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual unsigned checkEarlyTargetMatchPredicate(MCInst &Inst, const OperandVector &Operands)
Validate the instruction match against any complex target predicates before rendering any operands to...
bool isParsingMSInlineAsm()
virtual unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind)
Allow a target to add special case operand matching for things that tblgen doesn't/can't handle effec...
const FeatureBitset & getFeatures() const
MCTargetAsmParser(MCTargetOptions const &, const MCSubtargetInfo &STI, const MCInstrInfo &MII)
SmallVectorImpl< AsmRewrite > * AsmRewrites
Analysis containing CSE Info
MissedOpInfo MissedOperand
static NearMissInfo getMissedPredicate(unsigned FailureCode)
virtual bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc, AsmTypeInfo *TypeInfo)=0
Parse a primary expression.
DiagnosticPredicate(DiagnosticPredicateTy T)
const char AsmRewritePrecedence[]
virtual bool equalIsAsmAssignment()
DiagnosticPredicateTy Type
mir Rename Register Operands
FeatureBitset AvailableFeatures
AvailableFeatures - The current set of available features.
virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, AsmToken Token, OperandVector &Operands)
@ FIRST_TARGET_MATCH_RESULT_TY
The initial backend is deliberately restricted to z10 We should add support for later architectures at some point If an asm ties an i32 r result to an i64 the input will be treated as an leaving the upper bits uninitialised For i64 store i32 val
virtual bool isLabel(AsmToken &Token)
MCTargetOptions MCOptions
Set of options which affects instrumentation of inline assembly.
virtual void convertToMapAndConstraints(unsigned Kind, const OperandVector &Operands)=0
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)=0
virtual const MCExpr * createTargetUnaryExpr(const MCExpr *E, AsmToken::TokenKind OperatorToken, MCContext &Ctx)
unsigned getOpcode() const
virtual bool ParseDirective(AsmToken DirectiveID)=0
ParseDirective - Parse a target specific assembler directive.
static NearMissInfo getTooFewOperands(unsigned OperandClass, unsigned Opcode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual void onLabelParsed(MCSymbol *Symbol)
Base class for user error types.
const MCSubtargetInfo * STI
Current STI.
ParseInstructionInfo(SmallVectorImpl< AsmRewrite > *rewrites)
StringRef - Represent a constant reference to a string, i.e.
virtual void onBeginOfFile()
virtual unsigned getReg() const =0
Generic interface for extending the MCAsmParser, which is implemented by target and object file assem...
MCTargetAsmParser & operator=(const MCTargetAsmParser &)=delete
static uint64_t scale(uint64_t Num, uint32_t N, uint32_t D)
virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm)=0
MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst ...
bool ParsingMSInlineAsm
ParsingMSInlineAsm - Are we parsing ms-style inline assembly?
DiagnosticPredicate & operator=(const DiagnosticPredicate &)=default
unsigned getOperandError() const
Interface to description of machine instruction set.
const MCSubtargetInfo & getSTI() const
virtual void onEndOfFile()
virtual bool regsEqual(const MCParsedAsmOperand &Op1, const MCParsedAsmOperand &Op2) const
Returns whether two registers are equal and is used by the tied-operands checks in the AsmMatcher.
TooFewOperandsInfo TooFewOperands
Lightweight error class with error context and mandatory checking.
MCSubtargetInfo & copySTI()
Create a copy of STI and return a non-const reference to it.
unsigned getPredicateError() const
const FeatureBitset & getAvailableFeatures() const
MCTargetAsmParser - Generic interface to target specific assembly parsers.
@ Match_InvalidTiedOperand
~MCTargetAsmParser() override
virtual bool OmitRegisterFromClobberLists(unsigned RegNo)
Allows targets to let registers opt out of clobber lists.
static NearMissInfo getMissedOperand(unsigned OperandError, unsigned OperandClass, unsigned Opcode, unsigned OperandIndex)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
MCTargetOptions getTargetOptions() const
ParseInstructionInfo()=default
Generic base class for all target subtargets.
LLVM Value Representation.
Base class for the full range of assembler expressions which are needed for parsing.
MCAsmParser & getParser()
IntelExpr(StringRef baseReg, StringRef indexReg, unsigned scale, StringRef offsetName, int64_t imm, bool needBracs)