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Mips16ISelLowering.h
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1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Subclass of MipsTargetLowering specialized for mips16.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_MIPS_MIPS16ISELLOWERING_H
14 #define LLVM_LIB_TARGET_MIPS_MIPS16ISELLOWERING_H
15 
16 #include "MipsISelLowering.h"
17 
18 namespace llvm {
20  public:
22  const MipsSubtarget &STI);
23 
24  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
25  Align Alignment,
27  bool *Fast) const override;
28 
31  MachineBasicBlock *MBB) const override;
32 
33  private:
34  bool isEligibleForTailCallOptimization(
35  const CCState &CCInfo, unsigned NextStackOffset,
36  const MipsFunctionInfo &FI) const override;
37 
38  void setMips16HardFloatLibCalls();
39 
40  unsigned int
41  getMips16HelperFunctionStubNumber(ArgListTy &Args) const;
42 
43  const char *getMips16HelperFunction
44  (Type* RetTy, ArgListTy &Args, bool &needHelper) const;
45 
46  void
47  getOpndList(SmallVectorImpl<SDValue> &Ops,
48  std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
49  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
50  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
51  SDValue Chain) const override;
52 
53  MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr &MI,
54  MachineBasicBlock *BB) const;
55 
56  MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2,
58  MachineBasicBlock *BB) const;
59 
60  MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2,
62  MachineBasicBlock *BB) const;
63 
64  MachineBasicBlock *emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
66  MachineBasicBlock *BB) const;
67 
68  MachineBasicBlock *emitFEXT_T8I8I16_ins(unsigned BtOpc, unsigned CmpiOpc,
69  unsigned CmpiXOpc, bool ImmSigned,
71  MachineBasicBlock *BB) const;
72 
73  MachineBasicBlock *emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI,
74  MachineBasicBlock *BB) const;
75 
76  MachineBasicBlock *emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc,
78  MachineBasicBlock *BB) const;
79  };
80 }
81 
82 #endif
llvm::MipsTargetMachine
Definition: MipsTargetMachine.h:27
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::Mips16TargetLowering
Definition: Mips16ISelLowering.h:19
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::MipsFunctionInfo
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
Definition: MipsMachineFunction.h:25
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::Mips16TargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
Definition: Mips16ISelLowering.cpp:158
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::Mips16TargetLowering::Mips16TargetLowering
Mips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Definition: Mips16ISelLowering.cpp:120
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3747
llvm::Mips16TargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: Mips16ISelLowering.cpp:164
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::MipsTargetLowering
Definition: MipsISelLowering.h:261
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:304
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:206
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
MipsISelLowering.h
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389